diff options
author | Robb Glasser <rglasser@google.com> | 2017-11-17 15:19:30 -0800 |
---|---|---|
committer | Robb Glasser <rglasser@google.com> | 2017-11-22 15:36:06 -0800 |
commit | 30ecafeffccb997af944fdc69e266fb59ccc0f5c (patch) | |
tree | f1b8c56d96eafad05b1532153b435efc31eb09aa /init.power.rc | |
parent | 9d9ed3c176108fa46981248c6bbcdf6af80415ff (diff) | |
download | bonito-30ecafeffccb997af944fdc69e266fb59ccc0f5c.tar.gz |
Update power init scripts
Updating power init scripts with the latest settings for crosshatch and
enabling the Power HAL.
Bug: 69270928
Test: Compiled and booted
Test: Checked logcat for errors
Test: Verified writes made it to respective nodes
Change-Id: I417126cd1a56a82d53a1cf7455beccbd6240e76c
Diffstat (limited to 'init.power.rc')
-rw-r--r-- | init.power.rc | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/init.power.rc b/init.power.rc new file mode 100644 index 00000000..c20b3890 --- /dev/null +++ b/init.power.rc @@ -0,0 +1,68 @@ +# +# Copyright (C) 2017 The Android Open-Source Project +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +on property:sys.boot_completed=1 + # Enable bus-dcvs + write /sys/class/devfreq/soc:qcom,cpubw/governor "bw_hwmon" + write /sys/class/devfreq/soc:qcom,cpubw/polling_interval 50 + write /sys/class/devfreq/soc:qcom,cpubw/bw_hwmon/mbps_zones "2288 4577 6500 8132 9155 10681" + write /sys/class/devfreq/soc:qcom,cpubw/bw_hwmon/sample_ms 4 + write /sys/class/devfreq/soc:qcom,cpubw/bw_hwmon/io_percent 40 + write /sys/class/devfreq/soc:qcom,cpubw/bw_hwmon/hist_memory 20 + write /sys/class/devfreq/soc:qcom,cpubw/bw_hwmon/hyst_length 10 + write /sys/class/devfreq/soc:qcom,cpubw/bw_hwmon/low_power_ceil_mbps 0 + write /sys/class/devfreq/soc:qcom,cpubw/bw_hwmon/low_power_io_percent 40 + write /sys/class/devfreq/soc:qcom,cpubw/bw_hwmon/low_power_delay 20 + write /sys/class/devfreq/soc:qcom,cpubw/bw_hwmon/guard_band_mbps 0 + write /sys/class/devfreq/soc:qcom,cpubw/bw_hwmon/up_scale 250 + write /sys/class/devfreq/soc:qcom,cpubw/bw_hwmon/idle_mbps 1600 + + write /sys/class/devfreq/soc:qcom,llccbw/governor "bw_hwmon" + write /sys/class/devfreq/soc:qcom,llccbw/polling_interval 50 + write /sys/class/devfreq/soc:qcom,llccbw/bw_hwmon/mbps_zones "1720 2929 4943 5931 6881" + write /sys/class/devfreq/soc:qcom,llccbw/bw_hwmon/sample_ms 4 + write /sys/class/devfreq/soc:qcom,llccbw/bw_hwmon/io_percent 80 + write /sys/class/devfreq/soc:qcom,llccbw/bw_hwmon/hist_memory 20 + write /sys/class/devfreq/soc:qcom,llccbw/bw_hwmon/hyst_length 10 + write /sys/class/devfreq/soc:qcom,llccbw/bw_hwmon/low_power_ceil_mbps 0 + write /sys/class/devfreq/soc:qcom,llccbw/bw_hwmon/low_power_io_percent 80 + write /sys/class/devfreq/soc:qcom,llccbw/bw_hwmon/low_power_delay 20 + write /sys/class/devfreq/soc:qcom,llccbw/bw_hwmon/guard_band_mbps 0 + write /sys/class/devfreq/soc:qcom,llccbw/bw_hwmon/up_scale 250 + write /sys/class/devfreq/soc:qcom,llccbw/bw_hwmon/idle_mbps 1600 + + write /sys/class/devfreq/soc:qcom,mincpubw/governor "cpufreq" + + # Enable memlat governor + write /sys/class/devfreq/soc:qcom,memlat-cpu0/governor "mem_latency" + write /sys/class/devfreq/soc:qcom,memlat-cpu0/polling_interval 10 + write /sys/class/devfreq/soc:qcom,memlat-cpu0/mem_latency/ratio_ceil 400 + write /sys/class/devfreq/soc:qcom,memlat-cpu4/governor "mem_latency" + write /sys/class/devfreq/soc:qcom,memlat-cpu4/polling_interval 10 + write /sys/class/devfreq/soc:qcom,memlat-cpu4/mem_latency/ratio_ceil 400 + + write /sys/class/devfreq/soc:qcom,l3-cpu0/governor "mem_latency" + write /sys/class/devfreq/soc:qcom,l3-cpu0/polling_interval 10 + write /sys/class/devfreq/soc:qcom,l3-cpu0/mem_latency/ratio_ceil 400 + write /sys/class/devfreq/soc:qcom,l3-cpu4/governor "mem_latency" + write /sys/class/devfreq/soc:qcom,l3-cpu4/polling_interval 10 + write /sys/class/devfreq/soc:qcom,l3-cpu4/mem_latency/ratio_ceil 400 + + # Turn on sleep modes. + write /sys/module/lpm_levels/parameters/sleep_disabled 0 + + # Signal perfd that boot has completed + setprop sys.post_boot.parsed 1
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