Bonito: Phase-in appropriate RF config

Bug: 112677439
Test: NFC on/off, NFC CE/P2P/RW mode
Change-Id: I57e4a21b9df400b7ead460660d9323ec7858275f

2 files changed, 47 insertions, 75 deletions

diff --git a/nfc/libnfc-nxp.bonito.conf b/nfc/libnfc-nxp.bonito.conf
index ba24631e..73acdf6b 100644
--- a/nfc/libnfc-nxp.bonito.conf
+++ b/nfc/libnfc-nxp.bonito.conf
@@ -72,7 +72,7 @@ NXP_EXT_TVDD_CFG_1={20, 02, 0F, 01, A0, 0E, 0B, 31, 01, 01, 31, 00, 00, 00, 01,
 ###############################################################################
 #config2: use DCDC in CE, use Tx_Pwr_Req, set CFG2 mode, SLALM,
 #monitoring 5V from DCDC, 3.3V for both RM and CM, DCDCWaitTime=4.2ms
-NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, 82, 00, B2, 1E, 14, 00, D0, 0C}
+NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, 82, 00, BA, 1E, 10, 00, D0, 0C}
 
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
@@ -80,57 +80,39 @@ NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, 82, 00, B2, 1E, 14,
 NXP_RF_CONF_BLK_1={
 20, 02, 19, 03,
 A0, 0D, 03, 24, 03, 80,
-A0, 0D, 06, 08, 37, 08, 76, 00, 00,
-A0, 0D, 06, 08, 42, 00, 02, F8, F8
+A0, 0D, 06, 08, 37, 28, 76, 00, 00,
+A0, 0D, 06, 08, 42, 00, 02, FF, FF
 }
 
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
 # This section needs to be updated with the correct values based on the platform
 NXP_RF_CONF_BLK_2={
-20, 02, 10, 01, A0, AF, 0C, 83, E3, B9, 80, 00, 83, C2, B9, 80, 00, 77, 08
+20, 02, 5B, 01, A0, 0B, 57, F2, 12, 90, 5A, 0F, 4E, 00, 47, 15, B7, AA, 47,
+9F, A7, 99, 5C, 9F, 97, 99, 67, 9F, 97, 99, 69, 9F, 97, 00, 73, 9F, 07, 00,
+75, 9F, 07, 00, 80, 9F, 07, 00, 84, 9F, 07, 00, 8D, 9F, 07, 00, 8F, 9F, 07,
+00, 99, 9F, 04, 00, 9B, 9F, 04, 00, A6, 9F, 04, 00, A8, 9F, 04, 00, B2, 9F,
+02, 00, BB, 9F, 00, 00, C1, 9F, 00, 00, CC, 9F, 00, 00, D6, 1F, 00, 00
 }
 
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
 # This section needs to be updated with the correct values based on the platform
 NXP_RF_CONF_BLK_3={
-20, 02, 98, 01, A0, 34, 94, 23, 04, 18, 35, 00, 00, 4B, 00, 00, 71, 00, 00,
-71, 00, 00, 96, 00, 00, BC, 00, 00, BC, 00, 00, E1, 00, 00, 07, 01, 00, 07,
-01, 00, 2C, 01, 00, 2C, 01, 00, 52, 01, 00, 52, 01, 00, 77, 01, 00, 77, 01,
-00, C2, 01, 00, C2, 01, 00, 0D, 02, 00, 0D, 02, 00, 58, 02, 00, 58, 02, 00,
-EE, 02, 00, EE, 02, 00, 18, 35, 00, 00, 4B, 00, 00, 71, 00, 00, 96, 00, 00,
-96, 00, 00, 96, 00, 00, BC, 00, 00, BC, 00, 00, BC, 00, 00, BC, 00, 00, E1,
-00, 00, E1, 00, 00, 2C, 01, 00, 2C, 01, 00, 2C, 01, 00, 2C, 01, 00, 2C, 01,
-00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00,
-DC, 05, 00
+20, 02, 10, 01, A0, AF, 0C, 03, C0, 80, A0, 00, 03, 80, 80, A0, 00, 77, 08
 }
 
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
 # This section needs to be updated with the correct values based on the platform
-NXP_RF_CONF_BLK_4={
-20, 02, A4, 01, A0, A9, A0, 00, C1, 00, 0A, 01, 80, 41, 0A, 02, 81, 83, 0A,
-03, C0, 42, 06, 04, 80, 46, 06, 05, C3, 01, 03, 06, C2, 05, 03, 07, C2, 4A,
-03, 07, 81, 01, 01, 08, C3, 8B, 03, 08, C3, 05, 01, 09, C3, 92, 03, 09, C6,
-84, 01, 0A, C4, CC, 03, 0A, C6, 89, 01, 0B, C5, D4, 03, 0B, C7, 92, 01, 0C,
-44, 00, 03, 0C, C7, C6, 01, 0D, 42, 04, 03, 0D, C9, CE, 01, 0E, 42, 48, 03,
-0E, 03, 00, 01, 0F, 43, 50, 03, 0F, 43, 04, 01, 10, 43, 91, 03, 10, 45, 0A,
-01, 11, 44, 95, 03, 11, 46, 11, 01, 12, 46, 8E, 01, 13, 47, C5, 01, 14, 48,
-CC, 01, 15, 4B, D4, 01, 16, 4E, D7, 01, 17, 5E, A2, 01, 18, 5F, A6, 01, 19,
-5F, AE, 01, 1A, 60, B4, 01, 1B, 61, EA, 01, 1C, 62, F0, 01
-}
+#NXP_RF_CONF_BLK_4={
+#}
 
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
 # This section needs to be updated with the correct values based on the platform
-NXP_RF_CONF_BLK_5={
-20, 02, 5B, 01, A0, 0B, 57, ED, 0D, 90, 7F, 0F, 4E, 00, 3B, 95, 00, 00, 3B,
-9F, 00, 00, 4D, 9F, 00, 00, 56, 9F, 00, 00, 58, 9F, 00, 00, 60, 9F, 00, 00,
-62, 9F, 00, 00, 6B, 9F, 00, 00, 6F, 9F, 00, 00, 76, 9F, 00, 00, 77, 9F, 00,
-00, 80, 9F, 00, 00, 82, 9F, 00, 00, 8B, 9F, 00, 00, 8C, 1F, 00, 00, 95, 1F,
-00, 00, 9C, 1F, 00, 00, A2, 1F, 00, 00, AA, 1F, 00, 00, B3, 1F, 00, 00
-}
+#NXP_RF_CONF_BLK_5={
+#}
 
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
@@ -155,22 +137,26 @@ NXP_RF_CONF_BLK_5={
 # SWP1A interface A0D4
 # DWP intf behavior config, SVDD Load activated by default if set to 0x31 A037
 # SPI CL Sync enable  A098
-NXP_CORE_CONF_EXTN={20, 02, 4A, 0F,
+NXP_CORE_CONF_EXTN={20, 02, 5B, 13,
     A0, EC, 01, 01,
     A0, ED, 01, 01,
     A0, 5E, 01, 01,
     A0, 12, 01, 02,
     A0, 40, 01, 01,
+    A0, 41, 01, 03,
+    A0, 43, 01, 50,
     A0, D1, 01, 02,
     A0, D4, 01, 00,
     A0, 37, 01, 35,
     A0, D8, 01, 02,
     A0, D5, 01, 0A,
     A0, 98, 01, 03,
-    A0, AA, 04, FD, 03, F4, 01,
+    A0, 9C, 02, 00, 00,
+    A0, AA, 04, F1, 03, 2D, 01,
     A0, 38, 04, 14, 0B, 0B, 00,
-    A0, 3A, 08, C8, 00, C8, 00, C8, 00, C8, 00,
-    A0, B2, 01, 19
+    A0, 3A, 08, C3, 00, C3, 00, C3, 00, C3, 00,
+    A0, B2, 01, 19,
+    A0, 91, 01, 00
 }
 
 ###############################################################################
@@ -283,7 +269,7 @@ NFA_POLL_BAIL_OUT_MODE=0x01
 ###############################################################################
 # White list of Hosts
 # This values will be the Hosts(NFCEEs) in the HCI Network.
-DEVICE_HOST_WHITE_LIST={C0, 80}
+DEVICE_HOST_WHITE_LIST={C0, 02}
 
 ###############################################################################
 # Extended APDU length for ISO_DEP
@@ -302,7 +288,7 @@ PRESENCE_CHECK_ALGORITHM=2
 # destination gate (see NFA_HCI_DEFAULT_DEST_GATE).  Note there is a value
 # for each UICC (where F3="UICC0" and F4="UICC1")
 OFF_HOST_ESE_PIPE_ID=0x16
-OFF_HOST_SIM_PIPE_ID=0x70
+OFF_HOST_SIM_PIPE_ID=0x0A
 
 ###############################################################################
 #Set the Felica T3T System Code Power state :
diff --git a/nfc/libnfc-nxp.sargo.conf b/nfc/libnfc-nxp.sargo.conf
index 171c709d..e644cf18 100644
--- a/nfc/libnfc-nxp.sargo.conf
+++ b/nfc/libnfc-nxp.sargo.conf
@@ -72,65 +72,47 @@ NXP_EXT_TVDD_CFG_1={20, 02, 0F, 01, A0, 0E, 0B, 31, 01, 01, 31, 00, 00, 00, 01,
 ###############################################################################
 #config2: use DCDC in CE, use Tx_Pwr_Req, set CFG2 mode, SLALM,
 #monitoring 5V from DCDC, 3.3V for both RM and CM, DCDCWaitTime=4.2ms
-NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, 82, 00, B2, 1E, 14, 00, D0, 0C}
+NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, 82, 00, BA, 1E, 10, 00, D0, 0C}
 
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
 # This section needs to be updated with the correct values based on the platform
 NXP_RF_CONF_BLK_1={
 20, 02, 19, 03,
-A0, 0D, 03, 24, 03, 7F,
-A0, 0D, 06, 08, 37, 08, 76, 00, 00,
-A0, 0D, 06, 08, 42, 00, 02, F8, F8
+A0, 0D, 03, 24, 03, 80,
+A0, 0D, 06, 08, 37, 28, 76, 00, 00,
+A0, 0D, 06, 08, 42, 00, 02, FF, FF
 }
 
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
 # This section needs to be updated with the correct values based on the platform
 NXP_RF_CONF_BLK_2={
-20, 02, 10, 01, A0, AF, 0C, 83, E3, DF, 80, 00, 83, C1, DF, 80, 00, 77, 08
+20, 02, 5B, 01, A0, 0B, 57, F2, 12, 90, 79, 0F, 4E, 00, 3D, 15, B7, AA, 3D,
+9F, A7, 99, 4F, 9F, 97, 99, 58, 9F, 97, 99, 5A, 9F, 97, 00, 63, 9F, 07, 00,
+65, 9F, 07, 00, 6E, 9F, 07, 00, 72, 9F, 07, 00, 79, 9F, 07, 00, 7B, 9F, 07,
+00, 84, 9F, 04, 00, 85, 9F, 04, 00, 8E, 9F, 04, 00, 90, 9F, 04, 00, 99, 9F,
+02, 00, A1, 9F, 00, 00, A6, 9F, 00, 00, AF, 9F, 00, 00, B8, 1F, 00, 00
 }
 
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
 # This section needs to be updated with the correct values based on the platform
 NXP_RF_CONF_BLK_3={
-20, 02, 98, 01, A0, 34, 94, 23, 04, 18, 35, 00, 00, 4B, 00, 00, 71, 00, 00,
-71, 00, 00, 96, 00, 00, BC, 00, 00, BC, 00, 00, E1, 00, 00, 07, 01, 00, 07,
-01, 00, 2C, 01, 00, 2C, 01, 00, 52, 01, 00, 52, 01, 00, 77, 01, 00, 77, 01,
-00, C2, 01, 00, C2, 01, 00, 0D, 02, 00, 0D, 02, 00, 58, 02, 00, 58, 02, 00,
-EE, 02, 00, EE, 02, 00, 18, 35, 00, 00, 4B, 00, 00, 71, 00, 00, 96, 00, 00,
-96, 00, 00, 96, 00, 00, BC, 00, 00, BC, 00, 00, BC, 00, 00, BC, 00, 00, E1,
-00, 00, E1, 00, 00, 2C, 01, 00, 2C, 01, 00, 2C, 01, 00, 2C, 01, 00, 2C, 01,
-00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00,
-DC, 05, 00
+20, 02, 10, 01, A0, AF, 0C, 03, C0, 80, A0, 00, 03, 80, 80, A0, 00, 77, 08
 }
 
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
 # This section needs to be updated with the correct values based on the platform
-NXP_RF_CONF_BLK_4={
-20, 02, A4, 01, A0, A9, A0, 00, C1, 00, 0A, 01, 80, 41, 0A, 02, 81, 83, 0A,
-03, C0, 42, 06, 04, 80, 46, 06, 05, C3, 01, 03, 06, C2, 05, 03, 07, C2, 4A,
-03, 07, 81, 01, 01, 08, C3, 8B, 03, 08, C3, 05, 01, 09, C3, 92, 03, 09, C6,
-84, 01, 0A, C4, CC, 03, 0A, C6, 89, 01, 0B, C5, D4, 03, 0B, C7, 92, 01, 0C,
-44, 00, 03, 0C, C7, C6, 01, 0D, 42, 04, 03, 0D, C9, CE, 01, 0E, 42, 48, 03,
-0E, 03, 00, 01, 0F, 43, 50, 03, 0F, 43, 04, 01, 10, 43, 91, 03, 10, 45, 0A,
-01, 11, 44, 95, 03, 11, 46, 11, 01, 12, 46, 8E, 01, 13, 47, C5, 01, 14, 48,
-CC, 01, 15, 4B, D4, 01, 16, 4E, D7, 01, 17, 5E, A2, 01, 18, 5F, A6, 01, 19,
-5F, AE, 01, 1A, 60, B4, 01, 1B, 61, EA, 01, 1C, 62, F0, 01
-}
+#NXP_RF_CONF_BLK_4={
+#}
 
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
 # This section needs to be updated with the correct values based on the platform
-NXP_RF_CONF_BLK_5={
-20, 02, 5B, 01, A0, 0B, 57, ED, 0D, 90, 3F, 0F, 4E, 00, 53, 95, 00, 00, 53,
-9F, 00, 00, 6B, 9F, 00, 00, 78, 9F, 00, 00, 7A, 9F, 00, 00, 86, 9F, 00, 00,
-89, 9F, 00, 00, 95, 9F, 00, 00, 9A, 9F, 00, 00, A4, 9F, 00, 00, A6, 9F, 00,
-00, B3, 9F, 00, 00, B5, 9F, 00, 00, C1, 9F, 00, 00, C4, 1F, 00, 00, D0, 1F,
-00, 00, DA, 1F, 00, 00, E1, 1F, 00, 00, EE, 1F, 00, 00, FA, 1F, 00, 00
-}
+#NXP_RF_CONF_BLK_5={
+#}
 
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
@@ -155,22 +137,26 @@ NXP_RF_CONF_BLK_5={
 # SWP1A interface A0D4
 # DWP intf behavior config, SVDD Load activated by default if set to 0x31 A037
 # SPI CL Sync enable  A098
-NXP_CORE_CONF_EXTN={20, 02, 4A, 0F,
+NXP_CORE_CONF_EXTN={20, 02, 5B, 13,
     A0, EC, 01, 01,
     A0, ED, 01, 01,
     A0, 5E, 01, 01,
     A0, 12, 01, 02,
     A0, 40, 01, 01,
+    A0, 41, 01, 03,
+    A0, 43, 01, 50,
     A0, D1, 01, 02,
     A0, D4, 01, 00,
     A0, 37, 01, 35,
     A0, D8, 01, 02,
     A0, D5, 01, 0A,
     A0, 98, 01, 03,
-    A0, AA, 04, FD, 03, 2C, 01,
+    A0, 9C, 02, 00, 00,
+    A0, AA, 04, F1, 03, 2D, 01,
     A0, 38, 04, 14, 0B, 0B, 00,
-    A0, 3A, 08, B4, 00, B4, 00, B4, 00, B4, 00,
-    A0, B2, 01, 19
+    A0, 3A, 08, C3, 00, C3, 00, C3, 00, C3, 00,
+    A0, B2, 01, 19,
+    A0, 91, 01, 00
 }
 
 ###############################################################################
@@ -283,7 +269,7 @@ NFA_POLL_BAIL_OUT_MODE=0x01
 ###############################################################################
 # White list of Hosts
 # This values will be the Hosts(NFCEEs) in the HCI Network.
-DEVICE_HOST_WHITE_LIST={C0, 80}
+DEVICE_HOST_WHITE_LIST={C0, 02}
 
 ###############################################################################
 # Extended APDU length for ISO_DEP
@@ -302,7 +288,7 @@ PRESENCE_CHECK_ALGORITHM=2
 # destination gate (see NFA_HCI_DEFAULT_DEST_GATE).  Note there is a value
 # for each UICC (where F3="UICC0" and F4="UICC1")
 OFF_HOST_ESE_PIPE_ID=0x16
-OFF_HOST_SIM_PIPE_ID=0x70
+OFF_HOST_SIM_PIPE_ID=0x0A
 
 ###############################################################################
 #Set the Felica T3T System Code Power state :