363 files changed, 28670 insertions, 22521 deletions

diff --git a/.gitignore b/.gitignore
index 31160ad1..12303085 100644
--- a/.gitignore
+++ b/.gitignore
@@ -5,7 +5,6 @@
 *~
 *.d
 *.bin
-firmware/links
 *.napp
 # exclude IDE project files/directories
 .*
diff --git a/contexthubhal/Android.mk b/contexthubhal/Android.mk
index f5781616..2b9f0e49 100644
--- a/contexthubhal/Android.mk
+++ b/contexthubhal/Android.mk
@@ -14,6 +14,8 @@ LOCAL_MODULE_OWNER := google
 # Include target-specific files.
 LOCAL_SRC_FILES += nanohubhal_default.cpp
 
+LOCAL_STATIC_LIBRARIES += libnanohub_common
+
 LOCAL_MODULE := context_hub.default
 LOCAL_MODULE_TAGS := optional
 include $(BUILD_SHARED_LIBRARY)
diff --git a/contexthubhal/message_buf.h b/contexthubhal/message_buf.h
index 84866b6d..cc43579c 100644
--- a/contexthubhal/message_buf.h
+++ b/contexthubhal/message_buf.h
@@ -55,6 +55,7 @@ public:
         data = const_cast<char *>(buf);
         readOnly = true;
     }
+    void reset() { pos = 0; }
     const char *getData() const { return data; }
     size_t getSize() const { return size; }
     size_t getPos() const { return pos; }
diff --git a/contexthubhal/nanohubhal.cpp b/contexthubhal/nanohubhal.cpp
index d53a16c6..48ad40f3 100644
--- a/contexthubhal/nanohubhal.cpp
+++ b/contexthubhal/nanohubhal.cpp
@@ -18,7 +18,6 @@
 
 #include <fcntl.h>
 #include <poll.h>
-#include <pthread.h>
 #include <unistd.h>
 #include <sys/inotify.h>
 #include <sys/types.h>
@@ -30,6 +29,8 @@
 #include <utils/Log.h>
 #include <cutils/properties.h>
 
+#include <nanohub/nanohub.h>
+
 #include <cinttypes>
 #include <iomanip>
 #include <sstream>
@@ -145,17 +146,19 @@ static void wait_on_dev_lock(pollfd &pfd) {
     }
 }
 
-int NanoHub::doSendToDevice(const hub_app_name_t *name, const void *data, uint32_t len)
+int NanoHub::doSendToDevice(const hub_app_name_t *name, const void *data, uint32_t len, uint32_t messageType)
 {
-    if (len > MAX_RX_PACKET) {
+    if (len > MAX_RX_PACKET || name == nullptr) {
         return -EINVAL;
     }
 
-    nano_message msg = {
+    // transmit message to FW in CHRE format
+    nano_message_chre msg = {
         .hdr = {
-            .event_id = APP_FROM_HOST_EVENT_ID,
-            .app_name = *name,
+            .eventId = APP_FROM_HOST_CHRE_EVENT_ID,
+            .appId = name->id,
             .len = static_cast<uint8_t>(len),
+            .appEventId = messageType,
         },
     };
 
@@ -164,25 +167,32 @@ int NanoHub::doSendToDevice(const hub_app_name_t *name, const void *data, uint32
     return rwrite(mFd, &msg, len + sizeof(msg.hdr));
 }
 
-void NanoHub::doSendToApp(const hub_app_name_t *name, uint32_t typ, const void *data, uint32_t len)
+void NanoHub::doSendToApp(HubMessage &&msg)
 {
-    hub_message_t msg = {
-        .app_name = *name,
-        .message_type = typ,
-        .message_len = len,
-        .message = data,
-    };
-
-    mMsgCbkFunc(0, &msg, mMsgCbkData);
+    std::unique_lock<std::mutex> lk(mAppTxLock);
+    mAppTxQueue.push_back((HubMessage &&)msg);
+    lk.unlock();
+    mAppTxCond.notify_all();
 }
 
-void* NanoHub::run(void *data)
+void* NanoHub::runAppTx()
 {
-    NanoHub *self = static_cast<NanoHub*>(data);
-    return self->doRun();
+    std::unique_lock<std::mutex> lk(mAppTxLock);
+    while(true) {
+        mAppTxCond.wait(lk, [this] { return !mAppTxQueue.empty() || mAppQuit; });
+        if (mAppQuit) {
+            break;
+        }
+        HubMessage &m = mAppTxQueue.front();
+        lk.unlock();
+        mMsgCbkFunc(0, &m, mMsgCbkData);
+        lk.lock();
+        mAppTxQueue.pop_front();
+    };
+    return NULL;
 }
 
-void* NanoHub::doRun()
+void* NanoHub::runDeviceRx()
 {
     enum {
         IDX_NANOHUB,
@@ -236,6 +246,7 @@ void* NanoHub::doRun()
                 break;
             }
 
+            // receive message from FW in legacy format
             if (ret != (int)(sizeof(msg.hdr) + len)) {
                 ALOGE("Expected %zu bytes, read %d bytes", sizeof(msg.hdr) + len, ret);
                 break;
@@ -245,10 +256,11 @@ void* NanoHub::doRun()
             if (ret < 0) {
                 ALOGE("SystemComm::handleRx() returned %d", ret);
             } else if (ret) {
+                hub_app_name_t app_name = { .id = msg.hdr.appId };
                 if (messageTracingEnabled()) {
-                    dumpBuffer("DEV -> APP", msg.hdr.app_name, msg.hdr.event_id, &msg.data[0], msg.hdr.len);
+                    dumpBuffer("DEV -> APP", app_name, msg.hdr.eventId, &msg.data[0], msg.hdr.len);
                 }
-                doSendToApp(&msg.hdr.app_name, msg.hdr.event_id, &msg.data[0], msg.hdr.len);
+                doSendToApp(HubMessage(&app_name, msg.hdr.eventId, &msg.data[0], msg.hdr.len));
             }
         }
 
@@ -279,18 +291,10 @@ int NanoHub::openHub()
         goto fail_pipe;
     }
 
-    if (pthread_create(&mWorkerThread, NULL, &NanoHub::run, this)) {
-        ALOGE("failed to spawn worker thread");
-        ret = -errno;
-        goto fail_thread;
-    }
-
+    mPollThread = std::thread([this] { runDeviceRx(); });
+    mAppThread = std::thread([this] { runAppTx(); });
     return 0;
 
-fail_thread:
-    close(mThreadClosingPipe[0]);
-    close(mThreadClosingPipe[1]);
-
 fail_pipe:
     close(mFd);
 
@@ -302,15 +306,32 @@ int NanoHub::closeHub(void)
 {
     char zero = 0;
 
-    //signal
-    while(write(mThreadClosingPipe[1], &zero, 1) != 1);
+    // stop mPollThread
+    while(write(mThreadClosingPipe[1], &zero, 1) != 1) {
+        continue;
+    }
+
+    // stop mAppThread
+    {
+        std::unique_lock<std::mutex> lk(mAppTxLock);
+        mAppQuit = true;
+        lk.unlock();
+        mAppTxCond.notify_all();
+    }
 
     //wait
-    (void)pthread_join(mWorkerThread, NULL);
+    if (mPollThread.joinable()) {
+        mPollThread.join();
+    }
 
+    //wait
+    if (mAppThread.joinable()) {
+        mAppThread.join();
+    }
     //cleanup
     ::close(mThreadClosingPipe[0]);
     ::close(mThreadClosingPipe[1]);
+    ::close(mFd);
 
     reset();
 
@@ -323,7 +344,7 @@ int NanoHub::doSubscribeMessages(uint32_t hub_id, context_hub_callback *cbk, voi
         return -ENODEV;
     }
 
-    Mutex::Autolock _l(mLock);
+    std::lock_guard<std::mutex> _l(mLock);
     int ret = 0;
 
     if (!mMsgCbkFunc && !cbk) { //we're off and staying off - do nothing
@@ -356,7 +377,7 @@ int NanoHub::doSendToNanohub(uint32_t hub_id, const hub_message_t *msg)
     }
 
     int ret = 0;
-    Mutex::Autolock _l(mLock);
+    std::lock_guard<std::mutex> _l(mLock);
 
     if (!mMsgCbkFunc) {
         ALOGW("refusing to send a message when nobody around to get a reply!");
@@ -371,14 +392,14 @@ int NanoHub::doSendToNanohub(uint32_t hub_id, const hub_message_t *msg)
                 dumpBuffer("APP -> HAL", msg->app_name, msg->message_type, msg->message, msg->message_len);
             }
             ret = SystemComm::handleTx(msg);
-        } else if (msg->message_type || msg->message_len > MAX_RX_PACKET) {
+        } else if (msg->message_len > MAX_RX_PACKET) {
             ALOGW("not sending invalid message 2");
             ret = -EINVAL;
         } else {
             if (messageTracingEnabled()) {
-                dumpBuffer("APP -> DEV", msg->app_name, 0, msg->message, msg->message_len);
+                dumpBuffer("APP -> DEV", msg->app_name, msg->message_type, msg->message, msg->message_len);
             }
-            ret = doSendToDevice(&msg->app_name, msg->message, msg->message_len);
+            ret = doSendToDevice(&msg->app_name, msg->message, msg->message_len, msg->message_type);
         }
     }
 
diff --git a/contexthubhal/nanohubhal.h b/contexthubhal/nanohubhal.h
index 9014a5e7..20e8f727 100644
--- a/contexthubhal/nanohubhal.h
+++ b/contexthubhal/nanohubhal.h
@@ -17,16 +17,18 @@
 #ifndef _NANOHUB_HAL_H_
 #define _NANOHUB_HAL_H_
 
-#include <pthread.h>
+#include <mutex>
+#include <thread>
+#include <list>
 
 #include <hardware/context_hub.h>
-#include <utils/Mutex.h>
 
-#define NANOAPP_VENDOR_GOOGLE NANOAPP_VENDOR("Googl")
+#include <nanohub/nanohub.h>
 
 //as per protocol
-#define MAX_RX_PACKET           128
-#define APP_FROM_HOST_EVENT_ID  0x000000F8
+#define MAX_RX_PACKET               128
+#define APP_FROM_HOST_EVENT_ID      0x000000F8
+#define APP_FROM_HOST_CHRE_EVENT_ID 0x000000F9
 
 namespace android {
 
@@ -34,24 +36,59 @@ namespace nanohub {
 
 void dumpBuffer(const char *pfx, const hub_app_name_t &appId, uint32_t evtId, const void *data, size_t len, int status = 0);
 
-struct nano_message_hdr {
-    uint32_t event_id;
-    hub_app_name_t app_name;
-    uint8_t len;
+struct nano_message_chre {
+    HostMsgHdrChre hdr;
+    uint8_t data[MAX_RX_PACKET];
 } __attribute__((packed));
 
 struct nano_message {
-    nano_message_hdr hdr;
+    HostMsgHdr hdr;
     uint8_t data[MAX_RX_PACKET];
 } __attribute__((packed));
 
+class HubMessage : public hub_message_t {
+    std::unique_ptr<uint8_t> data_;
+public:
+    HubMessage(const HubMessage &other) = delete;
+    HubMessage &operator = (const HubMessage &other) = delete;
+
+    HubMessage(const hub_app_name_t *name, uint32_t typ, const void *data, uint32_t len) {
+        app_name = *name;
+        message_type = typ;
+        message_len = len;
+        message = data;
+        if (len > 0 && data != nullptr) {
+            data_ = std::unique_ptr<uint8_t>(new uint8_t[len]);
+            memcpy(data_.get(), data, len);
+            message = data_.get();
+        }
+    }
+
+    HubMessage(HubMessage &&other) {
+        *this = (HubMessage &&)other;
+    }
+
+    HubMessage &operator = (HubMessage &&other) {
+        *static_cast<hub_message_t *>(this) = static_cast<hub_message_t>(other);
+        data_ = std::move(other.data_);
+        other.message = nullptr;
+        other.message_len = 0;
+        return *this;
+    }
+};
+
 class NanoHub {
-    Mutex mLock;
+    std::mutex mLock;
+    bool mAppQuit;
+    std::mutex mAppTxLock;
+    std::condition_variable mAppTxCond;
+    std::list<HubMessage> mAppTxQueue;
+    std::thread mPollThread;
+    std::thread mAppThread;
     context_hub_callback *mMsgCbkFunc;
     int mThreadClosingPipe[2];
     int mFd; // [0] is read end
     void * mMsgCbkData;
-    pthread_t mWorkerThread;
 
     NanoHub() {
         reset();
@@ -63,11 +100,11 @@ class NanoHub {
         mFd = -1;
         mMsgCbkData = nullptr;
         mMsgCbkFunc = nullptr;
-        mWorkerThread = 0;
+        mAppQuit = false;
     }
 
-    static void* run(void *);
-    void* doRun();
+    void* runAppTx();
+    void* runDeviceRx();
 
     int openHub();
     int closeHub();
@@ -79,8 +116,8 @@ class NanoHub {
 
     int doSubscribeMessages(uint32_t hub_id, context_hub_callback *cbk, void *cookie);
     int doSendToNanohub(uint32_t hub_id, const hub_message_t *msg);
-    int doSendToDevice(const hub_app_name_t *name, const void *data, uint32_t len);
-    void doSendToApp(const hub_app_name_t *name, uint32_t typ, const void *data, uint32_t len);
+    int doSendToDevice(const hub_app_name_t *name, const void *data, uint32_t len, uint32_t messageType);
+    void doSendToApp(HubMessage &&msg);
 
     static constexpr unsigned int FL_MESSAGE_TRACING = 1;
 
@@ -112,11 +149,11 @@ public:
     }
     // passes message to kernel driver directly
     static int sendToDevice(const hub_app_name_t *name, const void *data, uint32_t len) {
-        return hubInstance()->doSendToDevice(name, data, len);
+        return hubInstance()->doSendToDevice(name, data, len, 0);
     }
     // passes message to APP via callback
-    static void sendToApp(const hub_app_name_t *name, uint32_t typ, const void *data, uint32_t len) {
-        hubInstance()->doSendToApp(name, typ, data, len);
+    static void sendToApp(HubMessage &&msg) {
+        hubInstance()->doSendToApp((HubMessage &&)msg);
     }
 };
 
diff --git a/contexthubhal/system_comms.cpp b/contexthubhal/system_comms.cpp
index 41afc837..c4e9b621 100644
--- a/contexthubhal/system_comms.cpp
+++ b/contexthubhal/system_comms.cpp
@@ -37,15 +37,18 @@ namespace android {
 
 namespace nanohub {
 
-static void readAppName(MessageBuf &buf, hub_app_name_t &name) {
+static void readAppName(MessageBuf &buf, hub_app_name_t &name)
+{
     name.id = buf.readU64();
 }
 
-static void writeAppName(MessageBuf &buf, const hub_app_name_t &name) {
+static void writeAppName(MessageBuf &buf, const hub_app_name_t &name)
+{
     buf.writeU64(name.id);
 }
 
-static void readNanohubAppInfo(MessageBuf &buf, NanohubAppInfo &info) {
+static void readNanohubAppInfo(MessageBuf &buf, NanohubAppInfo &info)
+{
     size_t pos = buf.getPos();
     readAppName(buf, info.name);
     info.version = buf.readU32();
@@ -56,7 +59,8 @@ static void readNanohubAppInfo(MessageBuf &buf, NanohubAppInfo &info) {
     }
 }
 
-static void readNanohubMemInfo(MessageBuf &buf,  NanohubMemInfo &mi) {
+static void readNanohubMemInfo(MessageBuf &buf,  NanohubMemInfo &mi)
+{
     size_t pos = buf.getPos();
     mi.flashSz = buf.readU32();
     mi.blSz = buf.readU32();
@@ -75,9 +79,11 @@ static void readNanohubMemInfo(MessageBuf &buf,  NanohubMemInfo &mi) {
     }
 }
 
-NanohubRsp::NanohubRsp(MessageBuf &buf, bool no_status) {
+NanohubRsp::NanohubRsp(MessageBuf &buf, bool no_status)
+{
     // all responses start with command
     // most of them have 4-byte status (result code)
+    buf.reset();
     cmd = buf.readU8();
     if (!buf.getSize()) {
         status = -EINVAL;
@@ -88,15 +94,17 @@ NanohubRsp::NanohubRsp(MessageBuf &buf, bool no_status) {
     }
 }
 
-int SystemComm::sendToSystem(const void *data, size_t len) {
+int SystemComm::sendToSystem(const void *data, size_t len)
+{
     if (NanoHub::messageTracingEnabled()) {
         dumpBuffer("HAL -> SYS", getSystem()->mHostIfAppName, 0, data, len);
     }
     return NanoHub::sendToDevice(&getSystem()->mHostIfAppName, data, len);
 }
 
-int SystemComm::AppInfoSession::setup(const hub_message_t *) {
-    Mutex::Autolock _l(mLock);
+int SystemComm::AppInfoSession::setup(const hub_message_t *)
+{
+    std::lock_guard<std::mutex> _l(mLock);
     int suggestedSize = mAppInfo.size() ? mAppInfo.size() : 20;
 
     mAppInfo.clear();
@@ -106,19 +114,21 @@ int SystemComm::AppInfoSession::setup(const hub_message_t *) {
     return requestNext();
 }
 
-inline hub_app_name_t deviceAppNameToHost(const hub_app_name_t src) {
+inline hub_app_name_t deviceAppNameToHost(const hub_app_name_t src)
+{
     hub_app_name_t res = { .id = le64toh(src.id) };
     return res;
 }
 
-inline hub_app_name_t hostAppNameToDevice(const hub_app_name_t src) {
+inline hub_app_name_t hostAppNameToDevice(const hub_app_name_t src)
+{
     hub_app_name_t res = { .id = htole64(src.id) };
     return res;
 }
 
 int SystemComm::AppInfoSession::handleRx(MessageBuf &buf)
 {
-    Mutex::Autolock _l(mLock);
+    std::lock_guard<std::mutex> _l(mLock);
 
     NanohubRsp rsp(buf, true);
     if (rsp.cmd != NANOHUB_QUERY_APPS) {
@@ -174,32 +184,9 @@ int SystemComm::AppInfoSession::requestNext()
     return sendToSystem(buf.getData(), buf.getPos());
 }
 
-int SystemComm::GlobalSession::setup(const hub_message_t *) {
-    Mutex::Autolock _l(mLock);
-
-    setState(SESSION_USER);
-
-    return 0;
-}
-
-int SystemComm::GlobalSession::handleRx(MessageBuf &buf)
-{
-    Mutex::Autolock _l(mLock);
-
-    NanohubRsp rsp(buf);
-    if (rsp.cmd != NANOHUB_REBOOT) {
-        return 1;
-    }
-
-    ALOGW("Nanohub reboot status [UNSOLICITED]: %08" PRIX32, rsp.status);
-    sendToApp(CONTEXT_HUB_OS_REBOOT, &rsp.status, sizeof(rsp.status));
-
-    return 0;
-}
-
 int SystemComm::MemInfoSession::setup(const hub_message_t *)
 {
-    Mutex::Autolock _l(mLock);
+    std::lock_guard<std::mutex> _l(mLock);
     char data[MAX_RX_PACKET];
     MessageBuf buf(data, sizeof(data));
     buf.writeU8(NANOHUB_QUERY_MEMINFO);
@@ -210,7 +197,7 @@ int SystemComm::MemInfoSession::setup(const hub_message_t *)
 
 int SystemComm::MemInfoSession::handleRx(MessageBuf &buf)
 {
-    Mutex::Autolock _l(mLock);
+    std::lock_guard<std::mutex> _l(mLock);
     NanohubRsp rsp(buf, true);
 
     if (rsp.cmd != NANOHUB_QUERY_MEMINFO)
@@ -277,7 +264,7 @@ int SystemComm::MemInfoSession::handleRx(MessageBuf &buf)
 
 int SystemComm::AppMgmtSession::setup(const hub_message_t *appMsg)
 {
-    Mutex::Autolock _l(mLock);
+    std::lock_guard<std::mutex> _l(mLock);
 
     char data[MAX_RX_PACKET];
     MessageBuf buf(data, sizeof(data));
@@ -294,16 +281,23 @@ int SystemComm::AppMgmtSession::setup(const hub_message_t *appMsg)
         return setupMgmt(appMsg, NANOHUB_EXT_APPS_OFF);
     case  CONTEXT_HUB_UNLOAD_APP:
         return setupMgmt(appMsg, NANOHUB_EXT_APP_DELETE);
-    case  CONTEXT_HUB_LOAD_OS:
     case  CONTEXT_HUB_LOAD_APP:
+    {
         mData.clear();
         mData = std::vector<uint8_t>(msgData, msgData + mLen);
+        const load_app_request_t *appReq = static_cast<const load_app_request_t*>(appMsg->message);
+        if (appReq == nullptr || mLen <= sizeof(*appReq)) {
+            ALOGE("%s: Invalid app header: too short\n", __func__);
+            return -EINVAL;
+        }
+        mAppName = appReq->app_binary.app_id;
         setState(TRANSFER);
 
         buf.writeU8(NANOHUB_START_UPLOAD);
-        buf.writeU8(mCmd == CONTEXT_HUB_LOAD_OS ? 1 : 0);
+        buf.writeU8(0);
         buf.writeU32(mLen);
         return sendToSystem(buf.getData(), buf.getPos());
+    }
 
     case  CONTEXT_HUB_OS_REBOOT:
         setState(REBOOT);
@@ -333,7 +327,7 @@ int SystemComm::AppMgmtSession::setupMgmt(const hub_message_t *appMsg, uint32_t
 int SystemComm::AppMgmtSession::handleRx(MessageBuf &buf)
 {
     int ret = 0;
-    Mutex::Autolock _l(mLock);
+    std::lock_guard<std::mutex> _l(mLock);
     NanohubRsp rsp(buf);
 
     switch (getState()) {
@@ -343,8 +337,11 @@ int SystemComm::AppMgmtSession::handleRx(MessageBuf &buf)
     case FINISH:
         ret = handleFinish(rsp);
         break;
-    case RELOAD:
-        ret = handleReload(rsp);
+    case RUN:
+        ret = handleRun(rsp);
+        break;
+    case RUN_FAILED:
+        ret = handleRunFailed(rsp);
         break;
     case REBOOT:
         ret = handleReboot(rsp);
@@ -399,9 +396,9 @@ int SystemComm::AppMgmtSession::handleFinish(NanohubRsp &rsp)
     if (success) {
         char data[MAX_RX_PACKET];
         MessageBuf buf(data, sizeof(data));
-        // until app header is passed, we don't know who to start, so we reboot
-        buf.writeU8(NANOHUB_REBOOT);
-        setState(RELOAD);
+        buf.writeU8(NANOHUB_EXT_APPS_ON);
+        writeAppName(buf, mAppName);
+        setState(RUN);
         ret = sendToSystem(buf.getData(), buf.getPos());
     } else {
         int32_t result = NANOHUB_APP_NOT_LOADED;
@@ -413,22 +410,48 @@ int SystemComm::AppMgmtSession::handleFinish(NanohubRsp &rsp)
     return ret;
 }
 
-/* reboot notification, when triggered as part of App reload sequence */
-int SystemComm::AppMgmtSession::handleReload(NanohubRsp &rsp)
+int SystemComm::AppMgmtSession::handleRun(NanohubRsp &rsp)
 {
-    int32_t result = NANOHUB_APP_LOADED;
+    if (rsp.cmd != NANOHUB_EXT_APPS_ON)
+        return 1;
+
+    MgmtStatus sts = { .value = (uint32_t)rsp.status };
 
-    ALOGI("Nanohub reboot status [NEW APP START]: %08" PRIX32, rsp.status);
+    // op counter returns number of nanoapps that were started as result of the command
+    // for successful start command it must be > 0
+    int32_t result = sts.value > 0 && sts.op > 0 && sts.op <= 0x7F ? 0 : -1;
 
+    ALOGI("Nanohub NEW APP START: %08" PRIX32 "\n", rsp.status);
+    if (result != 0) {
+        // if nanoapp failed to start we have to unload it
+        char data[MAX_RX_PACKET];
+        MessageBuf buf(data, sizeof(data));
+        buf.writeU8(NANOHUB_EXT_APP_DELETE);
+        writeAppName(buf, mAppName);
+        if (sendToSystem(buf.getData(), buf.getPos()) == 0) {
+            setState(RUN_FAILED);
+            return 0;
+        }
+        ALOGE("%s: failed to send DELETE for failed app\n", __func__);
+    }
+
+    // it is either success, and we report it, or
+    // it is a failure to load, and also failure to send erase command
     sendToApp(mCmd, &result, sizeof(result));
+    complete();
+    return 0;
+}
+
+int SystemComm::AppMgmtSession::handleRunFailed(NanohubRsp &rsp)
+{
+    if (rsp.cmd != NANOHUB_EXT_APP_DELETE)
+        return 1;
+
+    int32_t result = -1;
 
-    // in addition to sending response to the CONTEXT_HUB_LOAD_APP command,
-    // we should send unsolicited reboot notification;
-    // I choose to do it here rather than delegate it to global session
-    // because I want the log to clearly differentiate between UNSOLICITED reboots
-    // (meaning FW faults) and REQUESTED reboots.
-    sendToApp(CONTEXT_HUB_OS_REBOOT, &rsp.status, sizeof(rsp.status));
+    ALOGI("%s: APP DELETE [because it failed]: %08" PRIX32 "\n", __func__, rsp.status);
 
+    sendToApp(mCmd, &result, sizeof(result));
     complete();
 
     return 0;
@@ -437,9 +460,11 @@ int SystemComm::AppMgmtSession::handleReload(NanohubRsp &rsp)
 /* reboot notification, when triggered by App request */
 int SystemComm::AppMgmtSession::handleReboot(NanohubRsp &rsp)
 {
-    ALOGI("Nanohub reboot status [USER REQ]: %08" PRIX32, rsp.status);
+    if (rsp.cmd != NANOHUB_REBOOT)
+        return 1;
+    ALOGI("Nanohub reboot status [USER REQ]: %08" PRIX32 "\n", rsp.status);
 
-    sendToApp(mCmd, &rsp.status, sizeof(rsp.status));
+    // reboot notification is sent by SessionManager
     complete();
 
     return 0;
@@ -447,10 +472,18 @@ int SystemComm::AppMgmtSession::handleReboot(NanohubRsp &rsp)
 
 int SystemComm::AppMgmtSession::handleMgmt(NanohubRsp &rsp)
 {
-    Mutex::Autolock _l(mLock);
     bool valid = false;
 
-    ALOGI("Nanohub MGMT response: CMD=%02X; STATUS=%08" PRIX32, rsp.cmd, rsp.status);
+    int32_t result = rsp.status;
+
+    // TODO: remove this when context hub service can handle non-zero success status
+    if (result > 0) {
+        // something happened; assume it worked
+        result = 0;
+    } else if (result == 0) {
+        // nothing happened; this is provably an error
+        result = -1;
+    }
 
     switch (rsp.cmd) {
     case NANOHUB_EXT_APPS_OFF:
@@ -466,19 +499,20 @@ int SystemComm::AppMgmtSession::handleMgmt(NanohubRsp &rsp)
         return 1;
     }
 
+    ALOGI("Nanohub MGMT response: CMD=%02X; STATUS=%08" PRIX32, rsp.cmd, rsp.status);
     if (!valid) {
         ALOGE("Invalid response for this state: APP CMD=%02X", mCmd);
         return -EINVAL;
     }
 
-    sendToApp(mCmd, &rsp.status, sizeof(rsp.status));
+    sendToApp(mCmd, &result, sizeof(result));
     complete();
 
     return 0;
 }
 
 int SystemComm::KeyInfoSession::setup(const hub_message_t *) {
-    Mutex::Autolock _l(mLock);
+    std::lock_guard<std::mutex> _l(mLock);
     mRsaKeyData.clear();
     setState(SESSION_USER);
     mStatus = -EBUSY;
@@ -487,7 +521,7 @@ int SystemComm::KeyInfoSession::setup(const hub_message_t *) {
 
 int SystemComm::KeyInfoSession::handleRx(MessageBuf &buf)
 {
-    Mutex::Autolock _l(mLock);
+    std::lock_guard<std::mutex> _l(mLock);
     NanohubRsp rsp(buf, true);
 
     if (getState() != SESSION_USER) {
@@ -522,7 +556,7 @@ int SystemComm::KeyInfoSession::requestRsaKeys(void)
 int SystemComm::doHandleRx(const nano_message *msg)
 {
     //we only care for messages from HostIF
-    if (msg->hdr.app_name != mHostIfAppName)
+    if (msg->hdr.appId != mHostIfAppName.id)
         return 1;
 
     //they must all be at least 1 byte long
@@ -547,24 +581,64 @@ int SystemComm::doHandleRx(const nano_message *msg)
 int SystemComm::SessionManager::handleRx(MessageBuf &buf)
 {
     int status = 1;
+    std::unique_lock<std::mutex> lk(lock);
 
     // pass message to all active sessions, in arbitrary order
     // 1st session that handles the message terminates the loop
-    for (auto pos = sessions_.begin();
-         pos != sessions_.end() && status > 0; next(pos)) {
+    for (auto pos = sessions_.begin(); pos != sessions_.end() && status > 0; next(pos)) {
+        if (!isActive(pos)) {
+            continue;
+        }
         Session *session = pos->second;
         status = session->handleRx(buf);
         if (status < 0) {
             session->complete();
         }
     }
-    if (status > 0) {
-        status = mGlobal.handleRx(buf);
+
+    NanohubRsp rsp(buf);
+    if (rsp.cmd == NANOHUB_REBOOT) {
+        // if this is reboot notification, kill all sessions
+        for (auto pos = sessions_.begin(); pos != sessions_.end(); next(pos)) {
+            if (!isActive(pos)) {
+                continue;
+            }
+            Session *session = pos->second;
+            session->abort(-EINTR);
+        }
+        lk.unlock();
+        // log the reboot event, if not handled
+        if (status > 0) {
+            ALOGW("Nanohub reboot status [UNSOLICITED]: %08" PRIX32, rsp.status);
+            status = 0;
+        }
+        // report to java apps
+        sendToApp(CONTEXT_HUB_OS_REBOOT, &rsp.status, sizeof(rsp.status));
     }
 
     return status;
 }
 
+int SystemComm::SessionManager::setup_and_add(int id, Session *session, const hub_message_t *appMsg)
+{
+    std::lock_guard<std::mutex> _l(lock);
+
+    // scan sessions to release those that are already done
+    for (auto pos = sessions_.begin(); pos != sessions_.end(); next(pos)) {
+        continue;
+    }
+
+    if (sessions_.count(id) == 0 && !session->isRunning()) {
+        sessions_[id] = session;
+        int ret = session->setup(appMsg);
+        if (ret < 0) {
+            session->complete();
+        }
+        return ret;
+    }
+    return -EBUSY;
+}
+
 int SystemComm::doHandleTx(const hub_message_t *appMsg)
 {
     int status = 0;
diff --git a/contexthubhal/system_comms.h b/contexthubhal/system_comms.h
index a21aee75..e1b08e3e 100644
--- a/contexthubhal/system_comms.h
+++ b/contexthubhal/system_comms.h
@@ -18,12 +18,15 @@
 #define _NANOHUB_SYSTEM_COMMS_H_
 
 #include <utils/Condition.h>
-#include <utils/Mutex.h>
 
+#include <condition_variable>
 #include <map>
+#include <mutex>
 #include <vector>
 
 #include <hardware/context_hub.h>
+#include <nanohub/nanohub.h>
+
 #include "nanohubhal.h"
 #include "message_buf.h"
 
@@ -43,10 +46,6 @@
 #define NANOHUB_FINISH_UPLOAD      8 // () -> (char success)
 #define NANOHUB_REBOOT             9 // () -> (char success)
 
-// Custom defined private messages
-#define CONTEXT_HUB_LOAD_OS (CONTEXT_HUB_TYPE_PRIVATE_MSG_BASE + 1)
-
-
 #define NANOHUB_APP_NOT_LOADED  (-1)
 #define NANOHUB_APP_LOADED      (0)
 
@@ -65,6 +64,18 @@ struct NanohubAppInfo {
     uint32_t version, flashUse, ramUse;
 } __attribute__((packed));
 
+struct MgmtStatus {
+    union {
+        uint32_t value;
+        struct {
+            uint8_t app;
+            uint8_t task;
+            uint8_t op;
+            uint8_t erase;
+        } __attribute__((packed));
+    };
+} __attribute__((packed));
+
 struct NanohubMemInfo {
     //sizes
     uint32_t flashSz, blSz, osSz, sharedSz, eeSz;
@@ -110,6 +121,7 @@ private:
         virtual int handleRx(MessageBuf &buf) = 0;
         virtual int getState() const = 0; // FSM state
         virtual int getStatus() const = 0; // execution status (result code)
+        virtual void abort(int32_t) = 0;
         virtual ~ISession() {}
     };
 
@@ -118,12 +130,12 @@ private:
     class Session : public ISession {
         friend class SessionManager;
 
-        mutable Mutex mDoneLock; // controls condition and state transitions
-        Condition mDoneWait;
+        mutable std::mutex mDoneMutex; // controls condition and state transitions
+        std::condition_variable mDoneCond;
         volatile int mState;
 
     protected:
-        mutable Mutex mLock; // serializes message handling
+        mutable std::mutex mLock; // serializes message handling
         int32_t mStatus;
 
         enum {
@@ -133,43 +145,47 @@ private:
         };
 
         void complete() {
-            Mutex::Autolock _l(mDoneLock);
+            std::unique_lock<std::mutex> lk(mDoneMutex);
             if (mState != SESSION_DONE) {
                 mState = SESSION_DONE;
-                mDoneWait.broadcast();
+                lk.unlock();
+                mDoneCond.notify_all();
             }
         }
+        void abort(int32_t status) {
+            std::lock_guard<std::mutex> _l(mLock);
+            mStatus = status;
+            complete();
+        }
         void setState(int state) {
             if (state == SESSION_DONE) {
                 complete();
             } else {
-                Mutex::Autolock _l(mDoneLock);
+                std::lock_guard<std::mutex> _l(mDoneMutex);
                 mState = state;
             }
         }
     public:
         Session() { mState = SESSION_INIT; mStatus = -1; }
         int getStatus() const {
-            Mutex::Autolock _l(mLock);
+            std::lock_guard<std::mutex> _l(mLock);
             return mStatus;
         }
         int wait() {
-            Mutex::Autolock _l(mDoneLock);
-            while (mState != SESSION_DONE) {
-                mDoneWait.wait(mDoneLock);
-            }
+            std::unique_lock<std::mutex> lk(mDoneMutex);
+            mDoneCond.wait(lk, [this] { return mState == SESSION_DONE; });
             return 0;
         }
         virtual int getState() const override {
-            Mutex::Autolock _l(mDoneLock);
+            std::lock_guard<std::mutex> _l(mDoneMutex);
             return mState;
         }
         virtual bool isDone() const {
-            Mutex::Autolock _l(mDoneLock);
+            std::lock_guard<std::mutex> _l(mDoneMutex);
             return mState == SESSION_DONE;
         }
         virtual bool isRunning() const {
-            Mutex::Autolock _l(mDoneLock);
+            std::lock_guard<std::mutex> _l(mDoneMutex);
             return mState > SESSION_DONE;
         }
     };
@@ -178,20 +194,23 @@ private:
         enum {
             TRANSFER = SESSION_USER,
             FINISH,
-            RELOAD,
+            RUN,
+            RUN_FAILED,
             REBOOT,
             MGMT,
         };
-        uint32_t mCmd; // UPLOAD_APP | UPPLOAD_OS
+        uint32_t mCmd; // LOAD_APP, UNLOAD_APP, ENABLE_APP, DISABLE_APP
         uint32_t mResult;
         std::vector<uint8_t> mData;
         uint32_t mLen;
         uint32_t mPos;
+        hub_app_name_t mAppName;
 
         int setupMgmt(const hub_message_t *appMsg, uint32_t cmd);
         int handleTransfer(NanohubRsp &rsp);
         int handleFinish(NanohubRsp &rsp);
-        int handleReload(NanohubRsp &rsp);
+        int handleRun(NanohubRsp &rsp);
+        int handleRunFailed(NanohubRsp &rsp);
         int handleReboot(NanohubRsp &rsp);
         int handleMgmt(NanohubRsp &rsp);
     public:
@@ -200,6 +219,7 @@ private:
             mResult = 0;
             mPos = 0;
             mLen = 0;
+            memset(&mAppName, 0, sizeof(mAppName));
         }
         virtual int handleRx(MessageBuf &buf) override;
         virtual int setup(const hub_message_t *app_msg) override;
@@ -218,7 +238,7 @@ private:
         virtual int setup(const hub_message_t *) override;
         virtual int handleRx(MessageBuf &buf) override;
         bool haveKeys() const {
-            Mutex::Autolock _l(mLock);
+            std::lock_guard<std::mutex> _l(mLock);
             return mRsaKeyData.size() > 0 && !isRunning();
         }
     };
@@ -231,48 +251,28 @@ private:
         virtual int handleRx(MessageBuf &buf) override;
     };
 
-    class GlobalSession : public Session {
-    public:
-        virtual int setup(const hub_message_t *) override;
-        virtual int handleRx(MessageBuf &buf) override;
-    };
-
     class SessionManager {
         typedef std::map<int, Session* > SessionMap;
 
-        Mutex lock;
+        std::mutex lock;
         SessionMap sessions_;
-        GlobalSession mGlobal;
 
+        bool isActive(const SessionMap::iterator &pos) const
+        {
+            return !pos->second->isDone();
+        }
         void next(SessionMap::iterator &pos)
         {
-            Mutex::Autolock _l(lock);
-            pos->second->isDone() ? pos = sessions_.erase(pos) : ++pos;
+            isActive(pos) ? pos++ : pos = sessions_.erase(pos);
         }
 
     public:
-        SessionManager() {
-            mGlobal.setup(nullptr);
-        }
         int handleRx(MessageBuf &buf);
-        int setup_and_add(int id, Session *session, const hub_message_t *appMsg) {
-            Mutex::Autolock _l(lock);
-            if (sessions_.count(id) == 0 && !session->isRunning()) {
-                int ret = session->setup(appMsg);
-                if (ret < 0) {
-                    session->complete();
-                } else {
-                    sessions_[id] = session;
-                }
-                return ret;
-            }
-            return -EBUSY;
-        }
-
+        int setup_and_add(int id, Session *session, const hub_message_t *appMsg);
     } mSessions;
 
     const hub_app_name_t mHostIfAppName = {
-        .id = NANO_APP_ID(NANOAPP_VENDOR_GOOGLE, 0)
+        .id = APP_ID_MAKE(NANOHUB_VENDOR_GOOGLE, 0)
     };
 
     static SystemComm *getSystem() {
@@ -291,7 +291,7 @@ private:
         if (NanoHub::messageTracingEnabled()) {
             dumpBuffer("HAL -> APP", get_hub_info()->os_app_name, typ, data, len);
         }
-        NanoHub::sendToApp(&get_hub_info()->os_app_name, typ, data, len);
+        NanoHub::sendToApp(HubMessage(&get_hub_info()->os_app_name, typ, data, len));
     }
     static int sendToSystem(const void *data, size_t len);
 
diff --git a/contexthubhal/test/Android.mk b/contexthubhal/test/Android.mk
new file mode 100644
index 00000000..44d2744e
--- /dev/null
+++ b/contexthubhal/test/Android.mk
@@ -0,0 +1,48 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_PATH := $(call my-dir)
+
+include $(CLEAR_VARS)
+
+
+LOCAL_SRC_FILES := main.cpp \
+        ../../lib/nanohub/nanoapp.c \
+
+
+LOCAL_CFLAGS := \
+        -Wall \
+        -Werror \
+        -Wextra \
+        -DHOST_BUILD \
+        -DBOOTLOADER= \
+        -DBOOTLOADER_RO= \
+
+
+LOCAL_C_INCLUDES := \
+        device/google/contexthub/lib/include \
+        hardware/libhardware/include \
+
+LOCAL_SHARED_LIBRARIES := \
+        libhardware \
+        liblog \
+        libcutils \
+
+LOCAL_MODULE := nanohub_hal_test
+
+LOCAL_MODULE_TAGS := optional
+
+include $(BUILD_EXECUTABLE)
diff --git a/contexthubhal/test/main.cpp b/contexthubhal/test/main.cpp
new file mode 100644
index 00000000..fe21e998
--- /dev/null
+++ b/contexthubhal/test/main.cpp
@@ -0,0 +1,325 @@
+#define LOG_TAG "NanohubHAL_Test"
+
+#include <cstddef>
+#include <cstdint>
+#include <functional>
+#include <iostream>
+#include <iomanip>
+#include <map>
+#include <memory>
+#include <cstddef>
+#include <cstdint>
+#include <mutex>
+#include <vector>
+
+#include <dlfcn.h>
+#include <signal.h>
+#include <unistd.h>
+
+#include <sys/endian.h>
+#include <utils/Log.h>
+
+#include <hardware/hardware.h>
+#include <hardware/context_hub.h>
+#include <nanohub/nanoapp.h>
+
+inline std::ostream &operator << (std::ostream &os, const hub_app_name_t &appId)
+{
+    char vendor[6];
+    __be64 beAppId = htobe64(appId.id);
+    uint32_t seqId = appId.id & NANOAPP_VENDOR_ALL_APPS;
+
+    std::ios::fmtflags f(os.flags());
+    memcpy(vendor, (void*)&beAppId, sizeof(vendor) - 1);
+    vendor[sizeof(vendor) - 1] = 0;
+    if (strlen(vendor) == 5)
+        os << vendor << ", " << std::hex << std::setw(6)  << seqId;
+    else
+        os << "#" << std::hex << appId.id;
+    os.flags(f);
+
+    return os;
+}
+
+void dumpBuffer(std::ostream &os, const char *pfx, const hub_app_name_t &appId, uint32_t evtId, const void *data, size_t len, int status)
+{
+    const uint8_t *p = static_cast<const uint8_t *>(data);
+    os << pfx << ": [ID=" << appId << "; SZ=" << std::dec << len;
+    if (evtId)
+        os << "; EVT=" << std::hex << evtId;
+    os << "]:" << std::hex;
+    for (size_t i = 0; i < len; ++i) {
+        os << " "  << std::setfill('0') << std::setw(2) << (unsigned int)p[i];
+    }
+    if (status) {
+        os << "; status=" << status << " [" << std::setfill('0') << std::setw(8) << status << "]";
+    }
+}
+
+class CHub
+{
+public:
+    class IClient {
+    public:
+        virtual void onMessage(const hub_message_t &msg) = 0;
+        virtual ~IClient(){}
+    };
+    class Client : IClient {
+        CHub *mParent;
+        const context_hub_t *mHub;
+        std::function<void(const hub_message_t &)> mHandler;
+
+    public:
+        explicit Client(const context_hub_t *hub, CHub *parent) {
+            mHub = hub;
+            mParent = parent;
+        }
+        ~Client() = default;
+
+        void setHandler(std::function<void(const hub_message_t &)> handler) {
+            mHandler = handler;
+        }
+        void onMessage(const hub_message_t &msg) {
+            if ((bool)mHandler == true) {
+                mHandler(msg);
+            }
+        }
+        void sendMessage(const hub_message_t &msg) {
+            mParent->sendMessage(mHub->hub_id, msg);
+        }
+        void sendToSystem(uint32_t typ, void *data, uint32_t len) {
+            mParent->sendMessage(mHub->hub_id, mHub->os_app_name, typ, data, len);
+        }
+        void sendToApp(hub_app_name_t app, void *data, uint32_t len) {
+            mParent->sendMessage(mHub->hub_id, app, 0, data, len);
+        }
+        const hub_app_name_t getSystemApp() const { return mHub->os_app_name; }
+    };
+private:
+    static int contextHubCallback(uint32_t id, const hub_message_t *msg, void *cookie)
+    {
+        CHub *hub = static_cast<CHub*>(cookie);
+        hub->onMessage(id, msg);
+        return 0;
+    }
+
+    CHub() {
+        hw_get_module(CONTEXT_HUB_MODULE_ID, (const hw_module_t **)&mMod);
+        if (!mMod)
+            return;
+        mMod->subscribe_messages(0, contextHubCallback, this);
+        mHubArraySize = mMod->get_hubs(mMod, &mHubArray);
+        for (size_t i = 0; i < mHubArraySize; ++i) {
+            auto item = &mHubArray[i];
+            mHubs[item->hub_id] = std::unique_ptr<Client>(new Client(item, this));
+        }
+    }
+
+    ~CHub() {
+        // destroy all clients first
+        mHubs.clear();
+        if (mMod != nullptr) {
+            // unregister from HAL services
+            mMod->subscribe_messages(0, nullptr, nullptr);
+            // there is no hw_put_module(); release HAL fd directly
+            dlclose(mMod->common.dso);
+            mMod = nullptr;
+        }
+    }
+
+    void onMessage(uint32_t hubId, const hub_message_t *msg) {
+        Client *cli = getClientById(hubId);
+        if (cli != nullptr && msg != nullptr) {
+            cli->onMessage(*msg);
+        }
+    }
+
+    int sendMessage(uint32_t id, const hub_message_t &msg) {
+        return  (mMod != nullptr) ? mMod->send_message(id, &msg) : 0;
+    }
+
+    int sendMessage(uint32_t id, hub_app_name_t app, uint32_t typ, void *data, uint32_t len) {
+        hub_message_t msg = {
+            .app_name = app,
+            .message_type = typ,
+            .message = data,
+            .message_len = len,
+        };
+        return sendMessage(id, msg);
+    }
+
+    Client *getClientById(size_t id) { return mHubs.count(id) ? mHubs[id].get() : nullptr; }
+
+    context_hub_module_t *mMod = nullptr;
+    const context_hub_t  *mHubArray = nullptr;
+    size_t                mHubArraySize = 0;
+    std::map <size_t, std::unique_ptr<Client> > mHubs;
+
+public:
+    static CHub *instantiate() {
+        static CHub instance;
+
+        return &instance;
+    }
+    Client *getClientByIndex(size_t idx) {
+        return idx < mHubArraySize && mHubArray != nullptr ?
+               getClientById(mHubArray[idx].hub_id) : nullptr;
+    }
+};
+
+class NanoClient
+{
+    CHub::Client *mClient;
+    std::ostream &log;
+    std::mutex lock;
+    void onMessage(const hub_message_t &msg){
+        std::lock_guard<std::mutex> _l(lock);
+        dumpBuffer(log, "Rx", msg.app_name, msg.message_type, msg.message, msg.message_len, 0);
+        log << std::endl;
+    }
+public:
+    NanoClient(int idx = 0) : log(std::clog) {
+        CHub *hub = CHub::instantiate();
+        mClient = hub->getClientByIndex(idx);
+        if (mClient)
+            mClient->setHandler(std::function<void(const hub_message_t&)>([this] (const hub_message_t&msg) { onMessage(msg); }));
+    }
+    void sendMessage(const hub_message_t &msg) { mClient->sendMessage(msg); }
+    void sendMessageToSystem(uint32_t cmd, void * data, size_t dataSize) {
+        hub_message_t msg;
+        msg.message = data;
+        msg.message_len = dataSize;
+        msg.message_type = cmd;
+        msg.app_name = mClient->getSystemApp();
+        {
+            std::lock_guard<std::mutex> _l(lock);
+            dumpBuffer(log, "TxCmd", msg.app_name, msg.message_type, msg.message, msg.message_len, 0);
+            log << std::endl;
+        }
+        sendMessage(msg);
+    }
+    void sendMessageToApp(const hub_app_name_t appName, void * data, size_t dataSize, uint32_t msg_type) {
+        hub_message_t msg;
+        msg.message = data;
+        msg.message_len = dataSize;
+        msg.message_type = msg_type;
+        msg.app_name = appName;
+        {
+            std::lock_guard<std::mutex> _l(lock);
+            dumpBuffer(log, "TxMsg", msg.app_name, msg.message_type, msg.message, msg.message_len, 0);
+            log << std::endl;
+        }
+        sendMessage(msg);
+    }
+};
+
+void sigint_handler(int)
+{
+    exit(0);
+}
+
+int main(int argc, char *argv[])
+{
+    int opt;
+    long cmd = 0;
+    unsigned long msg = 0;
+    uint64_t appId = 0;
+    const char *appFileName = NULL;
+    uint32_t fileSize = 0;
+
+    while((opt = getopt(argc, argv, "c:i:a:m:")) != -1) {
+        char *end = NULL;
+        switch(opt) {
+        case 'm':
+            msg = strtoul(optarg, &end, 16);
+            break;
+        case 'c':
+            cmd = strtol(optarg, &end, 10);
+            break;
+        case 'i':
+            appId = strtoull(optarg, &end, 16);
+            break;
+        case 'a':
+            appFileName = optarg;
+            break;
+        }
+        if (end && *end != '\0') {
+            std::clog << "Invalid argument: " << optarg << std::endl;
+            return 1;
+        }
+    }
+
+    NanoClient cli;
+
+    std::vector<uint8_t> data;
+    for (int i = optind; i < argc; ++i) {
+        char *end;
+        unsigned long v = strtoul(argv[i], &end, 16);
+        // ignore any garbage after parsed hex value;
+        // ignore the fact it may not fit 1 byte;
+        // we're not testing user's ability to pass valid data,
+        // we're testing the system ability to transfer data.
+        data.push_back(v);
+    }
+    if (msg != 0) {
+        // send APP message
+        const hub_app_name_t app_name = { .id = appId };
+        cli.sendMessageToApp(app_name, data.data(), data.size(), msg);
+    } else {
+        // send HAL command
+        switch(cmd) {
+        case CONTEXT_HUB_APPS_ENABLE:
+        {
+            apps_enable_request_t req;
+            req.app_name.id = appId;
+            cli.sendMessageToSystem(CONTEXT_HUB_APPS_ENABLE, &req, sizeof(req));
+        }
+        break;
+        case CONTEXT_HUB_APPS_DISABLE:
+        {
+            apps_disable_request_t req;
+            req.app_name.id = appId;
+            cli.sendMessageToSystem(CONTEXT_HUB_APPS_DISABLE, &req, sizeof(req));
+        }
+        break;
+        case CONTEXT_HUB_LOAD_APP:
+        {
+            load_app_request_t *req = NULL;
+            if (appFileName)
+                req = (load_app_request_t *)loadFile(appFileName, &fileSize);
+            if (!req || fileSize < sizeof(*req) || req->app_binary.magic != NANOAPP_MAGIC) {
+                std::clog << "Invalid nanoapp image: " <<
+                             (appFileName != nullptr ? appFileName : "<NULL>") << std::endl;
+                return 1;
+            }
+            cli.sendMessageToSystem(CONTEXT_HUB_LOAD_APP, req, fileSize);
+            free(req);
+        }
+        break;
+        case CONTEXT_HUB_UNLOAD_APP:
+        {
+            unload_app_request_t req;
+            req.app_name.id = appId;
+            cli.sendMessageToSystem(CONTEXT_HUB_UNLOAD_APP, &req, sizeof(req));
+        }
+        break;
+        case CONTEXT_HUB_QUERY_APPS:
+        {
+            query_apps_request_t req;
+            req.app_name.id = appId;
+            cli.sendMessageToSystem(CONTEXT_HUB_QUERY_APPS, &req, sizeof(req));
+        }
+        break;
+        case CONTEXT_HUB_QUERY_MEMORY:
+        default:
+            std::clog << "Unknown command: " << cmd << std::endl;
+            break;
+        }
+    }
+
+    signal(SIGINT, sigint_handler);
+    while(1) {
+        sleep(1);
+    }
+    return 0;
+}
diff --git a/firmware/Android.mk b/firmware/Android.mk
new file mode 100644
index 00000000..85db8cae
--- /dev/null
+++ b/firmware/Android.mk
@@ -0,0 +1,99 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_PATH := $(call my-dir)
+
+ifneq ($(NANOHUB_OS_PATH),)
+
+include $(CLEAR_NANO_VARS)
+
+LOCAL_MODULE := libnanohub_os
+LOCAL_MODULE_TAGS := optional
+
+LOCAL_SRC_FILES := \
+    os/core/appSec.c \
+    os/core/eventQ.c \
+    os/core/floatRt.c \
+    os/core/heap.c \
+    os/core/hostIntf.c \
+    os/core/hostIntfI2c.c \
+    os/core/hostIntfSpi.c \
+    os/core/nanohubCommand.c \
+    os/core/nanohub_chre.c \
+    os/core/osApi.c \
+    os/core/printf.c \
+    os/core/sensors.c \
+    os/core/seos.c \
+    os/core/simpleQ.c \
+    os/core/syscall.c \
+    os/core/slab.c \
+    os/core/spi.c \
+    os/core/timer.c \
+    os/core/trylock.c \
+    os/algos/ap_hub_sync.c \
+
+LOCAL_C_INCLUDES := \
+    $(NANOHUB_OS_PATH)/external/freebsd/inc \
+
+LOCAL_EXPORT_C_INCLUDE_DIRS := $(LOCAL_C_INCLUDES)
+
+include $(BUILD_NANOHUB_OS_STATIC_LIBRARY)
+
+########################################################
+# BOOT LOADER BINARY
+########################################################
+
+include $(CLEAR_NANO_VARS)
+
+LOCAL_MODULE := nanohub_bl
+
+LOCAL_SRC_FILES := \
+    os/core/bl.c   \
+
+LOCAL_STATIC_LIBRARIES := \
+    libnanohub_common_bl \
+    libnanohub_os \
+    libnanolibc_os \
+
+LOCAL_OBJCOPY_SECT_cortexm4 := .bl .blrodata .eedata
+
+include $(BUILD_NANOHUB_BL_EXECUTABLE)
+
+########################################################
+# NANOHUB OS BINARY
+########################################################
+
+include $(CLEAR_NANO_VARS)
+
+LOCAL_MODULE := nanohub_os
+
+LOCAL_CFLAGS := \
+    -DPLATFORM_HW_VER=0 \
+
+LOCAL_WHOLE_STATIC_LIBRARIES := \
+    libnanohub_os \
+
+LOCAL_STATIC_LIBRARIES := \
+    libnanomath_os \
+    libnanolibc_os \
+
+LOCAL_OBJCOPY_SECT_cortexm4 := .data .text
+
+include $(BUILD_NANOHUB_OS_EXECUTABLE)
+
+include $(call first-makefiles-under,$(NANOHUB_OS_PATH))
+
+endif # NANOHUB_OS_PATH
diff --git a/CodingStandard.txt b/firmware/CodingStandard.txt
index ea40c45c..1681072c 100644
--- a/CodingStandard.txt
+++ b/firmware/CodingStandard.txt
@@ -5,54 +5,54 @@ Finding an example that does not obey these guidelines is not a cause for also d
  0. Code will not be wrapped to 80 characters. We all have 24+ inch high-res displays. Let's use them.
     That being said, this is not an endorsement of 500-character lines. Be reasonable.
  1. File names shall be camel case and descriptive. Keep them short too. Eg: spi.h is better than
-    spiInterfaceDriver.h
+    spiInterfaceDriver.h.
  2. All function names shall be camel-case, beginning with a lowercase letter.
  3. All functions that are visibile in the global scope (outside their C file) shall begin with the
-    name of their module (gpio, pwm, os)
- 4. All functions not visible in the global scope shall be declared static
- 5. Functions taking no parameters shall be declated as (void) and not as ()
- 6. All type names shall be camel-case, beginnign with a capital letter.
+    name of their module (gpio, pwm, os).
+ 4. All functions not visible in the global scope shall be declared static.
+ 5. Functions taking no parameters shall be declated as (void) and not as ().
+ 6. All type names shall be camel-case, beginning with a capital letter.
  7. All types in the global scope shall begin with their module name. (GpioPullType, SpiDeviceHandle)
  8. There should be *NO* globally-visible variables. All non-stack variables shall be declared
-    "static" and reside in one C file
+    "static" and reside in one C file.
  9. All global variables in a given C file shall begin with "m" and then be in camel case. This is to
-    make it easier to identify them
+    make it easier to identify them.
 10. All variables shall be declared in the beginning of the block where they reside. This facilitates
-    easily looking over code and estimating memory use
+    easily looking over code and estimating memory use.
 11. typedef is forbidden except for function pointer types. Do not typedef structs or unions. Use full
-    names - makes it easy to appreciate the cost (struct GpioHandle, union PwmDeviceData)
+    names - makes it easy to appreciate the cost (struct GpioHandle, union PwmDeviceData).
 12. Do not use short. char is allowed for actual printable strings only. Use uint8_t/uint16_t/
     uint32_t/uint64_t for clarity of intentions and clear delineation of size needed.
 13. int/unsigned int is allowed only for simple loop iterators only (or, if you must, as a return type
     when you wish to return more than one error class). Do not assume ints are 32 bits. Or 64. Or 16.
 14. Do not use uint16_t/uint8_t for function parameters/return types. Gcc generates very bad code for
-    those cases and you will lose. However, uint8_t/uint16_t are ok to use in structs/unions
-15. All structures shall be packed to avoid space waste, as compiler is not allowed to pack them for
+    those cases and you will lose. However, uint8_t/uint16_t are ok to use in structs/unions.
+15. All structures shall be packed to avoid space waste, as the compiler is not allowed to pack them for
     you. If you are not sure how to, sort members by size (uint64_t members first, then uint32_t
-    members, etc)
+    members, etc).
 16. Do not ever return structs or unions from functions. Pass a pointer and fill it in. Gcc will
-    optimize this better and it is better C
+    optimize this better and it is better C.
 17. All definitions/defines/structs/unions that are only used by one source file belong in that C
-    file. There is never a need for "myModule_priv.h" unless the module is made of a few C files
+    file. There is never a need for "myModule_priv.h" unless the module is made of a few C files.
 18. Absolutely no "double" types are allowed. Absolutely no passing of "float" vars through var-args
-    (it converts to double)
+    (it converts to double).
 19. Absolutely no inline assembly unless you're in a folder under "cpu" or "variant". Allowed in
-    "platform" only if platform only supports one CPU type
-20. You may use whatever comment style suits your heart, as long as the compiler can live with it
+    "platform" only if platform only supports one CPU type.
+20. You may use whatever comment style suits your heart, as long as the compiler can live with it.
 21. You may not change compiler flags in order to remove warnings or errors. They are there for a
     reason, listen to them and fix the code instead.
 22. Whenever possible, hide struct definitions from global scope. Eg: gpio funcs return
     "struct Gpio*". Actual struct Gpio definition is not public. Not only does this help with clean
-    code, it wil lwarn you if you accidentally try to derefernce it, or on purpiose try to access
+    code, it will warn you if you accidentally try to dereference it, or on purpose try to access
     internal private state. Also this allows platform-independence to continue.
-23. commit messages shall begin with module they touch and a colon, eg "spi: fix spi-dma on stm64"
+23. commit messages shall begin with module they touch and a colon, eg "spi: fix spi-dma on stm64".
 24. Do not divide 64-bit values. If you simply must, only do so by a constant, and use cpuMath.h.
     This will be enforced at compile time and will fail your build. This is intentional as the power
     and speed costs are substantial.
 25. Do not cast floats to 64-bit values or back, this is slow. Use floatRt.h. This will be enforced
     at compile time and will fail your build. This is intentional as the power and speed costs are
     substantial.
-26. Do not use types with uncertain sizes. NO size_t, ssize_t, etc. use uintXX_t or uintptr_t
+26. Do not use types with uncertain sizes. NO size_t, ssize_t, etc. use uintXX_t or uintptr_t.
 
 
-99. These guidelines will be kept updated as things come up/are decided
+99. These guidelines will be kept updated as things come up/are decided.
diff --git a/firmware/Makefile b/firmware/Makefile
deleted file mode 100644
index ce06a11b..00000000
--- a/firmware/Makefile
+++ /dev/null
@@ -1,130 +0,0 @@
-#
-# Copyright (C) 2016 The Android Open Source Project
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-
-#find build target
-PLATFORM ?= stm32f4xx
-CPU ?= cortexm4f
-VARIANT ?= lunchbox
-DEBUG ?= -DDEBUG
-
-#bad words
-BADWORDS += strcpy strcat atoi
-BADWORDS += "rsaPrivOp=RSA private ops must never be compiled into firmware."
-
-#find makefiles
-MAKE_PLAT = misc/platform/$(PLATFORM)/Makefile
-MAKE_CPU = misc/cpu/$(CPU)/Makefile
-
-#link paths
-ifdef VARIANT_PATH
-LINK_PATH_MISC = $(VARIANT_PATH)/misc
-LINK_PATH_SRC = $(VARIANT_PATH)/src
-LINK_PATH_INC = $(VARIANT_PATH)/inc
-else
-LINK_PATH_MISC = misc/variant/$(VARIANT)
-LINK_PATH_SRC = src/variant/$(VARIANT)
-LINK_PATH_INC = inc/variant/$(VARIANT)
-endif
-
-#variant makefile
-MAKE_VAR = $(LINK_PATH_MISC)/Makefile
-
-#top make target
-SRCS_os :=
-SRCS_bl :=
-DELIVERABLES :=
-real: all
-
-#include makefiles for plat and cpu
-include $(MAKE_PLAT)
-include $(MAKE_CPU)
-include $(MAKE_VAR)
-
-FLAGS += -Wall -Werror -Iinc -Ilinks -Iexternal/freebsd/inc -I../lib/include -fshort-double
-#help avoid commmon embedded C mistakes
-FLAGS += -Wmissing-declarations -Wlogical-op -Waddress -Wempty-body -Wpointer-arith -Wenum-compare -Wdouble-promotion -Wfloat-equal -Wshadow -fno-strict-aliasing
-
-OSFLAGS += -g -ggdb3 -D_OS_BUILD_ -O2
-APPFLAGS += -Os
-
-#debug mode
-FLAGS += $(DEBUG)
-
-#bootloader pieces
-SRCS_bl += ../lib/nanohub/sha2.c ../lib/nanohub/rsa.c ../lib/nanohub/aes.c src/seos.c
-
-#frameworks
-SRCS_os += src/printf.c src/timer.c src/seos.c src/heap.c src/slab.c src/spi.c src/trylock.c
-SRCS_os += src/hostIntf.c src/hostIntfI2c.c src/hostIntfSpi.c src/nanohubCommand.c src/sensors.c src/syscall.c
-SRCS_os += src/eventQ.c src/osApi.c src/appSec.c src/simpleQ.c src/floatRt.c
-SRCS_os += src/algos/ap_hub_sync.c
-
-#some help for bootloader
-SRCS_bl += src/printf.c
-
-ifndef PLATFORM_HAS_HARDWARE_CRC
-SRCS_os += ../lib/nanohub/softcrc.c
-endif
-
-#app code
-include $(wildcard app/*/Makefile)
-
-
-#extra deps
-DEPS += $(wildcard app/*.h)
-DEPS += $(wildcard inc/*.h)
-DEPS += Makefile $(MAKE_PLAT) $(MAKE_CPU) $(MAKE_VAR)
-
-all: symlinks $(DELIVERABLES)
-
-symlinks: links/p_$(PLATFORM) links/c_$(CPU) links/v_$(VARIANT)
-
-links/p_$(PLATFORM):
-	rm -rf links/plat links/p_*
-	mkdir -p links/plat
-	ln -s ../../misc/platform/$(PLATFORM) links/plat/misc
-	ln -s ../../src/platform/$(PLATFORM) links/plat/src
-	ln -s ../../inc/platform/$(PLATFORM) links/plat/inc
-	touch links/p_$(PLATFORM)
-
-links/c_$(CPU):
-	rm -rf links/cpu links/c_*
-	mkdir -p links/cpu
-	ln -s ../../misc/cpu/$(CPU) links/cpu/misc
-	ln -s ../../src/cpu/$(CPU) links/cpu/src
-	ln -s ../../inc/cpu/$(CPU) links/cpu/inc
-	touch links/c_$(CPU)
-
-links/v_$(VARIANT):
-	rm -rf links/variant links/v_*
-	mkdir -p links/variant
-	ln -s ../../$(LINK_PATH_MISC) links/variant/misc
-	ln -s ../../$(LINK_PATH_SRC) links/variant/src
-	ln -s ../../$(LINK_PATH_INC) links/variant/inc
-	touch links/v_$(VARIANT)
-
-%.unchecked.elf: symlinks $(SRCS_$*) $(DEPS)
-	$(GCC) -o $@ $(SRCS_$*) $(OSFLAGS) $(OSFLAGS_$*) $(FLAGS) -lgcc -nostdlib
-
-%.checked.elf : %.unchecked.elf  symcheck.sh
-	./symcheck.sh $< $@ $(BADWORDS)
-
-full.bin: $(BL_FILE) $(OS_FILE)
-	cat $(BL_FILE) $(OS_FILE) > $@
-
-clean:
-	rm -rf $(DELIVERABLES) os.elf bootloader.elf links $(CLEANFILES)
-
diff --git a/firmware/README b/firmware/README
new file mode 100644
index 00000000..197bbd33
--- /dev/null
+++ b/firmware/README
@@ -0,0 +1,58 @@
+0. ENVIRONMENT SETUP (Common ANDROID and NON-ANDROID builds)
+
+# Create Android lunch shell and add external toolchain
+
+bash
+. build/envsetup.sh
+. device/google/contexthub/firmware/toolchain-setup.sh
+lunch <your lunch option>
+
+# First time you run toolchain-setup.sh it will download and install
+# the external toolchain from linaro launchpad.
+# Next time it will simply define environment wariables for it.
+
+
+1. NON-ANDROID BUILD (unsupported)
+
+1.1. to build any OS variant, run
+
+make -C <variant_path>
+
+# where <variant_path> is relative path to OS variant dir;
+# or simply "cd  <variant_path>" and run "make".
+# for local variants, variant_path is variant/<variant_name>
+
+1.2. to build nanoapp, run
+
+make -C <nanapp_path>
+
+# where <nanoapp_path> is relative path to nanoapp;
+# or simply "cd  <nanoapp_path>" and run "make".
+# for local nanoapps, nanoapp_path is app/<app_name>
+
+
+2. ANDROID BUILD
+
+2.1 to build nanohub OS and all apps
+
+# execute
+make auxiliary -j24
+
+2.2 Build Artifacts Location
+
+# Artifacts will be found in
+# $OUT/aux/$(AUX_OS_VARIANT)/$(AUX_OS)-$(AUX_ARCH)-$(AUX_CPU)/bin
+# e.g. for nanohub OS on STM32 series MCU (ARM cortex m4 core) for Angler this will be in
+# $OUT/aux/angler/nanohub-stm32-cortexm4/bin
+# where $OUT is lunch shell environment variable
+
+2.3 partial build or build without dependencies
+
+# Any app or static library could be built in isolation with
+mmm <path-to-module>
+
+# or, for current path
+mm
+
+# Nanohub OS system image is only built with
+m auxiliary
diff --git a/firmware/app/Android.mk b/firmware/app/Android.mk
new file mode 100644
index 00000000..e6bbbc1e
--- /dev/null
+++ b/firmware/app/Android.mk
@@ -0,0 +1,18 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+subdirs := test0.app test1.app chre
+include $(call all-named-subdir-makefiles,$(subdirs))
diff --git a/firmware/app/app.mk b/firmware/app/app.mk
new file mode 100644
index 00000000..47c8de2e
--- /dev/null
+++ b/firmware/app/app.mk
@@ -0,0 +1,304 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+################################################################################
+#
+# NanoApp C/C++ Makefile Utils
+#
+################################################################################
+
+# Configuration ################################################################
+
+# Toolchain Prefix
+ifndef CROSS_COMPILE
+  $(error Please set the environment variable CROSS_COMPILE to the complete \
+          path to the toolchain directory plus the binary prefix, e.g. export \
+          CROSS_COMPILE=~/bin/gcc-arm-none-eabi-4_8-2014q3/bin/arm-none-eabi-)
+endif
+
+PREFIX = $(CROSS_COMPILE)
+TOOLCHAIN_DIR = $(shell dirname `which $(CROSS_COMPILE)gcc`)/..
+
+# NANOHUB_DIR is relative to CWD (which is always APP Makefile dir)
+
+NANOAPP_POSTPROCESS := $(NANOHUB_DIR)/../util/nanoapp_postprocess/nanoapp_postprocess
+NANOAPP_SIGN := $(NANOHUB_DIR)/../util/nanoapp_sign/nanoapp_sign
+
+# TOP_RELPATH is ANDROID_TOP relative to NANOHUB_DIR
+TOP_RELPATH := ../../../..
+TOP_ABSPATH := $(realpath $(NANOHUB_DIR)/$(TOP_RELPATH))
+
+# for local variants there is always a path; for out-of-tree variants there may be
+# - a $(VARIANT) soft link under firmware/variant subdir, or
+# - VARIANT_PATH is found as vendor/<vendor_name>/<variant_name>/nanohub, or
+# - explicitly provided in VARIANT_CONFIG_PATH (path, where <variant>_conf.mk is located)
+#
+ifeq ($(VARIANT_CONFIG_PATH),)
+  variant_conf := $(wildcard $(TOP_ABSPATH)/vendor/*/*/nanohub/$(VARIANT)_conf.mk)
+  ifeq ($(words $(variant_conf)),1)
+    VARIANT_CONFIG_PATH := $(patsubst $(TOP_ABSPATH)/%/$(VARIANT)_conf.mk,%,$(variant_conf))
+  else
+    VARIANT_CONFIG_PATH := device/google/contexthub/firmware/variant/$(VARIANT)
+  endif
+endif
+
+include $(TOP_ABSPATH)/$(VARIANT_CONFIG_PATH)/$(VARIANT)_conf.mk
+
+# $(VARIANT)_conf.mk defines VARIANT_PATH, PLATFORM, CHIP, CPU, VARIANT
+# VARIANT_PATH from $(VARIANT)_conf.mk is ANDROID_TOP relative
+
+# change VARIANT_PATH to become CWD-relative
+VARIANT_PATH := $(NANOHUB_DIR)/$(TOP_RELPATH)/$(VARIANT_PATH)
+
+# all output goes here
+ifndef OUT
+OUT:=out/nanohub/$(VARIANT)/app/$(BIN)
+else
+ifneq ($(filter $(TOP_ABSPATH)/out/target/product/%,$(OUT)),)
+# this looks like Android OUT env var; update it
+IMAGE_TARGET_OUT:=$(OUT)/vendor/firmware/$(BIN).napp
+OUT:=$(OUT)/nanohub/$(VARIANT)/app/$(BIN)
+endif
+endif
+
+################################################################################
+#
+# Nanoapp Libc/Libm Utils
+#
+################################################################################
+
+include $(NANOHUB_DIR)/lib/lib.mk
+
+# Tools ########################################################################
+
+AS := $(PREFIX)gcc
+CC := $(PREFIX)gcc
+CXX := $(PREFIX)g++
+OBJCOPY := $(PREFIX)objcopy
+OBJDUMP := $(PREFIX)objdump
+
+# Assembly Flags ###############################################################
+
+AS_FLAGS +=
+
+# C++ Flags ####################################################################
+
+CXX_CFLAGS += -std=c++11
+CXX_CFLAGS += -fno-exceptions
+CXX_CFLAGS += -fno-rtti
+
+# C Flags ######################################################################
+
+C_CFLAGS +=
+
+# Common Flags #################################################################
+
+# Defines
+CFLAGS += -DAPP_ID=$(APP_ID)
+CFLAGS += -DAPP_VERSION=$(APP_VERSION)
+CFLAGS += -D__NANOHUB__
+
+# Optimization/debug
+CFLAGS += -Os
+CFLAGS += -g
+
+# Include paths
+CFLAGS += -I$(NANOHUB_DIR)/os/inc
+CFLAGS += -I$(NANOHUB_DIR)/os/platform/$(PLATFORM)/inc
+CFLAGS += -I$(NANOHUB_DIR)/os/cpu/$(CPU)/inc
+CFLAGS += -I$(VARIANT_PATH)/inc
+CFLAGS += -I$(NANOHUB_DIR)/../lib/include
+
+# Warnings/error configuration.
+CFLAGS += -Wall
+CFLAGS += -Werror
+CFLAGS += -Wmissing-declarations
+CFLAGS += -Wlogical-op
+CFLAGS += -Waddress
+CFLAGS += -Wempty-body
+CFLAGS += -Wpointer-arith
+CFLAGS += -Wenum-compare
+CFLAGS += -Wdouble-promotion
+CFLAGS += -Wshadow
+CFLAGS += -Wno-attributes
+
+# Produce position independent code.
+CFLAGS += -fpic
+CFLAGS += -mno-pic-data-is-text-relative
+CFLAGS += -msingle-pic-base
+CFLAGS += -mpic-register=r9
+
+# Code generation options for Cortex-M4F
+CFLAGS += -mthumb
+CFLAGS += -mcpu=cortex-m4
+CFLAGS += -march=armv7e-m
+CFLAGS += -mfloat-abi=softfp
+CFLAGS += -mfpu=fpv4-sp-d16
+CFLAGS += -mno-thumb-interwork
+CFLAGS += -ffast-math
+CFLAGS += -fsingle-precision-constant
+
+# Platform defines
+CFLAGS += -DARM
+CFLAGS += -DUSE_NANOHUB_FLOAT_RUNTIME
+CFLAGS += -DARM_MATH_CM4
+CFLAGS += -D__FPU_PRESENT
+
+# Miscellaneous
+CFLAGS += -fno-strict-aliasing
+CFLAGS += -fshort-double
+CFLAGS += -fvisibility=hidden
+CFLAGS += -fno-unwind-tables
+CFLAGS += -fstack-reuse=all
+CFLAGS += -ffunction-sections
+CFLAGS += -fdata-sections
+
+# Linker Configuration #########################################################
+
+LD := $(PREFIX)g++
+
+LDFLAGS := -T $(NANOHUB_DIR)/os/platform/$(PLATFORM)/lkr/app.lkr
+LDFLAGS += -nostartfiles
+LDFLAGS += -Wl,--gc-sections
+LDFLAGS += -Wl,-Map,$(OUT)/$(BIN).map
+LDFLAGS += -Wl,--cref
+STATIC_LIBS += -lgcc
+ifeq ($(BIN_MODE),static)
+LDFLAGS += -Bstatic
+LDFLAGS += -Wl,--emit-relocs
+else
+LDFLAGS += -Bdynamic
+LDFLAGS += -Wl,--no-undefined
+LDFLAGS += -Wl,--no-allow-shlib-undefined
+endif
+
+# Build Rules ##################################################################
+
+AS_SRCS := $(filter %.S, $(SRCS))
+C_SRCS := $(filter %.c, $(SRCS))
+CXX_SRCS := $(filter %.cc, $(SRCS))
+CPP_SRCS := $(filter %.cpp, $(SRCS))
+
+OBJS := $(patsubst %.S, $(OUT)/%.o, $(AS_SRCS))
+OBJS += $(patsubst %.c, $(OUT)/%.o, $(C_SRCS))
+OBJS += $(patsubst %.cc, $(OUT)/%.o, $(CXX_SRCS))
+OBJS += $(patsubst %.cpp, $(OUT)/%.o, $(CPP_SRCS))
+
+UNSIGNED_BIN := $(BIN).unsigned.napp
+
+NANOHUB_KEY_PATH := $(NANOHUB_DIR)/os/platform/$(PLATFORM)/misc
+
+.PHONY: all clean sync
+all: $(OUT)/$(BIN).S $(OUT)/$(BIN).napp $(IMAGE_TARGET_OUT)
+
+$(OUT)/$(BIN).napp : $(OUT)/$(UNSIGNED_BIN) $(NANOAPP_SIGN)
+	@mkdir -p $(dir $@)
+	$(NANOAPP_SIGN) -e $(NANOHUB_KEY_PATH)/debug.privkey \
+		-m $(NANOHUB_KEY_PATH)/debug.pubkey -s $< $@
+ifdef IMAGE_TARGET_OUT
+$(IMAGE_TARGET_OUT): $(OUT)/$(BIN).napp
+	@mkdir -p $(dir $@)
+	cp $< $(IMAGE_TARGET_OUT)
+endif
+
+ifeq ($(BIN_MODE),static)
+$(OUT)/$(UNSIGNED_BIN) : $(OUT)/$(BIN).elf $(NANOAPP_POSTPROCESS)
+	@mkdir -p $(dir $@)
+	$(NANOAPP_POSTPROCESS) -s -a $(APP_ID) -v $(BIN_POSTPROCESS_ARGS) $< $@
+else
+$(OUT)/$(UNSIGNED_BIN) : $(OUT)/$(BIN).bin $(NANOAPP_POSTPROCESS)
+	@mkdir -p $(dir $@)
+	$(NANOAPP_POSTPROCESS) -a $(APP_ID) -v $(BIN_POSTPROCESS_ARGS) $< $@
+
+$(OUT)/$(BIN).bin : $(OUT)/$(BIN).elf
+	@mkdir -p $(dir $@)
+	$(OBJCOPY) -j.relocs -j.flash -j.data -j.dynsym -O binary $< $@
+endif
+
+$(OUT)/$(BIN).S : $(OUT)/$(BIN).elf
+	@mkdir -p $(dir $@)
+	$(OBJDUMP) $< -DS > $@
+
+$(OUT)/$(BIN).elf : $(OBJS)
+	@mkdir -p $(dir $@)
+	$(LD) $(CFLAGS) $(CXX_FLAGS) $(LDFLAGS) $(OBJS) $(STATIC_LIBS) -o $@
+
+$(OUT)/%.o : %.S
+	@mkdir -p $(dir $@)
+	$(AS) $(AS_FLAGS) $(CFLAGS) -c $< -o $@
+
+$(OUT)/%.o : %.c
+	@mkdir -p $(dir $@)
+	$(CC) $(C_CFLAGS) $(CFLAGS) -c $< -o $@
+
+$(OUT)/%.o : %.cc
+	@mkdir -p $(dir $@)
+	$(CXX) $(CXX_CFLAGS) $(CFLAGS) -c $< -o $@
+
+$(OUT)/%.o : %.cpp
+	@mkdir -p $(dir $@)
+	$(CXX) $(CXX_CFLAGS) $(CFLAGS) -c $< -o $@
+
+# Automatic dependency resolution ##############################################
+
+DEPS_AS = $(OUT)/deps_as
+DEPS_C = $(OUT)/deps_c
+DEPS_CXX = $(OUT)/deps_cxx
+
+$(DEPS_AS) : $(AS_SRCS)
+	@mkdir -p $(dir $@)
+	$(AS) $(AS_CFLAGS) $(CFLAGS) -MM $^ > $@
+
+$(DEPS_C) : $(C_SRCS)
+	@mkdir -p $(dir $@)
+	$(CC) $(C_CFLAGS) $(CFLAGS) -MM $^ > $@
+
+$(DEPS_CXX) : $(CXX_SRCS) $(CPP_SRCS)
+	@mkdir -p $(dir $@)
+	$(CXX) $(CXX_CFLAGS) $(CFLAGS) -MM $^ > $@
+
+NOAUTODEPTARGETS = clean
+
+ifeq ($(words $(findstring $(MAKECMDGOALS), $(NOAUTODEPTARGETS))), 0)
+
+ifneq ($(AS_SRCS), )
+-include $(DEPS_AS)
+endif
+
+ifneq ($(C_SRCS), )
+-include $(DEPS_C)
+endif
+
+ifneq ($(CXX_SRCS)$(CPP_SRCS),)
+-include $(DEPS_CXX)
+endif
+
+endif
+
+$(NANOAPP_POSTPROCESS): $(wildcard $(dir $(NANOAPP_POSTPROCESS))/*.c* $(dir $(NANOAPP_POSTPROCESS))/*.h)
+	echo DEPS [$@]: $^
+	make -C $(dir $@)
+
+$(NANOAPP_SIGN): $(wildcard $(dir $(NANOAPP_SIGN))/*.c* $(dir $(NANOAPP_SIGN))/*.h)
+	echo DEPS [$@]: $^
+	make -C $(dir $@)
+
+# Clean targets ################################################################
+
+clean :
+	rm -rf $(OUT)
+
+sync:   $(OUT)/$(BIN).napp
+	adb push $< /vendor/firmware/$(BIN).napp
diff --git a/firmware/app/chre/Android.mk b/firmware/app/chre/Android.mk
new file mode 100644
index 00000000..54d18ee0
--- /dev/null
+++ b/firmware/app/chre/Android.mk
@@ -0,0 +1,19 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_PATH := $(call my-dir)
+
+include $(call first-makefiles-under,$(LOCAL_PATH))
diff --git a/firmware/app/chre/chre.mk b/firmware/app/chre/chre.mk
new file mode 100644
index 00000000..a1476771
--- /dev/null
+++ b/firmware/app/chre/chre.mk
@@ -0,0 +1,32 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+################################################################################
+#
+# NanoApp C/C++ Makefile Utils
+#
+################################################################################
+
+SRCS += $(NANOHUB_DIR)/app/chre/common/chre_app.c
+SRCS += $(NANOHUB_DIR)/app/chre/common/chre_app_syscalls.c
+CFLAGS += -I$(NANOHUB_DIR)/../inc
+
+include $(NANOHUB_DIR)/firmware_conf.mk
+
+CFLAGS += $(COMMON_FLAGS)
+
+BIN_POSTPROCESS_ARGS := -f 0x10
+
+include $(NANOHUB_DIR)/app/app.mk
diff --git a/firmware/app/chre/chre_test0.app/Android.mk b/firmware/app/chre/chre_test0.app/Android.mk
new file mode 100644
index 00000000..4e265c20
--- /dev/null
+++ b/firmware/app/chre/chre_test0.app/Android.mk
@@ -0,0 +1,30 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_PATH := $(call my-dir)
+
+include $(CLEAR_NANO_VARS)
+
+LOCAL_MODULE := chre_test0
+LOCAL_MODULE_TAGS := optional
+
+# Googl + T + 0x9000
+LOCAL_NANO_APP_ID := 476f6f676c549000
+LOCAL_NANO_APP_VERSION := 0
+
+LOCAL_SRC_FILES := main.c
+
+include $(BUILD_NANOHUB_APP_CHRE_EXECUTABLE)
diff --git a/firmware/app/chre/chre_test0.app/Makefile b/firmware/app/chre/chre_test0.app/Makefile
new file mode 100644
index 00000000..135fe517
--- /dev/null
+++ b/firmware/app/chre/chre_test0.app/Makefile
@@ -0,0 +1,41 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+################################################################################
+#
+# test NanoApp Makefile
+#
+################################################################################
+
+
+SRCS := main.c
+BIN := chre_test0
+APP_ID := 476f6f676c549000
+APP_VERSION := 0
+
+# Nanohub relative path
+NANOHUB_DIR := ../../..
+
+# Device configuration #########################################################
+
+# select device variant for this app
+# if there is no path of the form $(NANOHUB_DIR)/variant/$(VARIANT), the
+# VARIANT_PATH variable must be set to ANDROID_TOP-relative valid path containing VARIANT subtree
+
+TARGET_PRODUCT ?= nucleo
+VARIANT := $(TARGET_PRODUCT)
+
+include $(NANOHUB_DIR)/app/chre/chre.mk
diff --git a/firmware/app/chre/chre_test0.app/main.c b/firmware/app/chre/chre_test0.app/main.c
new file mode 100644
index 00000000..acdba524
--- /dev/null
+++ b/firmware/app/chre/chre_test0.app/main.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+#include <inttypes.h>
+#include <chre.h>
+
+#define CHRE_APP_TAG "CHRE App 0: "
+
+/* chre.h does not define printf format attribute for chreLog() */
+void chreLog(enum chreLogLevel level, const char *str, ...) __attribute__ ((__format__ (__printf__, 2, 3)));
+
+#define EVT_LOCAL_SETUP CHRE_EVENT_FIRST_USER_VALUE
+
+struct MyTimer {
+    uint32_t timerId;
+};
+
+struct ExtMsg
+{
+    uint8_t msg;
+    uint32_t val;
+} __attribute__((packed));
+
+static const uint64_t kOneSecond = UINT64_C(1000000000); // in nanoseconds
+
+static uint32_t mMyTid;
+static uint64_t mMyAppId;
+static int cnt;
+static struct MyTimer mTimer;
+
+static void nanoappFreeEvent(uint16_t eventType, void *data)
+{
+    chreLog(CHRE_LOG_INFO, CHRE_APP_TAG "event callback invoked: eventType=%04" PRIX16
+            "; data=%p\n", eventType, data);
+}
+
+// Default implementation for message free
+static void nanoappFreeMessage(void *msg, size_t size)
+{
+    chreLog(CHRE_LOG_INFO, CHRE_APP_TAG "message callback invoked: msg=%p; size=%08zu\n",
+            msg, size);
+    chreHeapFree(msg);
+}
+
+bool nanoappStart(void)
+{
+    mMyAppId = chreGetAppId();
+    mMyTid = chreGetInstanceId();
+    cnt = 3;
+    chreSendEvent(EVT_LOCAL_SETUP, (void*)0x87654321, nanoappFreeEvent, mMyTid);
+    chreLog(CHRE_LOG_INFO, CHRE_APP_TAG "init\n");
+    return true;
+}
+
+void nanoappEnd(void)
+{
+}
+
+void nanoappHandleEvent(uint32_t srcTid, uint16_t evtType, const void* evtData)
+{
+    switch (evtType) {
+    case  EVT_LOCAL_SETUP:
+        mTimer.timerId = chreTimerSet(kOneSecond, &mTimer, false);
+        chreLog(CHRE_LOG_INFO, CHRE_APP_TAG "started with tid %04" PRIX32
+                               " timerid %" PRIu32
+                               "\n", mMyTid, mTimer.timerId);
+        break;
+    case CHRE_EVENT_TIMER:
+    {
+        const struct MyTimer *t = (const struct MyTimer *)evtData;
+        struct ExtMsg *extMsg = chreHeapAlloc(sizeof(*extMsg));
+
+        chreLog(CHRE_LOG_INFO, CHRE_APP_TAG "received timer %" PRIu32
+                               " (TIME: %" PRIu64
+                               ") cnt: %d\n", t->timerId, chreGetTime(), cnt);
+        extMsg->msg = 0x01;
+        extMsg->val = cnt;
+        chreSendMessageToHost(extMsg, sizeof(*extMsg), 0, nanoappFreeMessage);
+        if (cnt-- <= 0)
+            chreTimerCancel(t->timerId);
+        break;
+    }
+    case CHRE_EVENT_MESSAGE_FROM_HOST:
+    {
+        const struct chreMessageFromHostData *msg = (const struct chreMessageFromHostData *)evtData;
+        const uint8_t *data = (const uint8_t *)msg->message;
+        const size_t size = msg->messageSize;
+        chreLog(CHRE_LOG_INFO, CHRE_APP_TAG "message=%p; code=%d; size=%zu\n",
+                data, (data && size) ? data[0] : 0, size);
+        break;
+    }
+    }
+}
diff --git a/firmware/app/chre/chre_test1.app/Android.mk b/firmware/app/chre/chre_test1.app/Android.mk
new file mode 100644
index 00000000..f5a303c8
--- /dev/null
+++ b/firmware/app/chre/chre_test1.app/Android.mk
@@ -0,0 +1,31 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_PATH := $(call my-dir)
+
+include $(CLEAR_NANO_VARS)
+
+LOCAL_MODULE := chre_test1
+LOCAL_MODULE_TAGS := optional
+
+# Googl + T + 0x9001
+LOCAL_NANO_APP_ID := 476f6f676c549001
+LOCAL_NANO_APP_VERSION := 0
+
+LOCAL_SRC_FILES := \
+    main.cpp \
+
+include $(BUILD_NANOHUB_APP_CHRE_EXECUTABLE)
diff --git a/firmware/app/chre/chre_test1.app/Makefile b/firmware/app/chre/chre_test1.app/Makefile
new file mode 100644
index 00000000..6e6390c7
--- /dev/null
+++ b/firmware/app/chre/chre_test1.app/Makefile
@@ -0,0 +1,38 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+################################################################################
+#
+# test NanoApp Makefile
+#
+################################################################################
+
+
+SRCS := main.cpp
+BIN := chre_test1
+APP_ID := 476f6f676c549001
+APP_VERSION := 0
+
+# Nanohub relative path
+NANOHUB_DIR := ../../..
+
+# Device configuration #########################################################
+
+# select device variant for this app
+TARGET_PRODUCT ?= nucleo
+VARIANT := $(TARGET_PRODUCT)
+
+include $(NANOHUB_DIR)/app/chre/chre.mk
diff --git a/firmware/app/chre/chre_test1.app/main.cpp b/firmware/app/chre/chre_test1.app/main.cpp
new file mode 100644
index 00000000..22a33ce6
--- /dev/null
+++ b/firmware/app/chre/chre_test1.app/main.cpp
@@ -0,0 +1,120 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+#include <inttypes.h>
+#include <chre.h>
+
+#define APP_LABEL "CHRE App 1: "
+
+/* chre.h does not define printf format attribute for chreLog() */
+void chreLog(enum chreLogLevel level, const char *str, ...) __attribute__ ((__format__ (__printf__, 2, 3)));
+
+#define EVT_LOCAL_SETUP CHRE_EVENT_FIRST_USER_VALUE
+
+struct MyTimer {
+    uint32_t timerId;
+};
+
+struct ExtMsg
+{
+    uint8_t msg;
+    uint32_t val;
+} __attribute__((packed));
+
+static const uint64_t kOneSecond = UINT64_C(1000000000); // in nanoseconds
+
+static uint32_t mMyTid;
+static uint64_t mMyAppId;
+static int cnt;
+static struct MyTimer mTimer;
+
+// Default implementation for message free
+static void nanoappFreeMessage(void *msg, size_t size)
+{
+    chreHeapFree(msg);
+}
+
+bool nanoappStart(void)
+{
+    mMyAppId = chreGetAppId();
+    mMyTid = chreGetInstanceId();
+    cnt = 3;
+    chreSendEvent(EVT_LOCAL_SETUP, NULL, NULL, mMyTid);
+    chreLog(CHRE_LOG_INFO, APP_LABEL "init");
+    return true;
+}
+
+void nanoappEnd(void)
+{
+    chreLog(CHRE_LOG_INFO, APP_LABEL "terminating");
+}
+
+class A {
+    int *p;
+public:
+    A(int _x) {
+        p = new int[1];
+        if (p != nullptr)
+            *p = _x;
+        chreLog(CHRE_LOG_INFO, APP_LABEL "A::A(int): *p=%d", p != nullptr ? *p : 0);
+    }
+    ~A() {
+        chreLog(CHRE_LOG_INFO, APP_LABEL "A::~A(): *p=%d", p != nullptr ? *p : 0);
+        delete p;
+        p = nullptr;
+    }
+};
+
+static A global_with_ctor_dtor(1);  // test the behavior of global static constructors/destructors
+
+void nanoappHandleEvent(uint32_t srcTid, uint16_t evtType, const void* evtData)
+{
+    static A local_static_with_ctor_dtor(2); // test the behavior of local static constructors/destructors
+
+    switch (evtType) {
+    case  EVT_LOCAL_SETUP:
+        mTimer.timerId = chreTimerSet(kOneSecond, &mTimer, false);
+        chreLog(CHRE_LOG_INFO, APP_LABEL "started with tid %04" PRIX32
+                               " timerid %" PRIu32
+                               "\n", mMyTid, mTimer.timerId);
+        break;
+    case CHRE_EVENT_TIMER:
+    {
+        const struct MyTimer *t = (const struct MyTimer *)evtData;
+        auto extMsg = new ExtMsg;
+
+        chreLog(CHRE_LOG_INFO, APP_LABEL "received timer %" PRIu32
+                               " (TIME: %" PRIu64
+                               ") cnt: %d\n", t->timerId, chreGetTime(), cnt);
+        extMsg->msg = 0x01;
+        extMsg->val = cnt;
+        chreSendMessageToHost(extMsg, sizeof(*extMsg), 0, nanoappFreeMessage);
+        if (cnt-- <= 0)
+            chreTimerCancel(t->timerId);
+        break;
+    }
+    case CHRE_EVENT_MESSAGE_FROM_HOST:
+    {
+        const struct chreMessageFromHostData *msg = (const struct chreMessageFromHostData *)evtData;
+        const uint8_t *data = (const uint8_t *)msg->message;
+        const size_t size = msg->messageSize;
+        chreLog(CHRE_LOG_INFO, APP_LABEL "message=%p; code=%d; size=%zu",
+                data, (data && size) ? data[0] : 0, size);
+        break;
+    }
+    }
+}
diff --git a/firmware/app/chre/common/Android.mk b/firmware/app/chre/common/Android.mk
new file mode 100644
index 00000000..9a05b034
--- /dev/null
+++ b/firmware/app/chre/common/Android.mk
@@ -0,0 +1,30 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_PATH := $(call my-dir)
+
+include $(CLEAR_NANO_VARS)
+
+LOCAL_MODULE := libnanochre
+LOCAL_MODULE_TAGS := optional
+
+LOCAL_SRC_FILES :=      \
+    chre_app.c          \
+    chre_app_syscalls.c \
+
+LOCAL_STATIC_LIBRARIES += libnanolibc
+
+include $(BUILD_NANOHUB_APP_STATIC_LIBRARY)
diff --git a/firmware/app/chre/common/chre_app.c b/firmware/app/chre/common/chre_app.c
new file mode 100644
index 00000000..d12941a8
--- /dev/null
+++ b/firmware/app/chre/common/chre_app.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <eventnums.h>
+#include <seos.h>
+#include <timer.h>
+#include <toolchain.h>
+#include <crt_priv.h>
+
+#include <chre.h>
+
+/*
+ * Common CHRE App support code
+ */
+
+static bool chreappStart(uint32_t tid)
+{
+    __crt_init();
+    return nanoappStart();
+}
+
+static void chreappEnd(void)
+{
+    nanoappEnd();
+    __crt_exit();
+}
+
+static void chreappHandle(uint32_t eventTypeAndTid, const void *eventData)
+{
+    uint16_t evt = eventTypeAndTid;
+    uint16_t srcTid = eventTypeAndTid >> 16;
+    const void *data = eventData;
+
+    union EventLocalData {
+    struct chreMessageFromHostData msg;
+    } u;
+
+    switch(evt) {
+    case EVT_APP_TIMER:
+        evt = CHRE_EVENT_TIMER;
+        data = ((struct TimerEvent *)eventData)->data;
+        break;
+    case EVT_APP_FROM_HOST:
+        evt = CHRE_EVENT_MESSAGE_FROM_HOST;
+        data = &u.msg;
+        u.msg.message = (uint8_t*)eventData + 1;
+        u.msg.reservedMessageType = 0;
+        u.msg.messageSize = *(uint8_t*)eventData;
+        break;
+    case EVT_APP_FROM_HOST_CHRE:
+    {
+        const struct NanohubMsgChreHdr *hdr = eventData;
+        evt = CHRE_EVENT_MESSAGE_FROM_HOST;
+        data = &u.msg;
+        u.msg.message = hdr + 1;
+        u.msg.reservedMessageType = hdr->appEvent;
+        u.msg.messageSize = hdr->size;
+        break;
+    }
+    default:
+        // ignore any other system events; OS may send them to any app
+        if (evt < EVT_NO_FIRST_USER_EVENT)
+            return;
+    }
+    nanoappHandleEvent(srcTid, evt, data);
+}
+
+// Collect entry points
+const struct AppFuncs SET_EXTERNAL_APP_ATTRIBUTES(used, section (".app_init"),visibility("default")) _mAppFuncs = {
+    .init   = chreappStart,
+    .end    = chreappEnd,
+    .handle = chreappHandle,
+};
+
+// declare version for compatibility with current runtime
+const uint32_t SET_EXTERNAL_APP_VERSION(used, section (".app_version"), visibility("default")) _mAppVer = 0;
diff --git a/firmware/app/chre/common/chre_app_syscalls.c b/firmware/app/chre/common/chre_app_syscalls.c
new file mode 100644
index 00000000..666bdaed
--- /dev/null
+++ b/firmware/app/chre/common/chre_app_syscalls.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdarg.h>
+
+#include <gpio.h>
+#include <osApi.h>
+#include <sensors.h>
+#include <seos.h>
+#include <util.h>
+
+/* CHRE syscalls */
+#include <chre.h>
+#include <chreApi.h>
+#include <syscall.h>
+#include <syscall_defs.h>
+
+#define SYSCALL_CHRE_API(name) \
+    SYSCALL_NO(SYSCALL_DOMAIN_CHRE, SYSCALL_CHRE_MAIN, SYSCALL_CHRE_MAIN_API, SYSCALL_CHRE_MAIN_API_ ## name)
+
+uint64_t chreGetAppId(void)
+{
+    uint64_t appId = 0;
+    (void)syscallDo1P(SYSCALL_CHRE_API(GET_APP_ID), &appId);
+    return appId;
+}
+
+uint32_t chreGetInstanceId(void)
+{
+    return syscallDo0P(SYSCALL_CHRE_API(GET_INST_ID));
+}
+
+uint64_t chreGetTime(void) {
+    uint64_t time_ns = 0;
+    (void)syscallDo1P(SYSCALL_CHRE_API(GET_TIME), &time_ns);
+    return time_ns;
+}
+
+void chreLog(enum chreLogLevel level, const char *str, ...)
+{
+    va_list vl;
+
+    va_start(vl, str);
+    (void)syscallDo3P(SYSCALL_CHRE_API(LOG), level, str, VA_LIST_TO_INTEGER(vl));
+    va_end(vl);
+}
+
+uint32_t chreTimerSet(uint64_t duration, const void* cookie, bool oneShot)
+{
+    uint32_t dur_lo = duration;
+    uint32_t dur_hi = duration >> 32;
+    return syscallDo4P(SYSCALL_CHRE_API(TIMER_SET), dur_lo, dur_hi, cookie, oneShot);
+}
+
+bool chreTimerCancel(uint32_t timerId)
+{
+    return syscallDo1P(SYSCALL_CHRE_API(TIMER_CANCEL), timerId);
+}
+
+void chreAbort(uint32_t abortCode)
+{
+    (void)syscallDo1P(SYSCALL_CHRE_API(ABORT), abortCode);
+}
+
+void* chreHeapAlloc(uint32_t bytes)
+{
+    return (void *)syscallDo1P(SYSCALL_CHRE_API(HEAP_ALLOC), bytes);
+}
+
+void chreHeapFree(void* ptr)
+{
+    (void)syscallDo1P(SYSCALL_CHRE_API(HEAP_FREE), ptr);
+}
+
+bool chreSensorFindDefault(uint8_t sensorType, uint32_t *handle)
+{
+    return syscallDo2P(SYSCALL_CHRE_API(SENSOR_FIND_DEFAULT), sensorType, handle);
+}
+
+bool chreGetSensorInfo(uint32_t sensorHandle, struct chreSensorInfo *info)
+{
+    return syscallDo2P(SYSCALL_CHRE_API(SENSOR_GET_INFO), sensorHandle, info);
+}
+
+bool chreGetSensorSamplingStatus(uint32_t sensorHandle,
+                                 struct chreSensorSamplingStatus *status)
+{
+    return syscallDo2P(SYSCALL_CHRE_API(SENSOR_GET_STATUS), sensorHandle, status);
+}
+
+bool chreSensorConfigure(uint32_t sensorHandle,
+                         enum chreSensorConfigureMode mode,
+                         uint64_t interval, uint64_t latency)
+{
+    uint32_t interval_lo = interval;
+    uint32_t interval_hi = interval >> 32;
+    uint32_t latency_lo = latency;
+    uint32_t latency_hi = latency >> 32;
+    return syscallDo6P(SYSCALL_CHRE_API(SENSOR_CONFIG), sensorHandle, mode,
+                       interval_lo, interval_hi, latency_lo, latency_hi);
+}
+
+bool chreSendEvent(uint16_t eventType, void *eventData,
+                   chreEventCompleteFunction *freeCallback,
+                   uint32_t targetInstanceId)
+{
+    return syscallDo4P(SYSCALL_CHRE_API(SEND_EVENT), eventType, eventData, freeCallback, targetInstanceId);
+}
+
+bool chreSendMessageToHost(void *message, uint32_t messageSize,
+                           uint32_t reservedMessageType,
+                           chreMessageFreeFunction *freeCallback)
+{
+    return syscallDo4P(SYSCALL_CHRE_API(SEND_MSG), message, messageSize, reservedMessageType, freeCallback);
+}
+
+uint32_t chreGetApiVersion(void)
+{
+    return syscallDo0P(SYSCALL_CHRE_API(GET_OS_API_VERSION));
+}
+
+uint32_t chreGetVersion(void)
+{
+    return syscallDo0P(SYSCALL_CHRE_API(GET_OS_VERSION));
+}
+
+uint64_t chreGetPlatformId(void)
+{
+    uint64_t plat = 0;
+    (void)syscallDo1P(SYSCALL_CHRE_API(GET_PLATFORM_ID), &plat);
+    return plat;
+}
diff --git a/firmware/app/common.mk b/firmware/app/common.mk
deleted file mode 100644
index 81a96240..00000000
--- a/firmware/app/common.mk
+++ /dev/null
@@ -1,38 +0,0 @@
-#
-# Copyright (C) 2016 The Android Open Source Project
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-
-SELF_DIR := $(SELF_MKFILE:Makefile=)
-SELF_FILES := $(wildcard $(SELF_DIR)*.c)
-APP_NM := $(SELF_DIR)app
-CLEANFILES := $(CLEANFILES) $(APP_NM).elf  $(APP_NM).bin
-DELIVERABLES := $(DELIVERABLES) $(APP_NM).napp
-APP_ELF := $(APP_NM).elf
-APP_BIN := $(APP_NM).bin
-APP_APP := $(APP_NM).napp
-APPFLAGS += $(EXTRA_FLAGS) -Wall -Werror
-
-define APPRULE
-$(APP_APP): $(APP_BIN)
-	nanoapp_postprocess -v -a $(APP_ID) $(APP_BIN) $(APP_APP)
-
-$(APP_BIN): $(APP_ELF)
-	$(OBJCOPY) -j.relocs -j.flash -j.data -j.dynsym -O binary $(APP_ELF) $(APP_BIN)
-
-$(APP_ELF): $(SELF_FILES) symlinks
-	$(GCC) -o $(APP_ELF) $(FLAGS) $(APPFLAGS) -fvisibility=hidden $(SELF_FILES)
-endef
-
-$(eval $(APPRULE))
diff --git a/firmware/app/test0.app/Android.mk b/firmware/app/test0.app/Android.mk
new file mode 100644
index 00000000..3e7d6493
--- /dev/null
+++ b/firmware/app/test0.app/Android.mk
@@ -0,0 +1,30 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_PATH := $(call my-dir)
+
+include $(CLEAR_NANO_VARS)
+
+LOCAL_MODULE := test0
+LOCAL_MODULE_TAGS := optional
+
+# Googl + T + 0x8000
+LOCAL_NANO_APP_ID := 476f6f676c548000
+LOCAL_NANO_APP_VERSION := 0
+
+LOCAL_SRC_FILES := test_app0.c
+
+include $(BUILD_NANOHUB_APP_EXECUTABLE)
diff --git a/firmware/app/test0.app/Makefile b/firmware/app/test0.app/Makefile
index 0303b64e..0747921d 100644
--- a/firmware/app/test0.app/Makefile
+++ b/firmware/app/test0.app/Makefile
@@ -14,10 +14,28 @@
 # limitations under the License.
 #
 
-#makefile for test0 app
+################################################################################
+#
+# test NanoApp Makefile
+#
+################################################################################
 
-SELF_MKFILE := $(abspath $(lastword $(MAKEFILE_LIST)))
-# Googl + T + 0x8000
+
+SRCS := test_app0.c
+BIN := test0
 APP_ID := 476f6f676c548000
+APP_VERSION := 0
+
+# Nanohub relative path
+NANOHUB_DIR := ../..
+
+# Device configuration #########################################################
+
+# select device variant for this app
+# if there is no path of the form $(NANOHUB_DIR)/variant/$(VARIANT), the
+# VARIANT_PATH variable must be set to ANDROID_TOP-relative valid path containing VARIANT subtree
+
+TARGET_PRODUCT ?= nucleo
+VARIANT := $(TARGET_PRODUCT)
 
-include app/common.mk
+include $(NANOHUB_DIR)/app/app.mk
diff --git a/firmware/app/test0.app/test_app0.c b/firmware/app/test0.app/test_app0.c
index 9ea84179..1c02d159 100644
--- a/firmware/app/test0.app/test_app0.c
+++ b/firmware/app/test0.app/test_app0.c
@@ -58,7 +58,7 @@ static void handle_event(uint32_t evtType, const void* evtData)
         te = evtData;
         eOsLog(LOG_INFO, "App 0 received timer %u callback: %d (TIM: %lld, RTC: %lld, SENSOR: %lld, HOST: %lld)\n", te->timerId, *(int *)te->data, eOsTimGetTime(), eOsRtcGetTime(), eOsSensorGetTime(), eOsHostGetTime());
         extMsg = eOsHeapAlloc(sizeof(*extMsg));
-        extMsg->hdr.appId = APP_ID_MAKE(APP_ID_VENDOR_GOOGLE, 0x548000);
+        extMsg->hdr.appId = APP_ID_MAKE(NANOHUB_VENDOR_GOOGLE, 0x548000);
         extMsg->hdr.dataLen = 5;
         extMsg->msg = 0x01;
         extMsg->val = *(int *)te->data;
diff --git a/firmware/app/test1.app/Android.mk b/firmware/app/test1.app/Android.mk
new file mode 100644
index 00000000..7d04e3c6
--- /dev/null
+++ b/firmware/app/test1.app/Android.mk
@@ -0,0 +1,30 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_PATH := $(call my-dir)
+
+include $(CLEAR_NANO_VARS)
+
+LOCAL_MODULE := test1
+LOCAL_MODULE_TAGS := optional
+
+# Googl + T + 0x8000
+LOCAL_NANO_APP_ID := 476f6f676c548001
+LOCAL_NANO_APP_VERSION := 0
+
+LOCAL_SRC_FILES := test_app1.c
+
+include $(BUILD_NANOHUB_APP_EXECUTABLE)
diff --git a/firmware/app/test1.app/Makefile b/firmware/app/test1.app/Makefile
index 8cade3f9..b7e224e4 100644
--- a/firmware/app/test1.app/Makefile
+++ b/firmware/app/test1.app/Makefile
@@ -14,10 +14,30 @@
 # limitations under the License.
 #
 
-#makefile for test1 app
+################################################################################
+#
+# test1 NanoApp Makefile
+#
+################################################################################
+
+# Device configuration #########################################################
+
+SRCS := test_app1.c
+BIN := test1
 
-SELF_MKFILE := $(abspath $(lastword $(MAKEFILE_LIST)))
-# Googl + T + 0x8001
 APP_ID := 476f6f676c548001
+APP_VERSION := 0
+
+# Nanohub relative path
+NANOHUB_DIR := ../..
+
+# Device configuration #########################################################
+
+# select device variant for this app
+# if there is no path of the form $(NANOHUB_DIR)/variant/$(VARIANT), the
+# VARIANT_PATH variable must be set to ANDROID_TOP-relative valid path containing VARIANT subtree
+
+TARGET_PRODUCT ?= nucleo
+VARIANT := $(TARGET_PRODUCT)
 
-include app/common.mk
+include $(NANOHUB_DIR)/app/app.mk
diff --git a/firmware/build/app_chre_executable.mk b/firmware/build/app_chre_executable.mk
new file mode 100644
index 00000000..1007ec75
--- /dev/null
+++ b/firmware/build/app_chre_executable.mk
@@ -0,0 +1,39 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_MODULE_SUFFIX := .napp
+include $(NANOHUB_APP_CONFIG)
+
+my_variants := $(LOCAL_NANO_VARIANT_LIST)
+
+ifeq ($(strip $(my_variants)),)
+# default is to use all variants supported by this OS
+my_variants := $(AUX_OS_VARIANT_LIST_$(NANO_OS))
+endif
+
+# mark the app as CHRE nanoapp
+LOCAL_NANO_APP_POSTPROCESS_FLAGS += -f 0x10
+
+# add app-side CHRE implementation
+LOCAL_WHOLE_STATIC_LIBRARIES += \
+    libnanochre                 \
+
+# add standard libaries
+LOCAL_STATIC_LIBRARIES +=       \
+    libnanolibc                 \
+    libnanolibm                 \
+
+$(call for-each-variant,$(my_variants),APP,$(BUILD_NANOHUB_EXECUTABLE))
diff --git a/firmware/build/app_config.mk b/firmware/build/app_config.mk
new file mode 100644
index 00000000..1bb4177d
--- /dev/null
+++ b/firmware/build/app_config.mk
@@ -0,0 +1,37 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+include $(NANO_BUILD)/common_config.mk
+
+LOCAL_CFLAGS_cortexm4 +=                        \
+    -fpic                                       \
+    -mno-pic-data-is-text-relative              \
+    -msingle-pic-base                           \
+    -mpic-register=r9                           \
+
+LOCAL_NANO_MODULE_TYPE := APP
+LOCAL_OBJCOPY_SECT_cortexm4 := .flash .data .relocs .dynsym
+LOCAL_FORCE_STATIC_EXECUTABLE := false
+
+LOCAL_CFLAGS +=                                 \
+    -DAPP_ID=$(LOCAL_NANO_APP_ID)               \
+    -DAPP_VERSION=$(LOCAL_NANO_APP_VERSION)     \
+    -D__NANOHUB__                               \
+
+# Optimization/debug
+LOCAL_CFLAGS += \
+    -Os \
+    -g \
diff --git a/firmware/build/app_executable.mk b/firmware/build/app_executable.mk
new file mode 100644
index 00000000..bfd031df
--- /dev/null
+++ b/firmware/build/app_executable.mk
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_MODULE_SUFFIX := .napp
+include $(NANOHUB_APP_CONFIG)
+
+my_variants := $(LOCAL_NANO_VARIANT_LIST)
+
+ifeq ($(strip $(my_variants)),)
+# default is to use all variants supported by this OS
+my_variants := $(AUX_OS_VARIANT_LIST_$(NANO_OS))
+endif
+
+$(call for-each-variant,$(my_variants),APP,$(BUILD_NANOHUB_EXECUTABLE))
diff --git a/firmware/build/app_static_library.mk b/firmware/build/app_static_library.mk
new file mode 100644
index 00000000..0eed67ac
--- /dev/null
+++ b/firmware/build/app_static_library.mk
@@ -0,0 +1,26 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+include $(NANOHUB_APP_CONFIG)
+
+my_variants := $(LOCAL_NANO_VARIANT_LIST)
+
+ifeq ($(strip $(my_variants)),)
+# default is to use all variants supported by this OS
+my_variants := $(AUX_OS_VARIANT_LIST_$(NANO_OS))
+endif
+
+$(call for-each-variant,$(my_variants),,$(NANO_BUILD)/nanohub_static_library.mk)
diff --git a/firmware/build/bl_config.mk b/firmware/build/bl_config.mk
new file mode 100644
index 00000000..60af389e
--- /dev/null
+++ b/firmware/build/bl_config.mk
@@ -0,0 +1,29 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+include $(NANO_BUILD)/common_config.mk
+
+LOCAL_CFLAGS += \
+    -g \
+    -ggdb3 \
+    -D_OS_BUILD_ \
+    -O2
+
+LOCAL_CFLAGS_x86 += \
+    -m32
+
+LOCAL_NANO_MODULE_TYPE := BL
+LOCAL_FORCE_STATIC_EXECUTABLE := true
diff --git a/firmware/build/bl_executable.mk b/firmware/build/bl_executable.mk
new file mode 100644
index 00000000..4cbcfb24
--- /dev/null
+++ b/firmware/build/bl_executable.mk
@@ -0,0 +1,28 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_MODULE_SUFFIX := .bin
+
+include $(NANOHUB_BL_CONFIG)
+
+my_variants := $(LOCAL_NANO_VARIANT_LIST)
+
+ifeq ($(strip $(my_variants)),)
+# default is to use all variants supported by this OS
+my_variants := $(AUX_OS_VARIANT_LIST_$(NANO_OS))
+endif
+
+$(call for-each-variant,$(my_variants),BL,$(NANO_BUILD)/bl_executable_internal.mk)
diff --git a/firmware/build/bl_executable_internal.mk b/firmware/build/bl_executable_internal.mk
new file mode 100644
index 00000000..23f685f9
--- /dev/null
+++ b/firmware/build/bl_executable_internal.mk
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+ifeq ($(strip $(NANO_VARIANT_NO_BOOTLOADER_$(AUX_OS_VARIANT))),)
+
+LOCAL_WHOLE_STATIC_LIBRARIES += libnanohub_bl_$(AUX_CPU)
+LOCAL_WHOLE_STATIC_LIBRARIES += libnanohub_bl_$(AUX_ARCH)
+LOCAL_WHOLE_STATIC_LIBRARIES += $(NANO_VARIANT_BLCFG_STATIC_LIBRARIES_$(AUX_OS_VARIANT))
+
+LOCAL_SRC_FILES += $(NANO_VARIANT_BLCFG_SRC_FILES_$(AUX_OS_VARIANT))
+
+include $(BUILD_NANOHUB_EXECUTABLE)
+
+endif
diff --git a/firmware/build/bl_static_library.mk b/firmware/build/bl_static_library.mk
new file mode 100644
index 00000000..ead85c6c
--- /dev/null
+++ b/firmware/build/bl_static_library.mk
@@ -0,0 +1,26 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+include $(NANOHUB_BL_CONFIG)
+
+my_variants := $(LOCAL_NANO_VARIANT_LIST)
+
+ifeq ($(strip $(my_variants)),)
+# default is to use all variants supported by this OS
+my_variants := $(AUX_OS_VARIANT_LIST_$(NANO_OS))
+endif
+
+$(call for-each-variant,$(my_variants),BL,$(NANO_BUILD)/nanohub_static_library.mk)
diff --git a/firmware/build/clear_vars.mk b/firmware/build/clear_vars.mk
new file mode 100644
index 00000000..333602ec
--- /dev/null
+++ b/firmware/build/clear_vars.mk
@@ -0,0 +1,28 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+# used by NANOAPP and NANOHUB OS
+LOCAL_NANO_MODULE_TYPE :=
+LOCAL_NANO_IS_VARIANT :=
+
+# used by NANOAPP only
+LOCAL_NANO_APP_ID :=
+LOCAL_NANO_APP_VERSION :=
+LOCAL_NANO_APP_NO_POSTPROCESS :=
+LOCAL_NANO_APP_UNSIGNED :=
+LOCAL_NANO_APP_POSTPROCESS_FLAGS :=
+
+include $(CLEAR_VARS)
diff --git a/firmware/build/common_config.mk b/firmware/build/common_config.mk
new file mode 100644
index 00000000..b7731456
--- /dev/null
+++ b/firmware/build/common_config.mk
@@ -0,0 +1,72 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_CFLAGS += \
+    -Wall \
+    -Werror \
+    \
+    -Waddress \
+    -Wempty-body \
+    -Wenum-compare \
+    -Wlogical-op \
+    -Wmissing-declarations \
+    -Wpointer-arith \
+    -Wshadow \
+    \
+    -fdata-sections \
+    -ffunction-sections \
+    -fno-strict-aliasing \
+    -fno-unwind-tables \
+    -fstack-reuse=all \
+    -fvisibility=hidden \
+
+LOCAL_CPPFLAGS +=       \
+    -std=c++11          \
+    -fno-exceptions     \
+    -fno-rtti           \
+
+LOCAL_LDFLAGS +=                        \
+    -nostartfiles                       \
+    -Wl,--gc-sections                   \
+    -Wl,--no-undefined                  \
+    -Wl,--no-allow-shlib-undefined      \
+
+LOCAL_CFLAGS_cortexm4 += \
+    -mthumb \
+    -mcpu=cortex-m4 \
+    -march=armv7e-m \
+    -mfloat-abi=softfp \
+    -mfpu=fpv4-sp-d16 \
+    -mno-thumb-interwork \
+    -ffast-math \
+    -fshort-double \
+    -fsingle-precision-constant \
+    -DARM \
+    -DUSE_NANOHUB_FLOAT_RUNTIME \
+    -DARM_MATH_CM4 \
+    -D__FPU_PRESENT \
+    -DCPU_NUM_PERSISTENT_RAM_BITS=32 \
+
+LOCAL_CFLAGS_x86 += \
+    -march=core2 \
+    -msse2 \
+    -DSYSCALL_VARARGS_PARAMS_PASSED_AS_PTRS \
+
+LOCAL_CFLAGS_stm32 += \
+    -DPLATFORM_HW_VER=0 \
+
+# CHRE-specific
+LOCAL_CFLAGS += -DCHRE_MESSAGE_TO_HOST_MAX_SIZE=128
diff --git a/firmware/build/config.mk b/firmware/build/config.mk
new file mode 100644
index 00000000..e7dbbe45
--- /dev/null
+++ b/firmware/build/config.mk
@@ -0,0 +1,215 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+NANO_BUILD := $(NANOHUB_OS_PATH)/build
+
+NANO_OS := nanohub
+NANO_ALL_CLASSES := phone watch
+NANO_ALL_TARGETS := APP BL OS
+
+NANO_ALL_ALL := $(AUX_ALL_VARIANTS) $(AUX_ALL_OSES) $(AUX_ALL_ARCHS) $(AUX_ALL_SUBARCHS) $(AUX_ALL_CPUS) $(NANO_ALL_CLASSES) $(NANO_ALL_TARGETS)
+
+GLOBAL_NANO_OBJCOPY_FLAGS_cortexm4 := -I elf32-littlearm -O binary
+
+CLEAR_NANO_VARS := $(NANO_BUILD)/clear_vars.mk
+NANOHUB_BL_CONFIG := $(NANO_BUILD)/bl_config.mk
+NANOHUB_OS_CONFIG := $(NANO_BUILD)/os_config.mk
+NANOHUB_APP_CONFIG := $(NANO_BUILD)/app_config.mk
+
+BUILD_NANOHUB_BL_STATIC_LIBRARY := $(NANO_BUILD)/bl_static_library.mk
+BUILD_NANOHUB_OS_STATIC_LIBRARY := $(NANO_BUILD)/os_static_library.mk
+BUILD_NANOHUB_APP_STATIC_LIBRARY := $(NANO_BUILD)/app_static_library.mk
+BUILD_NANOHUB_EXECUTABLE := $(NANO_BUILD)/nanohub_executable.mk
+BUILD_NANOHUB_BL_EXECUTABLE := $(NANO_BUILD)/bl_executable.mk
+BUILD_NANOHUB_OS_EXECUTABLE := $(NANO_BUILD)/os_executable.mk
+BUILD_NANOHUB_OS_IMAGE := $(NANO_BUILD)/os_image.mk
+BUILD_NANOHUB_APP_EXECUTABLE := $(NANO_BUILD)/app_executable.mk
+BUILD_NANOHUB_APP_CHRE_EXECUTABLE := $(NANO_BUILD)/app_chre_executable.mk
+
+NANOAPP_POSTPROCESS := $(HOST_OUT_EXECUTABLES)/nanoapp_postprocess
+NANOAPP_SIGN := $(HOST_OUT_EXECUTABLES)/nanoapp_sign
+
+# $(1) - optional value to assign to
+#        pass empty to clear for repeated includes
+#        pass some definitive invalid value otherwise (after last repeat)
+define nano-reset-built-env
+$(eval OVERRIDE_BUILT_MODULE_PATH:=$(1)) \
+$(eval LOCAL_BUILT_MODULE:=$(1)) \
+$(eval LOCAL_INSTALLED_MODULE:=$(1)) \
+$(eval LOCAL_INTERMEDIATE_TARGETS:=$(1))
+endef
+
+# variant may declare it's class; default is phone
+define nano-variant-class
+$(if $(filter $(NANO_ALL_CLASSES),$(NANO_CLASS_$(AUX_OS_VARIANT))),$(NANO_CLASS_$(AUX_OS_VARIANT)),phone)
+endef
+
+# $(1) - target file
+# $(2) - list of dependencies
+define nano-gen-linker-script-from-list-body
+    mkdir -p $(dir $(1)) && \
+    rm -f $(1).tmp && \
+    touch $(1).tmp && \
+    $(foreach file,$(2),echo "INCLUDE $(file)"  >> $(1).tmp &&) \
+    mv -f $(1).tmp $(1)
+endef
+
+# $(1) - target file
+# $(2) - list of dependencies
+define nano-gen-linker-script-from-list
+$(1): $(2)
+	$(call nano-gen-linker-script-from-list-body,$(1),$(2))
+endef
+
+# create linker script rule
+#
+# $(1) - target file
+# $(2) - { os | bl }
+# $(3) - platform name
+# $(4) - platform class
+# $(5) - platform dir
+define nano-gen-linker-script
+$(eval $(call nano-gen-linker-script-from-list,$(1),$(patsubst %,$(NANOHUB_OS_PATH)/os/platform/$(5)/lkr/%.lkr,$(3).map $(4).$(2) $(4).common)))
+endef
+
+# create linker script rule
+#
+# $(1) - target file
+# $(2) - bl|os
+# $(3) - platform name
+# $(4) - platform class
+# $(5) - platform dir
+#
+# NOTE: ($(2), $(3) - unused; keep for argument compatibility with nano-gen-linker-script
+define nano-gen-linker-script-native
+$(eval $(call nano-gen-linker-script-from-list,$(1),$(NANOHUB_OS_PATH)/os/platform/$(5)/lkr/$(4).extra.lkr))
+endef
+
+# variables that Android.mk or our config files may define per-cpu, per-arch etc;
+# must include all LOCAL* variables we modify in any place within the scope of for-each-variant.
+#
+# workflow is as follows:
+# before starting iterations:
+#   all the LOCAL_<var> and LOCAL_<var>_<cpu,arch,subarch,variant,os,class> from NANO_VAR_LIST
+#   are copied to LOCAL_NANO_*; original LOCAL_* are erased to avoid conflicts fith underlaying build which also does suffix handling.
+#   this part is performed by nano-user-vars-save-all
+# on every iteration, before includeing file:
+#   all the LOCAL_NANO_<var>_<cpu,arch,subarch,variant,os,class> vars are loaded for the current variant,
+#   and then concatenated all toghether and also with
+#   NANO_VARIANT_<target>_<var>_<variant> (where target is OS or BL for system builds, or APP for nanoapp builds) and
+#   NANO_VARIANT_<var>_<variant>; result is stored in LOCAL_<var>
+#   this var is used by underlaying build infrastructure as usual
+#   this part is performed by nano-user-vars-load-all
+# on every iteration, after includeing file:
+#   reset "BUILT" variables in order to let next iteration going
+# after all iterations done:
+#   erase all volatile AUX* enviraonment, cleanup all the LOCAL* and LOCAL_NANO* vars
+NANO_VAR_LIST :=                \
+    C_INCLUDES                  \
+    CFLAGS                      \
+    ASFLAGS                     \
+    CPPFLAGS                    \
+    SRC_FILES                   \
+    STATIC_LIBRARIES            \
+    WHOLE_STATIC_LIBRARIES      \
+    LDFLAGS                     \
+    OBJCOPY_SECT                \
+
+# collect anything that user might define per-cpu, per-arch etc
+# $(1) - one of $(NANO_VAR_LIST)
+# $(2) - optional: one of { APP,BL,OS }
+define nano-user-var-load
+$(eval LOCAL_$(1) :=                                                    \
+    $(LOCAL_NANO_$(1))                                                  \
+    $(NANO_VARIANT_$(1)_$(AUX_OS_VARIANT))                              \
+    $(NANO_VARIANT_$(2)_$(1)_$(AUX_OS_VARIANT))                         \
+    $(LOCAL_NANO_$(1)_$(AUX_OS_VARIANT))                                \
+    $(LOCAL_NANO_$(1)_$(AUX_CPU))                                       \
+    $(LOCAL_NANO_$(1)_$(AUX_ARCH))                                      \
+    $(LOCAL_NANO_$(1)_$(AUX_SUBARCH))                                   \
+    $(LOCAL_NANO_$(1)_$(AUX_OS))                                        \
+    $(LOCAL_NANO_$(1)_$(call nano-variant-class,$(AUX_OS_VARIANT)))     \
+    $(LOCAL_NANO_$(1)_$(LOCAL_NANO_MODULE_TYPE))                        \
+)
+endef
+
+define nano-user-var-reset-final
+$(eval LOCAL_$(1):=) \
+$(eval LOCAL_NANO_$(1):=) \
+$(foreach v,$(NANO_ALL_ALL),\
+    $(eval LOCAL_NANO_$(1)_$(v):=) \
+    $(eval LOCAL_$(1)_$(v):=) \
+)
+endef
+
+define nano-user-vars-reset-final
+$(foreach _nuvrf_var,$(NANO_VAR_LIST),$(call nano-user-var-reset-final,$(_nuvrf_var)))
+endef
+
+# $(1) - optional: one of APP,BL,OS
+define nano-user-vars-load-all
+$(foreach _nuvla_var,$(NANO_VAR_LIST),$(call nano-user-var-load,$(_nuvla_var),$(1)))
+endef
+
+define nano-user-vars-save-all
+$(foreach _nuvsa_var,$(NANO_VAR_LIST),\
+    $(eval LOCAL_NANO_$(_nuvsa_var) := $(LOCAL_$(_nuvsa_var))) \
+    $(eval LOCAL_$(_nuvsa_var):=) \
+    $(foreach v,$(NANO_ALL_ALL),\
+        $(eval LOCAL_NANO_$(_nuvsa_var)_$(v):=$(LOCAL_$(_nuvsa_var)_$(v))) \
+        $(eval LOCAL_$(_nuvsa_var)_$(v):=) \
+    ) \
+)
+endef
+
+# $(1) - variant list
+# $(2) - optional: one of APP,BL,OS
+# $(3) - path to makefile which has to be included for each variant
+define for-each-variant-unchecked
+    $(eval AUX_RECURSIVE_VARIANT_LIST:=$(1)) \
+    $(call nano-user-vars-save-all) \
+    $(foreach _fev_variant,$(1),\
+        $(call aux-variant-load-env,$(_fev_variant)) \
+        $(call nano-user-vars-load-all,$(2)) \
+        $(info $(LOCAL_PATH): $(LOCAL_MODULE): OS=$(AUX_OS) ARCH=$(AUX_ARCH) SUBARCH=$(AUX_SUBARCH) CPU=$(AUX_CPU)) \
+        $(eval include $(3)) \
+        $(call nano-reset-built-env,) \
+    ) \
+    $(eval AUX_RECURSIVE_VARIANT_LIST:=) \
+    $(call aux-variant-load-env,) \
+    $(call nano-reset-built-env,$(LOCAL_MODULE)-module-is-poisoned) \
+    $(call nano-user-vars-reset-final) \
+
+endef
+
+# $(1),$(2) - two sets to compare for equality
+# returns true, if sets have the same items (not necessarily in the same order)
+# returns empty string on mismatch
+define equal-sets
+$(if $(strip $(filterout $(1),$(2))$(filterout $(2),$(1))),,true)
+endef
+
+# this call would include a given makefile in the loop,
+# and would iterate through available variants from $(1)
+# $(1) - variant list
+# $(2) - optional: one of APP,BL,OS
+# $(3) - path to makefile to include for each variant
+define for-each-variant
+$(if $(AUX_RECURSIVE_VARIANT_LIST),$(if \
+        $(call equal-sets,$(AUX_RECURSIVE_VARIANT_LIST),$(1)),,\
+        $(error $(LOCAL_PATH): Recursive variant list mismatch: "$(AUX_RECURSIVE_VARIANT_LIST)" and "$(1))),\
+    $(call for-each-variant-unchecked,$(1),$(2),$(3)))
+endef
diff --git a/firmware/build/config_internal.mk b/firmware/build/config_internal.mk
new file mode 100644
index 00000000..533d38f5
--- /dev/null
+++ b/firmware/build/config_internal.mk
@@ -0,0 +1,28 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_C_INCLUDES +=                                     \
+    $(NANOHUB_OS_PATH)/os/inc                           \
+    $(NANOHUB_OS_PATH)/os/platform/$(AUX_ARCH)/inc      \
+    $(NANOHUB_OS_PATH)/os/cpu/$(AUX_CPU)/inc            \
+    $(NANOHUB_OS_PATH)/../lib/include                   \
+    $(NANOHUB_OS_PATH)/../inc                           \
+
+LOCAL_WHOLE_STATIC_LIBRARIES_BL += libnanohub_bl_$(AUX_CPU)
+LOCAL_WHOLE_STATIC_LIBRARIES_BL += libnanohub_bl_$(AUX_ARCH)
+
+LOCAL_WHOLE_STATIC_LIBRARIES_OS += libnanohub_os_$(AUX_CPU)
+LOCAL_WHOLE_STATIC_LIBRARIES_OS += libnanohub_os_$(AUX_ARCH)
diff --git a/firmware/build/nanohub_executable.mk b/firmware/build/nanohub_executable.mk
new file mode 100644
index 00000000..b1e6ce69
--- /dev/null
+++ b/firmware/build/nanohub_executable.mk
@@ -0,0 +1,143 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+include $(BUILD_SYSTEM)/aux_toolchain.mk
+
+ifeq ($(AUX_BUILD_NOT_COMPATIBLE),)
+
+include $(NANO_BUILD)/config_internal.mk
+
+intermediates := $(call intermediates-dir-for,EXECUTABLES,$(LOCAL_MODULE),AUX)
+
+nanohub_linked_map := $(intermediates)/LINKED/$(LOCAL_MODULE).map
+nanohub_unchecked_elf := $(intermediates)/UNCHECKED/$(LOCAL_MODULE).elf
+nanohub_checked_elf := $(intermediates)/CHECKED/$(LOCAL_MODULE).elf
+nanohub_checked_bin := $(intermediates)/CHECKED/$(LOCAL_MODULE).bin
+
+LOCAL_CUSTOM_BUILD_STEP_INPUT := $(nanohub_unchecked_elf)
+
+
+gen := $(call generated-sources-dir-for,EXECUTABLES,$(LOCAL_MODULE),AUX)
+
+linker_script:=
+
+ifeq ($(LOCAL_NANO_MODULE_TYPE),APP)
+linker_script := $(NANOHUB_OS_PATH)/os/platform/$(AUX_ARCH)/lkr/app.lkr
+endif
+
+ifeq ($(LOCAL_NANO_MODULE_TYPE),BL)
+ifeq ($(AUX_ARCH),stm32)
+linker_script := $(gen)/bl.lkr
+$(call nano-gen-linker-script,$(linker_script),bl,$(AUX_SUBARCH),stm32f4xx,$(AUX_ARCH))
+endif
+endif
+
+ifeq ($(LOCAL_NANO_MODULE_TYPE),OS)
+ifeq ($(AUX_ARCH),native)
+linker_script := $(gen)/os.lkr
+$(call nano-gen-linker-script-native,$(linker_script),os,$(AUX_SUBARCH),native,$(AUX_ARCH))
+endif
+ifeq ($(AUX_ARCH),stm32)
+linker_script := $(gen)/os.lkr
+$(call nano-gen-linker-script,$(linker_script),os,$(AUX_SUBARCH),stm32f4xx,$(AUX_ARCH))
+endif
+endif
+
+ifeq ($(linker_script),)
+$(error $(LOCAL_PATH): $(LOCAL_MODULE): linker script is not defined for ARCH=$(AUX_ARCH) TYPE=$(LOCAL_NANO_MODULE_TYPE))
+endif
+
+LOCAL_ADDITIONAL_DEPENDENCIES += $(linker_script)
+LOCAL_LDFLAGS += -T $(linker_script)
+
+$(nanohub_checked_elf): $(nanohub_unchecked_elf)
+	$(hide)echo "nanohub Symcheck $@ <= $<"
+	$(copy-file-to-target)
+nanohub_output := $(nanohub_checked_elf)
+
+# objcopy is per-cpu only
+objcopy_params:=
+
+# optional objcopy step
+ifneq ($(strip $(LOCAL_OBJCOPY_SECT)),)
+
+objcopy_params := $(GLOBAL_NANO_OBJCOPY_FLAGS) $(GLOBAL_NANO_OBJCOPY_FLAGS_$(AUX_CPU)) $(foreach sect,$(LOCAL_OBJCOPY_SECT), -j $(sect))
+
+$(nanohub_checked_bin): PRIVATE_OBJCOPY_ARGS := $(objcopy_params)
+$(nanohub_checked_bin): PRIVATE_MODULE := $(LOCAL_MODULE)
+$(nanohub_checked_bin): PRIVATE_OBJCOPY := $(AUX_OBJCOPY)
+$(nanohub_checked_bin): $(nanohub_output)
+	$(hide)echo "nanohub OBJCOPY $(PRIVATE_MODULE) ($@)"
+	$(hide)$(PRIVATE_OBJCOPY) $(PRIVATE_OBJCOPY_ARGS) $< $@
+nanohub_output := $(nanohub_checked_bin)
+
+objcopy_params :=
+objcopy_sect :=
+else
+LOCAL_NANO_APP_NO_POSTPROCESS := true
+LOCAL_NANO_APP_UNSIGNED := true
+endif
+
+ifeq ($(LOCAL_NANO_MODULE_TYPE),APP)
+
+nanohub_napp := $(intermediates)/CHECKED/$(LOCAL_MODULE).napp
+nanohub_signed_napp := $(intermediates)/CHECKED/$(LOCAL_MODULE).signed.napp
+
+# postprocess only works on BIN; if it is used, objcopy must be used as well
+ifneq ($(LOCAL_NANO_APP_NO_POSTPROCESS),true)
+$(if $(LOCAL_OBJCOPY_SECT),,\
+    $(error $(LOCAL_PATH): $(LOCAL_MODULE): nanoapp postprocess step requires LOCAL_OBJCOPY_SECT defined))
+
+$(nanohub_napp): PRIVATE_NANO_APP_ID  := $(LOCAL_NANO_APP_ID)
+$(nanohub_napp): PRIVATE_NANO_APP_VER := $(LOCAL_NANO_APP_VERSION)
+$(nanohub_napp): PRIVATE_NANO_APP_POSTPROCESS_FLAGS := $(LOCAL_NANO_APP_POSTPROCESS_FLAGS)
+
+$(nanohub_napp): $(nanohub_output) $(NANOAPP_POSTPROCESS)
+	$(hide)echo "nanoapp POSTPROCESS $@ <= $<"
+	$(hide)$(NANOAPP_POSTPROCESS) -a $(PRIVATE_NANO_APP_ID) $(PRIVATE_NANO_APP_POSTPROCESS_FLAGS) $< $@
+nanohub_output := $(nanohub_napp)
+endif # NO_POSTPROCESS
+
+ifneq ($(LOCAL_NANO_APP_UNSIGNED),true)
+$(if $(filter true,$(LOCAL_NANO_APP_NO_POSTPROCESS)),\
+    $(error $(LOCAL_PATH): $(LOCAL_MODULE): nanoapp sign step requires nanoapp postprocess))
+
+nanohub_pvt_key := $(NANOHUB_OS_PATH)/os/platform/$(AUX_ARCH)/misc/debug.privkey
+nanohub_pub_key := $(NANOHUB_OS_PATH)/os/platform/$(AUX_ARCH)/misc/debug.pubkey
+
+$(nanohub_signed_napp): PRIVATE_PVT_KEY := $(nanohub_pvt_key)
+$(nanohub_signed_napp): PRIVATE_PUB_KEY := $(nanohub_pub_key)
+
+$(nanohub_signed_napp): $(nanohub_napp) $(NANOAPP_SIGN)
+	$(hide)echo "nanoapp SIGN $@ <= $<"
+	$(hide)$(NANOAPP_SIGN) -s -e $(PRIVATE_PVT_KEY) -m $(PRIVATE_PUB_KEY) $< $@
+
+nanohub_output := $(nanohub_signed_napp)
+endif # !UNSIGNED
+
+endif # TYPE == APP
+
+LOCAL_CUSTOM_BUILD_STEP_OUTPUT := $(nanohub_output)
+LOCAL_LDFLAGS += -Wl,-Map,$(nanohub_linked_map)
+
+###############################
+include $(BUILD_AUX_EXECUTABLE)
+###############################
+
+LOCAL_CUSTOM_BUILD_STEP_INPUT :=
+LOCAL_CUSTOM_BUILD_STEP_OUTPUT :=
+
+endif # AUX_BUILD_NOT_COMPATIBLE
diff --git a/firmware/app/external.app/Makefile b/firmware/build/nanohub_static_library.mk
index 7b3ae790..8421b6b0 100644
--- a/firmware/app/external.app/Makefile
+++ b/firmware/build/nanohub_static_library.mk
@@ -14,13 +14,11 @@
 # limitations under the License.
 #
 
-#makefile for all extrernal appspop app
+include $(BUILD_SYSTEM)/aux_toolchain.mk
 
-EXTRA_FLAGS ?= 
+ifeq ($(AUX_BUILD_NOT_COMPATIBLE),)
 
-ifneq ($(EXTERNAL_APP_BUILD),)
- SELF_MKFILE := $(EXTERNAL_APP_MAKEFILE)
- APP_ID := $(EXTERNAL_APP_ID)
- include app/common.mk
-endif
+include $(NANO_BUILD)/config_internal.mk
+include $(BUILD_AUX_STATIC_LIBRARY)
 
+endif # AUX_BUILD_NOT_COMPATIBLE
diff --git a/firmware/build/os_config.mk b/firmware/build/os_config.mk
new file mode 100644
index 00000000..2415711e
--- /dev/null
+++ b/firmware/build/os_config.mk
@@ -0,0 +1,29 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+include $(NANO_BUILD)/common_config.mk
+
+LOCAL_CFLAGS += \
+    -g \
+    -ggdb3 \
+    -D_OS_BUILD_ \
+    -O2
+
+LOCAL_CFLAGS_x86 += \
+    -m32
+
+LOCAL_NANO_MODULE_TYPE := OS
+LOCAL_FORCE_STATIC_EXECUTABLE := true
diff --git a/firmware/build/os_executable.mk b/firmware/build/os_executable.mk
new file mode 100644
index 00000000..14786643
--- /dev/null
+++ b/firmware/build/os_executable.mk
@@ -0,0 +1,28 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_MODULE_SUFFIX := .bin
+
+include $(NANOHUB_OS_CONFIG)
+
+my_variants := $(LOCAL_NANO_VARIANT_LIST)
+
+ifeq ($(strip $(my_variants)),)
+# default is to use all variants supported by this OS
+my_variants := $(AUX_OS_VARIANT_LIST_$(NANO_OS))
+endif
+
+$(call for-each-variant,$(my_variants),OS,$(NANO_BUILD)/os_executable_internal.mk)
diff --git a/firmware/build/os_executable_internal.mk b/firmware/build/os_executable_internal.mk
new file mode 100644
index 00000000..3acd8ad6
--- /dev/null
+++ b/firmware/build/os_executable_internal.mk
@@ -0,0 +1,44 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_WHOLE_STATIC_LIBRARIES += libnanohub_os_$(AUX_CPU)
+LOCAL_WHOLE_STATIC_LIBRARIES += libnanohub_os_$(AUX_ARCH)
+LOCAL_WHOLE_STATIC_LIBRARIES += $(NANO_VARIANT_OSCFG_STATIC_LIBRARIES_$(AUX_OS_VARIANT))
+
+LOCAL_SRC_FILES += $(NANO_VARIANT_OSCFG_SRC_FILES_$(AUX_OS_VARIANT))
+
+include $(BUILD_NANOHUB_EXECUTABLE)
+
+ifeq ($(AUX_BUILD_NOT_COMPATIBLE),)
+
+INSTALLED_AUX_TARGETS += $(AUX_OUT_EXECUTABLES_$(AUX_OS_VARIANT))/nanohub.full.bin
+
+nano_bl_bin := $(AUX_OUT_EXECUTABLES_$(AUX_OS_VARIANT))/nanohub_bl.bin
+nano_os_bin := $(AUX_OUT_EXECUTABLES_$(AUX_OS_VARIANT))/nanohub_os.bin
+
+nano_os_components :=
+
+ifneq ($(NANO_VARIANT_NO_BOOTLOADER_$(AUX_OS_VARIANT)),true)
+nano_os_components += $(nano_bl_bin)
+endif
+
+nano_os_components += $(nano_os_bin)
+
+$(AUX_OUT_EXECUTABLES_$(AUX_OS_VARIANT))/nanohub.full.bin: $(nano_os_components)
+	@echo "$(AUX_DISPLAY) GEN NANOHUB OS IMAGE: $(notdir $@) <= $(foreach f,$^,$(notdir $(f))")
+	$(hide) cat $^ > $@
+
+endif
diff --git a/firmware/build/os_static_library.mk b/firmware/build/os_static_library.mk
new file mode 100644
index 00000000..0299a253
--- /dev/null
+++ b/firmware/build/os_static_library.mk
@@ -0,0 +1,26 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+include $(NANOHUB_OS_CONFIG)
+
+my_variants := $(LOCAL_NANO_VARIANT_LIST)
+
+ifeq ($(strip $(my_variants)),)
+# default is to use all variants supported by this OS
+my_variants := $(AUX_OS_VARIANT_LIST_$(NANO_OS))
+endif
+
+$(call for-each-variant,$(my_variants),OS,$(NANO_BUILD)/nanohub_static_library.mk)
diff --git a/firmware/external/Android.mk b/firmware/external/Android.mk
new file mode 100644
index 00000000..31baa2bf
--- /dev/null
+++ b/firmware/external/Android.mk
@@ -0,0 +1,70 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_PATH := $(call my-dir)
+
+include $(CLEAR_NANO_VARS)
+
+LOCAL_MODULE := libnanomath_os
+LOCAL_MODULE_TAGS := optional
+
+LOCAL_SRC_FILES :=                      \
+    arm/arm_sin_cos_f32.c               \
+    freebsd/lib/msun/src/e_atan2f.c     \
+    freebsd/lib/msun/src/e_expf.c       \
+    freebsd/lib/msun/src/s_atanf.c      \
+
+
+LOCAL_CFLAGS :=    \
+    -DFLT_EVAL_METHOD=0 \
+
+LOCAL_C_INCLUDES := \
+    $(LOCAL_PATH)/freebsd/lib/msun/src \
+    $(NANOHUB_OS_PATH)/inc \
+    $(NANOHUB_OS_PATH)/src/platform/$(AUX_ARCH)/inc \
+    $(NANOHUB_OS_PATH)/src/platform/$(AUX_ARCH)/inc/plat/cmsis \
+    $(NANOHUB_OS_PATH)/src/cpu/$(AUX_CPU)/inc \
+
+LOCAL_EXPORT_C_INCLUDE_DIRS := \
+    $(LOCAL_PATH)/freebsd/inc \
+
+include $(BUILD_NANOHUB_OS_STATIC_LIBRARY)
+
+include $(CLEAR_NANO_VARS)
+
+LOCAL_MODULE := libnanomath
+LOCAL_MODULE_TAGS := optional
+
+LOCAL_SRC_FILES :=                      \
+    arm/arm_sin_cos_f32.c               \
+    freebsd/lib/msun/src/e_atan2f.c     \
+    freebsd/lib/msun/src/e_expf.c       \
+    freebsd/lib/msun/src/s_atanf.c      \
+
+LOCAL_CFLAGS :=    \
+    -DFLT_EVAL_METHOD=0 \
+
+LOCAL_C_INCLUDES := \
+    $(LOCAL_PATH)/freebsd/lib/msun/src \
+    $(NANOHUB_OS_PATH)/inc \
+    $(NANOHUB_OS_PATH)/src/platform/$(AUX_ARCH)/inc \
+    $(NANOHUB_OS_PATH)/src/platform/$(AUX_ARCH)/inc/plat/cmsis \
+    $(NANOHUB_OS_PATH)/src/cpu/$(AUX_CPU)/inc \
+
+LOCAL_EXPORT_C_INCLUDE_DIRS := \
+    $(LOCAL_PATH)/freebsd/inc \
+
+include $(BUILD_NANOHUB_APP_STATIC_LIBRARY)
diff --git a/firmware/external/arm/arm_common_tables.c b/firmware/external/arm/arm_common_tables.c
index 7f1ac845..148d9855 100644
--- a/firmware/external/arm/arm_common_tables.c
+++ b/firmware/external/arm/arm_common_tables.c
@@ -40,7 +40,7 @@
 
 
 #include <arm_math.h>
-#include <plat/inc/cmsis/arm_common_tables.h>
+#include <plat/cmsis/arm_common_tables.h>
 
 /**    
  * @ingroup groupTransforms    
diff --git a/firmware/external/freebsd/lib/msun/src/e_atan2f.c b/firmware/external/freebsd/lib/msun/src/e_atan2f.c
index fc77bffa..90883233 100644
--- a/firmware/external/freebsd/lib/msun/src/e_atan2f.c
+++ b/firmware/external/freebsd/lib/msun/src/e_atan2f.c
@@ -17,7 +17,7 @@
 __FBSDID("$FreeBSD$");
 
 #include "math.h"
-#include "math_private.h"
+#include <math_private.h>
 
 static volatile float
 tiny  = 1.0e-30;
diff --git a/firmware/external/freebsd/lib/msun/src/e_expf.c b/firmware/external/freebsd/lib/msun/src/e_expf.c
index b1fe2c53..19931da8 100644
--- a/firmware/external/freebsd/lib/msun/src/e_expf.c
+++ b/firmware/external/freebsd/lib/msun/src/e_expf.c
@@ -19,7 +19,7 @@ __FBSDID("$FreeBSD$");
 #include <float.h>
 
 #include "math.h"
-#include "math_private.h"
+#include <math_private.h>
 
 static const float
 one	= 1.0,
diff --git a/firmware/external/freebsd/lib/msun/src/s_atanf.c b/firmware/external/freebsd/lib/msun/src/s_atanf.c
index b3a371f3..965fea50 100644
--- a/firmware/external/freebsd/lib/msun/src/s_atanf.c
+++ b/firmware/external/freebsd/lib/msun/src/s_atanf.c
@@ -17,7 +17,7 @@
 __FBSDID("$FreeBSD$");
 
 #include "math.h"
-#include "math_private.h"
+#include <math_private.h>
 
 static const float atanhi[] = {
   4.6364760399e-01, /* atan(0.5)hi 0x3eed6338 */
diff --git a/firmware/firmware.mk b/firmware/firmware.mk
new file mode 100644
index 00000000..eb98b4dc
--- /dev/null
+++ b/firmware/firmware.mk
@@ -0,0 +1,116 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+#find build target
+PLATFORM ?= stm32
+CHIP ?= stm32f411
+CPU ?= cortexm4
+VARIANT ?= lunchbox
+DEBUG ?= -DDEBUG
+OUT := out/nanohub/$(VARIANT)
+
+#bad words
+BADWORDS += strcpy strcat atoi
+BADWORDS += "rsaPrivOp=RSA private ops must never be compiled into firmware."
+
+#find makefiles
+MAKE_PLAT = os/platform/$(PLATFORM)/$(PLATFORM).mk
+MAKE_CPU = os/cpu/$(CPU)/$(CPU).mk
+
+ifndef VARIANT_PATH
+VARIANT_PATH := variant/$(VARIANT)
+endif
+
+MAKE_VAR = $(VARIANT_PATH)/$(VARIANT).mk
+
+#top make target
+SRCS_os :=
+SRCS_bl :=
+DELIVERABLES :=
+
+.PHONY: real all
+real: all
+
+#include makefiles for plat and cpu
+include $(MAKE_PLAT)
+include $(MAKE_CPU)
+include $(MAKE_VAR)
+
+FLAGS += -Ios/inc
+FLAGS += -Ios/platform/$(PLATFORM)/inc
+FLAGS += -Ios/cpu/$(CPU)/inc
+FLAGS += -I$(VARIANT_PATH)/inc
+FLAGS += -Iexternal/freebsd/inc
+FLAGS += -I../lib/include
+FLAGS += -I../inc
+
+FLAGS += -Wall -Werror -fshort-double
+#help avoid commmon embedded C mistakes
+FLAGS += -Wmissing-declarations -Wlogical-op -Waddress -Wempty-body -Wpointer-arith -Wenum-compare -Wdouble-promotion -Wfloat-equal -Wshadow -fno-strict-aliasing
+
+OSFLAGS += -g -ggdb3 -D_OS_BUILD_ -O2
+
+#debug mode
+FLAGS += $(DEBUG)
+
+include firmware_conf.mk
+
+FLAGS += $(COMMON_FLAGS)
+
+#bootloader pieces
+SRCS_bl += ../lib/nanohub/sha2.c ../lib/nanohub/rsa.c ../lib/nanohub/aes.c os/core/seos.c
+
+#frameworks
+SRCS_os += os/core/printf.c os/core/timer.c os/core/seos.c os/core/heap.c os/core/slab.c os/core/spi.c os/core/trylock.c
+SRCS_os += os/core/hostIntf.c os/core/hostIntfI2c.c os/core/hostIntfSpi.c os/core/nanohubCommand.c os/core/sensors.c os/core/syscall.c
+SRCS_os += os/core/eventQ.c os/core/osApi.c os/core/appSec.c os/core/simpleQ.c os/core/floatRt.c os/core/nanohub_chre.c
+SRCS_os += os/algos/ap_hub_sync.c
+SRCS_bl += os/core/bl.c
+
+#some help for bootloader
+SRCS_bl += os/core/printf.c
+
+ifndef PLATFORM_HAS_HARDWARE_CRC
+SRCS_os += ../lib/nanohub/softcrc.c
+endif
+
+#extra deps
+DEPS += $(wildcard inc/*.h)
+DEPS += $(wildcard ../inc/*.h)
+DEPS += $(wildcard ../inc/chre/*.h)
+DEPS += firmware.mk firmware_conf.mk $(MAKE_PLAT) $(MAKE_CPU) $(MAKE_VAR)
+DELIVERABLES += $(OUT)/full.bin
+
+all: $(DELIVERABLES)
+
+$(OUT)/bl.unchecked.elf: $(SRCS_bl) $(DEPS)
+	mkdir -p $(dir $@)
+	$(GCC) -o $@ $(SRCS_bl) $(OSFLAGS) $(OSFLAGS_bl) $(FLAGS)
+
+$(OUT)/os.unchecked.elf: $(SRCS_os) $(DEPS)
+	mkdir -p $(dir $@)
+	$(GCC) -o $@ $(SRCS_os) $(OSFLAGS) $(OSFLAGS_os) $(FLAGS)
+
+$(OUT)/%.checked.elf : $(OUT)/%.unchecked.elf  symcheck.sh
+	mkdir -p $(dir $@)
+	./symcheck.sh $< $@ $(BADWORDS)
+
+$(OUT)/full.bin: $(BL_FILE) $(OS_FILE)
+	mkdir -p $(dir $@)
+	cat $(BL_FILE) $(OS_FILE) > $@
+
+clean:
+	rm -rf $(OUT)
diff --git a/firmware/firmware_conf.mk b/firmware/firmware_conf.mk
new file mode 100644
index 00000000..a4fffcb0
--- /dev/null
+++ b/firmware/firmware_conf.mk
@@ -0,0 +1,18 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+# parameters common for OS and APPs
+COMMON_FLAGS += -DCHRE_MESSAGE_TO_HOST_MAX_SIZE=128
diff --git a/firmware/lib/lib.mk b/firmware/lib/lib.mk
new file mode 100644
index 00000000..965a4afb
--- /dev/null
+++ b/firmware/lib/lib.mk
@@ -0,0 +1,71 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+################################################################################
+#
+# Nanoapp Libc/Libm build helper script
+#
+################################################################################
+
+# Libm #########################################################################
+
+LIBM_PATH := $(NANOHUB_DIR)/lib/libm
+
+CFLAGS += -D_IEEE_LIBM
+
+SRCS += $(LIBM_PATH)/ef_atan2.c
+SRCS += $(LIBM_PATH)/ef_asin.c
+SRCS += $(LIBM_PATH)/ef_exp.c
+SRCS += $(LIBM_PATH)/ef_fmod.c
+SRCS += $(LIBM_PATH)/ef_pow.c
+SRCS += $(LIBM_PATH)/ef_rem_pio2.c
+SRCS += $(LIBM_PATH)/ef_sqrt.c
+SRCS += $(LIBM_PATH)/kf_cos.c
+SRCS += $(LIBM_PATH)/kf_rem_pio2.c
+SRCS += $(LIBM_PATH)/kf_sin.c
+SRCS += $(LIBM_PATH)/sf_atan.c
+SRCS += $(LIBM_PATH)/sf_cos.c
+SRCS += $(LIBM_PATH)/sf_floor.c
+SRCS += $(LIBM_PATH)/sf_fpclassify.c
+SRCS += $(LIBM_PATH)/sf_round.c
+SRCS += $(LIBM_PATH)/sf_scalbn.c
+SRCS += $(LIBM_PATH)/sf_sin.c
+SRCS += $(LIBM_PATH)/wf_atan2.c
+SRCS += $(LIBM_PATH)/wf_asin.c
+SRCS += $(LIBM_PATH)/wf_exp.c
+SRCS += $(LIBM_PATH)/wf_fmod.c
+SRCS += $(LIBM_PATH)/wf_pow.c
+
+# Libc #########################################################################
+
+LIBC_PATH := $(NANOHUB_DIR)/lib/libc
+
+SRCS += $(LIBC_PATH)/memcmp.c
+#SRCS += $(LIBC_PATH)/memcpy-armv7m.S
+SRCS += $(LIBC_PATH)/memcpy.c
+SRCS += $(LIBC_PATH)/memmove.c
+SRCS += $(LIBC_PATH)/memset.c
+SRCS += $(LIBC_PATH)/strcasecmp.c
+SRCS += $(LIBC_PATH)/strncpy.c
+SRCS += $(LIBC_PATH)/strlen.c
+
+# C++ support
+
+SRCS += $(LIBC_PATH)/crt.c
+SRCS += $(LIBC_PATH)/aeabi.cpp
+SRCS += $(LIBC_PATH)/cxa.cpp
+SRCS += $(LIBC_PATH)/new.cpp
+CFLAGS += -I$(LIBC_PATH)
diff --git a/firmware/lib/libc/Android.mk b/firmware/lib/libc/Android.mk
new file mode 100644
index 00000000..1558e473
--- /dev/null
+++ b/firmware/lib/libc/Android.mk
@@ -0,0 +1,56 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_PATH := $(call my-dir)
+
+include $(CLEAR_NANO_VARS)
+
+src_files :=            \
+    memcmp.c            \
+    memmove.c           \
+    memset.c            \
+    strcasecmp.c        \
+    strlen.c            \
+    strncpy.c           \
+
+LOCAL_MODULE := libnanolibc_os
+LOCAL_MODULE_TAGS := optional
+
+LOCAL_SRC_FILES := $(src_files)
+
+LOCAL_SRC_FILES_cortexm4 += memcpy-armv7m.S
+LOCAL_SRC_FILES_x86 += memcpy.c
+
+include $(BUILD_NANOHUB_OS_STATIC_LIBRARY)
+
+include $(CLEAR_NANO_VARS)
+
+LOCAL_MODULE := libnanolibc
+LOCAL_MODULE_TAGS := optional
+
+LOCAL_SRC_FILES := $(src_files)
+LOCAL_SRC_FILES +=      \
+    memcpy.c            \
+    aeabi.cpp           \
+    cxa.cpp             \
+    new.cpp             \
+    crt.c               \
+
+LOCAL_C_INCLUDES = $(LOCAL_PATH)
+LOCAL_EXPORT_C_INCLUDE_DIRS := \
+    $(LOCAL_C_INCLUDES)
+
+include $(BUILD_NANOHUB_APP_STATIC_LIBRARY)
diff --git a/lib/libc/acle-compat.h b/firmware/lib/libc/acle-compat.h
index 888ae2ea..888ae2ea 100644
--- a/lib/libc/acle-compat.h
+++ b/firmware/lib/libc/acle-compat.h
diff --git a/firmware/lib/libc/aeabi.cpp b/firmware/lib/libc/aeabi.cpp
new file mode 100644
index 00000000..0b9d0bf8
--- /dev/null
+++ b/firmware/lib/libc/aeabi.cpp
@@ -0,0 +1,263 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * THis file is based on the template provided in the reference doc:
+ * http://infocenter.arm.com/help/topic/com.arm.doc.ihi0041e/IHI0041E_cppabi.pdf
+ *
+ * ARM reference implementation is not changed, except as follows:
+ *
+ * 1 Function prototypes added to avoid compiler warning "no previous function declaration".
+ *   Since all of those are internal functions presumably exclusively used by the compiler,
+ *   I decided not to provide header file for those and embed function prototypes in the source.
+ *
+ * 2 Methods calling into __cxa_*() primitives;
+ *   I decided to not implement such __cxa_*() primitives, and code the functionality directly in aeabi.
+ *   this works because the toolchain we use is generating calls to aeabi, and not generic calls.
+ *   Decision was made to simplify the solution, because generic code must take care of more corner
+ *   cases than necessary in ARM case.
+ *   strictly speaking, aeabi.cpp is ARM-specific and should be annotated as such.
+ *   This is easy to do in Android.mk build, but not that easy with original Makefile build.
+ *   For now, I'm going to ignore both the missing ARM-specific annotation, and missing
+ *   certain __cxa_*() calls; I'll deal with both when it comes to that (i.e. when we actually
+ *   have an offending use case).
+ *
+ * 3 __aeabi_atexit() was originally calling __cxa_atexit(); I changed that to do-nothing stub;
+ *   this is because dynamic registration of destructors as per standard would require one to reserve
+ *   sizeof(uintptr_t) * 32 bytes (i.e. 128 bytes on ARM Cortex M4) to comply with standard,
+ *   and on top of that, be able to register variable amount of destructor methods (which may be of any size).
+ *   possible solution would be to reserve extra space for BSS as boot time, and release extra space
+ *   after init is done, however this does not solve entire problem, only global part of it, since
+ *   local static registration may happen at any time.
+ *   Another possible solution is to provide size of destructor allocation heap at build time;
+ *   I reserved a field for that in application data segment for future use.
+ */
+
+#include <cstddef>
+#include <cstdint>
+#include <cxxabi.h>
+
+using namespace __cxxabiv1;
+
+namespace __aeabiv1 {
+
+using ::std::size_t;
+
+// Note: Only the __aeabi_* names are exported.
+// array_cookie, cookie_size, cookie_of, etc. are presented for exposition only.
+// They are not expected to be available to users, but implementers may find them useful.
+struct array_cookie {
+    size_t element_size; // element_size != 0
+    size_t element_count;
+};
+// The struct array_cookie fields and the arguments element_size and element_count
+// are ordered for convenient use of LDRD/STRD on architecture 5TE and above.
+const size_t cookie_size = sizeof(array_cookie);
+
+// cookie_of() takes a pointer to the user array and returns a reference to the cookie.
+inline array_cookie& cookie_of(void* user_array)
+{
+    return reinterpret_cast<array_cookie*>(user_array)[-1];
+}
+
+// element_size_of() takes a pointer to the user array and returns a reference to the
+// element_size field of the cookie.
+inline size_t& element_size_of(void* user_array)
+{
+    return cookie_of(user_array).element_size;
+}
+
+// element_count_of() takes a pointer to the user array and returns a reference to the
+// element_count field of the cookie.
+inline size_t& element_count_of(void* user_array)
+{
+    return cookie_of(user_array).element_count;
+}
+
+// user_array_of() takes a pointer to the cookie and returns a pointer to the user array.
+inline void* user_array_of(array_cookie* cookie_address)
+{
+    return cookie_address + 1;
+}
+
+extern "C" void* __aeabi_vec_ctor_nocookie_nodtor(void* user_array,
+                                                  void* (*constructor)(void*),
+                                                  size_t element_size, size_t element_count);
+extern "C" void* __aeabi_vec_ctor_cookie_nodtor(array_cookie* cookie,
+                                                void*(*constructor)(void*),
+                                                size_t element_size, size_t element_count);
+extern "C" void* __aeabi_vec_cctor_nocookie_nodtor(void* user_array_dest,
+                                                   void* user_array_src,
+                                                   size_t element_size, size_t element_count,
+                                                   void* (*copy_constructor)(void*, void*));
+extern "C" void* __aeabi_vec_new_cookie_noctor(size_t element_size, size_t element_count);
+extern "C" int __aeabi_atexit(void* object, void (*destroyer)(void*), void* dso_handle);
+extern "C" void __aeabi_vec_delete3_nodtor(void* user_array, void (*dealloc)(void*, size_t));
+extern "C" void __aeabi_vec_delete3(void* user_array, void* (*destructor)(void*),
+                                    void (*dealloc)(void*, size_t));
+extern "C" void __aeabi_vec_delete(void* user_array, void* (*destructor)(void*));
+extern "C" void* __aeabi_vec_dtor_cookie(void* user_array, void* (*destructor)(void*));
+extern "C" void* __aeabi_vec_dtor(void* user_array,
+                                  void* (*destructor)(void*),
+                                  size_t element_size, size_t element_count);
+extern "C" void* __aeabi_vec_new_cookie(size_t element_size, size_t element_count,
+                                        void* (*constructor)(void*),
+                                        void* (*destructor)(void*));
+extern "C" void* __aeabi_vec_new_cookie_nodtor(size_t element_size,
+                                               size_t element_count,
+                                               void* (*constructor)(void*));
+extern "C" void* __aeabi_vec_new_nocookie(size_t element_size, size_t element_count,
+                                          void* (*constructor)(void*));
+
+extern "C" void* __aeabi_vec_ctor_nocookie_nodtor(void* user_array,
+                                       void* (*constructor)(void*),
+                                       size_t element_size, size_t element_count)
+{
+    if (constructor != nullptr) {
+        uintptr_t addr = reinterpret_cast<uintptr_t>(user_array);
+        for (size_t i = 0; i < element_count; ++i, addr += element_size) {
+            constructor(reinterpret_cast<void*>(addr));
+        }
+    }
+    return user_array;
+}
+
+// __aeabi_vec_ctor_cookie_nodtor is like __aeabi_vec_ctor_nocookie_nodtor but sets
+// cookie fields and returns user_array. The parameters are arranged to make STRD
+// usable. Does nothing and returns NULL if cookie is NULL.
+extern "C" void* __aeabi_vec_ctor_cookie_nodtor(array_cookie* cookie,
+                                                void*(*constructor)(void*),
+                                                size_t element_size, size_t element_count)
+{
+    if (cookie == nullptr) {
+        return nullptr;
+    } else {
+        cookie->element_size = element_size;
+        cookie->element_count = element_count;
+        return __aeabi_vec_ctor_nocookie_nodtor(user_array_of(cookie), constructor,
+                                                element_size, element_count);
+    }
+}
+
+extern "C" void* __aeabi_vec_cctor_nocookie_nodtor(void* user_array_dest,
+                                                   void* user_array_src,
+                                                   size_t element_size, size_t element_count,
+                                                   void* (*copy_constructor)(void*, void*))
+{
+    if (copy_constructor != nullptr) {
+        uintptr_t src_addr = reinterpret_cast<uintptr_t>(user_array_src);
+        uintptr_t dest_addr = reinterpret_cast<uintptr_t>(user_array_dest);
+        for (size_t i = 0; i < element_count; ++i, src_addr += element_size, dest_addr += element_size) {
+            copy_constructor(reinterpret_cast<void*>(dest_addr), reinterpret_cast<void*>(src_addr));
+        }
+    }
+    return user_array_dest;
+}
+
+extern "C" void* __aeabi_vec_new_cookie_noctor(size_t element_size, size_t element_count)
+{
+    array_cookie* cookie = reinterpret_cast<array_cookie*>(
+            ::operator new[](element_count * element_size + cookie_size)
+    );
+    cookie->element_size = element_size;
+    cookie->element_count = element_count;
+    return user_array_of(cookie);
+}
+
+extern "C" void* __aeabi_vec_new_nocookie(size_t element_size, size_t element_count,
+                                          void* (*constructor)(void*))
+{
+    return __aeabi_vec_ctor_nocookie_nodtor(::operator new[](element_count * element_size),
+            constructor, element_size, element_count);
+}
+
+extern "C" void* __aeabi_vec_new_cookie_nodtor(size_t element_size,
+                                               size_t element_count,
+                                               void* (*constructor)(void*))
+{
+    array_cookie* cookie = reinterpret_cast<array_cookie*>(
+            ::operator new[](element_count * element_size + cookie_size)
+    );
+    return __aeabi_vec_ctor_cookie_nodtor(cookie, constructor, element_size, element_count);
+}
+
+extern "C" void* __aeabi_vec_new_cookie(size_t element_size, size_t element_count,
+                                        void* (*constructor)(void*),
+                                        void* (*destructor)(void*))
+{
+    return __aeabi_vec_new_cookie_nodtor(element_size, element_count, constructor);
+}
+
+// __aeabi_vec_dtor is like __cxa_vec_dtor but has its parameters reordered and returns
+// a pointer to the cookie (assuming user_array has one).
+// Unlike __cxa_vec_dtor, destructor must not be NULL.
+// user_array must not be NULL.
+extern "C" void* __aeabi_vec_dtor(void* user_array,
+                                  void* (*destructor)(void*),
+                                  size_t element_size, size_t element_count)
+{
+    uintptr_t addr = reinterpret_cast<uintptr_t>(user_array);
+    for (size_t i = 0; i < element_count; ++i, addr += element_size) {
+        destructor(reinterpret_cast<void*>(addr));
+    }
+    return &cookie_of(user_array);
+}
+
+// __aeabi_vec_dtor_cookie is only used on arrays that have cookies.
+// __aeabi_vec_dtor is like __cxa_vec_dtor but returns a pointer to the cookie.
+// That is, it takes a pointer to the user array, calls the given destructor on
+// each element (from highest index down to zero) and returns a pointer to the cookie.
+// Does nothing and returns NULL if cookie is NULL.
+// Unlike __cxa_vec_dtor, destructor must not be NULL.
+// Exceptions are handled as in __cxa_vec_dtor.
+// __aeabi_vec_dtor_cookie must not change the element count in the cookie.
+// (But it may corrupt the element size if desired.)
+extern "C" void* __aeabi_vec_dtor_cookie(void* user_array, void* (*destructor)(void*))
+{
+    return user_array == nullptr ? nullptr :
+                         __aeabi_vec_dtor(user_array, destructor,
+                                          element_size_of(user_array),
+                                          element_count_of(user_array));
+}
+
+extern "C" void __aeabi_vec_delete(void* user_array, void* (*destructor)(void*))
+{
+    ::operator delete[](__aeabi_vec_dtor_cookie(user_array, destructor));
+}
+
+extern "C" void __aeabi_vec_delete3(void* user_array, void* (*destructor)(void*), void (*dealloc)(void*, size_t))
+{
+    if (user_array != NULL) {
+        size_t size = element_size_of(user_array) * element_count_of(user_array) + cookie_size;
+        void *array_cookie = __aeabi_vec_dtor_cookie(user_array, destructor);
+        dealloc(array_cookie, size);
+    }
+}
+
+extern "C" void __aeabi_vec_delete3_nodtor(void* user_array, void (*dealloc)(void*, size_t))
+{
+    if (user_array != NULL) {
+        size_t size = element_size_of(user_array) * element_count_of(user_array) + cookie_size;
+        (*dealloc)(&cookie_of(user_array), size);
+    }
+}
+
+extern "C" int __aeabi_atexit(void* object, void (*destroyer)(void*), void* dso_handle)
+{
+    return 0;
+}
+
+} // namespace __aeabiv1
diff --git a/lib/libc/arm_asm.h b/firmware/lib/libc/arm_asm.h
index 1bb5edb2..1bb5edb2 100644
--- a/lib/libc/arm_asm.h
+++ b/firmware/lib/libc/arm_asm.h
diff --git a/lib/libc/bcopy.c b/firmware/lib/libc/bcopy.c
index 854e9649..854e9649 100644
--- a/lib/libc/bcopy.c
+++ b/firmware/lib/libc/bcopy.c
diff --git a/firmware/lib/libc/crt.c b/firmware/lib/libc/crt.c
new file mode 100644
index 00000000..60363f83
--- /dev/null
+++ b/firmware/lib/libc/crt.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <crt_priv.h>
+
+static void callVectors(const void *from_addr, const void *to_addr)
+{
+    typedef void (* const callVect)(void);
+    callVect *start = (callVect *)from_addr;
+    callVect *end = (callVect *)to_addr;
+    const int32_t step = from_addr < to_addr ? 1 : -1;
+    const int32_t count = step > 0 ? end - start : start - end;
+
+    // basic sanity check
+    if (&start[step * count] != end)
+        return;
+
+    for (; start != end; start += step) {
+        callVect vec = *start;
+        if (vec != NULL)
+            vec();
+    }
+}
+
+void __crt_init(void)
+{
+    extern uint32_t __init_array_start[];
+    extern uint32_t __init_array_end[];
+
+    callVectors(__init_array_start, __init_array_end);
+}
+
+void __crt_exit(void)
+{
+    extern uint32_t __fini_array_start[];
+    extern uint32_t __fini_array_end[];
+    extern uint32_t __bss_end[];
+    extern uint32_t __got_start[];
+
+    // call global destructors
+    callVectors(__fini_array_start, __fini_array_end);
+    if (&__fini_array_end[1] <= __got_start) {
+        // call registered static destructors
+        callVectors(__bss_end + __fini_array_end[0] * (sizeof(uint32_t)), __bss_end);
+    }
+}
diff --git a/firmware/lib/libc/crt_priv.h b/firmware/lib/libc/crt_priv.h
new file mode 100644
index 00000000..b9695fd0
--- /dev/null
+++ b/firmware/lib/libc/crt_priv.h
@@ -0,0 +1,7 @@
+#ifndef _LIBC_CRT_PRIV_H_
+#define _LIBC_CRT_PRIV_H_
+
+void __crt_init(void);
+void __crt_exit(void);
+
+#endif /* _LIBC_CRT_PRIV_H_ */
diff --git a/firmware/lib/libc/cxa.cpp b/firmware/lib/libc/cxa.cpp
new file mode 100644
index 00000000..746a507b
--- /dev/null
+++ b/firmware/lib/libc/cxa.cpp
@@ -0,0 +1,43 @@
+#include <cstdlib>
+#include <cstdint>
+#include <cxxabi.h>
+
+namespace __cxxabiv1
+{
+// 3.2.6 Pure Virtual Function API
+extern "C" void __cxa_pure_virtual ()
+{
+    while(true);
+}
+
+// 3.2.7 Deleted Virtual Function API
+extern "C" void __cxa_deleted_virtual ()
+{
+    while(true);
+}
+
+// 3.3.2 One-time Construction API
+// NOTE: Implementation does not support threads; no locking involved
+
+extern "C" int
+__cxa_guard_acquire(__guard *_guard)
+{
+    uint8_t *guard = reinterpret_cast<uint8_t*>(_guard);
+    return guard[0] ? 0 : 1;
+}
+
+extern "C" void
+__cxa_guard_release(__guard *_guard)
+{
+    uint8_t *guard = reinterpret_cast<uint8_t*>(_guard);
+    guard[0] = 1;
+}
+
+extern "C" void
+__cxa_guard_abort(__guard *_guard)
+{
+    uint8_t *guard = reinterpret_cast<uint8_t*>(_guard);
+    guard[0] = 0;
+}
+
+} // namespace __cxxabiv1
diff --git a/lib/libc/memcmp.c b/firmware/lib/libc/memcmp.c
index 9e6a575f..9e6a575f 100644
--- a/lib/libc/memcmp.c
+++ b/firmware/lib/libc/memcmp.c
diff --git a/lib/libc/memcpy-armv7m.S b/firmware/lib/libc/memcpy-armv7m.S
index 8a70c7d7..8a70c7d7 100644
--- a/lib/libc/memcpy-armv7m.S
+++ b/firmware/lib/libc/memcpy-armv7m.S
diff --git a/lib/libc/memcpy.c b/firmware/lib/libc/memcpy.c
index 72b8e339..72b8e339 100644
--- a/lib/libc/memcpy.c
+++ b/firmware/lib/libc/memcpy.c
diff --git a/lib/libc/memmove.c b/firmware/lib/libc/memmove.c
index cdfededc..cdfededc 100644
--- a/lib/libc/memmove.c
+++ b/firmware/lib/libc/memmove.c
diff --git a/lib/libc/memset.c b/firmware/lib/libc/memset.c
index 0f3ba012..0f3ba012 100644
--- a/lib/libc/memset.c
+++ b/firmware/lib/libc/memset.c
diff --git a/firmware/lib/libc/new.cpp b/firmware/lib/libc/new.cpp
new file mode 100644
index 00000000..f093d2a1
--- /dev/null
+++ b/firmware/lib/libc/new.cpp
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <cstddef>
+#include <cstdlib>
+#include <new>
+
+#include <syscallDo.h>
+
+using std::size_t;
+
+void* operator new(size_t sz)
+{
+    return eOsHeapAlloc(sz);
+}
+
+void* operator new[](size_t sz)
+{
+    return eOsHeapAlloc(sz);
+}
+
+void operator delete(void *p)
+{
+    eOsHeapFree(p);
+}
+
+void operator delete[](void *p)
+{
+    eOsHeapFree(p);
+}
diff --git a/lib/libc/strcasecmp.c b/firmware/lib/libc/strcasecmp.c
index 2be09136..2be09136 100644
--- a/lib/libc/strcasecmp.c
+++ b/firmware/lib/libc/strcasecmp.c
diff --git a/lib/libc/strlen.c b/firmware/lib/libc/strlen.c
index 7e59e755..bf56ed66 100644
--- a/lib/libc/strlen.c
+++ b/firmware/lib/libc/strlen.c
@@ -84,6 +84,7 @@ strlen (const char* str)
 size_t __attribute__((naked))
 strlen (const char* str)
 {
+  (void)str; /* disable unused argument warning */
   asm ("len .req r0\n\t"
        "data .req r3\n\t"
        "addr .req r1\n\t"
diff --git a/lib/libc/strncpy.c b/firmware/lib/libc/strncpy.c
index 5003a199..5003a199 100644
--- a/lib/libc/strncpy.c
+++ b/firmware/lib/libc/strncpy.c
diff --git a/firmware/lib/libm/Android.mk b/firmware/lib/libm/Android.mk
new file mode 100644
index 00000000..b2f872fe
--- /dev/null
+++ b/firmware/lib/libm/Android.mk
@@ -0,0 +1,53 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_PATH := $(call my-dir)
+
+include $(CLEAR_NANO_VARS)
+
+LOCAL_MODULE := libnanolibm
+LOCAL_MODULE_TAGS := optional
+
+LOCAL_SRC_FILES :=      \
+    ef_asin.c           \
+    ef_atan2.c          \
+    ef_exp.c            \
+    ef_fmod.c           \
+    ef_pow.c            \
+    ef_rem_pio2.c       \
+    ef_sqrt.c           \
+    kf_cos.c            \
+    kf_rem_pio2.c       \
+    kf_sin.c            \
+    sf_atan.c           \
+    sf_cos.c            \
+    sf_floor.c          \
+    sf_fpclassify.c     \
+    sf_round.c          \
+    sf_scalbn.c         \
+    sf_sin.c            \
+    wf_asin.c           \
+    wf_atan2.c          \
+    wf_exp.c            \
+    wf_fmod.c           \
+    wf_pow.c            \
+
+LOCAL_CFLAGS :=         \
+    -DARM_MATH_CM4      \
+    -D__FPU_PRESENT     \
+    -D_IEEE_LIBM        \
+
+include $(BUILD_NANOHUB_APP_STATIC_LIBRARY)
diff --git a/lib/libm/ef_asin.c b/firmware/lib/libm/ef_asin.c
index c49dcbbc..c49dcbbc 100644
--- a/lib/libm/ef_asin.c
+++ b/firmware/lib/libm/ef_asin.c
diff --git a/lib/libm/ef_atan2.c b/firmware/lib/libm/ef_atan2.c
index d57480b0..d57480b0 100644
--- a/lib/libm/ef_atan2.c
+++ b/firmware/lib/libm/ef_atan2.c
diff --git a/lib/libm/ef_exp.c b/firmware/lib/libm/ef_exp.c
index 6824f991..6824f991 100644
--- a/lib/libm/ef_exp.c
+++ b/firmware/lib/libm/ef_exp.c
diff --git a/lib/libm/ef_fmod.c b/firmware/lib/libm/ef_fmod.c
index 53c1ba28..53c1ba28 100644
--- a/lib/libm/ef_fmod.c
+++ b/firmware/lib/libm/ef_fmod.c
diff --git a/lib/libm/ef_pow.c b/firmware/lib/libm/ef_pow.c
index b3041dbd..b3041dbd 100644
--- a/lib/libm/ef_pow.c
+++ b/firmware/lib/libm/ef_pow.c
diff --git a/lib/libm/ef_rem_pio2.c b/firmware/lib/libm/ef_rem_pio2.c
index f1191d09..f1191d09 100644
--- a/lib/libm/ef_rem_pio2.c
+++ b/firmware/lib/libm/ef_rem_pio2.c
diff --git a/lib/libm/ef_sqrt.c b/firmware/lib/libm/ef_sqrt.c
index 80e7f360..80e7f360 100644
--- a/lib/libm/ef_sqrt.c
+++ b/firmware/lib/libm/ef_sqrt.c
diff --git a/lib/libm/fdlibm.h b/firmware/lib/libm/fdlibm.h
index a4b7fffe..a4b7fffe 100644
--- a/lib/libm/fdlibm.h
+++ b/firmware/lib/libm/fdlibm.h
diff --git a/lib/libm/kf_cos.c b/firmware/lib/libm/kf_cos.c
index 4f71af23..4f71af23 100644
--- a/lib/libm/kf_cos.c
+++ b/firmware/lib/libm/kf_cos.c
diff --git a/lib/libm/kf_rem_pio2.c b/firmware/lib/libm/kf_rem_pio2.c
index 261c4812..261c4812 100644
--- a/lib/libm/kf_rem_pio2.c
+++ b/firmware/lib/libm/kf_rem_pio2.c
diff --git a/lib/libm/kf_sin.c b/firmware/lib/libm/kf_sin.c
index e81fa0bd..e81fa0bd 100644
--- a/lib/libm/kf_sin.c
+++ b/firmware/lib/libm/kf_sin.c
diff --git a/lib/libm/sf_atan.c b/firmware/lib/libm/sf_atan.c
index 6edf05fe..6edf05fe 100644
--- a/lib/libm/sf_atan.c
+++ b/firmware/lib/libm/sf_atan.c
diff --git a/lib/libm/sf_cos.c b/firmware/lib/libm/sf_cos.c
index 4c0a9a53..4c0a9a53 100644
--- a/lib/libm/sf_cos.c
+++ b/firmware/lib/libm/sf_cos.c
diff --git a/lib/libm/sf_floor.c b/firmware/lib/libm/sf_floor.c
index 9264d81e..9264d81e 100644
--- a/lib/libm/sf_floor.c
+++ b/firmware/lib/libm/sf_floor.c
diff --git a/lib/libm/sf_fpclassify.c b/firmware/lib/libm/sf_fpclassify.c
index 878457f3..878457f3 100644
--- a/lib/libm/sf_fpclassify.c
+++ b/firmware/lib/libm/sf_fpclassify.c
diff --git a/lib/libm/sf_round.c b/firmware/lib/libm/sf_round.c
index c8f1d773..c8f1d773 100644
--- a/lib/libm/sf_round.c
+++ b/firmware/lib/libm/sf_round.c
diff --git a/lib/libm/sf_scalbn.c b/firmware/lib/libm/sf_scalbn.c
index 70006001..70006001 100644
--- a/lib/libm/sf_scalbn.c
+++ b/firmware/lib/libm/sf_scalbn.c
diff --git a/lib/libm/sf_sin.c b/firmware/lib/libm/sf_sin.c
index da81845d..da81845d 100644
--- a/lib/libm/sf_sin.c
+++ b/firmware/lib/libm/sf_sin.c
diff --git a/lib/libm/wf_asin.c b/firmware/lib/libm/wf_asin.c
index 385de549..385de549 100644
--- a/lib/libm/wf_asin.c
+++ b/firmware/lib/libm/wf_asin.c
diff --git a/lib/libm/wf_atan2.c b/firmware/lib/libm/wf_atan2.c
index eb2a76b1..eb2a76b1 100644
--- a/lib/libm/wf_atan2.c
+++ b/firmware/lib/libm/wf_atan2.c
diff --git a/lib/libm/wf_exp.c b/firmware/lib/libm/wf_exp.c
index 70f4459b..70f4459b 100644
--- a/lib/libm/wf_exp.c
+++ b/firmware/lib/libm/wf_exp.c
diff --git a/lib/libm/wf_fmod.c b/firmware/lib/libm/wf_fmod.c
index 030ca3e7..030ca3e7 100644
--- a/lib/libm/wf_fmod.c
+++ b/firmware/lib/libm/wf_fmod.c
diff --git a/lib/libm/wf_pow.c b/firmware/lib/libm/wf_pow.c
index a30f8808..a30f8808 100644
--- a/lib/libm/wf_pow.c
+++ b/firmware/lib/libm/wf_pow.c
diff --git a/firmware/linux_aux_variant_config.mk b/firmware/linux_aux_variant_config.mk
new file mode 100644
index 00000000..d3559a82
--- /dev/null
+++ b/firmware/linux_aux_variant_config.mk
@@ -0,0 +1,49 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+# only locally defined variables can be used at this time
+
+my_variant := linux
+
+AUX_OS_$(my_variant)             := nanohub
+AUX_ARCH_$(my_variant)           := native
+AUX_SUBARCH_$(my_variant)        := native
+AUX_CPU_$(my_variant)            := x86
+
+# variant supports building OS bootloader, main OS image and application as targets
+# target should one of the following:
+#   "" (empty) -- applies to all (OS, BL, APP)
+#  _BL -- applies to OS bootloader target build only
+#  _OS -- applies to OS image target build only
+# _APP -- applies to application target build only
+#
+# the following variables may be defined in variant script for any target:
+# NANO_VARIANT<target>_CFLAGS_<variant>
+# NANO_VARIANT<target>_C_INCLUDES_<variant>
+# NANO_VARIANT<target>_STATIC_LIBRARIRES_<variant>
+# NANO_VARIANT<target>_WHOLE_STATIC_LIBRARIRES_<variant>
+#
+# the following may be defined for _OS and _BL only, to control
+# what additional source files need to be included in the build;
+# the file paths in this list are relative to the target (_OS or _BL) LOCAL_PATH;
+# NANO_VARIANT<target>_SRC_FILES_<variant>
+
+# 100K heap
+NANO_VARIANT_CFLAGS_$(my_variant)  := -DHEAP_SIZE=102400
+
+NANO_VARIANT_C_INCLUDES_$(my_variant) := device/google/contexthub/firmware/variant/linux/inc
+
+NANO_VARIANT_NO_BOOTLOADER_$(my_variant) := true
diff --git a/firmware/lunchbox_aux_variant_config.mk b/firmware/lunchbox_aux_variant_config.mk
new file mode 100644
index 00000000..b9043dd5
--- /dev/null
+++ b/firmware/lunchbox_aux_variant_config.mk
@@ -0,0 +1,82 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+# only locally defined variables can be used at this time
+
+my_variant := lunchbox
+
+AUX_OS_$(my_variant)             := nanohub
+AUX_ARCH_$(my_variant)           := stm32
+AUX_SUBARCH_$(my_variant)        := stm32f411
+AUX_CPU_$(my_variant)            := cortexm4
+
+# variant supports building OS bootloader, main OS image and application as targets
+# target should one of the following:
+#   "" (empty) -- applies to all targets
+#  _BL -- applies to OS bootloader target build only
+#  _OS -- applies to OS image target build only
+# _APP -- applies to application target build only
+#
+# special targets:
+# _OSCFG - apply only at build stage of OS binary image
+# _BLCFG - apply only at build stage of BL binary image
+#
+# the following variables may be defined in variant script for any target:
+# NANO_VARIANT<target>_CFLAGS_<variant>
+# NANO_VARIANT<target>_C_INCLUDES_<variant>
+# NANO_VARIANT<target>_STATIC_LIBRARIRES_<variant>
+# NANO_VARIANT<target>_WHOLE_STATIC_LIBRARIRES_<variant>
+#
+# the following may be defined for _OS and _BL only, to control
+# what additional source files need to be included in the build;
+# the file paths in this list are relative to the target (_OS or _BL) LOCAL_PATH;
+# NANO_VARIANT<target>_SRC_FILES_<variant>
+
+NANO_VARIANT_OSCFG_STATIC_LIBRARIES_$(my_variant) := libnanohub_os_$(my_variant)
+
+NANO_VARIANT_OS_CFLAGS_$(my_variant) :=
+
+NANO_VARIANT_OS_CFLAGS_$(my_variant) += \
+    -DUSE_BMM150                        \
+    -DMAG_SLAVE_PRESENT                 \
+
+#GPIOB0 is debug uart at 2MBps
+NANO_VARIANT_OS_CFLAGS_$(my_variant) += -DDEBUG_UART_PIN=16
+
+#'Lu' -> lunchbox
+NANO_VARIANT_CFLAGS_$(my_variant) += -DPLATFORM_HW_TYPE=0x4C75
+
+NANO_VARIANT_C_INCLUDES_$(my_variant) :=                    \
+    device/google/contexthub/firmware/variant/lunchbox/inc  \
+
+# this is relative to NANOHUB_OS_PATH
+NANO_VARIANT_OSCFG_SRC_FILES_$(my_variant) :=           \
+    os/algos/fusion.c                                   \
+    os/algos/mag_cal.c                                  \
+    os/algos/mat.c                                      \
+    os/algos/quat.c                                     \
+    os/algos/time_sync.c                                \
+    os/algos/vec.c                                      \
+    os/drivers/ams_tmd2772/ams_tmd2772.c                \
+    os/drivers/bosch_bmi160/bosch_bmi160.c              \
+    os/drivers/bosch_bmi160/bosch_bmm150_slave.c        \
+    os/drivers/bosch_bmp280/bosch_bmp280.c              \
+    os/drivers/hall/hall.c                              \
+    os/drivers/orientation/orientation.c                \
+    os/drivers/rohm_rpr0521/rohm_rpr0521.c              \
+    os/drivers/tilt_detection/tilt_detection.c          \
+    os/drivers/vsync/vsync.c                            \
+    os/drivers/window_orientation/window_orientation.c  \
diff --git a/firmware/misc/platform/stm32f4xx/Makefile b/firmware/misc/platform/stm32f4xx/Makefile
deleted file mode 100644
index c21fd8f3..00000000
--- a/firmware/misc/platform/stm32f4xx/Makefile
+++ /dev/null
@@ -1,80 +0,0 @@
-#
-# Copyright (C) 2016 The Android Open Source Project
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-
-M3DEBUG ?= m3debug
-
-ifneq ($(CPU),cortexm4f)
-        $(error "stm32f4xx cplatform only supports Cortex-M4F CPUs")
-endif
-
-DELIVERABLES = os.checked.bin bl.unchecked.bin full.bin showsizes
-BL_FILE = bl.unchecked.bin
-OS_FILE = os.checked.bin
-
-FLAGS += -I. -fno-unwind-tables -fstack-reuse=all -ffunction-sections -fdata-sections
-FLAGS += -Wl,--gc-sections
-FLAGS += -Iinc/platform/$(PLATFORM)/cmsis
-
-APPFLAGS += -msingle-pic-base -mpic-register=r9 -nostartfiles -fpic -shared
-
-#platform bootloader
-SRCS_bl += src/platform/$(PLATFORM)/bl.c
-
-#platform runtime
-SRCS_os +=  src/platform/$(PLATFORM)/crt_$(PLATFORM).c
-
-#platform drivers
-SRCS_os += src/platform/$(PLATFORM)/platform.c \
-	src/platform/$(PLATFORM)/usart.c \
-	src/platform/$(PLATFORM)/gpio.c \
-	src/platform/$(PLATFORM)/pwr.c \
-	src/platform/$(PLATFORM)/wdt.c \
-	src/platform/$(PLATFORM)/i2c.c \
-	src/platform/$(PLATFORM)/exti.c \
-	src/platform/$(PLATFORM)/syscfg.c \
-	src/platform/$(PLATFORM)/spi.c \
-	src/platform/$(PLATFORM)/rtc.c \
-	src/platform/$(PLATFORM)/mpu.c \
-	src/platform/$(PLATFORM)/dma.c \
-	src/platform/$(PLATFORM)/crc.c \
-	src/platform/$(PLATFORM)/hostIntf.c \
-	src/platform/$(PLATFORM)/apInt.c \
-	src/platform/$(PLATFORM)/eeData.c
-
-
-#platform drivers for bootloader
-SRCS_bl += src/platform/$(PLATFORM)/pwr.c src/platform/$(PLATFORM)/gpio.c
-
-#extra deps
-DEPS += $(wildcard inc/platform/$(PLATFORM)/*.h)
-DEPS += $(wildcard inc/platform/$(PLATFORM)/cmsis/*.h)
-
-#platform flags
-PLATFORM_HAS_HARDWARE_CRC = true
-FLAGS += -DPLATFORM_HW_VER=0
-
-#platform-specific rules
-OBJCOPY_PARAMS = -I elf32-littlearm -O binary
-
-bl.%.bin : bl.%.elf
-	$(OBJCOPY) -j .bl -j .blrodata -j .eedata $(OBJCOPY_PARAMS) $< $@
-
-os.%.bin : os.%.elf
-	$(OBJCOPY) -j .data -j .text $(OBJCOPY_PARAMS) $< $@
-
-showsizes: os.unchecked.elf
-	misc/platform/$(PLATFORM)/showsizes.sh $<
-
diff --git a/firmware/nanohub_aux_os_config.mk b/firmware/nanohub_aux_os_config.mk
new file mode 100644
index 00000000..79cbdf08
--- /dev/null
+++ b/firmware/nanohub_aux_os_config.mk
@@ -0,0 +1,19 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+NANOHUB_OS_PATH := device/google/contexthub/firmware
+
+include $(NANOHUB_OS_PATH)/build/config.mk
diff --git a/firmware/nucleo_aux_variant_config.mk b/firmware/nucleo_aux_variant_config.mk
new file mode 100644
index 00000000..b5b85157
--- /dev/null
+++ b/firmware/nucleo_aux_variant_config.mk
@@ -0,0 +1,74 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+# only locally defined variables can be used at this time
+
+my_variant := nucleo
+
+AUX_OS_$(my_variant)             := nanohub
+AUX_ARCH_$(my_variant)           := stm32
+AUX_SUBARCH_$(my_variant)        := stm32f411
+AUX_CPU_$(my_variant)            := cortexm4
+
+# variant supports building OS bootloader, main OS image and application as targets
+# target should one of the following:
+#   "" (empty) -- applies to all targets
+#  _BL -- applies to OS bootloader target build only
+#  _OS -- applies to OS image target build only
+# _APP -- applies to application target build only
+#
+# the following variables may be defined in variant script for any target:
+# NANO_VARIANT<target>_CFLAGS_<variant>
+# NANO_VARIANT<target>_C_INCLUDES_<variant>
+# NANO_VARIANT<target>_STATIC_LIBRARIRES_<variant>
+# NANO_VARIANT<target>_WHOLE_STATIC_LIBRARIRES_<variant>
+#
+# the following may be defined for _OS and _BL only, to control
+# what additional source files need to be included in the build;
+# the file paths in this list are relative to the target (_OS or _BL) LOCAL_PATH;
+# NANO_VARIANT<target>_SRC_FILES_<variant>
+
+NANO_VARIANT_OSCFG_STATIC_LIBRARIES_$(my_variant) := libnanohub_os_$(my_variant)
+
+NANO_VARIANT_OS_CFLAGS_$(my_variant) := \
+    -DUSE_BMM150                        \
+    -DMAG_SLAVE_PRESENT                 \
+    -DDEBUG_SWD                         \
+
+#'Nu' ->nucleo
+NANO_VARIANT_CFLAGS_$(my_variant) := -DPLATFORM_HW_TYPE=0x4E75
+
+NANO_VARIANT_C_INCLUDES_$(my_variant) := \
+    device/google/contexthub/firmware/variant/nucleo/inc \
+
+# this is relative to NANOHUB_OS_PATH
+NANO_VARIANT_OSCFG_SRC_FILES_$(my_variant) :=           \
+    os/algos/fusion.c                                   \
+    os/algos/mag_cal.c                                  \
+    os/algos/mat.c                                      \
+    os/algos/quat.c                                     \
+    os/algos/time_sync.c                                \
+    os/algos/vec.c                                      \
+    os/drivers/ams_tmd2772/ams_tmd2772.c                \
+    os/drivers/bosch_bmi160/bosch_bmi160.c              \
+    os/drivers/bosch_bmi160/bosch_bmm150_slave.c        \
+    os/drivers/bosch_bmp280/bosch_bmp280.c              \
+    os/drivers/hall/hall.c                              \
+    os/drivers/orientation/orientation.c                \
+    os/drivers/rohm_rpr0521/rohm_rpr0521.c              \
+    os/drivers/tilt_detection/tilt_detection.c          \
+    os/drivers/vsync/vsync.c                            \
+    os/drivers/window_orientation/window_orientation.c  \
diff --git a/firmware/src/algos/accel_cal.c b/firmware/os/algos/accel_cal.c
index a1db612e..a1db612e 100644
--- a/firmware/src/algos/accel_cal.c
+++ b/firmware/os/algos/accel_cal.c
diff --git a/firmware/src/algos/ap_hub_sync.c b/firmware/os/algos/ap_hub_sync.c
index ac04d370..f771163b 100644
--- a/firmware/src/algos/ap_hub_sync.c
+++ b/firmware/os/algos/ap_hub_sync.c
@@ -15,7 +15,7 @@
  */
 
 #include <algos/ap_hub_sync.h>
-#include <cpu/inc/cpuMath.h>
+#include <cpu/cpuMath.h>
 
 #include <limits.h>
 #include <seos.h>
diff --git a/firmware/src/algos/fusion.c b/firmware/os/algos/fusion.c
index a786cef5..a786cef5 100644
--- a/firmware/src/algos/fusion.c
+++ b/firmware/os/algos/fusion.c
diff --git a/firmware/src/algos/gyro_cal.c b/firmware/os/algos/gyro_cal.c
index 0b30fc32..0b30fc32 100644
--- a/firmware/src/algos/gyro_cal.c
+++ b/firmware/os/algos/gyro_cal.c
diff --git a/firmware/src/algos/gyro_stillness_detect.c b/firmware/os/algos/gyro_stillness_detect.c
index 89f4ab81..89f4ab81 100644
--- a/firmware/src/algos/gyro_stillness_detect.c
+++ b/firmware/os/algos/gyro_stillness_detect.c
diff --git a/firmware/src/algos/mag_cal.c b/firmware/os/algos/mag_cal.c
index e8b27ea7..e8b27ea7 100644
--- a/firmware/src/algos/mag_cal.c
+++ b/firmware/os/algos/mag_cal.c
diff --git a/firmware/src/algos/mat.c b/firmware/os/algos/mat.c
index d5ae315a..d5ae315a 100644
--- a/firmware/src/algos/mat.c
+++ b/firmware/os/algos/mat.c
diff --git a/firmware/src/algos/quat.c b/firmware/os/algos/quat.c
index b7be5a5d..b7be5a5d 100644
--- a/firmware/src/algos/quat.c
+++ b/firmware/os/algos/quat.c
diff --git a/firmware/src/algos/time_sync.c b/firmware/os/algos/time_sync.c
index 830fe7f3..830fe7f3 100644
--- a/firmware/src/algos/time_sync.c
+++ b/firmware/os/algos/time_sync.c
diff --git a/firmware/src/algos/vec.c b/firmware/os/algos/vec.c
index 3f7493ce..3f7493ce 100644
--- a/firmware/src/algos/vec.c
+++ b/firmware/os/algos/vec.c
diff --git a/firmware/src/appSec.c b/firmware/os/core/appSec.c
index de7421ac..94cfedac 100644
--- a/firmware/src/appSec.c
+++ b/firmware/os/core/appSec.c
@@ -14,20 +14,19 @@
  * limitations under the License.
  */
 
+#include <inttypes.h>
 #include <stdint.h>
+#include <stdio.h>
+#include <string.h>
 
-#include <plat/inc/bl.h>
-
-#include <nanohub/sha2.h>
-#include <nanohub/rsa.h>
 #include <nanohub/aes.h>
+#include <nanohub/rsa.h>
+#include <nanohub/sha2.h>
 
 #include <appSec.h>
-#include <string.h>
-#include <stdio.h>
+#include <bl.h>
 #include <heap.h>
 #include <seos.h>
-#include <inttypes.h>
 
 #define APP_HDR_SIZE                (sizeof(struct ImageHeader))
 #define APP_HDR_MAX_SIZE            (sizeof(struct ImageHeader) + sizeof(struct AppSecSignHdr) + sizeof(struct AppSecEncrHdr))
diff --git a/firmware/src/platform/stm32f4xx/bl.c b/firmware/os/core/bl.c
index 2786c365..706a7492 100644
--- a/firmware/src/platform/stm32f4xx/bl.c
+++ b/firmware/os/core/bl.c
@@ -14,13 +14,12 @@
  * limitations under the License.
  */
 
+#include <variant/variant.h>
 
-#include <variant/inc/variant.h>
+#include <bl.h>
 
-#include <plat/inc/cmsis.h>
-#include <plat/inc/gpio.h>
-#include <plat/inc/pwr.h>
-#include <plat/inc/bl.h>
+#include <plat/cmsis.h>
+#include <plat/gpio.h>
 
 #include <nanohub/sha2.h>
 #include <nanohub/aes.h>
@@ -29,128 +28,9 @@
 
 #include <printf.h>
 #include <string.h>
-#include <alloca.h>
-#include <gpio.h>
 
 static uint32_t blVerifyOsImage(const uint8_t *addr, struct OsUpdateHdr **start, uint32_t *size);
 
-struct StmCrc
-{
-    volatile uint32_t DR;
-    volatile uint32_t IDR;
-    volatile uint32_t CR;
-};
-
-struct StmFlash
-{
-    volatile uint32_t ACR;
-    volatile uint32_t KEYR;
-    volatile uint32_t OPTKEYR;
-    volatile uint32_t SR;
-    volatile uint32_t CR;
-    volatile uint32_t OPTCR;
-};
-
-struct StmRcc {
-    volatile uint32_t CR;
-    volatile uint32_t PLLCFGR;
-    volatile uint32_t CFGR;
-    volatile uint32_t CIR;
-    volatile uint32_t AHB1RSTR;
-    volatile uint32_t AHB2RSTR;
-    volatile uint32_t AHB3RSTR;
-    uint8_t unused0[4];
-    volatile uint32_t APB1RSTR;
-    volatile uint32_t APB2RSTR;
-    uint8_t unused1[8];
-    volatile uint32_t AHB1ENR;
-    volatile uint32_t AHB2ENR;
-    volatile uint32_t AHB3ENR;
-    uint8_t unused2[4];
-    volatile uint32_t APB1ENR;
-    volatile uint32_t APB2ENR;
-    uint8_t unused3[8];
-    volatile uint32_t AHB1LPENR;
-    volatile uint32_t AHB2LPENR;
-    volatile uint32_t AHB3LPENR;
-    uint8_t unused4[4];
-    volatile uint32_t APB1LPENR;
-    volatile uint32_t APB2LPENR;
-    uint8_t unused5[8];
-    volatile uint32_t BDCR;
-    volatile uint32_t CSR;
-    uint8_t unused6[8];
-    volatile uint32_t SSCGR;
-    volatile uint32_t PLLI2SCFGR;
-};
-
-struct StmUdid
-{
-    volatile uint32_t U_ID[3];
-};
-
-struct StmSpi {
-    volatile uint32_t CR1;
-    volatile uint32_t CR2;
-    volatile uint32_t SR;
-    volatile uint32_t DR;
-    volatile uint32_t CRCPR;
-    volatile uint32_t RXCRCR;
-    volatile uint32_t TXCRCR;
-    volatile uint32_t I2SCFGR;
-    volatile uint32_t I2SPR;
-};
-
-struct StmGpio {
-    volatile uint32_t MODER;
-    volatile uint32_t OTYPER;
-    volatile uint32_t OSPEEDR;
-    volatile uint32_t PUPDR;
-    volatile uint32_t IDR;
-    volatile uint32_t ODR;
-    volatile uint32_t BSRR;
-    volatile uint32_t LCKR;
-    volatile uint32_t AFR[2];
-};
-
-//stm defines
-#define BL_MAX_FLASH_CODE   1024
-
-
-#define FLASH_ACR_LAT(x)    ((x) & FLASH_ACR_LAT_MASK)
-#define FLASH_ACR_LAT_MASK  0x0F
-#define FLASH_ACR_PRFTEN    0x00000100
-#define FLASH_ACR_ICEN      0x00000200
-#define FLASH_ACR_DCEN      0x00000400
-#define FLASH_ACR_ICRST     0x00000800
-#define FLASH_ACR_DCRST     0x00001000
-
-#define FLASH_SR_EOP        0x00000001
-#define FLASH_SR_OPERR      0x00000002
-#define FLASH_SR_WRPERR     0x00000010
-#define FLASH_SR_PGAERR     0x00000020
-#define FLASH_SR_PGPERR     0x00000040
-#define FLASH_SR_PGSERR     0x00000080
-#define FLASH_SR_RDERR      0x00000100
-#define FLASH_SR_BSY        0x00010000
-
-#define FLASH_CR_PG         0x00000001
-#define FLASH_CR_SER        0x00000002
-#define FLASH_CR_MER        0x00000004
-#define FLASH_CR_SNB(x)     (((x) << FLASH_CR_SNB_SHIFT) & FLASH_CR_SNB_MASK)
-#define FLASH_CR_SNB_MASK   0x00000078
-#define FLASH_CR_SNB_SHIFT  3
-#define FLASH_CR_PSIZE(x)   (((x) << FLASH_CR_PSIZE_SHIFT) & FLASH_CR_PSIZE_MASK)
-#define FLASH_CR_PSIZE_MASK 0x00000300
-#define FLASH_CR_PSIZE_SHIFT 8
-#define FLASH_CR_PSIZE_8    0x0
-#define FLASH_CR_PSIZE_16   0x1
-#define FLASH_CR_PSIZE_32   0x2
-#define FLASH_CR_PSIZE_64   0x3
-#define FLASH_CR_STRT       0x00010000
-#define FLASH_CR_EOPIE      0x01000000
-#define FLASH_CR_ERRIE      0x02000000
-#define FLASH_CR_LOCK       0x80000000
 
 //for comms protocol
 #define BL_SYNC_IN                      0x5A
@@ -165,29 +45,22 @@ struct StmGpio {
 #define BL_CMD_GET_SIZES                0xEE /* our own command. reports: {u32 osSz, u32 sharedSz, u32 eeSz} all in big endian */
 #define BL_CMD_UPDATE_FINISHED          0xEF /* our own command. attempts to verify the update -> ACK/NAK. MUST be called after upload to mark it as completed */
 
+#define BL_ERROR                        0xDEADBEAF /* returned in place of command in case of exchange errors */
+
+
 #define BL_SHARED_AREA_FAKE_ERASE_BLK   0xFFF0
 #define BL_SHARED_AREA_FAKE_ADDR        0x50000000
 
 
-typedef void (*FlashEraseF)(volatile uint32_t *, uint32_t, volatile uint32_t *);
-typedef void (*FlashWriteF)(volatile uint8_t *, uint8_t, volatile uint32_t *);
-
 //linker provides these
 extern uint32_t __pubkeys_start[];
 extern uint32_t __pubkeys_end[];
-extern uint8_t __stack_top[];
-extern uint8_t __ram_start[];
-extern uint8_t __ram_end[];
 extern uint8_t __eedata_start[];
 extern uint8_t __eedata_end[];
 extern uint8_t __code_start[];
 extern uint8_t __code_end[];
 extern uint8_t __shared_start[];
 extern uint8_t __shared_end[];
-extern void __VECTORS();
-
-//make GCC happy
-void __blEntry(void);
 
 enum BlFlashType
 {
@@ -220,10 +93,6 @@ BL_FLASH_TABLE;
 
 static const char mOsUpdateMagic[] = OS_UPDT_MAGIC;
 
-//BL stack
-uint64_t __attribute__ ((section (".stack"))) _STACK[BL_STACK_SIZE / sizeof(uint64_t)];
-
-
 #ifdef DEBUG_UART_PIN
 
 static bool blLogPutcharF(void *userData, char ch)
@@ -251,186 +120,15 @@ void blLog(const char *str, ...)
 
 #endif
 
-static inline uint32_t blDisableInts(void)
-{
-    uint32_t state;
-
-    asm volatile (
-        "mrs %0, PRIMASK    \n"
-        "cpsid i            \n"
-        :"=r"(state)
-    );
-
-    return state;
-}
-
-static inline void blRestoreInts(uint32_t state)
-{
-    asm volatile(
-        "msr PRIMASK, %0   \n"
-        ::"r"((uint32_t)state)
-    );
-}
-
 static uint32_t blExtApiGetVersion(void)
 {
     return BL_VERSION_CUR;
 }
 
-static void blExtApiReboot(void)
-{
-    SCB->AIRCR = 0x05FA0004;
-    //we never get here
-    while(1);
-}
-
-static void blExtApiGetSnum(uint32_t *snum, uint32_t length)
-{
-    struct StmUdid *reg = (struct StmUdid *)UDID_BASE;
-    uint32_t i;
-
-    if (length > 3)
-        length = 3;
-
-    for (i = 0; i < length; i++)
-        snum[i] = reg->U_ID[i];
-}
-
-/*
- * Return the address of the erase code and the length of the code
- *
- * This code needs to run out of ram and not flash since accessing flash
- * while erasing is undefined (best case the processor stalls, worst case
- * it starts executing garbage)
- *
- * This function is used to get a pointer to the actual code that does the
- * erase and polls for completion (so we can copy it to ram) as well as the
- * length of the code (so we know how much space to allocate for it)
- *
- * void FlashEraseF(volatile uint32_t *addr, uint32_t value, volatile uint32_t *status)
- * {
- *     *addr = value;
- *     while (*status & FLASH_SR_BSY) ;
- * }
- */
-static void __attribute__((naked)) blGetFlashEraseCode(uint16_t **addr, uint32_t *size)
-{
-    asm volatile (
-        "  push {lr}          \n"
-        "  bl   9f            \n"
-        "  str  r1, [r0, #0]  \n" // *addr = value
-        "1:                   \n"
-        "  ldr  r3, [r2, #0]  \n" // r3 = *status
-        "  lsls r3, #15       \n" // r3 <<= 15
-        "  bmi  1b            \n" // if (r3 < 0) goto 1
-        "  bx   lr            \n" // return
-        "9:                   \n"
-        "  bic  lr, #0x1      \n"
-        "  adr  r3, 9b        \n"
-        "  sub  r3, lr        \n"
-        "  str  lr, [r0]      \n"
-        "  str  r3, [r1]      \n"
-        "  pop {pc}           \n"
-    );
-}
-
-/*
- * Return the address of the write code and the length of the code
- *
- * This code needs to run out of ram and not flash since accessing flash
- * while writing to flash is undefined (best case the processor stalls, worst
- * case it starts executing garbage)
- *
- * This function is used to get a pointer to the actual code that does the
- * write and polls for completion (so we can copy it to ram) as well as the
- * length of the code (so we know how much space to allocate for it)
- *
- * void FlashWriteF(volatile uint8_t *addr, uint8_t value, volatile uint32_t *status)
- * {
- *     *addr = value;
- *     while (*status & FLASH_SR_BSY) ;
- * }
- */
-static void __attribute__((naked)) blGetFlashWriteCode(uint16_t **addr, uint32_t *size)
-{
-    asm volatile (
-        "  push {lr}          \n"
-        "  bl   9f            \n"
-        "  strb r1, [r0, #0]  \n" // *addr = value
-        "1:                   \n"
-        "  ldr  r3, [r2, #0]  \n" // r3 = *status
-        "  lsls r3, #15       \n" // r3 <<= 15
-        "  bmi  1b            \n" // if (r3 < 0) goto 1
-        "  bx   lr            \n" // return
-        "9:                   \n"
-        "  bic  lr, #0x1      \n"
-        "  adr  r3, 9b        \n"
-        "  sub  r3, lr        \n"
-        "  str  lr, [r0]      \n"
-        "  str  r3, [r1]      \n"
-        "  pop {pc}           \n"
-    );
-}
-
-static void blEraseSectors(uint32_t sector_cnt, uint8_t *erase_mask)
-{
-    struct StmFlash *flash = (struct StmFlash *)FLASH_BASE;
-    uint16_t *code_src, *code;
-    uint32_t i, code_length;
-    FlashEraseF func;
-
-    blGetFlashEraseCode(&code_src, &code_length);
-
-    if (code_length < BL_MAX_FLASH_CODE) {
-        code = (uint16_t *)(((uint32_t)alloca(code_length + 1) + 1) & ~0x1);
-        func = (FlashEraseF)((uint8_t *)code+1);
-
-        for (i = 0; i < code_length / sizeof(uint16_t); i++)
-            code[i] = code_src[i];
-
-        for (i = 0; i < sector_cnt; i++) {
-            if (erase_mask[i]) {
-                flash->CR = (flash->CR & ~(FLASH_CR_SNB_MASK)) |
-                    FLASH_CR_SNB(i) | FLASH_CR_SER;
-                func(&flash->CR, flash->CR | FLASH_CR_STRT, &flash->SR);
-                flash->CR &= ~(FLASH_CR_SNB_MASK | FLASH_CR_SER);
-            }
-        }
-    }
-}
-
-static void blWriteBytes(uint8_t *dst, const uint8_t *src, uint32_t length)
-{
-    struct StmFlash *flash = (struct StmFlash *)FLASH_BASE;
-    uint16_t *code_src, *code;
-    uint32_t i, code_length;
-    FlashWriteF func;
-
-    blGetFlashWriteCode(&code_src, &code_length);
-
-    if (code_length < BL_MAX_FLASH_CODE) {
-        code = (uint16_t *)(((uint32_t)alloca(code_length+1) + 1) & ~0x1);
-        func = (FlashWriteF)((uint8_t *)code+1);
-
-        for (i = 0; i < code_length / sizeof(uint16_t); i++)
-            code[i] = code_src[i];
-
-        flash->CR |= FLASH_CR_PG;
-
-        for (i = 0; i < length; i++) {
-            if (dst[i] != src[i])
-                func(&dst[i], src[i], &flash->SR);
-        }
-
-        flash->CR &= ~FLASH_CR_PG;
-    }
-}
-
 static bool blProgramFlash(uint8_t *dst, const uint8_t *src, uint32_t length, uint32_t key1, uint32_t key2)
 {
-    struct StmFlash *flash = (struct StmFlash *)FLASH_BASE;
     const uint32_t sector_cnt = sizeof(mBlFlashTable) / sizeof(struct blFlashTable);
-    uint32_t acr_cache, cr_cache, offset, i, j = 0, int_state = 0;
+    uint32_t offset, i, j = 0;
     uint8_t *ptr;
 
     if (((length == 0)) ||
@@ -469,47 +167,17 @@ static bool blProgramFlash(uint8_t *dst, const uint8_t *src, uint32_t length, ui
         }
     }
 
-    // disable interrupts
-    // otherwise an interrupt during flash write will stall the processor
-    // until the write completes
-    int_state = blDisableInts();
-
-    // wait for flash to not be busy (should never be set at this point)
-    while (flash->SR & FLASH_SR_BSY);
-
-    cr_cache = flash->CR;
-
-    if (flash->CR & FLASH_CR_LOCK) {
-        // unlock flash
-        flash->KEYR = key1;
-        flash->KEYR = key2;
-    }
-
-    if (flash->CR & FLASH_CR_LOCK) {
-        // unlock failed, restore interrupts
-        blRestoreInts(int_state);
-
+    if (!blPlatProgramFlash(dst, src, length, key1, key2))
         return false;
-    }
-
-    flash->CR = FLASH_CR_PSIZE(FLASH_CR_PSIZE_8);
-
-    acr_cache = flash->ACR;
-
-    // disable and flush data and instruction caches
-    flash->ACR &= ~(FLASH_ACR_DCEN | FLASH_ACR_ICEN);
-    flash->ACR |= (FLASH_ACR_DCRST | FLASH_ACR_ICRST);
-
-    blWriteBytes(dst, src, length);
-
-    flash->ACR = acr_cache;
-    flash->CR = cr_cache;
-
-    blRestoreInts(int_state);
 
     return !memcmp(dst, src, length);
 }
 
+static void blExtApiGetSnum(uint32_t *snum, uint32_t length)
+{
+    blGetSnum(snum, length);
+}
+
 static bool blProgramTypedArea(uint8_t *dst, const uint8_t *src, uint32_t length, uint32_t type, uint32_t key1, uint32_t key2)
 {
     const uint32_t sector_cnt = sizeof(mBlFlashTable) / sizeof(struct blFlashTable);
@@ -541,9 +209,8 @@ static bool blExtApiProgramEe(uint8_t *dst, const uint8_t *src, uint32_t length,
 
 static bool blEraseTypedArea(uint32_t type, uint32_t key1, uint32_t key2)
 {
-    struct StmFlash *flash = (struct StmFlash *)FLASH_BASE;
     const uint32_t sector_cnt = sizeof(mBlFlashTable) / sizeof(struct blFlashTable);
-    uint32_t i, acr_cache, cr_cache, erase_cnt = 0, int_state = 0;
+    uint32_t i, erase_cnt = 0;
     uint8_t erase_mask[sector_cnt];
 
     for (i = 0; i < sector_cnt; i++) {
@@ -555,45 +222,8 @@ static bool blEraseTypedArea(uint32_t type, uint32_t key1, uint32_t key2)
         }
     }
 
-    // disable interrupts
-    // otherwise an interrupt during flash write/erase will stall the processor
-    // until the write/erase completes
-    int_state = blDisableInts();
-
-    // wait for flash to not be busy (should never be set at this point)
-    while (flash->SR & FLASH_SR_BSY);
-
-    cr_cache = flash->CR;
-
-    if (flash->CR & FLASH_CR_LOCK) {
-        // unlock flash
-        flash->KEYR = key1;
-        flash->KEYR = key2;
-    }
-
-    if (flash->CR & FLASH_CR_LOCK) {
-        // unlock failed, restore interrupts
-        blRestoreInts(int_state);
-
-        return false;
-    }
-
-    flash->CR = FLASH_CR_PSIZE(FLASH_CR_PSIZE_8);
-
-    acr_cache = flash->ACR;
-
-    // disable and flush data and instruction caches
-    flash->ACR &= ~(FLASH_ACR_DCEN | FLASH_ACR_ICEN);
-    flash->ACR |= (FLASH_ACR_DCRST | FLASH_ACR_ICRST);
-
     if (erase_cnt)
-        blEraseSectors(sector_cnt, erase_mask);
-
-    flash->ACR = acr_cache;
-    flash->CR = cr_cache;
-
-    // restore interrupts
-    blRestoreInts(int_state);
+        blEraseSectors(sector_cnt, erase_mask, key1, key2);
 
     return true; //we assume erase worked
 }
@@ -622,10 +252,9 @@ static uint32_t blExtApiVerifyOsUpdate(void)
     return blVerifyOsUpdate(NULL, NULL);
 }
 
-static void blSupirousIntHandler(void)
+static void blExtApiReboot(void)
 {
-    //BAD!
-    blExtApiReboot();
+    blReboot();
 }
 
 static const uint32_t *blExtApiGetRsaKeyInfo(uint32_t *numKeys)
@@ -668,40 +297,6 @@ static const uint32_t* blExtApiSigPaddingVerify(const uint32_t *rsaResult)
     return rsaResult;
 }
 
-const struct BlVecTable __attribute__((section(".blvec"))) __BL_VECTORS =
-{
-    /* cortex */
-    .blStackTop = (uint32_t)&__stack_top,
-    .blEntry = &__blEntry,
-    .blNmiHandler = &blSupirousIntHandler,
-    .blMmuFaultHandler = &blSupirousIntHandler,
-    .blBusFaultHandler = &blSupirousIntHandler,
-    .blUsageFaultHandler = &blSupirousIntHandler,
-
-    /* api */
-    .blGetVersion = &blExtApiGetVersion,
-    .blReboot = &blExtApiReboot,
-    .blGetSnum = &blExtApiGetSnum,
-    .blProgramShared = &blExtApiProgramSharedArea,
-    .blEraseShared = &blExtApiEraseSharedArea,
-    .blProgramEe = &blExtApiProgramEe,
-    .blGetPubKeysInfo = &blExtApiGetRsaKeyInfo,
-    .blRsaPubOpIterative = &rsaPubOpIterative,
-    .blSha2init = &sha2init,
-    .blSha2processBytes = &sha2processBytes,
-    .blSha2finish = &sha2finish,
-    .blAesInitForEncr = &aesInitForEncr,
-    .blAesInitForDecr = &aesInitForDecr,
-    .blAesEncr = &aesEncr,
-    .blAesDecr = &aesDecr,
-    .blAesCbcInitForEncr = &aesCbcInitForEncr,
-    .blAesCbcInitForDecr = &aesCbcInitForDecr,
-    .blAesCbcEncr = &aesCbcEncr,
-    .blAesCbcDecr = &aesCbcDecr,
-    .blSigPaddingVerify = &blExtApiSigPaddingVerify,
-    .blVerifyOsUpdate = &blExtApiVerifyOsUpdate,
-};
-
 static void blApplyVerifiedUpdate(const struct OsUpdateHdr *os) //only called if an update has been found to exist and be valid, signed, etc!
 {
     //copy shared to code, and if successful, erase shared area
@@ -832,124 +427,86 @@ static inline bool blUpdateVerify()
     return blVerifyOsImage(__shared_start, NULL, NULL) == OS_UPDT_SUCCESS;
 }
 
-static void blSpiLoaderDrainRxFifo(struct StmSpi *spi)
+static uint8_t blLoaderRxByte()
 {
-    (void)spi->DR;
-    while (!(spi->SR & 1));
-    (void)spi->DR;
+    return blSpiTxRxByte(0);
 }
 
-static uint8_t blSpiLoaderTxRxByte(struct StmSpi *spi, uint32_t val)
+static void blLoaderTxByte(uint32_t val)
 {
-    while (!(spi->SR & 2));
-    spi->DR = val;
-    while (!(spi->SR & 1));
-    return spi->DR;
+    blSpiTxRxByte(val);
 }
 
-static void blSpiLoaderTxBytes(struct StmSpi *spi, const void *data, uint32_t len)
+static void blLoaderTxBytes(const void *data, uint32_t len)
 {
     const uint8_t *buf = (const uint8_t*)data;
 
-    blSpiLoaderTxRxByte(spi, len - 1);
+    blLoaderTxByte(len - 1);
     while (len--)
-        blSpiLoaderTxRxByte(spi, *buf++);
+        blLoaderTxByte(*buf++);
 }
 
-static bool blSpiLoaderSendSyncOut(struct StmSpi *spi)
+static bool blLoaderSendSyncOut()
 {
-    return blSpiLoaderTxRxByte(spi, BL_SYNC_OUT) == BL_SYNC_IN;
+    return blSpiTxRxByte(BL_SYNC_OUT) == BL_SYNC_IN;
 }
 
-static bool blSpiLoaderSendAck(struct StmSpi *spi, bool ack)
+static bool blLoaderSendAck(bool ack)
 {
-    blSpiLoaderTxRxByte(spi, 0);
-    blSpiLoaderTxRxByte(spi, ack ? BL_ACK : BL_NAK);
-    return blSpiLoaderTxRxByte(spi, 0) == BL_ACK;
+    blLoaderRxByte();
+    blLoaderTxByte(ack ? BL_ACK : BL_NAK);
+    return blLoaderRxByte() == BL_ACK;
 }
 
-static void blSpiLoader(bool force)
+static uint32_t blLoaderRxCmd()
+{
+    uint8_t cmd = blLoaderRxByte();
+    uint8_t cmdNot = blSpiTxRxByte(BL_ACK);
+    return (cmd ^ cmdNot) == 0xFF ? cmd : BL_ERROR;
+}
+
+static void blLoader(bool force)
 {
-    const uint32_t intInPin = SH_INT_WAKEUP - GPIO_PA(0);
-    struct StmGpio *gpioa = (struct StmGpio*)GPIOA_BASE;
-    struct StmSpi *spi = (struct StmSpi*)SPI1_BASE;
-    struct StmRcc *rcc = (struct StmRcc*)RCC_BASE;
-    uint32_t oldApb2State, oldAhb1State, nRetries;
     bool seenErase = false;
     uint32_t nextAddr = 0;
     uint32_t expectedSize = 0;
 
-    if (SH_INT_WAKEUP < GPIO_PA(0) || SH_INT_WAKEUP > GPIO_PA(15)) {
-
-        //link time assert :)
-        extern void ThisIsAnError_BlIntPinNotInGpioA(void);
-        ThisIsAnError_BlIntPinNotInGpioA();
-    }
-
-    //SPI & GPIOA on
-    oldApb2State = rcc->APB2ENR;
-    oldAhb1State = rcc->AHB1ENR;
-    rcc->APB2ENR |= PERIPH_APB2_SPI1;
-    rcc->AHB1ENR |= PERIPH_AHB1_GPIOA;
-
-    //reset units
-    rcc->APB2RSTR |= PERIPH_APB2_SPI1;
-    rcc->AHB1RSTR |= PERIPH_AHB1_GPIOA;
-    rcc->APB2RSTR &=~ PERIPH_APB2_SPI1;
-    rcc->AHB1RSTR &=~ PERIPH_AHB1_GPIOA;
-
-    //configure GPIOA for SPI A4..A7 for SPI use (function 5), int pin as not func, high speed, no pullups, not open drain, proper directions
-    gpioa->AFR[0] = (gpioa->AFR[0] & 0x0000ffff & ~(0x0f << (intInPin * 4))) | 0x55550000;
-    gpioa->OSPEEDR |= 0x0000ff00 | (3 << (intInPin * 2));
-    gpioa->PUPDR &=~ (0x0000ff00 | (3 << (intInPin * 2)));
-    gpioa->OTYPER &=~ (0x00f0 | (1 << intInPin));
-    gpioa->MODER = (gpioa->MODER & 0xffff00ff & ~(0x03 << (intInPin * 2))) | 0x0000aa00;
+    blSetup();
 
     //if int pin is not low, do not bother any further
-    if (!(gpioa->IDR & (1 << intInPin)) || force) {
+    if (blHostActive() || force) {
 
-        //config SPI
-        spi->CR1 = 0x00000040; //spi is on, configured same as bootloader would
-        spi->CR2 = 0x00000000; //spi is on, configured same as bootloader would
-
-        //wait for sync
-        for (nRetries = 10000; nRetries; nRetries--) {
-            if (spi->SR & 1) {
-                if (spi->DR == BL_SYNC_IN)
-                    break;
-                (void)spi->SR; //re-read to clear overlfow condition (if any)
-            }
-        }
+        blConfigIo();
 
         //if we saw a sync, do the bootloader thing
-        if (nRetries) {
+        if (blSyncWait(BL_SYNC_IN)) {
             static const uint8_t supportedCmds[] = {BL_CMD_GET, BL_CMD_READ_MEM, BL_CMD_WRITE_MEM, BL_CMD_ERASE, BL_CMD_GET_SIZES, BL_CMD_UPDATE_FINISHED};
             uint32_t allSizes[] = {__builtin_bswap32(__code_end - __code_start), __builtin_bswap32(__shared_end - __shared_start), __builtin_bswap32(__eedata_end - __eedata_start)};
             bool ack = true;  //we ack the sync
 
-            ack = blSpiLoaderSendSyncOut(spi);
+            ack = blLoaderSendSyncOut();
 
             //loop forever listening to commands
             while (1) {
-                uint32_t sync, cmd, cmdNot, addr = 0, len, checksum = 0, i;
+                uint32_t sync, cmd, addr = 0, len, checksum = 0, i;
                 uint8_t data[256];
 
                 //send ack or NAK for last thing
-                if (!blSpiLoaderSendAck(spi, ack))
+                if (!blLoaderSendAck(ack))
                     goto out;
 
-                while ((sync = blSpiLoaderTxRxByte(spi, 0)) != BL_SYNC_IN);
-                cmd = blSpiLoaderTxRxByte(spi, 0);
-                cmdNot = blSpiLoaderTxRxByte(spi, BL_ACK);
+                while ((sync = blLoaderRxByte()) != BL_SYNC_IN);
+                cmd = blLoaderRxCmd();
 
                 ack = false;
-                if (sync == BL_SYNC_IN && (cmd ^ cmdNot) == 0xff) switch (cmd) {
+                if (sync == BL_SYNC_IN && cmd != BL_ERROR)
+                switch (cmd) {
                 case BL_CMD_GET:
 
                     //ACK the command
-                    (void)blSpiLoaderSendAck(spi, true);
+                    (void)blLoaderSendAck(true);
 
-                    blSpiLoaderTxBytes(spi, supportedCmds, sizeof(supportedCmds));
+                    blLoaderTxBytes(supportedCmds, sizeof(supportedCmds));
                     ack = true;
                     break;
 
@@ -958,27 +515,27 @@ static void blSpiLoader(bool force)
                         break;
 
                     //ACK the command
-                    (void)blSpiLoaderSendAck(spi, true);
+                    (void)blLoaderSendAck(true);
 
                     //get address
                     for (i = 0; i < 4; i++) {
-                        uint32_t byte = blSpiLoaderTxRxByte(spi, 0);
+                        uint32_t byte = blLoaderRxByte();
                         checksum ^= byte;
                         addr = (addr << 8) + byte;
                     }
 
                     //reject addresses outside of our fake area or on invalid checksum
-                    if (blSpiLoaderTxRxByte(spi, 0) != checksum || addr < BL_SHARED_AREA_FAKE_ADDR || addr - BL_SHARED_AREA_FAKE_ADDR > __shared_end - __shared_start)
+                    if (blLoaderRxByte() != checksum || addr < BL_SHARED_AREA_FAKE_ADDR || addr - BL_SHARED_AREA_FAKE_ADDR > __shared_end - __shared_start)
                        break;
 
                     //ack the address
-                    (void)blSpiLoaderSendAck(spi, true);
+                    (void)blLoaderSendAck(true);
 
                     //get the length
-                    len = blSpiLoaderTxRxByte(spi, 0);
+                    len = blLoaderRxByte();
 
                     //reject invalid checksum
-                    if (blSpiLoaderTxRxByte(spi, 0) != (uint8_t)~len || addr + len - BL_SHARED_AREA_FAKE_ADDR > __shared_end - __shared_start)
+                    if (blLoaderRxByte() != (uint8_t)~len || addr + len - BL_SHARED_AREA_FAKE_ADDR > __shared_end - __shared_start)
                        break;
 
                     len++;
@@ -988,10 +545,10 @@ static void blSpiLoader(bool force)
                        break;
 
                     //ack the length
-                    (void)blSpiLoaderSendAck(spi, true);
+                    (void)blLoaderSendAck(true);
 
                     //read the data & send it
-                    blSpiLoaderTxBytes(spi, __shared_start + addr - BL_SHARED_AREA_FAKE_ADDR, len);
+                    blLoaderTxBytes(__shared_start + addr - BL_SHARED_AREA_FAKE_ADDR, len);
                     ack = true;
                     break;
 
@@ -1000,17 +557,17 @@ static void blSpiLoader(bool force)
                         break;
 
                     //ACK the command
-                    (void)blSpiLoaderSendAck(spi, true);
+                    (void)blLoaderSendAck(true);
 
                     //get address
                     for (i = 0; i < 4; i++) {
-                        uint32_t byte = blSpiLoaderTxRxByte(spi, 0);
+                        uint32_t byte = blLoaderRxByte();
                         checksum ^= byte;
                         addr = (addr << 8) + byte;
                     }
 
                     //reject addresses outside of our fake area or on invalid checksum
-                    if (blSpiLoaderTxRxByte(spi, 0) != checksum ||
+                    if (blLoaderRxByte() != checksum ||
                         addr < BL_SHARED_AREA_FAKE_ADDR ||
                         addr - BL_SHARED_AREA_FAKE_ADDR > __shared_end - __shared_start)
                         break;
@@ -1020,21 +577,21 @@ static void blSpiLoader(bool force)
                         break;
 
                     //ack the address
-                    (void)blSpiLoaderSendAck(spi, true);
+                    (void)blLoaderSendAck(true);
 
                     //get the length
-                    checksum = len = blSpiLoaderTxRxByte(spi, 0);
+                    checksum = len = blLoaderRxByte();
                     len++;
 
                     //get bytes
                     for (i = 0; i < len; i++) {
-                        uint32_t byte = blSpiLoaderTxRxByte(spi, 0);
+                        uint32_t byte = blLoaderRxByte();
                         checksum ^= byte;
                         data[i] = byte;
                     }
 
                     //reject writes that takes out outside fo shared area or invalid checksums
-                    if (blSpiLoaderTxRxByte(spi, 0) != checksum || addr + len > __shared_end - __shared_start)
+                    if (blLoaderRxByte() != checksum || addr + len > __shared_end - __shared_start)
                        break;
 
                     // OBSOLETE: superseded by sequential contiguous write requirement
@@ -1062,24 +619,24 @@ static void blSpiLoader(bool force)
 
                     //do it
                     ack = blExtApiProgramSharedArea(__shared_start + addr, data, len, BL_FLASH_KEY1, BL_FLASH_KEY2);
-                    blSpiLoaderDrainRxFifo(spi);
+                    blResetRxData();
                     nextAddr += len;
                     break;
 
                 case BL_CMD_ERASE:
 
                     //ACK the command
-                    (void)blSpiLoaderSendAck(spi, true);
+                    (void)blLoaderSendAck(true);
 
                     //get address
                     for (i = 0; i < 2; i++) {
-                        uint32_t byte = blSpiLoaderTxRxByte(spi, 0);
+                        uint32_t byte = blLoaderRxByte();
                         checksum ^= byte;
                         addr = (addr << 8) + byte;
                     }
 
                     //reject addresses that are not our magic address or on invalid checksum
-                    if (blSpiLoaderTxRxByte(spi, 0) != checksum || addr != BL_SHARED_AREA_FAKE_ERASE_BLK)
+                    if (blLoaderRxByte() != checksum || addr != BL_SHARED_AREA_FAKE_ERASE_BLK)
                         break;
 
                     //do it
@@ -1089,15 +646,15 @@ static void blSpiLoader(bool force)
                         nextAddr = 0;
                         expectedSize = 0;
                     }
-                    blSpiLoaderDrainRxFifo(spi);
+                    blResetRxData();
                     break;
 
                 case BL_CMD_GET_SIZES:
 
                     //ACK the command
-                    (void)blSpiLoaderSendAck(spi, true);
+                    (void)blLoaderSendAck(true);
 
-                    blSpiLoaderTxBytes(spi, allSizes, sizeof(allSizes));
+                    blLoaderTxBytes(allSizes, sizeof(allSizes));
                     break;
 
                 case BL_CMD_UPDATE_FINISHED:
@@ -1110,38 +667,21 @@ static void blSpiLoader(bool force)
     }
 
 out:
-    //reset units & return APB2 & AHB1 to initial state
-    rcc->APB2RSTR |= PERIPH_APB2_SPI1;
-    rcc->AHB1RSTR |= PERIPH_AHB1_GPIOA;
-    rcc->APB2RSTR &=~ PERIPH_APB2_SPI1;
-    rcc->AHB1RSTR &=~ PERIPH_AHB1_GPIOA;
-    rcc->APB2ENR = oldApb2State;
-    rcc->AHB1ENR = oldAhb1State;
+    blCleanup();
 }
 
-void __blEntry(void)
+void blMain(uint32_t appBase)
 {
-    extern char __bss_end[], __bss_start[], __data_end[], __data_start[], __data_data[];
-    uint32_t appBase = ((uint32_t)&__code_start) & ~1;
     bool forceLoad = false;
 
-    //make sure we're the vector table and no ints happen (BL does not use them)
-    blDisableInts();
-    SCB->VTOR = (uint32_t)&BL;
-
-    //init things a little for the higher levels
-    memset(__bss_start, 0, __bss_end - __bss_start);
-    memcpy(__data_start, __data_data, __data_end - __data_start);
-
-    //say hello
-    blLog("NanohubOS bootloader up @ %p\n", &__blEntry);
+    blLog("NanohubOS bootloader up @ %p\n", &blMain);
 
     //enter SPI loader if requested
     do {
         uint32_t res;
         struct OsUpdateHdr *os;
 
-        blSpiLoader(forceLoad);
+        blLoader(forceLoad);
         res = blVerifyOsUpdate(&os, NULL);
         if (res == OS_UPDT_SUCCESS)
             blApplyVerifiedUpdate(os);
@@ -1150,18 +690,29 @@ void __blEntry(void)
 
         forceLoad = true;
     } while (*(volatile uint32_t*)appBase == 0xFFFFFFFF);
-
-    //call main app with ints off
-    blDisableInts();
-    SCB->VTOR = appBase;
-    asm volatile(
-        "LDR SP, [%0, #0]    \n"
-        "LDR PC, [%0, #4]    \n"
-        :
-        :"r"(appBase)
-        :"memory", "cc"
-    );
-
-    //we should never return here
-    while(1);
 }
+
+const struct BlApiTable __attribute__((section(".blapi"))) __BL_API =
+{
+    .blGetVersion = &blExtApiGetVersion,
+    .blReboot = &blExtApiReboot,
+    .blGetSnum = &blExtApiGetSnum,
+    .blProgramShared = &blExtApiProgramSharedArea,
+    .blEraseShared = &blExtApiEraseSharedArea,
+    .blProgramEe = &blExtApiProgramEe,
+    .blGetPubKeysInfo = &blExtApiGetRsaKeyInfo,
+    .blRsaPubOpIterative = &rsaPubOpIterative,
+    .blSha2init = &sha2init,
+    .blSha2processBytes = &sha2processBytes,
+    .blSha2finish = &sha2finish,
+    .blAesInitForEncr = &aesInitForEncr,
+    .blAesInitForDecr = &aesInitForDecr,
+    .blAesEncr = &aesEncr,
+    .blAesDecr = &aesDecr,
+    .blAesCbcInitForEncr = &aesCbcInitForEncr,
+    .blAesCbcInitForDecr = &aesCbcInitForDecr,
+    .blAesCbcEncr = &aesCbcEncr,
+    .blAesCbcDecr = &aesCbcDecr,
+    .blSigPaddingVerify = &blExtApiSigPaddingVerify,
+    .blVerifyOsUpdate = &blExtApiVerifyOsUpdate,
+};
diff --git a/firmware/os/core/eventQ.c b/firmware/os/core/eventQ.c
new file mode 100644
index 00000000..af77528e
--- /dev/null
+++ b/firmware/os/core/eventQ.c
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <platform.h>
+#include <eventQ.h>
+#include <stddef.h>
+#include <timer.h>
+#include <stdio.h>
+#include <heap.h>
+#include <slab.h>
+#include <cpu.h>
+#include <util.h>
+#include <plat/plat.h>
+#include <plat/taggedPtr.h>
+
+#define for_each_item_safe(head, pos, tmp) \
+    for (pos = (head)->next; tmp = (pos)->next, (pos) != (head); pos = (tmp))
+
+struct EvtList
+{
+    struct EvtList *next;
+    struct EvtList *prev;
+};
+
+struct EvtRecord {
+    struct EvtList item;
+    uint32_t evtType;
+    void* evtData;
+    TaggedPtr evtFreeData;
+};
+
+struct EvtQueue {
+    struct EvtList head;
+    struct SlabAllocator *evtsSlab;
+    EvtQueueForciblyDiscardEvtCbkF forceDiscardCbk;
+};
+
+struct EvtQueue* evtQueueAlloc(uint32_t size, EvtQueueForciblyDiscardEvtCbkF forceDiscardCbk)
+{
+    struct EvtQueue *q = heapAlloc(sizeof(struct EvtQueue));
+    struct SlabAllocator *slab = slabAllocatorNew(sizeof(struct EvtRecord),
+                                                  alignof(struct EvtRecord), size);
+
+    if (q && slab) {
+        q->forceDiscardCbk = forceDiscardCbk;
+        q->evtsSlab = slab;
+        q->head.next = &q->head;
+        q->head.prev = &q->head;
+        return q;
+    }
+
+    if (q)
+        heapFree(q);
+    if (slab)
+        slabAllocatorDestroy(slab);
+
+    return NULL;
+}
+
+void evtQueueFree(struct EvtQueue* q)
+{
+    struct EvtList *pos, *tmp;
+
+    for_each_item_safe (&q->head, pos, tmp) {
+        struct EvtRecord * rec = container_of(pos, struct EvtRecord, item);
+
+        q->forceDiscardCbk(rec->evtType, rec->evtData, rec->evtFreeData);
+        slabAllocatorFree(q->evtsSlab, rec);
+    }
+
+    slabAllocatorDestroy(q->evtsSlab);
+    heapFree(q);
+}
+
+bool evtQueueEnqueue(struct EvtQueue* q, uint32_t evtType, void *evtData,
+                    TaggedPtr evtFreeData, bool atFront)
+{
+    struct EvtRecord *rec;
+    uint64_t intSta;
+    struct EvtList *item = NULL, *a, *b;
+
+    if (!q)
+        return false;
+
+    rec = slabAllocatorAlloc(q->evtsSlab);
+    if (!rec) {
+        struct EvtList *pos;
+
+        intSta = cpuIntsOff();
+        //find a victim for discarding
+        for (pos = q->head.next; pos != &q->head; pos = pos->next) {
+            rec = container_of(pos, struct EvtRecord, item);
+            if (!(rec->evtType & EVENT_TYPE_BIT_DISCARDABLE))
+                continue;
+            a = pos->prev;
+            b = pos->next;
+
+            q->forceDiscardCbk(rec->evtType, rec->evtData, rec->evtFreeData);
+            a->next = b;
+            b->prev = a;
+            item = pos;
+        }
+        cpuIntsRestore (intSta);
+    } else {
+        item = &rec->item;
+    }
+
+    if (!item)
+        return false;
+
+    item->prev = item->next = NULL;
+
+    rec->evtType = evtType;
+    rec->evtData = evtData;
+    rec->evtFreeData = evtFreeData;
+
+    intSta = cpuIntsOff();
+
+    if (unlikely(atFront)) {
+        b = q->head.next;
+        a = b->prev;
+    } else {
+        a = q->head.prev;
+        b = a->next;
+    }
+
+    a->next = item;
+    item->prev = a;
+    b->prev = item;
+    item->next = b;
+
+    cpuIntsRestore(intSta);
+    platWake();
+    return true;
+}
+
+void evtQueueRemoveAllMatching(struct EvtQueue* q,
+                               bool (*match)(uint32_t evtType, const void *data, void *context),
+                               void *context)
+{
+    uint64_t intSta = cpuIntsOff();
+    struct EvtList *pos, *tmp;
+
+    for_each_item_safe (&q->head, pos, tmp) {
+        struct EvtRecord * rec = container_of(pos, struct EvtRecord, item);
+
+        if (match(rec->evtType, rec->evtData, context)) {
+            q->forceDiscardCbk(rec->evtType, rec->evtData, rec->evtFreeData);
+            slabAllocatorFree(q->evtsSlab, rec);
+        }
+    }
+    cpuIntsRestore(intSta);
+}
+
+bool evtQueueDequeue(struct EvtQueue* q, uint32_t *evtTypeP, void **evtDataP,
+                     TaggedPtr *evtFreeDataP, bool sleepIfNone)
+{
+    struct EvtRecord *rec = NULL;
+    uint64_t intSta;
+
+    while(1) {
+        struct EvtList *pos, *a, *b;
+        intSta = cpuIntsOff();
+
+        pos = q->head.next;
+        if (pos != &q->head) {
+            a = pos->prev;
+            b = pos->next;
+            a->next = b;
+            b->prev = a;
+            pos->prev = pos->next = NULL;
+            rec = container_of(pos, struct EvtRecord, item);
+            break;
+        }
+        else if (!sleepIfNone)
+            break;
+        else if (!timIntHandler()) {
+            // check for timers
+            // if any fire, do not sleep (since by the time callbacks run, more might be due)
+            platSleep();
+            //first thing when awake: check timers again
+            timIntHandler();
+        }
+        cpuIntsRestore(intSta);
+    }
+
+    cpuIntsRestore(intSta);
+
+    if (!rec)
+        return false;
+
+    *evtTypeP = rec->evtType;
+    *evtDataP = rec->evtData;
+    *evtFreeDataP = rec->evtFreeData;
+    slabAllocatorFree(q->evtsSlab, rec);
+
+    return true;
+}
diff --git a/firmware/src/floatRt.c b/firmware/os/core/floatRt.c
index f5a10d9f..f5a10d9f 100644
--- a/firmware/src/floatRt.c
+++ b/firmware/os/core/floatRt.c
diff --git a/firmware/src/heap.c b/firmware/os/core/heap.c
index b172c708..2f38a0da 100644
--- a/firmware/src/heap.c
+++ b/firmware/os/core/heap.c
@@ -216,16 +216,15 @@ int heapFreeAll(uint32_t tid)
     if (!haveLock)
         return -1;
 
-    node = gHeapHead;
     tid &= TIDX_MASK;
-    do {
+    for (node = gHeapHead; node; node = heapPrvGetNext(node)) {
         if (node->tidx == tid) {
             node->used = 0;
             node->tidx = 0;
             count++;
         }
-    } while ((node = heapPrvGetNext(node)) != NULL);
-    gNeedFreeMerge = true;
+    }
+    gNeedFreeMerge = count > 0;
     trylockRelease(&gHeapLock);
 
     return count;
diff --git a/firmware/src/hostIntf.c b/firmware/os/core/hostIntf.c
index a9a6ceee..21cc64e6 100644
--- a/firmware/src/hostIntf.c
+++ b/firmware/os/core/hostIntf.c
@@ -20,10 +20,10 @@
 #include <string.h>
 #include <alloca.h>
 
-#include <variant/inc/variant.h>
+#include <variant/variant.h>
 #include <eventnums.h>
 
-#include <plat/inc/pwr.h>
+#include <plat/pwr.h>
 
 #include <nanohub/crc.h>
 
@@ -542,6 +542,17 @@ void hostIntfSetBusy(bool busy)
     mBusy = busy;
 }
 
+static inline struct ActiveSensor *getActiveSensorByType(uint32_t sensorType)
+{
+    struct ActiveSensor *sensor = NULL;
+
+    if (sensorType > SENS_TYPE_INVALID && sensorType <= SENS_TYPE_LAST_USER &&
+        mSensorList[sensorType - 1] < MAX_REGISTERED_SENSORS)
+        sensor = mActiveSensorTable + mSensorList[sensorType - 1];
+
+    return sensor;
+}
+
 bool hostIntfPacketDequeue(void *data, uint32_t *wakeup, uint32_t *nonwakeup)
 {
     struct HostIntfDataBuffer *buffer = data;
@@ -551,8 +562,9 @@ bool hostIntfPacketDequeue(void *data, uint32_t *wakeup, uint32_t *nonwakeup)
 
     ret = simpleQueueDequeue(mOutputQ, buffer);
     while (ret) {
-        if (buffer->sensType > SENS_TYPE_INVALID && buffer->sensType <= SENS_TYPE_LAST_USER && mSensorList[buffer->sensType - 1] < MAX_REGISTERED_SENSORS) {
-            sensor = mActiveSensorTable + mSensorList[buffer->sensType - 1];
+        sensor = getActiveSensorByType(buffer->sensType);
+        if (sensor) {
+            // do not sent sensor data if sensor is not requested; only maintain stats
             if (sensor->sensorHandle == 0 && !buffer->firstSample.biasPresent && !buffer->firstSample.numFlushes) {
                 if (sensor->interrupt == NANOHUB_INT_WAKEUP)
                     mWakeupBlocks--;
@@ -589,8 +601,8 @@ bool hostIntfPacketDequeue(void *data, uint32_t *wakeup, uint32_t *nonwakeup)
     }
 
     if (ret) {
-        if (buffer->sensType > SENS_TYPE_INVALID && buffer->sensType <= SENS_TYPE_LAST_USER && mSensorList[buffer->sensType - 1] < MAX_REGISTERED_SENSORS) {
-            sensor = mActiveSensorTable + mSensorList[buffer->sensType - 1];
+        sensor = getActiveSensorByType(buffer->sensType);
+        if (sensor) {
             if (sensor->interrupt == NANOHUB_INT_WAKEUP)
                 mWakeupBlocks--;
             else if (sensor->interrupt == NANOHUB_INT_NONWAKEUP)
@@ -619,11 +631,9 @@ static void initCompleteCallback(uint32_t timerId, void *data)
 static bool queueDiscard(void *data, bool onDelete)
 {
     struct HostIntfDataBuffer *buffer = data;
-    struct ActiveSensor *sensor;
-
-    if (buffer->sensType > SENS_TYPE_INVALID && buffer->sensType <= SENS_TYPE_LAST_USER && mSensorList[buffer->sensType - 1] < MAX_REGISTERED_SENSORS) { // data
-        sensor = mActiveSensorTable + mSensorList[buffer->sensType - 1];
+    struct ActiveSensor *sensor = getActiveSensorByType(buffer->sensType);
 
+    if (sensor) {
         if (sensor->curSamples - buffer->firstSample.numSamples >= sensor->minSamples || onDelete) {
             if (sensor->interrupt == NANOHUB_INT_WAKEUP)
                 mWakeupBlocks--;
@@ -804,14 +814,12 @@ static uint32_t encodeDeltaTime(uint64_t time)
     return deltaTime;
 }
 
-static int enqueueSensorBufferEx(struct ActiveSensor *sensor, bool doResetOnError)
+static bool enqueueSensorBuffer(struct ActiveSensor *sensor)
 {
     bool queued = simpleQueueEnqueue(mOutputQ, &sensor->buffer,
                                      sizeof(uint32_t) + sensor->buffer.length, sensor->discard);
 
     if (!queued) {
-        if (!doResetOnError)
-            return -1;
         // undo counters if failed to add buffer
         if (sensor->interrupt == NANOHUB_INT_WAKEUP)
             mWakeupBlocks--;
@@ -820,12 +828,7 @@ static int enqueueSensorBufferEx(struct ActiveSensor *sensor, bool doResetOnErro
         sensor->curSamples -= sensor->buffer.firstSample.numSamples;
     }
     resetBuffer(sensor);
-    return queued ? 1 : 0;
-}
-
-static inline int enqueueSensorBuffer(struct ActiveSensor *sensor)
-{
-    return enqueueSensorBufferEx(sensor, true);
+    return queued;
 }
 
 static void copySingleSamples(struct ActiveSensor *sensor, const struct SingleAxisDataEvent *single)
@@ -833,11 +836,11 @@ static void copySingleSamples(struct ActiveSensor *sensor, const struct SingleAx
     int i;
     uint32_t deltaTime;
     uint8_t numSamples;
+    uint8_t evtNumSamples = single->samples[0].firstSample.numSamples;
 
-    for (i = 0; i < single->samples[0].firstSample.numSamples; i++) {
-        if (sensor->buffer.firstSample.numSamples == sensor->packetSamples) {
+    for (i = 0; i < evtNumSamples; i++) {
+        if (sensor->buffer.firstSample.numSamples == sensor->packetSamples)
             enqueueSensorBuffer(sensor);
-        }
 
         if (sensor->buffer.firstSample.numSamples == 0) {
             if (i == 0) {
@@ -898,9 +901,8 @@ static void copyTripleSamples(struct ActiveSensor *sensor, const struct TripleAx
     uint8_t numSamples;
 
     for (i = 0; i < triple->samples[0].firstSample.numSamples; i++) {
-        if (sensor->buffer.firstSample.numSamples == sensor->packetSamples) {
+        if (sensor->buffer.firstSample.numSamples == sensor->packetSamples)
             enqueueSensorBuffer(sensor);
-        }
 
         if (sensor->buffer.firstSample.numSamples == 0) {
             if (i == 0) {
@@ -987,14 +989,12 @@ static void copyTripleSamplesBias(struct ActiveSensor *sensor, const struct Trip
     } else {
         // Bias needs to be sent with a different sensType, so enqueue any pending buffer, enqueue
         // bias with a different sensor type, then restore the sensType
-        if (sensor->buffer.firstSample.numSamples > 0) {
+        if (sensor->buffer.firstSample.numSamples > 0)
             enqueueSensorBuffer(sensor);
-        }
         sensor->buffer.sensType = sensor->biasReportType;
         copyTripleSamples(sensor, triple);
-        if (sensor->buffer.firstSample.numSamples > 0) {
+        if (sensor->buffer.firstSample.numSamples > 0)
             enqueueSensorBuffer(sensor);
-        }
         sensor->buffer.sensType = sensType;
     }
 }
@@ -1013,9 +1013,8 @@ static void copyTripleSamplesRaw(struct ActiveSensor *sensor, const struct Tripl
     }
 
     for (i = 0; i < triple->samples[0].firstSample.numSamples; i++) {
-        if (sensor->buffer.firstSample.numSamples == sensor->packetSamples) {
+        if (sensor->buffer.firstSample.numSamples == sensor->packetSamples)
             enqueueSensorBuffer(sensor);
-        }
 
         if (sensor->buffer.firstSample.numSamples == 0) {
             if (i == 0) {
@@ -1094,7 +1093,7 @@ static void hostIntfNotifyReboot(uint32_t reason)
 
     if (resp) {
         resp->hdr = (struct NanohubHalHdr){
-            .appId = APP_ID_MAKE(APP_ID_VENDOR_GOOGLE, 0),
+            .appId = APP_ID_MAKE(NANOHUB_VENDOR_GOOGLE, 0),
             .len = sizeof(*resp) - sizeof(resp->hdr) + sizeof(resp->hdr.msg),
             .msg = NANOHUB_HAL_REBOOT,
         };
@@ -1136,244 +1135,357 @@ static void fakeFlush(struct ConfigCmd *cmd)
         mWakeupBlocks--;
 }
 
-static void hostIntfHandleEvent(uint32_t evtType, const void* evtData)
+static void onEvtAppStart(const void *evtData)
 {
-    struct ConfigCmd *cmd;
-    uint32_t i, cnt;
-    uint64_t sensorTime;
-    struct ActiveSensor *sensor;
-    uint32_t tempSensorHandle;
-    const struct HostHubRawPacket *hostMsg;
-    struct HostIntfDataBuffer *data;
-    const struct NanohubHalCommand *halCmd;
-    const uint8_t *halMsg;
-    uint32_t reason;
-    uint32_t interrupt = HOSTINTF_MAX_INTERRUPTS;
+    if (initSensors()) {
+        uint32_t reason;
+        struct HostIntfDataBuffer *data;
 
-    if (evtType == EVT_APP_START) {
-        if (initSensors()) {
-            osEventUnsubscribe(mHostIntfTid, EVT_APP_START);
-            osEventSubscribe(mHostIntfTid, EVT_NO_SENSOR_CONFIG_EVENT);
-            osEventSubscribe(mHostIntfTid, EVT_APP_TO_HOST);
+        osEventUnsubscribe(mHostIntfTid, EVT_APP_START);
+        osEventSubscribe(mHostIntfTid, EVT_NO_SENSOR_CONFIG_EVENT);
+        osEventSubscribe(mHostIntfTid, EVT_APP_TO_HOST);
 #ifdef DEBUG_LOG_EVT
-            osEventSubscribe(mHostIntfTid, EVT_DEBUG_LOG);
-            platEarlyLogFlush();
+        osEventSubscribe(mHostIntfTid, EVT_DEBUG_LOG);
+        platEarlyLogFlush();
 #endif
-            reason = pwrResetReason();
-            data = alloca(sizeof(uint32_t) + sizeof(reason));
-            data->sensType = SENS_TYPE_INVALID;
-            data->length = sizeof(reason);
-            data->dataType = HOSTINTF_DATA_TYPE_RESET_REASON;
-            data->interrupt = NANOHUB_INT_WAKEUP;
-            memcpy(data->buffer, &reason, sizeof(reason));
-            hostIntfAddBlock(data, false);
-            hostIntfNotifyReboot(reason);
-        }
-    } else if (evtType == EVT_APP_TO_HOST) {
-        hostMsg = evtData;
-        if (hostMsg->dataLen <= HOST_HUB_RAW_PACKET_MAX_LEN) {
-            data = alloca(sizeof(uint32_t) + sizeof(*hostMsg) + hostMsg->dataLen);
-            data->sensType = SENS_TYPE_INVALID;
-            data->length = sizeof(*hostMsg) + hostMsg->dataLen;
-            data->dataType = HOSTINTF_DATA_TYPE_APP_TO_HOST;
-            data->interrupt = NANOHUB_INT_WAKEUP;
-            memcpy(data->buffer, evtData, data->length);
-            hostIntfAddBlock(data, false);
-        }
-    } else if (evtType == EVT_APP_FROM_HOST) {
-        halMsg = evtData;
-        if ((halCmd = nanohubHalFindCommand(halMsg[1])))
-            halCmd->handler((void *)&halMsg[2], halMsg[0] - 1);
+        reason = pwrResetReason();
+        data = alloca(sizeof(uint32_t) + sizeof(reason));
+        data->sensType = SENS_TYPE_INVALID;
+        data->length = sizeof(reason);
+        data->dataType = HOSTINTF_DATA_TYPE_RESET_REASON;
+        data->interrupt = NANOHUB_INT_WAKEUP;
+        memcpy(data->buffer, &reason, sizeof(reason));
+        hostIntfAddBlock(data, false);
+        hostIntfNotifyReboot(reason);
     }
-#ifdef DEBUG_LOG_EVT
-    else if (evtType == EVT_DEBUG_LOG) {
-        data = (struct HostIntfDataBuffer *)evtData;
-        if (data->sensType == SENS_TYPE_INVALID && data->dataType == HOSTINTF_DATA_TYPE_LOG) {
-            hostIntfAddBlock(data, true);
-        }
+}
+
+static void onEvtAppToHost(const void *evtData)
+{
+    const struct HostHubRawPacket *hostMsg = evtData;
+
+    if (hostMsg->dataLen <= HOST_HUB_RAW_PACKET_MAX_LEN) {
+        struct HostIntfDataBuffer *data = alloca(sizeof(uint32_t) + sizeof(*hostMsg) + hostMsg->dataLen);
+
+        data->sensType = SENS_TYPE_INVALID;
+        data->length = sizeof(*hostMsg) + hostMsg->dataLen;
+        data->dataType = HOSTINTF_DATA_TYPE_APP_TO_HOST;
+        data->interrupt = NANOHUB_INT_WAKEUP;
+        memcpy(data->buffer, evtData, data->length);
+        hostIntfAddBlock(data, false);
     }
+}
+
+static void onEvtAppFromHost(const void *evtData)
+{
+    const uint8_t *halMsg = evtData;
+    const struct NanohubHalCommand *halCmd = nanohubHalFindCommand(halMsg[1]);
+    if (halCmd)
+        halCmd->handler((void *)&halMsg[2], halMsg[0] - 1);
+}
+
+#ifdef DEBUG_LOG_EVT
+static void onEvtDebugLog(const void *evtData)
+{
+    struct HostIntfDataBuffer *data = (struct HostIntfDataBuffer *)evtData;
+
+    if (data->sensType == SENS_TYPE_INVALID && data->dataType == HOSTINTF_DATA_TYPE_LOG)
+        hostIntfAddBlock(data, true);
+}
 #endif
-    else if (evtType == EVT_LATENCY_TIMER) {
-        sensorTime = sensorGetTime();
-
-        for (i = 0, cnt = 0; i < mNumSensors && cnt < mLatencyCnt; i++) {
-            if (mActiveSensorTable[i].latency > 0) {
-                cnt++;
-                if (mActiveSensorTable[i].firstTime && sensorTime >= mActiveSensorTable[i].firstTime + mActiveSensorTable[i].latency) {
-                    hostIntfSetInterrupt(mActiveSensorTable[i].interrupt);
-                }
+
+static void onEvtLatencyTimer(const void *evtData)
+{
+    uint64_t sensorTime = sensorGetTime();
+    uint32_t i, cnt;
+
+    for (i = 0, cnt = 0; i < mNumSensors && cnt < mLatencyCnt; i++) {
+        if (mActiveSensorTable[i].latency > 0) {
+            cnt++;
+            if (mActiveSensorTable[i].firstTime &&
+                sensorTime >= mActiveSensorTable[i].firstTime + mActiveSensorTable[i].latency) {
+                hostIntfSetInterrupt(mActiveSensorTable[i].interrupt);
             }
         }
-    } else if (evtType == EVT_NO_SENSOR_CONFIG_EVENT) { // config
-        cmd = (struct ConfigCmd *)evtData;
-        if (cmd->sensType > SENS_TYPE_INVALID && cmd->sensType <= SENS_TYPE_LAST_USER && mSensorList[cmd->sensType - 1] < MAX_REGISTERED_SENSORS) {
-            sensor = mActiveSensorTable + mSensorList[cmd->sensType - 1];
-
-            if (sensor->sensorHandle) {
-                if (cmd->cmd == CONFIG_CMD_FLUSH) {
-                    sensorFlush(sensor->sensorHandle);
-                } else if (cmd->cmd == CONFIG_CMD_ENABLE) {
-                    if (sensorRequestRateChange(mHostIntfTid, sensor->sensorHandle, cmd->rate, cmd->latency)) {
-                        sensor->rate = cmd->rate;
-                        if (sensor->latency != cmd->latency) {
-                            if (!sensor->latency) {
-                                if (mLatencyCnt++ == 0)
-                                    mLatencyTimer = timTimerSet(CHECK_LATENCY_TIME, 100, 100, latencyTimerCallback, NULL, false);
-                            } else if (!cmd->latency) {
-                                if (--mLatencyCnt == 0) {
-                                    timTimerCancel(mLatencyTimer);
-                                    mLatencyTimer = 0;
-                                }
-                            }
-                            sensor->latency = cmd->latency;
-                        }
-                    }
-                } else if (cmd->cmd == CONFIG_CMD_DISABLE) {
-                    sensorRelease(mHostIntfTid, sensor->sensorHandle);
-                    osEventUnsubscribe(mHostIntfTid, sensorGetMyEventType(cmd->sensType));
-                    if (sensor->latency) {
-                        if (--mLatencyCnt == 0) {
-                            timTimerCancel(mLatencyTimer);
-                            mLatencyTimer = 0;
-                        }
-                    }
-                    sensor->rate = 0;
-                    sensor->latency = 0;
-                    sensor->oneshot = false;
-                    sensor->sensorHandle = 0;
-                    if (sensor->buffer.length) {
-                        enqueueSensorBuffer(sensor);
-                        hostIntfSetInterrupt(sensor->interrupt);
-                    }
-                }
-            } else if (cmd->cmd == CONFIG_CMD_ENABLE) {
-                for (i = 0; sensorFind(cmd->sensType, i, &sensor->sensorHandle) != NULL; i++) {
-                    if (cmd->rate == SENSOR_RATE_ONESHOT) {
-                        cmd->rate = SENSOR_RATE_ONCHANGE;
-                        sensor->oneshot = true;
-                    } else {
-                        sensor->oneshot = false;
-                    }
+    }
+}
 
-                    if (sensorRequest(mHostIntfTid, sensor->sensorHandle, cmd->rate, cmd->latency)) {
-                        if (cmd->latency) {
-                            if (mLatencyCnt++ == 0)
-                                mLatencyTimer = timTimerSet(CHECK_LATENCY_TIME, 100, 100, latencyTimerCallback, NULL, false);
-                        }
-                        sensor->rate = cmd->rate;
-                        sensor->latency = cmd->latency;
-                        osEventSubscribe(mHostIntfTid, sensorGetMyEventType(cmd->sensType));
-                        break;
-                    } else {
-                        sensor->sensorHandle = 0;
-                    }
+static void onConfigCmdFlushOne(struct ActiveSensor *sensor, struct ConfigCmd *cmd)
+{
+    sensorFlush(sensor->sensorHandle);
+}
+
+static void onConfigCmdEnableOne(struct ActiveSensor *sensor, struct ConfigCmd *cmd)
+{
+    if (sensorRequestRateChange(mHostIntfTid, sensor->sensorHandle, cmd->rate, cmd->latency)) {
+        sensor->rate = cmd->rate;
+        if (sensor->latency != cmd->latency) {
+            if (!sensor->latency) {
+                if (mLatencyCnt++ == 0)
+                    mLatencyTimer = timTimerSet(CHECK_LATENCY_TIME, 100, 100, latencyTimerCallback, NULL, false);
+            } else if (!cmd->latency) {
+                if (--mLatencyCnt == 0) {
+                    timTimerCancel(mLatencyTimer);
+                    mLatencyTimer = 0;
                 }
-            } else if (cmd->cmd == CONFIG_CMD_CALIBRATE) {
-                for (i = 0; sensorFind(cmd->sensType, i, &tempSensorHandle) != NULL; i++)
-                    sensorCalibrate(tempSensorHandle);
-            } else if (cmd->cmd == CONFIG_CMD_SELF_TEST) {
-                for (i = 0; sensorFind(cmd->sensType, i, &tempSensorHandle) != NULL; i++)
-                    sensorSelfTest(tempSensorHandle);
-            } else if (cmd->cmd == CONFIG_CMD_CFG_DATA) {
-                for (i = 0; sensorFind(cmd->sensType, i, &tempSensorHandle) != NULL; i++)
-                    sensorCfgData(tempSensorHandle, (void *)(cmd+1));
-            } else if (cmd->cmd == CONFIG_CMD_FLUSH) {
-                    queueFlush(sensor);
             }
-        } else if (cmd->cmd == CONFIG_CMD_FLUSH && cmd->sensType > SENS_TYPE_INVALID) {
-            // if a flush event is for an unknown sensor, we just return a fake flush event.
-            osLog(LOG_INFO, "Flush request from unrecognized sensor, returning a fake flush\n");
-            fakeFlush(cmd);
+            sensor->latency = cmd->latency;
         }
-    } else if (evtType > EVT_NO_FIRST_SENSOR_EVENT && evtType < EVT_NO_SENSOR_CONFIG_EVENT && mSensorList[(evtType & 0xFF)-1] < MAX_REGISTERED_SENSORS) { // data
-        sensor = mActiveSensorTable + mSensorList[(evtType & 0xFF) - 1];
+    }
+}
 
-        if (sensor->sensorHandle) {
-            if (evtData == SENSOR_DATA_EVENT_FLUSH) {
-                queueFlush(sensor);
-            } else {
-                bool haveFlush = sensor->buffer.firstSample.numFlushes > 0;
-                if (sensor->buffer.length > 0 &&
-                    (haveFlush || sensor->buffer.firstSample.numSamples == sensor->packetSamples)) {
-                    // processing will be aborted if we have pending flush and are not able to send;
-                    // in this case, send eventually will be retried, otherwise data will be lost.
-                    if (enqueueSensorBufferEx(sensor, !haveFlush) < 0)
-                        return;
-                }
+static void onConfigCmdEnableAll(struct ActiveSensor *sensor, struct ConfigCmd *cmd)
+{
+    for (uint32_t i = 0; sensorFind(cmd->sensType, i, &sensor->sensorHandle) != NULL; i++) {
+        if (cmd->rate == SENSOR_RATE_ONESHOT) {
+            cmd->rate = SENSOR_RATE_ONCHANGE;
+            sensor->oneshot = true;
+        } else {
+            sensor->oneshot = false;
+        }
 
-                switch (sensor->numAxis) {
-                case NUM_AXIS_EMBEDDED:
-                    sensorTime = sensorGetTime();
-                    if (sensor->buffer.length > 0 && sensorTime - sensor->lastTime >= delta_time_max) {
-                        enqueueSensorBuffer(sensor);
-                    }
-                    if (sensor->buffer.length == 0) {
-                        sensor->buffer.length = sizeof(struct SingleAxisDataEvent) + sizeof(struct SingleAxisDataPoint);
-                        sensor->lastTime = sensor->buffer.referenceTime = sensorTime;
-                        if (sensor->interrupt == NANOHUB_INT_WAKEUP)
-                            mWakeupBlocks++;
-                        else if (sensor->interrupt == NANOHUB_INT_NONWAKEUP)
-                            mNonWakeupBlocks++;
-                        sensor->buffer.firstSample.numSamples = 1;
-                        sensor->buffer.firstSample.interrupt = sensor->interrupt;
-                        sensor->buffer.single[0].idata = (uint32_t)evtData;
-                    } else {
-                        sensor->buffer.length += sizeof(struct SingleAxisDataPoint);
-                        sensor->buffer.single[sensor->buffer.firstSample.numSamples].deltaTime = encodeDeltaTime(sensorTime - sensor->lastTime);
-                        sensor->lastTime = sensorTime;
-                        sensor->buffer.single[sensor->buffer.firstSample.numSamples].idata = (uint32_t)evtData;
-                        sensor->buffer.firstSample.numSamples++;
-                    }
-                    if (sensor->curSamples++ == 0)
-                        sensor->firstTime = sensor->buffer.referenceTime;
-                    break;
-                case NUM_AXIS_ONE:
-                    copySingleSamples(sensor, evtData);
-                    break;
-                case NUM_AXIS_THREE:
-                    if (sensor->raw)
-                        copyTripleSamplesRaw(sensor, evtData);
-                    else
-                        copyTripleSamples(sensor, evtData);
-                    break;
-                default:
-                    return;
-                }
+        if (sensorRequest(mHostIntfTid, sensor->sensorHandle, cmd->rate, cmd->latency)) {
+            if (cmd->latency) {
+                if (mLatencyCnt++ == 0)
+                    mLatencyTimer = timTimerSet(CHECK_LATENCY_TIME, 100, 100, latencyTimerCallback, NULL, false);
             }
+            sensor->rate = cmd->rate;
+            sensor->latency = cmd->latency;
+            osEventSubscribe(mHostIntfTid, sensorGetMyEventType(cmd->sensType));
+            break;
+        } else {
+            sensor->sensorHandle = 0;
+        }
+    }
+}
+
+static void onConfigCmdDisableOne(struct ActiveSensor *sensor, struct ConfigCmd *cmd)
+{
+    sensorRelease(mHostIntfTid, sensor->sensorHandle);
+    osEventUnsubscribe(mHostIntfTid, sensorGetMyEventType(cmd->sensType));
+    if (sensor->latency) {
+        if (--mLatencyCnt == 0) {
+            timTimerCancel(mLatencyTimer);
+            mLatencyTimer = 0;
+        }
+    }
+    sensor->rate = 0;
+    sensor->latency = 0;
+    sensor->oneshot = false;
+    sensor->sensorHandle = 0;
+    if (sensor->buffer.length) {
+        enqueueSensorBuffer(sensor);
+        hostIntfSetInterrupt(sensor->interrupt);
+    }
+}
 
-            sensorTime = sensorGetTime();
+static void onConfigCmdCalibrateAll(struct ActiveSensor *sensor, struct ConfigCmd *cmd)
+{
+    uint32_t tempSensorHandle;
+    for (uint32_t i = 0; sensorFind(cmd->sensType, i, &tempSensorHandle) != NULL; i++)
+        sensorCalibrate(tempSensorHandle);
+}
 
-            if (sensor->firstTime &&
-                ((sensorTime >= sensor->firstTime + sensor->latency) ||
-                 ((sensor->latency > sensorGetCurLatency(sensor->sensorHandle)) &&
-                  (sensorTime + sensorGetCurLatency(sensor->sensorHandle) > sensor->firstTime + sensor->latency)))) {
-                interrupt = sensor->interrupt;
-            } else if (mWakeupBlocks + mNonWakeupBlocks >= mTotalBlocks) {
-                interrupt = sensor->interrupt;
-            }
+static void onConfigCmdSelfTestAll(struct ActiveSensor *sensor, struct ConfigCmd *cmd)
+{
+    uint32_t tempSensorHandle;
+    for (uint32_t i = 0; sensorFind(cmd->sensType, i, &tempSensorHandle) != NULL; i++)
+        sensorSelfTest(tempSensorHandle);
+}
 
-            nanohubPrefetchTx(interrupt, mWakeupBlocks, mNonWakeupBlocks);
+static void onConfigCmdCfgDataAll(struct ActiveSensor *sensor, struct ConfigCmd *cmd)
+{
+    uint32_t tempSensorHandle;
+    for (uint32_t i = 0; sensorFind(cmd->sensType, i, &tempSensorHandle) != NULL; i++)
+        sensorCfgData(tempSensorHandle, (void *)(cmd+1));
+}
 
-            if (sensor->oneshot) {
-                sensorRelease(mHostIntfTid, sensor->sensorHandle);
-                osEventUnsubscribe(mHostIntfTid, evtType);
-                sensor->sensorHandle = 0;
-                sensor->oneshot = false;
+static void onEvtNoSensorConfigEvent(const void *evtData)
+{
+    struct ConfigCmd *cmd = (struct ConfigCmd *)evtData;
+    struct ActiveSensor *sensor = getActiveSensorByType(cmd->sensType);
+    if (sensor) {
+        if (sensor->sensorHandle) {
+            switch (cmd->cmd) {
+            case CONFIG_CMD_FLUSH:
+                onConfigCmdFlushOne(sensor, cmd);
+                break;
+            case CONFIG_CMD_ENABLE:
+                onConfigCmdEnableOne(sensor, cmd);
+                break;
+            case CONFIG_CMD_DISABLE:
+                onConfigCmdDisableOne(sensor, cmd);
+                break;
             }
-        } else if (evtData != SENSOR_DATA_EVENT_FLUSH) {
-            // handle bias data which can be generated for sensors that are
-            // not currently requested by the AP
-            switch (sensor->numAxis) {
-            case NUM_AXIS_THREE:
-                if (((const struct TripleAxisDataEvent *)evtData)->samples[0].firstSample.biasPresent) {
-                    copyTripleSamplesBias(sensor, evtData);
-                    nanohubPrefetchTx(HOSTINTF_MAX_INTERRUPTS, mWakeupBlocks, mNonWakeupBlocks);
-                }
+        } else {
+            switch (cmd->cmd) {
+            case CONFIG_CMD_ENABLE:
+                onConfigCmdEnableAll(sensor, cmd);
+                break;
+            case CONFIG_CMD_CALIBRATE:
+                onConfigCmdCalibrateAll(sensor, cmd);
+                break;
+            case CONFIG_CMD_SELF_TEST:
+                onConfigCmdSelfTestAll(sensor, cmd);
+                break;
+            case CONFIG_CMD_CFG_DATA:
+                onConfigCmdCfgDataAll(sensor, cmd);
                 break;
-            default:
+            case CONFIG_CMD_FLUSH:
+                queueFlush(sensor);
                 break;
             }
         }
+    } else if (cmd->cmd == CONFIG_CMD_FLUSH && cmd->sensType > SENS_TYPE_INVALID) {
+        // if a flush event is for an unknown sensor, we just return a fake flush event.
+        osLog(LOG_INFO, "Flush request from unrecognized sensor, returning a fake flush\n");
+        fakeFlush(cmd);
+    }
+}
+
+static void copyEmbeddedSamples(struct ActiveSensor *sensor, const void* evtData)
+{
+    uint64_t sensorTime = sensorGetTime();
+
+    if (sensor->buffer.length > 0 && sensorTime - sensor->lastTime >= delta_time_max)
+        enqueueSensorBuffer(sensor);
+
+    if (sensor->buffer.length == 0) {
+        sensor->buffer.length = sizeof(struct SingleAxisDataEvent) + sizeof(struct SingleAxisDataPoint);
+        sensor->lastTime = sensor->buffer.referenceTime = sensorTime;
+        if (sensor->interrupt == NANOHUB_INT_WAKEUP)
+            mWakeupBlocks++;
+        else if (sensor->interrupt == NANOHUB_INT_NONWAKEUP)
+            mNonWakeupBlocks++;
+        sensor->buffer.firstSample.numSamples = 1;
+        sensor->buffer.firstSample.interrupt = sensor->interrupt;
+        sensor->buffer.single[0].idata = (uint32_t)evtData;
+    } else {
+        sensor->buffer.length += sizeof(struct SingleAxisDataPoint);
+        sensor->buffer.single[sensor->buffer.firstSample.numSamples].deltaTime =
+                encodeDeltaTime(sensorTime - sensor->lastTime);
+        sensor->lastTime = sensorTime;
+        sensor->buffer.single[sensor->buffer.firstSample.numSamples].idata = (uint32_t)evtData;
+        sensor->buffer.firstSample.numSamples++;
+    }
+    if (sensor->curSamples++ == 0)
+        sensor->firstTime = sensor->buffer.referenceTime;
+}
+
+static uint32_t getSensorInterrupt(struct ActiveSensor *sensor)
+{
+    uint32_t interrupt = HOSTINTF_MAX_INTERRUPTS;
+    uint64_t sensorTime = sensorGetTime();
+
+    if (sensor->firstTime &&
+        ((sensorTime >= sensor->firstTime + sensor->latency) ||
+         ((sensor->latency > sensorGetCurLatency(sensor->sensorHandle)) &&
+          (sensorTime + sensorGetCurLatency(sensor->sensorHandle) > sensor->firstTime + sensor->latency)))) {
+        interrupt = sensor->interrupt;
+    } else if (mWakeupBlocks + mNonWakeupBlocks >= mTotalBlocks) {
+        interrupt = sensor->interrupt;
+    }
+
+    return interrupt;
+}
+
+static void onEvtSensorDataActive(struct ActiveSensor *sensor, uint32_t evtType, const void* evtData)
+{
+    if (evtData == SENSOR_DATA_EVENT_FLUSH) {
+        queueFlush(sensor);
+    } else {
+        bool haveFlush = sensor->buffer.firstSample.numFlushes > 0;
+        if (sensor->buffer.length > 0 &&
+            (haveFlush || sensor->buffer.firstSample.numSamples == sensor->packetSamples)) {
+                // processing will be aborted if we have pending flush and are not able to send
+                // in this case, send eventually will be retried, otherwise data will be lost
+                if (!enqueueSensorBuffer(sensor) && haveFlush)
+                    return;
+        }
+
+        switch (sensor->numAxis) {
+        case NUM_AXIS_EMBEDDED:
+            copyEmbeddedSamples(sensor, evtData);
+            break;
+        case NUM_AXIS_ONE:
+            copySingleSamples(sensor, evtData);
+            break;
+        case NUM_AXIS_THREE:
+            if (sensor->raw)
+                copyTripleSamplesRaw(sensor, evtData);
+            else
+                copyTripleSamples(sensor, evtData);
+            break;
+        default:
+            return;
+        }
+    }
+
+    nanohubPrefetchTx(getSensorInterrupt(sensor), mWakeupBlocks, mNonWakeupBlocks);
+
+    if (sensor->oneshot) {
+        sensorRelease(mHostIntfTid, sensor->sensorHandle);
+        osEventUnsubscribe(mHostIntfTid, evtType);
+        sensor->sensorHandle = 0;
+        sensor->oneshot = false;
+    }
+}
+
+static void onEvtSensorDataInactive(struct ActiveSensor *sensor, uint32_t evtType, const void* evtData)
+{
+    if (evtData != SENSOR_DATA_EVENT_FLUSH) {
+        // handle bias data which can be generated for sensors that are
+        // not currently requested by the AP
+        switch (sensor->numAxis) {
+        case NUM_AXIS_THREE:
+            if (((const struct TripleAxisDataEvent *)evtData)->samples[0].firstSample.biasPresent) {
+                copyTripleSamplesBias(sensor, evtData);
+                nanohubPrefetchTx(HOSTINTF_MAX_INTERRUPTS, mWakeupBlocks, mNonWakeupBlocks);
+            }
+            break;
+        }
+    }
+}
+
+static void onEvtSensorData(uint32_t evtType, const void* evtData)
+{
+    if (evtType > EVT_NO_FIRST_SENSOR_EVENT && evtType < EVT_NO_SENSOR_CONFIG_EVENT) {
+        struct ActiveSensor *sensor = getActiveSensorByType(evtType & 0xFF);
+        if (sensor) {
+            if (sensor->sensorHandle)
+                onEvtSensorDataActive(sensor, evtType, evtData);
+            else
+                onEvtSensorDataInactive(sensor, evtType, evtData);
+        }
+    }
+}
+
+static void hostIntfHandleEvent(uint32_t evtType, const void* evtData)
+{
+    switch (evtType) {
+    case EVT_APP_START:
+        onEvtAppStart(evtData);
+        break;
+    case EVT_APP_TO_HOST:
+        onEvtAppToHost(evtData);
+        break;
+    case EVT_APP_FROM_HOST:
+        onEvtAppFromHost(evtData);
+        break;
+#ifdef DEBUG_LOG_EVT
+    case EVT_DEBUG_LOG:
+        onEvtDebugLog(evtData);
+        break;
+#endif
+    case EVT_LATENCY_TIMER:
+        onEvtLatencyTimer(evtData);
+        break;
+    case EVT_NO_SENSOR_CONFIG_EVENT:
+        onEvtNoSensorConfigEvent(evtData);
+        break;
+    default:
+        onEvtSensorData(evtType, evtData);
+        break;
     }
 }
 
@@ -1475,4 +1587,4 @@ void hostIntfClearInterruptMask(uint32_t bit)
     cpuIntsRestore(state);
 }
 
-INTERNAL_APP_INIT(APP_ID_MAKE(APP_ID_VENDOR_GOOGLE, 0), 0, hostIntfRequest, hostIntfRelease, hostIntfHandleEvent);
+INTERNAL_APP_INIT(APP_ID_MAKE(NANOHUB_VENDOR_GOOGLE, 0), 0, hostIntfRequest, hostIntfRelease, hostIntfHandleEvent);
diff --git a/firmware/src/hostIntfI2c.c b/firmware/os/core/hostIntfI2c.c
index 36763768..36763768 100644
--- a/firmware/src/hostIntfI2c.c
+++ b/firmware/os/core/hostIntfI2c.c
diff --git a/firmware/src/hostIntfSpi.c b/firmware/os/core/hostIntfSpi.c
index 761325cf..761325cf 100644
--- a/firmware/src/hostIntfSpi.c
+++ b/firmware/os/core/hostIntfSpi.c
diff --git a/firmware/src/nanohubCommand.c b/firmware/os/core/nanohubCommand.c
index 0d981874..58d1ad42 100644
--- a/firmware/src/nanohubCommand.c
+++ b/firmware/os/core/nanohubCommand.c
@@ -19,16 +19,17 @@
 #include <stdint.h>
 #include <sys/endian.h>
 
-#include <variant/inc/variant.h>
+#include <variant/variant.h>
 #include <eventnums.h>
 
-#include <plat/inc/taggedPtr.h>
-#include <plat/inc/bl.h>
-#include <plat/inc/plat.h>
+#include <plat/taggedPtr.h>
+#include <plat/plat.h>
 
 #include <nanohub/crc.h>
 #include <nanohub/rsa.h>
+#include <nanohub/nanohub.h>
 
+#include <bl.h>
 #include <atomicBitset.h>
 #include <atomic.h>
 #include <hostIntf.h>
@@ -45,7 +46,7 @@
 #include <timer.h>
 #include <appSec.h>
 #include <cpu.h>
-#include <cpu/inc/cpuMath.h>
+#include <cpu/cpuMath.h>
 #include <algos/ap_hub_sync.h>
 
 #define NANOHUB_COMMAND(_reason, _fastHandler, _handler, _minReqType, _maxReqType) \
@@ -109,6 +110,18 @@ void nanohubInitCommand(void)
     mEventSlab = slabAllocatorNew(NANOHUB_PACKET_PAYLOAD_MAX-sizeof(__le32), 4, 2);
 }
 
+static inline uint64_t unaligned_u64(uint64_t *val) {
+    uint64_t local;
+    memcpy(&local, val, sizeof(local));
+    return local;
+}
+
+static inline uint32_t unaligned_u32(uint32_t *val) {
+    uint32_t local;
+    memcpy(&local, val, sizeof(local));
+    return local;
+}
+
 static uint32_t getOsHwVersion(void *rx, uint8_t rx_len, void *tx, uint64_t timestamp)
 {
     struct NanohubOsHwVersionsResponse *resp = tx;
@@ -127,7 +140,7 @@ static uint32_t getAppVersion(void *rx, uint8_t rx_len, void *tx, uint64_t times
     struct NanohubAppVersionsResponse *resp = tx;
     uint32_t appIdx, appVer, appSize;
 
-    if (osAppInfoById(le64toh(req->appId), &appIdx, &appVer, &appSize)) {
+    if (osAppInfoById(le64toh(unaligned_u64(&req->appId)), &appIdx, &appVer, &appSize)) {
         resp->appVer = htole32(appVer);
         return sizeof(*resp);
     }
@@ -142,7 +155,7 @@ static uint32_t queryAppInfo(void *rx, uint8_t rx_len, void *tx, uint64_t timest
     uint64_t appId;
     uint32_t appVer, appSize;
 
-    if (osAppInfoByIndex(le32toh(req->appIdx), &appId, &appVer, &appSize)) {
+    if (osAppInfoByIndex(le32toh(unaligned_u32(&req->appIdx)), &appId, &appVer, &appSize)) {
         resp->appId = htole64(appId);
         resp->appVer = htole32(appVer);
         resp->appSize = htole32(appSize);
@@ -698,7 +711,8 @@ static int fillBuffer(void *tx, uint32_t totLength, uint32_t *wakeup, uint32_t *
                 packet->firstSample.interrupt = NANOHUB_INT_WAKEUP;
         }
 
-        if ((!totLength || (isSensorEvent(firstPacket->evtType) && isSensorEvent(packet->evtType))) && totLength + length <= sizeof(struct HostIntfDataBuffer)) {
+        if ((!totLength || (isSensorEvent(firstPacket->evtType) && isSensorEvent(packet->evtType))) &&
+             totLength + length <= sizeof(struct HostIntfDataBuffer)) {
             memcpy(buf + totLength, &mTxNext, length);
             totLength += length;
             if (isSensorEvent(packet->evtType) && packet->firstSample.interrupt == NANOHUB_INT_WAKEUP)
@@ -856,47 +870,82 @@ static uint32_t readEvent(void *rx, uint8_t rx_len, void *tx, uint64_t timestamp
     return totLength;
 }
 
+static bool forwardPacket(uint32_t event, void *data, size_t data_size,
+                          void *hdr, size_t hdr_size, uint32_t tid)
+{
+    bool res;
+    uint8_t *hostPacket = data;
+    uint8_t *packet = slabAllocatorAlloc(mEventSlab);
+    EventFreeF free = slabFree;
+
+    if (!packet) {
+        packet = heapAlloc(data_size + hdr_size);
+        free = heapFree;
+    }
+    if (!packet)
+        return false;
+
+    if (hdr && hdr_size)
+        memcpy(packet, hdr, hdr_size);
+
+    memcpy(packet + hdr_size, hostPacket, data_size);
+    if (tid) {
+        // send to specific TID
+        res = osEnqueuePrivateEvt(event, packet, free, tid);
+        if (!res)
+            free(packet);
+    } else {
+        // broadcast to all
+        res = osEnqueueEvtOrFree(event, packet, free);
+    }
+
+    return res;
+}
+
 static uint32_t writeEvent(void *rx, uint8_t rx_len, void *tx, uint64_t timestamp)
 {
     struct NanohubWriteEventRequest *req = rx;
     struct NanohubWriteEventResponse *resp = tx;
-    uint8_t *packet;
-    struct HostHubRawPacket *rawPacket;
     uint32_t tid;
-    EventFreeF free = slabFree;
-
-    if (le32toh(req->evtType) == EVT_APP_FROM_HOST) {
-        rawPacket = (struct HostHubRawPacket *)req->evtData;
-        if (rx_len >= sizeof(req->evtType) + sizeof(struct HostHubRawPacket) && rx_len == sizeof(req->evtType) + sizeof(struct HostHubRawPacket) + rawPacket->dataLen && osTidById(rawPacket->appId, &tid)) {
-            packet = slabAllocatorAlloc(mEventSlab);
-            if (!packet) {
-                packet = heapAlloc(rawPacket->dataLen + 1);
-                free = heapFree;
-            }
-            if (!packet) {
-                resp->accepted = false;
+    uint32_t event = le32toh(req->evtType);
+
+    if (event == EVT_APP_FROM_HOST) {
+        // old version of HAL; message_type is not delivered to CHRE apps
+        struct HostMsgHdr *hostPacket = rx;
+        if (rx_len >= sizeof(struct HostMsgHdr) &&
+            rx_len == sizeof(struct HostMsgHdr) + hostPacket->len &&
+            osTidById(&hostPacket->appId, &tid)) {
+            resp->accepted = forwardPacket(event, hostPacket + 1, hostPacket->len,
+                                           &hostPacket->len, sizeof(hostPacket->len), tid);
+        } else {
+            resp->accepted = false;
+        }
+    } else if (event == EVT_APP_FROM_HOST_CHRE) {
+        // new version of HAL; full support for CHRE apps
+        struct HostMsgHdrChre *hostPacket = rx;
+        if (rx_len >= sizeof(struct HostMsgHdrChre) &&
+            rx_len == sizeof(struct HostMsgHdrChre) + hostPacket->len &&
+            osTidById(&hostPacket->appId, &tid)) {
+            if (osAppIsChre(tid)) {
+                struct NanohubMsgChreHdr hdr = {
+                    .size = hostPacket->len,
+                    .appEvent = hostPacket->appEventId,
+                };
+                // CHRE app receives message in new format
+                resp->accepted = forwardPacket(event, hostPacket + 1, hostPacket->len,
+                                               &hdr, sizeof(hdr), tid);
             } else {
-                packet[0] = rawPacket->dataLen;
-                memcpy(packet + 1, rawPacket + 1, rawPacket->dataLen);
-                resp->accepted = osEnqueuePrivateEvt(EVT_APP_FROM_HOST, packet, free, tid);
-                if (!resp->accepted)
-                    free(packet);
+                // legacy app receives message in old format
+                resp->accepted = forwardPacket(EVT_APP_FROM_HOST, hostPacket + 1, hostPacket->len,
+                                               &hostPacket->len, sizeof(hostPacket->len), tid);
             }
         } else {
             resp->accepted = false;
         }
     } else {
-        packet = slabAllocatorAlloc(mEventSlab);
-        if (!packet) {
-            packet = heapAlloc(rx_len - sizeof(req->evtType));
-            free = heapFree;
-        }
-        if (!packet) {
-            resp->accepted = false;
-        } else {
-            memcpy(packet, req->evtData, rx_len - sizeof(req->evtType));
-            resp->accepted = osEnqueueEvtOrFree(le32toh(req->evtType), packet, free);
-        }
+        resp->accepted = forwardPacket(event,
+                                       req->evtData, rx_len - sizeof(req->evtType),
+                                       NULL, 0, 0);
     }
 
     return sizeof(*resp);
@@ -979,7 +1028,7 @@ static void halSendMgmtResponse(uint32_t cmd, uint32_t status)
     resp = heapAlloc(sizeof(*resp));
     if (resp) {
         resp->hdr = (struct NanohubHalHdr) {
-            .appId = APP_ID_MAKE(APP_ID_VENDOR_GOOGLE, 0),
+            .appId = APP_ID_MAKE(NANOHUB_VENDOR_GOOGLE, 0),
             .len = sizeof(*resp) - sizeof(resp->hdr) + sizeof(resp->hdr.msg),
             .msg = cmd,
         };
@@ -992,21 +1041,21 @@ static void halExtAppsOn(void *rx, uint8_t rx_len)
 {
     struct NanohubHalMgmtRx *req = rx;
 
-    halSendMgmtResponse(NANOHUB_HAL_EXT_APPS_ON, osExtAppStartApps(le64toh(req->appId)));
+    halSendMgmtResponse(NANOHUB_HAL_EXT_APPS_ON, osExtAppStartApps(le64toh(unaligned_u64(&req->appId))));
 }
 
 static void halExtAppsOff(void *rx, uint8_t rx_len)
 {
     struct NanohubHalMgmtRx *req = rx;
 
-    halSendMgmtResponse(NANOHUB_HAL_EXT_APPS_OFF, osExtAppStopApps(le64toh(req->appId)));
+    halSendMgmtResponse(NANOHUB_HAL_EXT_APPS_OFF, osExtAppStopApps(le64toh(unaligned_u64(&req->appId))));
 }
 
 static void halExtAppDelete(void *rx, uint8_t rx_len)
 {
     struct NanohubHalMgmtRx *req = rx;
 
-    halSendMgmtResponse(NANOHUB_HAL_EXT_APP_DELETE, osExtAppEraseApps(le64toh(req->appId)));
+    halSendMgmtResponse(NANOHUB_HAL_EXT_APP_DELETE, osExtAppEraseApps(le64toh(unaligned_u64(&req->appId))));
 }
 
 static void halQueryMemInfo(void *rx, uint8_t rx_len)
@@ -1023,7 +1072,7 @@ static void halQueryApps(void *rx, uint8_t rx_len)
 
     if (osAppInfoByIndex(le32toh(req->idx), &appId, &appVer, &appSize)) {
         resp = heapAlloc(sizeof(*resp));
-        resp->hdr.appId = APP_ID_MAKE(APP_ID_VENDOR_GOOGLE, 0);
+        resp->hdr.appId = APP_ID_MAKE(NANOHUB_VENDOR_GOOGLE, 0);
         resp->hdr.len = sizeof(*resp) - sizeof(struct NanohubHalHdr) + 1;
         resp->hdr.msg = NANOHUB_HAL_QUERY_APPS;
         resp->appId = appId;
@@ -1033,7 +1082,7 @@ static void halQueryApps(void *rx, uint8_t rx_len)
         osEnqueueEvtOrFree(EVT_APP_TO_HOST, resp, heapFree);
     } else {
         hdr = heapAlloc(sizeof(*hdr));
-        hdr->appId = APP_ID_MAKE(APP_ID_VENDOR_GOOGLE, 0);
+        hdr->appId = APP_ID_MAKE(NANOHUB_VENDOR_GOOGLE, 0);
         hdr->len = 1;
         hdr->msg = NANOHUB_HAL_QUERY_APPS;
         osEnqueueEvtOrFree(EVT_APP_TO_HOST, hdr, heapFree);
@@ -1059,7 +1108,7 @@ static void halQueryRsaKeys(void *rx, uint8_t rx_len)
         memcpy(resp->data, (uint8_t *)ptr + req->offset, len);
     }
 
-    resp->hdr.appId = APP_ID_MAKE(APP_ID_VENDOR_GOOGLE, 0);
+    resp->hdr.appId = APP_ID_MAKE(NANOHUB_VENDOR_GOOGLE, 0);
     resp->hdr.len = sizeof(*resp) - sizeof(struct NanohubHalHdr) + 1 + len;
     resp->hdr.msg = NANOHUB_HAL_QUERY_RSA_KEYS;
 
@@ -1077,7 +1126,7 @@ static void halStartUpload(void *rx, uint8_t rx_len)
     if (!(resp = heapAlloc(sizeof(*resp))))
         return;
 
-    resp->hdr.appId = APP_ID_MAKE(APP_ID_VENDOR_GOOGLE, 0);
+    resp->hdr.appId = APP_ID_MAKE(NANOHUB_VENDOR_GOOGLE, 0);
     resp->hdr.len = sizeof(*resp) - sizeof(struct NanohubHalHdr) + 1;
     resp->hdr.msg = NANOHUB_HAL_START_UPLOAD;
     resp->success = doStartFirmwareUpload(&hwReq);
@@ -1096,7 +1145,7 @@ static void halContUpload(void *rx, uint8_t rx_len)
     if (!(resp = heapAlloc(sizeof(*resp))))
         return;
 
-    resp->hdr.appId = APP_ID_MAKE(APP_ID_VENDOR_GOOGLE, 0);
+    resp->hdr.appId = APP_ID_MAKE(NANOHUB_VENDOR_GOOGLE, 0);
     resp->hdr.len = sizeof(*resp) - sizeof(struct NanohubHalHdr) + 1;
     resp->hdr.msg = NANOHUB_HAL_CONT_UPLOAD;
 
@@ -1124,7 +1173,7 @@ static void halFinishUpload(void *rx, uint8_t rx_len)
     if (!(resp = heapAlloc(sizeof(*resp))))
         return;
 
-    resp->hdr.appId = APP_ID_MAKE(APP_ID_VENDOR_GOOGLE, 0);
+    resp->hdr.appId = APP_ID_MAKE(NANOHUB_VENDOR_GOOGLE, 0);
     resp->hdr.len = sizeof(*resp) - sizeof(struct NanohubHalHdr) + 1;
     resp->hdr.msg = NANOHUB_HAL_FINISH_UPLOAD;
 
@@ -1202,9 +1251,10 @@ struct ApHubSyncDebug {
     uint32_t printTimer;
 };
 
-struct ApHubSyncDebug mApHubSyncDebug = {0};
+static struct ApHubSyncDebug mApHubSyncDebug;
 
-static void syncDebugCallback(uint32_t timerId, void *data) {
+static void syncDebugCallback(uint32_t timerId, void *data)
+{
 
     if (mApHubSyncDebug.printIndex >= mApHubSyncDebug.writeIndex ||
         mApHubSyncDebug.printIndex >= N_APHUB_SYNC_DATA) {
@@ -1231,7 +1281,8 @@ static void syncDebugCallback(uint32_t timerId, void *data) {
     }
 }
 
-static void syncDebugTriggerPrint() {
+static void syncDebugTriggerPrint()
+{
     if (mApHubSyncDebug.printTimer) {
         //printing already going
         return;
@@ -1249,7 +1300,8 @@ static void syncDebugTriggerPrint() {
     }
 }
 
-static void syncDebugAdd(uint64_t ap, uint64_t hub) {
+static void syncDebugAdd(uint64_t ap, uint64_t hub)
+{
     if (mApHubSyncDebug.writeIndex >= N_APHUB_SYNC_DATA) {
         //full
         syncDebugTriggerPrint();
diff --git a/firmware/os/core/nanohub_chre.c b/firmware/os/core/nanohub_chre.c
new file mode 100644
index 00000000..7bb42c8c
--- /dev/null
+++ b/firmware/os/core/nanohub_chre.c
@@ -0,0 +1,375 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdarg.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <cpu.h>
+#include <heap.h>
+#include <sensors.h>
+#include <sensors_priv.h>
+#include <seos.h>
+#include <seos_priv.h>
+#include <syscall.h>
+#include <timer.h>
+#include <util.h>
+
+#include <chre.h>
+#include <chreApi.h>
+
+/*
+ * This is to ensure that message size and some extra headers will stay representable with 1 byte
+ * Code relies on that in many places.
+ */
+C_STATIC_ASSERT(max_chre_msg_size, CHRE_MESSAGE_TO_HOST_MAX_SIZE <= 240);
+
+/*
+ * Many syscalls rely on the property that uintptr_t can hold uint32_t without data loss
+ * This is enforced by static assertion in chreApi.h
+ * None of the methods returning uint32_t are cast to uintptr_t
+ * This is done in order to let compiler warn us if our assumption is not safe for some reason
+ */
+
+static inline uint64_t osChreGetAppId(void)
+{
+    struct Task *task = osGetCurrentTask();
+    const struct AppHdr *app = task ? task->app : NULL;
+
+    return app ? app->hdr.appId : 0;
+}
+
+static void osChreApiGetAppId(uintptr_t *retValP, va_list args)
+{
+    uint64_t *appId = va_arg(args, uint64_t *);
+    if (appId)
+        *appId = osChreGetAppId();
+}
+
+static void osChreApiGetInstanceId(uintptr_t *retValP, va_list args)
+{
+    *retValP = osGetCurrentTid();
+}
+
+static void osChreApiLogLogv(uintptr_t *retValP, va_list args)
+{
+    va_list innerArgs;
+    enum chreLogLevel level = va_arg(args, int /* enums promoted to ints in va_args in C */);
+    const static char levels[] = "EWIDV";
+    char clevel = level > CHRE_LOG_DEBUG || level < 0 ? 'V' : levels[level];
+    const char *str = va_arg(args, const char*);
+    uintptr_t inner = va_arg(args, uintptr_t);
+
+    va_copy(innerArgs, INTEGER_TO_VA_LIST(inner));
+    osLogv(clevel, str, innerArgs);
+    va_end(innerArgs);
+}
+
+static void osChreApiGetTime(uintptr_t *retValP, va_list args)
+{
+    uint64_t *timeNanos = va_arg(args, uint64_t *);
+    if (timeNanos)
+        *timeNanos = timGetTime();
+}
+
+static inline uint32_t osChreTimerSet(uint64_t duration, const void* cookie, bool oneShot)
+{
+    uint32_t timId = timTimerSetNew(duration, cookie, oneShot);
+
+    return timId == 0 ? CHRE_TIMER_INVALID : timId;
+}
+
+static void osChreApiTimerSet(uintptr_t *retValP, va_list args)
+{
+    uint32_t length_lo = va_arg(args, uint32_t);
+    uint32_t length_hi = va_arg(args, uint32_t);
+    void *cookie = va_arg(args, void *);
+    bool oneshot = va_arg(args, int);
+    uint64_t length = (((uint64_t)length_hi) << 32) | length_lo;
+
+    *retValP = osChreTimerSet(length, cookie, oneshot);
+}
+
+static void osChreApiTimerCancel(uintptr_t *retValP, va_list args)
+{
+    uint32_t timerId = va_arg(args, uint32_t);
+    *retValP = timTimerCancelEx(timerId, true);
+}
+
+static inline void osChreAbort(uint32_t abortCode)
+{
+    struct Task *task = osGetCurrentTask();
+    osLog(LOG_ERROR, "APP ID=0x%" PRIX64 "TID=0x%" PRIX16 " aborted [code 0x%" PRIX32 "]",
+          task->app->hdr.appId, task->tid, abortCode);
+    osTaskAbort(task);
+}
+
+static void osChreApiAbort(uintptr_t *retValP, va_list args)
+{
+    uint32_t code = va_arg(args, uint32_t);
+    osChreAbort(code);
+}
+
+static void osChreApiHeapAlloc(uintptr_t *retValP, va_list args)
+{
+    uint32_t size = va_arg(args, uint32_t);
+    *retValP = (uintptr_t)heapAlloc(size);
+}
+
+static void osChreApiHeapFree(uintptr_t *retValP, va_list args)
+{
+    void *ptr = va_arg(args, void *);
+    heapFree(ptr);
+}
+
+/*
+ * we have no way to verify if this is a CHRE event; just trust the caller to do the right thing
+ */
+void osChreFreeEvent(uint32_t tid, chreEventCompleteFunction *cbFreeEvt, uint32_t evtType, void * evtData)
+{
+    struct Task *chreTask = osTaskFindByTid(tid);
+    struct Task *preempted = osSetCurrentTask(chreTask);
+    if (chreTask && osTaskIsChre(chreTask))
+        osTaskInvokeEventFreeCallback(chreTask, cbFreeEvt, evtType, evtData);
+    osSetCurrentTask(preempted);
+}
+
+static bool osChreSendEvent(uint16_t evtType, void *evtData,
+                            chreEventCompleteFunction *evtFreeCallback,
+                            uint32_t toTid)
+{
+    /*
+     * this primitive may only be used for USER CHRE events;
+     * system events come from the OS itself through different path,
+     * and are interpreted by the CHRE app compatibility library.
+     * therefore, we have to enforce the evtType >= CHRE_EVENT_FIRST_USER_VALUE.
+     */
+    if (evtType < CHRE_EVENT_FIRST_USER_VALUE) {
+        osChreFreeEvent(osGetCurrentTid(), evtFreeCallback, evtType, evtData);
+        return false;
+    }
+    return osEnqueuePrivateEvtNew(evtType, evtData, evtFreeCallback, toTid);
+}
+
+static void osChreApiSendEvent(uintptr_t *retValP, va_list args)
+{
+    uint16_t evtType = va_arg(args, uint32_t); // stored as 32-bit
+    void *evtData = va_arg(args, void *);
+    chreEventCompleteFunction *freeCallback = va_arg(args, chreEventCompleteFunction *);
+    uint32_t toTid = va_arg(args, uint32_t);
+    *retValP = osChreSendEvent(evtType, evtData, freeCallback, toTid);
+}
+
+static bool osChreSendMessageToHost(void *message, uint32_t messageSize,
+                           uint32_t reservedMessageType,
+                           chreMessageFreeFunction *freeCallback)
+{
+    bool result = false;
+    struct HostHubRawPacket *hostMsg = NULL;
+
+    if (messageSize > CHRE_MESSAGE_TO_HOST_MAX_SIZE || (messageSize && !message))
+        goto out;
+
+    hostMsg = heapAlloc(sizeof(*hostMsg) + messageSize);
+    if (!hostMsg)
+        goto out;
+
+    if (messageSize)
+        memcpy(hostMsg+1, message, messageSize);
+
+    hostMsg->appId = osChreGetAppId();
+    hostMsg->dataLen = messageSize;
+    result = osEnqueueEvtOrFree(EVT_APP_TO_HOST, hostMsg, heapFree);
+
+out:
+    if (freeCallback)
+        osTaskInvokeMessageFreeCallback(osGetCurrentTask(), freeCallback, message, messageSize);
+    return result;
+}
+
+static void osChreApiSendMessageToHost(uintptr_t *retValP, va_list args)
+{
+    void *message = va_arg(args, void *);
+    uint32_t messageSize = va_arg(args, uint32_t);
+    uint32_t reservedMessageType = va_arg(args, uint32_t);
+    chreMessageFreeFunction *freeCallback = va_arg(args, chreMessageFreeFunction *);
+
+    *retValP = osChreSendMessageToHost(message, messageSize, reservedMessageType, freeCallback);
+}
+
+static bool osChreSensorFindDefault(uint8_t sensorType, uint32_t *pHandle)
+{
+    if (!pHandle)
+        return false;
+
+    const struct SensorInfo *info = sensorFind(sensorType, 0, pHandle);
+
+    return info != NULL;
+}
+
+static void osChreApiSensorFindDefault(uintptr_t *retValP, va_list args)
+{
+    uint8_t sensorType = va_arg(args, uint32_t);
+    uint32_t *pHandle = va_arg(args, uint32_t *);
+    *retValP = osChreSensorFindDefault(sensorType, pHandle);
+}
+
+static bool osChreSensorGetInfo(uint32_t sensorHandle, struct chreSensorInfo *info)
+{
+    struct Sensor *s = sensorFindByHandle(sensorHandle);
+    if (!s || !info)
+        return false;
+    const struct SensorInfo *si = s->si;
+    info->sensorName = si->sensorName;
+    info->sensorType = si->sensorType;
+    info->unusedFlags = 0;
+
+    // TODO: check if the two lines below deliver intended semantics
+    info->isOnChange = s->hasOnchange;
+    info->isOneShot = s->hasOndemand;
+
+    return true;
+}
+
+static void osChreApiSensorGetInfo(uintptr_t *retValP, va_list args)
+{
+    uint32_t sensorHandle = va_arg(args, uint32_t);
+    struct chreSensorInfo *info = va_arg(args, struct chreSensorInfo *);
+    *retValP = osChreSensorGetInfo(sensorHandle, info);
+}
+
+static bool osChreSensorGetSamplingStatus(uint32_t sensorHandle,
+                                 struct chreSensorSamplingStatus *status)
+{
+    struct Sensor *s = sensorFindByHandle(sensorHandle);
+    if (!s || !status)
+        return false;
+
+    // TODO
+    status->interval = 0;
+    status->latency = 0;
+    status->enabled = 0;
+    return true;
+}
+
+static void osChreApiSensorGetStatus(uintptr_t *retValP, va_list args)
+{
+    uint32_t sensorHandle = va_arg(args, uint32_t);
+    struct chreSensorSamplingStatus *status = va_arg(args, struct chreSensorSamplingStatus *);
+    *retValP = osChreSensorGetSamplingStatus(sensorHandle, status);
+}
+
+static bool osChreSensorConfigure(uint32_t sensorHandle,
+                         enum chreSensorConfigureMode mode,
+                         uint64_t interval, uint64_t latency)
+{
+    // TODO
+    osLog(LOG_ERROR, "%s: not implemented\n", __func__);
+    return false;
+}
+
+static void osChreApiSensorConfig(uintptr_t *retValP, va_list args)
+{
+    uint32_t sensorHandle = va_arg(args, uint32_t);
+    enum chreSensorConfigureMode mode = va_arg(args, int);
+    uint64_t interval = va_arg(args, uint32_t);
+    uint32_t interval_hi = va_arg(args, uint32_t);
+    uint64_t latency = va_arg(args, uint32_t);
+    uint32_t latency_hi = va_arg(args, uint32_t);
+
+    interval |= ((uint64_t)interval_hi) << 32;
+    latency  |= ((uint64_t)latency_hi) << 32;
+
+    *retValP = osChreSensorConfigure(sensorHandle, mode, interval, latency);
+}
+
+static uint32_t osChreGetApiVersion(void)
+{
+    return CHRE_API_VERSION;
+}
+
+static void osChreApiChreApiVersion(uintptr_t *retValP, va_list args)
+{
+    *retValP = osChreGetApiVersion();
+}
+
+static uint32_t osChreGetVersion(void)
+{
+    return CHRE_API_VERSION | NANOHUB_OS_PATCH_LEVEL;
+}
+
+static void osChreApiChreOsVersion(uintptr_t *retValP, va_list args)
+{
+    *retValP = (uintptr_t)osChreGetVersion();
+}
+
+static uint64_t osChreGetPlatformId(void)
+{
+    return HW_ID_MAKE(NANOHUB_VENDOR_GOOGLE, 0);
+}
+
+static void osChreApiPlatformId(uintptr_t *retValP, va_list args)
+{
+    uint64_t *pHwId = va_arg(args, uint64_t*);
+    if (pHwId)
+        *pHwId = osChreGetPlatformId();
+}
+
+static const struct SyscallTable chreMainApiTable = {
+    .numEntries = SYSCALL_CHRE_MAIN_API_LAST,
+    .entry = {
+        [SYSCALL_CHRE_MAIN_API_LOG]                     = { .func = osChreApiLogLogv },
+        [SYSCALL_CHRE_MAIN_API_GET_APP_ID]              = { .func = osChreApiGetAppId },
+        [SYSCALL_CHRE_MAIN_API_GET_INST_ID]             = { .func = osChreApiGetInstanceId },
+        [SYSCALL_CHRE_MAIN_API_GET_TIME]                = { .func = osChreApiGetTime },
+        [SYSCALL_CHRE_MAIN_API_TIMER_SET]               = { .func = osChreApiTimerSet },
+        [SYSCALL_CHRE_MAIN_API_TIMER_CANCEL]            = { .func = osChreApiTimerCancel },
+        [SYSCALL_CHRE_MAIN_API_ABORT]                   = { .func = osChreApiAbort },
+        [SYSCALL_CHRE_MAIN_API_HEAP_ALLOC]              = { .func = osChreApiHeapAlloc },
+        [SYSCALL_CHRE_MAIN_API_HEAP_FREE]               = { .func = osChreApiHeapFree },
+        [SYSCALL_CHRE_MAIN_API_SEND_EVENT]              = { .func = osChreApiSendEvent },
+        [SYSCALL_CHRE_MAIN_API_SEND_MSG]                = { .func = osChreApiSendMessageToHost },
+        [SYSCALL_CHRE_MAIN_API_SENSOR_FIND_DEFAULT]     = { .func = osChreApiSensorFindDefault },
+        [SYSCALL_CHRE_MAIN_API_SENSOR_GET_INFO]         = { .func = osChreApiSensorGetInfo },
+        [SYSCALL_CHRE_MAIN_API_SENSOR_GET_STATUS]       = { .func = osChreApiSensorGetStatus },
+        [SYSCALL_CHRE_MAIN_API_SENSOR_CONFIG]           = { .func = osChreApiSensorConfig },
+        [SYSCALL_CHRE_MAIN_API_GET_OS_API_VERSION]      = { .func = osChreApiChreApiVersion },
+        [SYSCALL_CHRE_MAIN_API_GET_OS_VERSION]          = { .func = osChreApiChreOsVersion },
+        [SYSCALL_CHRE_MAIN_API_GET_PLATFORM_ID]         = { .func = osChreApiPlatformId },
+    },
+};
+
+static const struct SyscallTable chreMainTable = {
+    .numEntries = SYSCALL_CHRE_MAIN_LAST,
+    .entry = {
+        [SYSCALL_CHRE_MAIN_API]     = { .subtable = (struct SyscallTable*)&chreMainApiTable,     },
+    },
+};
+
+static const struct SyscallTable chreTable = {
+    .numEntries = SYSCALL_CHRE_LAST,
+    .entry = {
+        [SYSCALL_CHRE_MAIN]    = { .subtable = (struct SyscallTable*)&chreMainTable,    },
+    },
+};
+
+void osChreApiExport()
+{
+    if (!syscallAddTable(SYSCALL_NO(SYSCALL_DOMAIN_CHRE,0,0,0), 1, (struct SyscallTable*)&chreTable))
+            osLog(LOG_ERROR, "Failed to export CHRE OS API");
+}
diff --git a/firmware/src/osApi.c b/firmware/os/core/osApi.c
index 1e1ec7b9..6158ac74 100644
--- a/firmware/src/osApi.c
+++ b/firmware/os/core/osApi.c
@@ -14,8 +14,8 @@
  * limitations under the License.
  */
 
-#include <plat/inc/taggedPtr.h>
-#include <plat/inc/rtc.h>
+#include <plat/taggedPtr.h>
+#include <plat/rtc.h>
 #include <syscall.h>
 #include <sensors.h>
 #include <errno.h>
@@ -89,7 +89,7 @@ static void osExpApiLogLogv(uintptr_t *retValP, va_list args)
     const char *str = va_arg(args, const char*);
     va_list innerArgs;
     va_copy(innerArgs, INTEGER_TO_VA_LIST(va_arg(args, uintptr_t)));
-    osLogv(level, str, innerArgs);
+    osLogv((char)level, str, innerArgs);
     va_end(innerArgs);
 }
 
@@ -621,7 +621,6 @@ void osApiExport(struct SlabAllocator *mainSlubAllocator)
         },
     };
 
-    if (!syscallAddTable(SYSCALL_DOMAIN_OS, 1, (struct SyscallTable*)&osTable))
+    if (!syscallAddTable(SYSCALL_NO(SYSCALL_DOMAIN_OS,0,0,0), 1, (struct SyscallTable*)&osTable))
         osLog(LOG_ERROR, "Failed to export OS base API");
 }
-
diff --git a/firmware/src/printf.c b/firmware/os/core/printf.c
index 6f3d94a8..9c10dc3d 100644
--- a/firmware/src/printf.c
+++ b/firmware/os/core/printf.c
@@ -16,7 +16,7 @@
 
 #include <stdio.h>
 #include <printf.h>
-#include <cpu/inc/cpuMath.h>
+#include <cpu/cpuMath.h>
 
 
 static uint32_t StrPrvPrintfEx_number(printf_write_c putc_, void* userData, uint64_t number, bool base10, bool zeroExtend, bool isSigned, uint32_t padToLength, bool caps, bool* bail)
diff --git a/firmware/src/sensors.c b/firmware/os/core/sensors.c
index b5f6cc67..2b7b5fdd 100644
--- a/firmware/src/sensors.c
+++ b/firmware/os/core/sensors.c
@@ -14,9 +14,9 @@
  * limitations under the License.
  */
 
-#include <plat/inc/taggedPtr.h>
-#include <plat/inc/rtc.h>
-#include <cpu/inc/barrier.h>
+#include <plat/taggedPtr.h>
+#include <plat/rtc.h>
+#include <cpu/barrier.h>
 #include <atomicBitset.h>
 #include <inttypes.h>
 #include <sensors.h>
@@ -26,54 +26,8 @@
 #include <seos.h>
 #include <util.h>
 
-#define MAX_INTERNAL_EVENTS       32 //also used for external app sensors' setRate() calls
-#define MAX_CLI_SENS_MATRIX_SZ    64 /* MAX(numClients * numSensors) */
-
-#define SENSOR_RATE_OFF           0x00000000UL /* used in sensor state machine */
-#define SENSOR_RATE_POWERING_ON   0xFFFFFFF0UL /* used in sensor state machine */
-#define SENSOR_RATE_POWERING_OFF  0xFFFFFFF1UL /* used in sensor state machine */
-#define SENSOR_RATE_FW_UPLOADING  0xFFFFFFF2UL /* used in sensor state machine */
-#define SENSOR_RATE_IMPOSSIBLE    0xFFFFFFF3UL /* used in rate calc to indicate impossible combinations */
-#define SENSOR_LATENCY_INVALID    0xFFFFFFFFFFFFFFFFULL
-
-#define HANDLE_TO_TID(handle) (((handle) >> (32 - TASK_TID_BITS)) & TASK_TID_MASK)
-#define EXT_APP_TID(s) HANDLE_TO_TID(s->handle)
-#define LOCAL_APP_OPS(s) ((const struct SensorOps*)taggedPtrToPtr(s->callInfo))
-#define IS_LOCAL_APP(s) (taggedPtrIsPtr(s->callInfo))
-
-struct Sensor {
-    const struct SensorInfo *si;
-    uint32_t handle;         /* here 0 means invalid */
-    uint64_t currentLatency; /* here 0 means no batching */
-    uint32_t currentRate;    /* here 0 means off */
-    TaggedPtr callInfo;      /* pointer to ops struct or app tid */
-    void *callData;
-    uint32_t initComplete:1; /* sensor finished initializing */
-    uint32_t hasOnchange :1; /* sensor supports onchange and wants to be notified to send new clients current state */
-    uint32_t hasOndemand :1; /* sensor supports ondemand and wants to get triggers */
-};
-
-struct SensorsInternalEvent {
-    union {
-        struct {
-            uint32_t handle;
-            uint32_t value1;
-            uint64_t value2;
-        };
-        struct SensorPowerEvent externalPowerEvt;
-        struct SensorSetRateEvent externalSetRateEvt;
-        struct SensorCfgDataEvent externalCfgDataEvt;
-        struct SensorSendDirectEventEvent externalSendDirectEvt;
-        struct SensorMarshallUserEventEvent externalMarshallEvt;
-    };
-};
+#include <sensors_priv.h>
 
-struct SensorsClientRequest {
-    uint32_t handle;
-    uint32_t clientTid;
-    uint64_t latency;
-    uint32_t rate;
-};
 
 static struct Sensor mSensors[MAX_REGISTERED_SENSORS];
 ATOMIC_BITSET_DECL(mSensorsUsed, MAX_REGISTERED_SENSORS, static);
@@ -107,7 +61,7 @@ bool sensorsInit(void)
     return false;
 }
 
-static struct Sensor* sensorFindByHandle(uint32_t handle)
+struct Sensor* sensorFindByHandle(uint32_t handle)
 {
     uint32_t i;
 
diff --git a/firmware/src/seos.c b/firmware/os/core/seos.c
index fbed656a..450fb66c 100644
--- a/firmware/src/seos.c
+++ b/firmware/os/core/seos.c
@@ -14,115 +14,44 @@
  * limitations under the License.
  */
 
-#include <plat/inc/eeData.h>
-#include <plat/inc/plat.h>
-#include <plat/inc/bl.h>
-#include <plat/inc/wdt.h>
-#include <platform.h>
-#include <hostIntf.h>
 #include <inttypes.h>
-#include <syscall.h>
-#include <sensors.h>
-#include <string.h>
-#include <stdlib.h>
 #include <stdarg.h>
-#include <printf.h>
-#include <eventQ.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <plat/eeData.h>
+#include <plat/plat.h>
+#include <plat/wdt.h>
+
 #include <apInt.h>
-#include <timer.h>
+#include <atomic.h>
+#include <bl.h>
+#include <cpu.h>
+#include <crc.h>
+#include <eventQ.h>
+#include <heap.h>
+#include <hostIntf.h>
+#include <mpu.h>
+#include <nanohubPacket.h>
 #include <osApi.h>
+#include <platform.h>
+#include <printf.h>
+#include <sensors.h>
 #include <seos.h>
-#include <heap.h>
+#include <seos_priv.h>
 #include <slab.h>
-#include <cpu.h>
+#include <syscall.h>
+#include <timer.h>
 #include <util.h>
-#include <mpu.h>
-#include <nanohubPacket.h>
-#include <atomic.h>
 
 #include <nanohub/nanohub.h>
-#include <nanohub/crc.h>
-
-#define NO_NODE (TaskIndex)(-1)
-#define for_each_task(listHead, task) for (task = osTaskByIdx((listHead)->next); task; task = osTaskByIdx(task->list.next))
-#define MAKE_NEW_TID(task) task->tid = ((task->tid + TASK_TID_INCREMENT) & TASK_TID_COUNTER_MASK) | \
-                                       (osTaskIndex(task) & TASK_TID_IDX_MASK);
-#define TID_TO_TASK_IDX(tid) (tid & TASK_TID_IDX_MASK)
-
-#define FL_TASK_STOPPED 1
-
-#define EVT_SUBSCRIBE_TO_EVT         0x00000000
-#define EVT_UNSUBSCRIBE_TO_EVT       0x00000001
-#define EVT_DEFERRED_CALLBACK        0x00000002
-#define EVT_PRIVATE_EVT              0x00000003
 
-#define EVENT_WITH_ORIGIN(evt, origin)       (((evt) & EVT_MASK) | ((origin) << (32 - TASK_TID_BITS)))
-#define EVENT_GET_ORIGIN(evt) ((evt) >> (32 - TASK_TID_BITS))
-#define EVENT_GET_EVENT(evt) ((evt) & (EVT_MASK & ~EVENT_TYPE_BIT_DISCARDABLE))
-
-/*
- * Since locking is difficult to do right for adding/removing listeners and such
- * since it can happen in interrupt context and not, and one such operation can
- * interrupt another, and we do have a working event queue, we enqueue all the
- * requests and then deal with them in the main code only when the event bubbles
- * up to the front of the queue. This allows us to not need locks around the
- * data structures.
- */
-
-SET_PACKED_STRUCT_MODE_ON
-struct TaskList {
-    TaskIndex prev;
-    TaskIndex next;
-} ATTRIBUTE_PACKED;
-SET_PACKED_STRUCT_MODE_OFF
-
-struct Task {
-    /* App entry points */
-    const struct AppHdr *app;
-
-    /* per-platform app info */
-    struct PlatAppInfo platInfo;
-
-    /* for some basic number of subbed events, the array is stored directly here. after that, a heap chunk is used */
-    uint32_t subbedEventsInt[MAX_EMBEDDED_EVT_SUBS];
-    uint32_t *subbedEvents; /* NULL for invalid tasks */
-
-    struct TaskList list;
-
-    /* task pointer will not change throughout task lifetime,
-     * however same task pointer may be reused for a new task; to eliminate the ambiguity,
-     * TID is maintained for each task such that new tasks will be guaranteed to receive different TID */
-    uint16_t tid;
-
-    uint8_t  subbedEvtCount;
-    uint8_t  subbedEvtListSz;
-    uint8_t  flags;
-    uint8_t  ioCount;
-
-};
+#include <chreApi.h>
 
 struct TaskPool {
     struct Task data[MAX_TASKS];
 };
 
-union InternalThing {
-    struct {
-        uint32_t tid;
-        uint32_t evt;
-    } evtSub;
-    struct {
-        OsDeferCbkF callback;
-        void *cookie;
-    } deferred;
-    struct {
-        uint32_t evtType;
-        void *evtData;
-        TaggedPtr evtFreeInfo;
-        uint32_t toTid;
-    } privateEvt;
-    union OsApiSlabItem osApiItem;
-};
-
 static struct TaskPool mTaskPool;
 static struct EvtQueue *mEvtsInternal;
 static struct SlabAllocator* mMiscInternalThingsSlab;
@@ -137,12 +66,12 @@ static inline void list_init(struct TaskList *l)
     l->prev = l->next = NO_NODE;
 }
 
-static inline struct Task *osGetCurrentTask()
+struct Task *osGetCurrentTask()
 {
     return mCurrentTask;
 }
 
-static struct Task *osSetCurrentTask(struct Task *task)
+struct Task *osSetCurrentTask(struct Task *task)
 {
     struct Task *old = mCurrentTask;
     while (true) {
@@ -161,6 +90,13 @@ static inline bool osTaskTestFlags(struct Task *task, uint32_t mask)
     return (atomicReadByte(&task->flags) & mask) != 0;
 }
 
+bool osAppIsChre(uint16_t tid)
+{
+    struct Task *task = osTaskFindByTid(tid);
+
+    return task && osTaskIsChre(task);
+}
+
 static inline uint32_t osTaskClrSetFlags(struct Task *task, uint32_t clrMask, uint32_t setMask)
 {
     while (true) {
@@ -185,7 +121,7 @@ static inline uint32_t osTaskGetIoCount(struct Task *task)
     return atomicReadByte(&task->ioCount);
 }
 
-static inline uint8_t osTaskIndex(struct Task *task)
+uint8_t osTaskIndex(struct Task *task)
 {
     // we don't need signed diff here: this way we simplify boundary check
     size_t idx = task - &mTaskPool.data[0];
@@ -337,7 +273,7 @@ static void osAddTask(struct Task *task)
     osTaskListAddTail(&mTasks, task);
 }
 
-static inline struct Task* osTaskFindByTid(uint32_t tid)
+struct Task* osTaskFindByTid(uint32_t tid)
 {
     TaskIndex idx = TID_TO_TASK_IDX(tid);
 
@@ -352,20 +288,27 @@ static inline bool osTaskInit(struct Task *task)
     return done;
 }
 
-static inline void osTaskEnd(struct Task *task)
+static void osTaskRelease(struct Task *task)
 {
-    struct Task *preempted = osSetCurrentTask(task);
     uint16_t tid = task->tid;
 
-    cpuAppEnd(task->app, &task->platInfo);
-
-    // task was supposed to release it's resources,
-    // but we do our cleanup anyway
     osSetCurrentTask(mSystemTask);
+
     platFreeResources(tid); // HW resources cleanup (IRQ, DMA etc)
     sensorUnregisterAll(tid);
     timTimerCancelAll(tid);
     heapFreeAll(tid);
+}
+
+static inline void osTaskEnd(struct Task *task)
+{
+    struct Task *preempted = osSetCurrentTask(task);
+
+    cpuAppEnd(task->app, &task->platInfo);
+
+    // task was supposed to release it's resources,
+    // but we do our cleanup anyway
+    osTaskRelease(task);
     // NOTE: we don't need to unsubscribe from events
     osSetCurrentTask(preempted);
 }
@@ -373,27 +316,60 @@ static inline void osTaskEnd(struct Task *task)
 static inline void osTaskHandle(struct Task *task, uint32_t evtType, const void* evtData)
 {
     struct Task *preempted = osSetCurrentTask(task);
-    cpuAppHandle(task->app, &task->platInfo, evtType, evtData);
+    cpuAppHandle(task->app, &task->platInfo,
+                 osTaskIsChre(task) ? evtType : EVENT_GET_EVENT(evtType), evtData);
     osSetCurrentTask(preempted);
 }
 
+void osTaskInvokeMessageFreeCallback(struct Task *task, void (*freeCallback)(void *, size_t), void *message, uint32_t messageSize)
+{
+    if (!task || !freeCallback)
+        return;
+    cpuAppInvoke(task->app, &task->platInfo, (void (*)(uintptr_t,uintptr_t))freeCallback, (uintptr_t)message, (uintptr_t)messageSize);
+}
+
+void osTaskInvokeEventFreeCallback(struct Task *task, void (*freeCallback)(uint16_t, void *), uint16_t event, void *data)
+{
+    if (!task || !freeCallback)
+        return;
+    cpuAppInvoke(task->app, &task->platInfo,
+                 (void (*)(uintptr_t,uintptr_t))freeCallback,
+                 (uintptr_t)event, (uintptr_t)data);
+}
+
+void osEventHeapFree(uint16_t event, void *data)
+{
+    heapFree(data);
+}
+
 static void handleEventFreeing(uint32_t evtType, void *evtData, TaggedPtr evtFreeData) // watch out, this is synchronous
 {
-    if ((taggedPtrIsPtr(evtFreeData) && !taggedPtrToPtr(evtFreeData)) ||
-        (taggedPtrIsUint(evtFreeData) && !taggedPtrToUint(evtFreeData)))
+    struct Task *srcTask = osTaskFindByTid(EVENT_GET_ORIGIN(evtType));
+
+    if (!taggedPtrToUint(evtFreeData) || !evtData)
         return;
 
-    if (taggedPtrIsPtr(evtFreeData))
+    if (!srcTask) {
+        osLog(LOG_ERROR, "ERROR: Failed to find task to free event: evtType=%08" PRIX32 "\n", evtType);
+        return;
+    }
+
+    // release non-CHRE event; we can't determine if this is CHRE or non-CHRE event, but
+    // this method is only called to release non-CHRE events, so we make use of that fact
+
+    if (taggedPtrIsPtr(evtFreeData)) {
+        // this is for internal non-CHRE tasks, and CHRE tasks
+        // System may schedule non-CHRE events on behalf of CHRE app;
+        // this is the place we release them
+        struct Task *preempted = osSetCurrentTask(srcTask);
         ((EventFreeF)taggedPtrToPtr(evtFreeData))(evtData);
-    else {
+        osSetCurrentTask(preempted);
+    } else {
+        // this is for external non-CHRE tasks
         struct AppEventFreeData fd = {.evtType = evtType, .evtData = evtData};
-        struct Task* task = osTaskFindByTid(taggedPtrToUint(evtFreeData));
-
-        if (!task)
-            osLog(LOG_ERROR, "EINCEPTION: Failed to find app to call app to free event sent to app(s).\n");
-        else
-            osTaskHandle(task, EVT_APP_FREE_EVT_DATA, &fd);
+        osTaskHandle(srcTask, EVT_APP_FREE_EVT_DATA, &fd);
     }
+    osTaskAddIoCount(srcTask, -1);
 }
 
 static void osInit(void)
@@ -410,7 +386,7 @@ static void osInit(void)
         return;
     }
 
-    mMiscInternalThingsSlab = slabAllocatorNew(sizeof(union InternalThing), alignof(union InternalThing), 64 /* for now? */);
+    mMiscInternalThingsSlab = slabAllocatorNew(sizeof(union SeosInternalSlabData), alignof(union SeosInternalSlabData), 64 /* for now? */);
     if (!mMiscInternalThingsSlab) {
         osLog(LOG_INFO, "deferred actions list failed to init\n");
         return;
@@ -699,7 +675,7 @@ static bool osStartApp(const struct AppHdr *app)
     if ((task = osLoadApp(app)) != NULL) {
         task->subbedEvtListSz = MAX_EMBEDDED_EVT_SUBS;
         task->subbedEvents = task->subbedEventsInt;
-        MAKE_NEW_TID(task);
+        osTaskMakeNewTid(task);
 
         // print external NanoApp info to facilitate NanoApp debugging
         if (!(task->app->hdr.fwFlags & FL_APP_HDR_INTERNAL))
@@ -724,20 +700,32 @@ static bool osStopTask(struct Task *task)
     if (!task)
         return false;
 
-    osTaskClrSetFlags(task, 0, FL_TASK_STOPPED);
     osRemoveTask(task);
 
-    if (osTaskGetIoCount(task)) {
+    if (osTaskGetIoCount(task))
+    {
         osTaskHandle(task, EVT_APP_STOP, NULL);
         osEnqueueEvtOrFree(EVT_APP_END, task, NULL);
     } else {
-        osTaskEnd(task);
+        osTaskEnd(task); // calls app END() and Release()
         osUnloadApp(task);
     }
 
+    osTaskClrSetFlags(task, 0, FL_TASK_STOPPED);
     return true;
 }
 
+void osTaskAbort(struct Task *task)
+{
+    if (!task)
+        return;
+
+    osRemoveTask(task); // remove from active task list
+    // do not call app END()
+    osTaskRelease(task); // release all system resources
+    osUnloadApp(task); // destroy platform app object in RAM
+}
+
 static bool osExtAppFind(struct SegmentIterator *it, uint64_t appId)
 {
     uint64_t vendor = APP_ID_GET_VENDOR(appId);
@@ -748,6 +736,8 @@ static bool osExtAppFind(struct SegmentIterator *it, uint64_t appId)
 
     while (osSegmentIteratorNext(it)) {
         seg = it->seg;
+        if (!seg)
+            break;
         if (seg->state == SEG_ST_EMPTY)
             break;
         if (seg->state != SEG_ST_VALID)
@@ -767,13 +757,13 @@ static uint32_t osExtAppStopEraseApps(uint64_t appId, bool doErase)
 {
     const struct AppHdr *app;
     int32_t len;
-    struct Task *task;
     struct SegmentIterator it;
     uint32_t stopCount = 0;
     uint32_t eraseCount = 0;
     uint32_t appCount = 0;
     uint32_t taskCount = 0;
     struct MgmtStatus stat = { .value = 0 };
+    struct Task *task;
 
     osSegmentIteratorInit(&it);
     while (osExtAppFind(&it, appId)) {
@@ -782,16 +772,16 @@ static uint32_t osExtAppStopEraseApps(uint64_t appId, bool doErase)
         if (!osExtAppIsValid(app, len))
             continue;
         appCount++;
+        /* it is safe to erase a running app;
+         * erase merely sets a flag in the header,
+         * and app keeps running until it is stopped */
+        if (doErase && osExtAppErase(app))
+            eraseCount++;
         task = osTaskFindByAppID(app->hdr.appId);
-        if (task)
+        if (task) {
             taskCount++;
-        if (task && task->app == app) {
             if (osStopTask(task))
-                stopCount++;
-            else
-                continue;
-            if (doErase && osExtAppErase(app))
-                eraseCount++;
+               stopCount++;
         }
     }
     SET_COUNTER(stat.app,   appCount);
@@ -942,11 +932,15 @@ static void osStartTasks(void)
 
 static void osInternalEvtHandle(uint32_t evtType, void *evtData)
 {
-    union InternalThing *da = (union InternalThing*)evtData;
+    union SeosInternalSlabData *da = (union SeosInternalSlabData*)evtData;
     struct Task *task;
     uint32_t i;
+    uint16_t tid = EVENT_GET_ORIGIN(evtType);
+    uint16_t evt = EVENT_GET_EVENT(evtType);
+    struct Task *srcTask = osTaskFindByTid(tid);
+    struct Task *preempted = osSetCurrentTask(srcTask);
 
-    switch (evtType) {
+    switch (evt) {
     case EVT_SUBSCRIBE_TO_EVT:
     case EVT_UNSUBSCRIBE_TO_EVT:
         /* get task */
@@ -958,10 +952,10 @@ static void osInternalEvtHandle(uint32_t evtType, void *evtData)
         for (i = 0; i < task->subbedEvtCount && task->subbedEvents[i] != da->evtSub.evt; i++);
 
         /* if unsub & found -> unsub */
-        if (evtType == EVT_UNSUBSCRIBE_TO_EVT && i != task->subbedEvtCount)
+        if (evt == EVT_UNSUBSCRIBE_TO_EVT && i != task->subbedEvtCount)
             task->subbedEvents[i] = task->subbedEvents[--task->subbedEvtCount];
         /* if sub & not found -> sub */
-        else if (evtType == EVT_SUBSCRIBE_TO_EVT && i == task->subbedEvtCount) {
+        else if (evt == EVT_SUBSCRIBE_TO_EVT && i == task->subbedEvtCount) {
             if (task->subbedEvtListSz == task->subbedEvtCount) { /* enlarge the list */
                 uint32_t newSz = (task->subbedEvtListSz * 3 + 1) / 2;
                 uint32_t *newList = heapAlloc(sizeof(uint32_t[newSz])); /* grow by 50% */
@@ -991,19 +985,25 @@ static void osInternalEvtHandle(uint32_t evtType, void *evtData)
 
     case EVT_PRIVATE_EVT:
         task = osTaskFindByTid(da->privateEvt.toTid);
+        evtType = EVENT_WITH_ORIGIN(da->privateEvt.evtType & EVT_MASK, da->privateEvt.fromTid);
+        evtData = da->privateEvt.evtData;
         if (task) {
             //private events cannot be retained
             TaggedPtr *tmp = mCurEvtEventFreeingInfo;
             mCurEvtEventFreeingInfo = NULL;
-
-            osTaskHandle(task, da->privateEvt.evtType, da->privateEvt.evtData);
-
+            osTaskHandle(task, evtType, da->privateEvt.evtData);
             mCurEvtEventFreeingInfo = tmp;
         }
-
-        handleEventFreeing(da->privateEvt.evtType, da->privateEvt.evtData, da->privateEvt.evtFreeInfo);
+        if ((da->privateEvt.evtType >> 16) == EVT_PRIVATE_CLASS_CHRE) {
+            osChreFreeEvent(da->privateEvt.fromTid,
+                            (void (*)(uint16_t, void *))taggedPtrToPtr(da->privateEvt.evtFreeInfo),
+                            evtType, evtData);
+        } else {
+            handleEventFreeing(evtType, evtData, da->privateEvt.evtFreeInfo);
+        }
         break;
     }
+    osSetCurrentTask(preempted);
 }
 
 void abort(void)
@@ -1025,6 +1025,7 @@ bool osRetainCurrentEvent(TaggedPtr *evtFreeingInfoP)
 
 void osFreeRetainedEvent(uint32_t evtType, void *evtData, TaggedPtr *evtFreeingInfoP)
 {
+    //TODO: figure the way to calcualte src tid here to pass to handleEventFreeing
     handleEventFreeing(evtType, evtData, *evtFreeingInfoP);
 }
 
@@ -1037,6 +1038,7 @@ void osMainInit(void)
     sensorsInit();
     syscallInit();
     osApiExport(mMiscInternalThingsSlab);
+    osChreApiExport();
     apIntInit();
     cpuIntsOn();
     wdtInit();
@@ -1052,29 +1054,24 @@ void osMainDequeueLoop(void)
     uint32_t evtType, j;
     void *evtData;
     struct Task *task;
-    uint16_t tid;
+    uint16_t evt;
 
     /* get an event */
     if (!evtQueueDequeue(mEvtsInternal, &evtType, &evtData, &evtFreeingInfo, true))
         return;
 
-    evtType = EVENT_GET_EVENT(evtType);
-    tid = EVENT_GET_ORIGIN(evtType);
-    task = osTaskFindByTid(tid);
-    if (task)
-        osTaskAddIoCount(task, -1);
-
     /* by default we free them when we're done with them */
     mCurEvtEventFreeingInfo = &evtFreeingInfo;
+    evt = EVENT_GET_EVENT(evtType);
 
-    if (evtType < EVT_NO_FIRST_USER_EVENT) {
+    if (evt < EVT_NO_FIRST_USER_EVENT) {
         /* handle deferred actions and other reserved events here */
         osInternalEvtHandle(evtType, evtData);
     } else {
         /* send this event to all tasks who want it */
         for_each_task(&mTasks, task) {
             for (j = 0; j < task->subbedEvtCount; j++) {
-                if (task->subbedEvents[j] == evtType) {
+                if (task->subbedEvents[j] == evt) {
                     osTaskHandle(task, evtType, evtData);
                     break;
                 }
@@ -1108,7 +1105,7 @@ static void osDeferredActionFreeF(void* event)
 
 static bool osEventSubscribeUnsubscribe(uint32_t tid, uint32_t evtType, bool sub)
 {
-    union InternalThing *act = slabAllocatorAlloc(mMiscInternalThingsSlab);
+    union SeosInternalSlabData *act = slabAllocatorAlloc(mMiscInternalThingsSlab);
 
     if (!act)
         return false;
@@ -1130,28 +1127,35 @@ bool osEventUnsubscribe(uint32_t tid, uint32_t evtType)
     return osEventSubscribeUnsubscribe(osGetCurrentTid(), evtType, false);
 }
 
-static bool osEnqueueEvtCommon(uint32_t evtType, void *evtData, TaggedPtr evtFreeInfo)
+static bool osEnqueueEvtCommon(uint32_t evt, void *evtData, TaggedPtr evtFreeInfo, bool urgent)
 {
     struct Task *task = osGetCurrentTask();
+    uint32_t evtType = EVENT_WITH_ORIGIN(evt, osGetCurrentTid());
+
+    if (taggedPtrToUint(evtFreeInfo) && evtData)
+        osTaskAddIoCount(task, 1);
 
     if (osTaskTestFlags(task, FL_TASK_STOPPED)) {
         handleEventFreeing(evtType, evtData, evtFreeInfo);
         return true;
     }
 
-    evtType = EVENT_WITH_ORIGIN(evtType, osGetCurrentTid());
-    osTaskAddIoCount(task, 1);
+    if (!evtQueueEnqueue(mEvtsInternal, evtType, evtData, evtFreeInfo, urgent)) {
+        osTaskAddIoCount(task, -1);
+        return false;
+    }
 
-    if (evtQueueEnqueue(mEvtsInternal, evtType, evtData, evtFreeInfo, false))
-        return true;
+    return true;
+}
 
-    osTaskAddIoCount(task, -1);
-    return false;
+void osRemovePendingEvents(bool (*match)(uint32_t evtType, const void *evtData, void *context), void *context)
+{
+    evtQueueRemoveAllMatching(mEvtsInternal, match, context);
 }
 
 bool osEnqueueEvt(uint32_t evtType, void *evtData, EventFreeF evtFreeF)
 {
-    return osEnqueueEvtCommon(evtType, evtData, taggedPtrMakeFromPtr(evtFreeF));
+    return osEnqueueEvtCommon(evtType, evtData, taggedPtrMakeFromPtr(evtFreeF), false);
 }
 
 bool osEnqueueEvtOrFree(uint32_t evtType, void *evtData, EventFreeF evtFreeF)
@@ -1171,19 +1175,19 @@ bool osEnqueueEvtAsApp(uint32_t evtType, void *evtData, uint32_t fromAppTid)
         evtType |= EVENT_TYPE_BIT_DISCARDABLE;
 
     (void)fromAppTid;
-    return osEnqueueEvtCommon(evtType, evtData, taggedPtrMakeFromUint(osGetCurrentTid()));
+    return osEnqueueEvtCommon(evtType, evtData, taggedPtrMakeFromUint(osGetCurrentTid()), false);
 }
 
 bool osDefer(OsDeferCbkF callback, void *cookie, bool urgent)
 {
-    union InternalThing *act = slabAllocatorAlloc(mMiscInternalThingsSlab);
+    union SeosInternalSlabData *act = slabAllocatorAlloc(mMiscInternalThingsSlab);
     if (!act)
             return false;
 
     act->deferred.callback = callback;
     act->deferred.cookie = cookie;
 
-    if (evtQueueEnqueue(mEvtsInternal, EVT_DEFERRED_CALLBACK, act, taggedPtrMakeFromPtr(osDeferredActionFreeF), urgent))
+    if (osEnqueueEvtCommon(EVT_DEFERRED_CALLBACK, act, taggedPtrMakeFromPtr(osDeferredActionFreeF), urgent))
         return true;
 
     slabAllocatorFree(mMiscInternalThingsSlab, act);
@@ -1192,37 +1196,59 @@ bool osDefer(OsDeferCbkF callback, void *cookie, bool urgent)
 
 static bool osEnqueuePrivateEvtEx(uint32_t evtType, void *evtData, TaggedPtr evtFreeInfo, uint32_t toTid)
 {
-    union InternalThing *act = slabAllocatorAlloc(mMiscInternalThingsSlab);
+    union SeosInternalSlabData *act = slabAllocatorAlloc(mMiscInternalThingsSlab);
+    bool result;
+
     if (!act) {
         osLog(LOG_ERROR, "[seos] ERROR: osEnqueuePrivateEvtEx: call to slabAllocatorAlloc() failed\n");
         return false;
     }
+    struct Task *task = osGetCurrentTask();
+    if (taggedPtrToUint(evtFreeInfo) && evtData)
+        osTaskAddIoCount(task, 1);
 
     act->privateEvt.evtType = evtType;
     act->privateEvt.evtData = evtData;
     act->privateEvt.evtFreeInfo = evtFreeInfo;
+    act->privateEvt.fromTid = task->tid;
     act->privateEvt.toTid = toTid;
 
-    return osEnqueueEvtOrFree(EVT_PRIVATE_EVT, act, osDeferredActionFreeF);
+    osSetCurrentTask(mSystemTask);
+    result = osEnqueueEvtOrFree(EVT_PRIVATE_EVT, act, osDeferredActionFreeF);
+    osSetCurrentTask(task);
+    return result;
+}
+
+// only called to send events for CHRE apps
+bool osEnqueuePrivateEvtNew(uint16_t evtType, void *evtData,
+                                   void (*evtFreeCallback)(uint16_t evtType, void *evtData),
+                                   uint32_t toTid)
+{
+    if (!osEnqueuePrivateEvtEx(evtType | (EVT_PRIVATE_CLASS_CHRE << 16), evtData,
+                               taggedPtrMakeFromPtr(evtFreeCallback), toTid)) {
+        osChreFreeEvent(osGetCurrentTid(), evtFreeCallback, evtType, evtData);
+        return false;
+    }
+    return true;
 }
 
 bool osEnqueuePrivateEvt(uint32_t evtType, void *evtData, EventFreeF evtFreeF, uint32_t toTid)
 {
-    return osEnqueuePrivateEvtEx(evtType, evtData, taggedPtrMakeFromPtr(evtFreeF), toTid);
+    return osEnqueuePrivateEvtEx(evtType & EVT_MASK, evtData, taggedPtrMakeFromPtr(evtFreeF), toTid);
 }
 
 bool osEnqueuePrivateEvtAsApp(uint32_t evtType, void *evtData, uint32_t fromAppTid, uint32_t toTid)
 {
     (void)fromAppTid;
-    return osEnqueuePrivateEvtEx(evtType, evtData, taggedPtrMakeFromUint(osGetCurrentTid()), toTid);
+    return osEnqueuePrivateEvtEx(evtType & EVT_MASK, evtData, taggedPtrMakeFromUint(osGetCurrentTid()), toTid);
 }
 
-bool osTidById(uint64_t appId, uint32_t *tid)
+bool osTidById(uint64_t *appId, uint32_t *tid)
 {
     struct Task *task;
 
     for_each_task(&mTasks, task) {
-        if (task->app && task->app->hdr.appId == appId) {
+        if (task->app && !memcmp(&task->app->hdr.appId, appId, sizeof(*appId))) {
             *tid = task->tid;
             return true;
         }
@@ -1270,11 +1296,11 @@ bool osAppInfoByIndex(uint32_t appIdx, uint64_t *appId, uint32_t *appVer, uint32
     return false;
 }
 
-void osLogv(enum LogLevel level, const char *str, va_list vl)
+void osLogv(char clevel, const char *str, va_list vl)
 {
     void *userData = platLogAllocUserData();
 
-    platLogPutcharF(userData, level);
+    platLogPutcharF(userData, clevel);
     cvprintf(platLogPutcharF, userData, str, vl);
 
     platLogFlush(userData);
@@ -1285,7 +1311,7 @@ void osLog(enum LogLevel level, const char *str, ...)
     va_list vl;
 
     va_start(vl, str);
-    osLogv(level, str, vl);
+    osLogv((char)level, str, vl);
     va_end(vl);
 }
 
diff --git a/firmware/src/simpleQ.c b/firmware/os/core/simpleQ.c
index 3b897121..3b897121 100644
--- a/firmware/src/simpleQ.c
+++ b/firmware/os/core/simpleQ.c
diff --git a/firmware/src/slab.c b/firmware/os/core/slab.c
index 13400e5f..13400e5f 100644
--- a/firmware/src/slab.c
+++ b/firmware/os/core/slab.c
diff --git a/firmware/src/spi.c b/firmware/os/core/spi.c
index afa58a3e..afa58a3e 100644
--- a/firmware/src/spi.c
+++ b/firmware/os/core/spi.c
diff --git a/firmware/src/syscall.c b/firmware/os/core/syscall.c
index 2bd9169e..2bd9169e 100644
--- a/firmware/src/syscall.c
+++ b/firmware/os/core/syscall.c
diff --git a/firmware/src/timer.c b/firmware/os/core/timer.c
index e64c5579..76df80bb 100644
--- a/firmware/src/timer.c
+++ b/firmware/os/core/timer.c
@@ -14,8 +14,8 @@
  * limitations under the License.
  */
 
-#include <cpu/inc/atomicBitset.h>
-#include <plat/inc/rtc.h>
+#include <cpu/atomicBitset.h>
+#include <plat/rtc.h>
 #include <atomicBitset.h>
 #include <platform.h>
 #include <atomic.h>
@@ -27,6 +27,8 @@
 #include <slab.h>
 #include <util.h>
 
+#include "seos_priv.h"
+
 #define MAX_INTERNAL_EVENTS       32 //also used for external app timer() calls
 
 #define INFO_PRINT(fmt, ...) do { \
@@ -200,13 +202,37 @@ uint32_t timTimerSetAsApp(uint64_t length, uint32_t jitterPpm, uint32_t driftPpm
     return timTimerSetEx(length, jitterPpm, driftPpm, taggedPtrMakeFromUint(0), data, oneShot);
 }
 
-bool timTimerCancel(uint32_t timerId)
+uint32_t timTimerSetNew(uint64_t length, const void* data, bool oneShot)
+{
+    return timTimerSetEx(length, 0, 0, taggedPtrMakeFromUint(0), (void *)data, oneShot);
+}
+
+static bool timerEventMatch(uint32_t evtType, const void *evtData, void *context)
+{
+    struct Timer *t = (struct Timer *)context;
+    union SeosInternalSlabData *da = (union SeosInternalSlabData*)evtData;
+    struct TimerEvent *evt;
+
+    if (evtType != EVT_PRIVATE_EVT || !da || da->privateEvt.evtType != EVT_APP_TIMER || !da->privateEvt.evtData)
+        return false;
+
+    evt = (struct TimerEvent *)da->privateEvt.evtData;
+
+    return evt->timerId == t->id;
+}
+
+bool timTimerCancelEx(uint32_t timerId, bool cancelPending)
 {
     uint64_t intState = cpuIntsOff();
     struct Timer *t = timFindTimerById(timerId);
 
-    if (t)
+    if (t && t->tid == osGetCurrentTid()) {
+        if (cancelPending)
+            osRemovePendingEvents(timerEventMatch, t);
         t->id = 0; /* this disables it */
+    } else {
+        t = NULL;
+    }
 
     cpuIntsRestore(intState);
 
@@ -219,6 +245,11 @@ bool timTimerCancel(uint32_t timerId)
     return false;
 }
 
+bool timTimerCancel(uint32_t timerId)
+{
+    return timTimerCancelEx(timerId, false);
+}
+
 int timTimerCancelAll(uint32_t tid)
 {
     uint64_t intState;
@@ -231,6 +262,7 @@ int timTimerCancelAll(uint32_t tid)
         if (tim->tid != tid)
             continue;
         count++;
+        osRemovePendingEvents(timerEventMatch, tim);
         tim->id = 0; /* this disables it */
         /* this frees struct */
         atomicBitsetClearBit(mTimersValid, tim - mTimers);
diff --git a/firmware/src/trylock.c b/firmware/os/core/trylock.c
index 62b3a10e..62b3a10e 100644
--- a/firmware/src/trylock.c
+++ b/firmware/os/core/trylock.c
diff --git a/firmware/os/cpu/cortexm4/Android.mk b/firmware/os/cpu/cortexm4/Android.mk
new file mode 100644
index 00000000..db79e029
--- /dev/null
+++ b/firmware/os/cpu/cortexm4/Android.mk
@@ -0,0 +1,48 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_PATH := $(call my-dir)
+
+########################################################
+# COMMON OS & BL defs
+########################################################
+
+include $(CLEAR_NANO_VARS)
+
+LOCAL_MODULE := libnanohub_bl_cortexm4
+LOCAL_AUX_CPU := cortexm4
+
+LOCAL_SRC_FILES := \
+    atomic.c \
+    atomicBitset.c \
+    cpu.c \
+
+include $(BUILD_NANOHUB_BL_STATIC_LIBRARY)
+
+include $(CLEAR_NANO_VARS)
+
+LOCAL_MODULE := libnanohub_os_cortexm4
+LOCAL_AUX_CPU := cortexm4
+
+LOCAL_SRC_FILES := \
+    appSupport.c \
+    atomic.c \
+    atomicBitset.c \
+    cpu.c \
+    cpuMath.c \
+    pendsv.c \
+
+include $(BUILD_NANOHUB_OS_STATIC_LIBRARY)
diff --git a/firmware/src/cpu/cortexm4f/appSupport.c b/firmware/os/cpu/cortexm4/appSupport.c
index 927fc905..41bf8a37 100644
--- a/firmware/src/cpu/cortexm4f/appSupport.c
+++ b/firmware/os/cpu/cortexm4/appSupport.c
@@ -22,7 +22,7 @@
 #include <seos.h>
 #include <cpu.h>
 
-
+#include <plat/cmsis.h>
 
 //reloc types for this cpu type
 #define NANO_RELOC_TYPE_RAM	0
@@ -202,6 +202,7 @@ void cpuAppEnd(const struct AppHdr *app, struct PlatAppInfo *platInfo)
         (void)callWithR9((const void*)APP_FLASH_RELOC_BASE(app), app->vec.end, platInfo->data, 0, 0);
     else
         APP_VEC(app)->end();
+    osLog(LOG_INFO, "App ID %016" PRIX64 "; TID=%04" PRIX32 " terminated\n", app->hdr.appId, osGetCurrentTid());
 }
 
 void cpuAppHandle(const struct AppHdr *app, struct PlatAppInfo *platInfo, uint32_t evtType, const void* evtData)
@@ -211,3 +212,17 @@ void cpuAppHandle(const struct AppHdr *app, struct PlatAppInfo *platInfo, uint32
     else
         APP_VEC(app)->handle(evtType, evtData);
 }
+
+void cpuAppInvoke(const struct AppHdr *app, struct PlatAppInfo *platInfo,
+                  void (*method)(uintptr_t, uintptr_t),uintptr_t arg1, uintptr_t arg2)
+{
+    if (platInfo->data) {
+        uint32_t hasSvcAct = SCB->SHCSR & SCB_SHCSR_SVCALLACT_Msk;
+
+        SCB->SHCSR &= ~SCB_SHCSR_SVCALLACT_Msk;
+        (void)callWithR9(0, (uint32_t)method, platInfo->data, arg1, arg2);
+        SCB->SHCSR |= hasSvcAct;
+    } else {
+        method(arg1, arg2);
+    }
+}
diff --git a/firmware/src/cpu/cortexm4f/atomic.c b/firmware/os/cpu/cortexm4/atomic.c
index 15963cd1..15963cd1 100644
--- a/firmware/src/cpu/cortexm4f/atomic.c
+++ b/firmware/os/cpu/cortexm4/atomic.c
diff --git a/firmware/src/cpu/cortexm4f/atomicBitset.c b/firmware/os/cpu/cortexm4/atomicBitset.c
index 9e5ce09e..9e5ce09e 100644
--- a/firmware/src/cpu/cortexm4f/atomicBitset.c
+++ b/firmware/os/cpu/cortexm4/atomicBitset.c
diff --git a/firmware/misc/cpu/cortexm4f/Makefile b/firmware/os/cpu/cortexm4/cortexm4.mk
index e81465c1..c8ac99a6 100644
--- a/firmware/misc/cpu/cortexm4f/Makefile
+++ b/firmware/os/cpu/cortexm4/cortexm4.mk
@@ -18,33 +18,53 @@ GCC = $(CROSS_COMPILE)gcc
 OBJCOPY = $(CROSS_COMPILE)objcopy
 
 FLAGS += -mthumb -mcpu=cortex-m4 -march=armv7e-m -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -mno-thumb-interwork -ffast-math -fsingle-precision-constant -DARM -DUSE_NANOHUB_FLOAT_RUNTIME
-APPFLAGS += -Wl,-T misc/cpu/$(CPU)/app.lkr -mno-pic-data-is-text-relative
+
+LIB_PATH := lib
 
 #defines
 FLAGS += -DCPU_NUM_PERSISTENT_RAM_BITS=32
 
 #cpu runtime
-SRCS_os += src/cpu/$(CPU)/atomicBitset.c src/cpu/$(CPU)/cpu.c src/cpu/$(CPU)/pendsv.c src/cpu/$(CPU)/atomic.c src/cpu/$(CPU)/appSupport.c src/cpu/$(CPU)/cpuMath.c
+SRCS_os += \
+    os/cpu/$(CPU)/atomicBitset.c \
+    os/cpu/$(CPU)/cpu.c \
+    os/cpu/$(CPU)/pendsv.c \
+    os/cpu/$(CPU)/atomic.c \
+    os/cpu/$(CPU)/appSupport.c \
+    os/cpu/$(CPU)/cpuMath.c \
 
 #cpu runtime for bootloader
-SRCS_bl += src/cpu/$(CPU)/cpu.c
+SRCS_bl += os/cpu/$(CPU)/cpu.c
 
 #c runtime
-SRCS_os += ../lib/libc/memcpy-armv7m.S ../lib/libc/memset.c ../lib/libc/memcmp.c ../lib/libc/memmove.c
+SRCS_os += \
+    $(LIB_PATH)/libc/memcpy-armv7m.S \
+    $(LIB_PATH)/libc/memset.c \
+    $(LIB_PATH)/libc/memcmp.c \
+    $(LIB_PATH)/libc/memmove.c \
 
 #c runtime for bootloader
-SRCS_bl += ../lib/libc/memcpy-armv7m.S ../lib/libc/memset.c ../lib/libc/memcmp.c ../lib/libc/memmove.c
+SRCS_bl += \
+    $(LIB_PATH)/libc/memcpy-armv7m.S \
+    $(LIB_PATH)/libc/memset.c \
+    $(LIB_PATH)/libc/memcmp.c \
+    $(LIB_PATH)/libc/memmove.c \
 
 #floating point runtime (ARM)
 SRCS_os += external/arm/arm_sin_cos_f32.c
 FLAGS += -DARM_MATH_CM4 -D__FPU_PRESENT
 
 #floating point runtime (FreeBSD)
-SRCS_os += external/freebsd/lib/msun/src/e_atan2f.c external/freebsd/lib/msun/src/e_expf.c external/freebsd/lib/msun/src/s_atanf.c
-FLAGS += -DFLT_EVAL_METHOD
+SRCS_os += \
+    external/freebsd/lib/msun/src/e_atan2f.c \
+    external/freebsd/lib/msun/src/e_expf.c \
+    external/freebsd/lib/msun/src/s_atanf.c \
+
+FLAGS += -DFLT_EVAL_METHOD -Iexternal/freebsd/lib/msun/src
 
 #extra deps
-DEPS += $(wildcard inc/cpu/$(CPU)/*.h)
+DEPS += $(wildcard os/cpu/$(CPU)/inc/cpu/*.h)
+DEPS += $(wildcard os/cpu/$(CPU)/inc/cpu/cmsis/*.h)
 
 #bad words for C-M4F
 BADWORDS += "__floatundisf=When casting a uint64_t to float, use floatFromUint64"
@@ -60,6 +80,4 @@ BADWORDS += "asinf=include nanhub_math.h before using asinf()"
 #all softfloat double funcs are forbidden
 BADWORDS += __muldf3 __divdf3 __subdf3 __adddf3 __truncdfsf2
 
-
-
-
+$(info Included CORTEX-M4 CPU)
diff --git a/firmware/src/cpu/cortexm4f/cpu.c b/firmware/os/cpu/cortexm4/cpu.c
index 3aea26a3..2c887e9e 100644
--- a/firmware/src/cpu/cortexm4f/cpu.c
+++ b/firmware/os/cpu/cortexm4/cpu.c
@@ -14,10 +14,10 @@
  * limitations under the License.
  */
 
-#include <plat/inc/cmsis.h>
-#include <plat/inc/plat.h>
-#include <plat/inc/pwr.h>
-#include <plat/inc/wdt.h>
+#include <plat/cmsis.h>
+#include <plat/plat.h>
+#include <plat/pwr.h>
+#include <plat/wdt.h>
 #include <syscall.h>
 #include <string.h>
 #include <seos.h>
diff --git a/firmware/src/cpu/cortexm4f/cpuMath.c b/firmware/os/cpu/cortexm4/cpuMath.c
index f7e3970c..af2df53d 100644
--- a/firmware/src/cpu/cortexm4f/cpuMath.c
+++ b/firmware/os/cpu/cortexm4/cpuMath.c
@@ -1,4 +1,4 @@
-#include <cpu/inc/cpuMath.h>
+#include <cpu/cpuMath.h>
 
 uint32_t cpuMathUint44Div1000ToUint32_slow_path(uint64_t val)
 {
diff --git a/firmware/inc/cpu/cortexm4f/atomic.h b/firmware/os/cpu/cortexm4/inc/cpu/atomic.h
index b9423401..3eb66c2a 100644
--- a/firmware/inc/cpu/cortexm4f/atomic.h
+++ b/firmware/os/cpu/cortexm4/inc/cpu/atomic.h
@@ -17,9 +17,6 @@
 #ifndef _CM4F_ATOMIC_H_
 #define _CM4F_ATOMIC_H_
 
-// real definition available in CPU-independent header file
-extern bool atomicCmpXchg32bits(volatile uint32_t *word, uint32_t prevVal, uint32_t newVal);
-
 static inline bool atomicCmpXchgPtr(volatile uintptr_t *word, uintptr_t prevVal, uintptr_t newVal) {
     // 32-bit CPU architecture so fall back appropriately
     return atomicCmpXchg32bits((volatile uint32_t *) word, (uint32_t) prevVal, (uint32_t) newVal);
diff --git a/firmware/inc/cpu/cortexm4f/atomicBitset.h b/firmware/os/cpu/cortexm4/inc/cpu/atomicBitset.h
index 75a12fe6..75a12fe6 100644
--- a/firmware/inc/cpu/cortexm4f/atomicBitset.h
+++ b/firmware/os/cpu/cortexm4/inc/cpu/atomicBitset.h
diff --git a/firmware/inc/cpu/cortexm4f/barrier.h b/firmware/os/cpu/cortexm4/inc/cpu/barrier.h
index 2c70ff88..2c70ff88 100644
--- a/firmware/inc/cpu/cortexm4f/barrier.h
+++ b/firmware/os/cpu/cortexm4/inc/cpu/barrier.h
diff --git a/firmware/os/cpu/cortexm4/inc/cpu/cmsis.h b/firmware/os/cpu/cortexm4/inc/cpu/cmsis.h
new file mode 100644
index 00000000..d740542d
--- /dev/null
+++ b/firmware/os/cpu/cortexm4/inc/cpu/cmsis.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _CPU_CMSIS_H_
+#define _CPU_CMSIS_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define __NVIC_PRIO_BITS 4
+#define __FPU_PRESENT 1
+
+#include <cpu/cmsis/core_cm4.h>
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif // _CPU_CMSIS_H_
diff --git a/firmware/inc/platform/stm32f4xx/cmsis/arm_common_tables.h b/firmware/os/cpu/cortexm4/inc/cpu/cmsis/arm_common_tables.h
index 06a63487..76aadca4 100644
--- a/firmware/inc/platform/stm32f4xx/cmsis/arm_common_tables.h
+++ b/firmware/os/cpu/cortexm4/inc/cpu/cmsis/arm_common_tables.h
@@ -1,136 +1,136 @@
-/* ----------------------------------------------------------------------

-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.

-*

-* $Date:        31. July 2014

-* $Revision: 	V1.4.4

-*

-* Project: 	    CMSIS DSP Library

-* Title:	    arm_common_tables.h

-*

-* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions

-*

-* Target Processor: Cortex-M4/Cortex-M3

-*

-* Redistribution and use in source and binary forms, with or without

-* modification, are permitted provided that the following conditions

-* are met:

-*   - Redistributions of source code must retain the above copyright

-*     notice, this list of conditions and the following disclaimer.

-*   - Redistributions in binary form must reproduce the above copyright

-*     notice, this list of conditions and the following disclaimer in

-*     the documentation and/or other materials provided with the

-*     distribution.

-*   - Neither the name of ARM LIMITED nor the names of its contributors

-*     may be used to endorse or promote products derived from this

-*     software without specific prior written permission.

-*

-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,

-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,

-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT

-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN

-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-* POSSIBILITY OF SUCH DAMAGE.

-* -------------------------------------------------------------------- */

-

-#ifndef _ARM_COMMON_TABLES_H

-#define _ARM_COMMON_TABLES_H

-

-#include "arm_math.h"

-

-extern const uint16_t armBitRevTable[1024];

-extern const q15_t armRecipTableQ15[64];

-extern const q31_t armRecipTableQ31[64];

-//extern const q31_t realCoefAQ31[1024];

-//extern const q31_t realCoefBQ31[1024];

-extern const float32_t twiddleCoef_16[32];

-extern const float32_t twiddleCoef_32[64];

-extern const float32_t twiddleCoef_64[128];

-extern const float32_t twiddleCoef_128[256];

-extern const float32_t twiddleCoef_256[512];

-extern const float32_t twiddleCoef_512[1024];

-extern const float32_t twiddleCoef_1024[2048];

-extern const float32_t twiddleCoef_2048[4096];

-extern const float32_t twiddleCoef_4096[8192];

-#define twiddleCoef twiddleCoef_4096

-extern const q31_t twiddleCoef_16_q31[24];

-extern const q31_t twiddleCoef_32_q31[48];

-extern const q31_t twiddleCoef_64_q31[96];

-extern const q31_t twiddleCoef_128_q31[192];

-extern const q31_t twiddleCoef_256_q31[384];

-extern const q31_t twiddleCoef_512_q31[768];

-extern const q31_t twiddleCoef_1024_q31[1536];

-extern const q31_t twiddleCoef_2048_q31[3072];

-extern const q31_t twiddleCoef_4096_q31[6144];

-extern const q15_t twiddleCoef_16_q15[24];

-extern const q15_t twiddleCoef_32_q15[48];

-extern const q15_t twiddleCoef_64_q15[96];

-extern const q15_t twiddleCoef_128_q15[192];

-extern const q15_t twiddleCoef_256_q15[384];

-extern const q15_t twiddleCoef_512_q15[768];

-extern const q15_t twiddleCoef_1024_q15[1536];

-extern const q15_t twiddleCoef_2048_q15[3072];

-extern const q15_t twiddleCoef_4096_q15[6144];

-extern const float32_t twiddleCoef_rfft_32[32];

-extern const float32_t twiddleCoef_rfft_64[64];

-extern const float32_t twiddleCoef_rfft_128[128];

-extern const float32_t twiddleCoef_rfft_256[256];

-extern const float32_t twiddleCoef_rfft_512[512];

-extern const float32_t twiddleCoef_rfft_1024[1024];

-extern const float32_t twiddleCoef_rfft_2048[2048];

-extern const float32_t twiddleCoef_rfft_4096[4096];

-

-

-/* floating-point bit reversal tables */

-#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )

-#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )

-#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )

-#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )

-#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )

-#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )

-#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)

-#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)

-#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)

-

-extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];

-

-/* fixed-point bit reversal tables */

-#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )

-#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )

-#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )

-#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )

-#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )

-#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )

-#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )

-#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)

-#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)

-

-extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];

-

-/* Tables for Fast Math Sine and Cosine */

-extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];

-extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];

-extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];

-

-#endif /*  ARM_COMMON_TABLES_H */

+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_common_tables.h
+*
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+//extern const q31_t realCoefAQ31[1024];
+//extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */
diff --git a/firmware/inc/platform/stm32f4xx/cmsis/arm_const_structs.h b/firmware/os/cpu/cortexm4/inc/cpu/cmsis/arm_const_structs.h
index 21c79d69..217f1d50 100644
--- a/firmware/inc/platform/stm32f4xx/cmsis/arm_const_structs.h
+++ b/firmware/os/cpu/cortexm4/inc/cpu/cmsis/arm_const_structs.h
@@ -1,79 +1,79 @@
-/* ----------------------------------------------------------------------

-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.

-*

-* $Date:        31. July 2014

-* $Revision: 	V1.4.4

-*

-* Project: 	    CMSIS DSP Library

-* Title:	    arm_const_structs.h

-*

-* Description:	This file has constant structs that are initialized for

-*              user convenience.  For example, some can be given as

-*              arguments to the arm_cfft_f32() function.

-*

-* Target Processor: Cortex-M4/Cortex-M3

-*

-* Redistribution and use in source and binary forms, with or without

-* modification, are permitted provided that the following conditions

-* are met:

-*   - Redistributions of source code must retain the above copyright

-*     notice, this list of conditions and the following disclaimer.

-*   - Redistributions in binary form must reproduce the above copyright

-*     notice, this list of conditions and the following disclaimer in

-*     the documentation and/or other materials provided with the

-*     distribution.

-*   - Neither the name of ARM LIMITED nor the names of its contributors

-*     may be used to endorse or promote products derived from this

-*     software without specific prior written permission.

-*

-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,

-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,

-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT

-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN

-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-* POSSIBILITY OF SUCH DAMAGE.

-* -------------------------------------------------------------------- */

-

-#ifndef _ARM_CONST_STRUCTS_H

-#define _ARM_CONST_STRUCTS_H

-

-#include "arm_math.h"

-#include "arm_common_tables.h"

-

-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;

-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;

-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;

-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;

-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;

-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;

-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;

-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;

-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;

-

-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;

-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;

-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;

-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;

-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;

-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;

-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;

-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;

-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;

-

-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;

-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;

-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;

-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;

-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;

-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;

-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;

-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;

-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;

-

-#endif

+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_const_structs.h
+*
+* Description:	This file has constant structs that are initialized for
+*              user convenience.  For example, some can be given as
+*              arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/firmware/inc/platform/stm32f4xx/cmsis/arm_math.h b/firmware/os/cpu/cortexm4/inc/cpu/cmsis/arm_math.h
index 422ec13e..0ae8b207 100644
--- a/firmware/inc/platform/stm32f4xx/cmsis/arm_math.h
+++ b/firmware/os/cpu/cortexm4/inc/cpu/cmsis/arm_math.h
@@ -1,7538 +1,7538 @@
-/* ----------------------------------------------------------------------

-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.

-*

-* $Date:        12. March 2014

-* $Revision:    V1.4.4

-*

-* Project:      CMSIS DSP Library

-* Title:        arm_math.h

-*

-* Description:  Public header file for CMSIS DSP Library

-*

-* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0

-*

-* Redistribution and use in source and binary forms, with or without

-* modification, are permitted provided that the following conditions

-* are met:

-*   - Redistributions of source code must retain the above copyright

-*     notice, this list of conditions and the following disclaimer.

-*   - Redistributions in binary form must reproduce the above copyright

-*     notice, this list of conditions and the following disclaimer in

-*     the documentation and/or other materials provided with the

-*     distribution.

-*   - Neither the name of ARM LIMITED nor the names of its contributors

-*     may be used to endorse or promote products derived from this

-*     software without specific prior written permission.

-*

-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,

-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,

-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT

-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN

-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-* POSSIBILITY OF SUCH DAMAGE.

- * -------------------------------------------------------------------- */

-

-/**

-   \mainpage CMSIS DSP Software Library

-   *

-   * Introduction

-   * ------------

-   *

-   * This user manual describes the CMSIS DSP software library,

-   * a suite of common signal processing functions for use on Cortex-M processor based devices.

-   *

-   * The library is divided into a number of functions each covering a specific category:

-   * - Basic math functions

-   * - Fast math functions

-   * - Complex math functions

-   * - Filters

-   * - Matrix functions

-   * - Transforms

-   * - Motor control functions

-   * - Statistical functions

-   * - Support functions

-   * - Interpolation functions

-   *

-   * The library has separate functions for operating on 8-bit integers, 16-bit integers,

-   * 32-bit integer and 32-bit floating-point values.

-   *

-   * Using the Library

-   * ------------

-   *

-   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.

-   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)

-   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)

-   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)

-   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)

-   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)

-   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)

-   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)

-   * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)

-   *

-   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.

-   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single

-   * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.

-   * Define the appropriate pre processor MACRO ARM_MATH_CM4 or  ARM_MATH_CM3 or

-   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.

-   *

-   * Examples

-   * --------

-   *

-   * The library ships with a number of examples which demonstrate how to use the library functions.

-   *

-   * Toolchain Support

-   * ------------

-   *

-   * The library has been developed and tested with MDK-ARM version 4.60.

-   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.

-   *

-   * Building the Library

-   * ------------

-   *

-   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.

-   * - arm_cortexM_math.uvproj

-   *

-   *

-   * The libraries can be built by opening the arm_cortexM_math.uvproj project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.

-   *

-   * Pre-processor Macros

-   * ------------

-   *

-   * Each library project have differant pre-processor macros.

-   *

-   * - UNALIGNED_SUPPORT_DISABLE:

-   *

-   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access

-   *

-   * - ARM_MATH_BIG_ENDIAN:

-   *

-   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.

-   *

-   * - ARM_MATH_MATRIX_CHECK:

-   *

-   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices

-   *

-   * - ARM_MATH_ROUNDING:

-   *

-   * Define macro ARM_MATH_ROUNDING for rounding on support functions

-   *

-   * - ARM_MATH_CMx:

-   *

-   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target

-   * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.

-   *

-   * - __FPU_PRESENT:

-   *

-   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries

-   *

-   * <hr>

-   * CMSIS-DSP in ARM::CMSIS Pack

-   * -----------------------------

-   * 

-   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:

-   * |File/Folder                   |Content                                                                 |

-   * |------------------------------|------------------------------------------------------------------------|

-   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |

-   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |

-   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |

-   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |

-   * 

-   * <hr>

-   * Revision History of CMSIS-DSP

-   * ------------

-   * Please refer to \ref ChangeLog_pg.

-   *

-   * Copyright Notice

-   * ------------

-   *

-   * Copyright (C) 2010-2014 ARM Limited. All rights reserved.

-   */

-

-

-/**

- * @defgroup groupMath Basic Math Functions

- */

-

-/**

- * @defgroup groupFastMath Fast Math Functions

- * This set of functions provides a fast approximation to sine, cosine, and square root.

- * As compared to most of the other functions in the CMSIS math library, the fast math functions

- * operate on individual values and not arrays.

- * There are separate functions for Q15, Q31, and floating-point data.

- *

- */

-

-/**

- * @defgroup groupCmplxMath Complex Math Functions

- * This set of functions operates on complex data vectors.

- * The data in the complex arrays is stored in an interleaved fashion

- * (real, imag, real, imag, ...).

- * In the API functions, the number of samples in a complex array refers

- * to the number of complex values; the array contains twice this number of

- * real values.

- */

-

-/**

- * @defgroup groupFilters Filtering Functions

- */

-

-/**

- * @defgroup groupMatrix Matrix Functions

- *

- * This set of functions provides basic matrix math operations.

- * The functions operate on matrix data structures.  For example,

- * the type

- * definition for the floating-point matrix structure is shown

- * below:

- * <pre>

- *     typedef struct

- *     {

- *       uint16_t numRows;     // number of rows of the matrix.

- *       uint16_t numCols;     // number of columns of the matrix.

- *       float32_t *pData;     // points to the data of the matrix.

- *     } arm_matrix_instance_f32;

- * </pre>

- * There are similar definitions for Q15 and Q31 data types.

- *

- * The structure specifies the size of the matrix and then points to

- * an array of data.  The array is of size <code>numRows X numCols</code>

- * and the values are arranged in row order.  That is, the

- * matrix element (i, j) is stored at:

- * <pre>

- *     pData[i*numCols + j]

- * </pre>

- *

- * \par Init Functions

- * There is an associated initialization function for each type of matrix

- * data structure.

- * The initialization function sets the values of the internal structure fields.

- * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>

- * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.

- *

- * \par

- * Use of the initialization function is optional. However, if initialization function is used

- * then the instance structure cannot be placed into a const data section.

- * To place the instance structure in a const data

- * section, manually initialize the data structure.  For example:

- * <pre>

- * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>

- * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>

- * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>

- * </pre>

- * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>

- * specifies the number of columns, and <code>pData</code> points to the

- * data array.

- *

- * \par Size Checking

- * By default all of the matrix functions perform size checking on the input and

- * output matrices.  For example, the matrix addition function verifies that the

- * two input matrices and the output matrix all have the same number of rows and

- * columns.  If the size check fails the functions return:

- * <pre>

- *     ARM_MATH_SIZE_MISMATCH

- * </pre>

- * Otherwise the functions return

- * <pre>

- *     ARM_MATH_SUCCESS

- * </pre>

- * There is some overhead associated with this matrix size checking.

- * The matrix size checking is enabled via the \#define

- * <pre>

- *     ARM_MATH_MATRIX_CHECK

- * </pre>

- * within the library project settings.  By default this macro is defined

- * and size checking is enabled.  By changing the project settings and

- * undefining this macro size checking is eliminated and the functions

- * run a bit faster.  With size checking disabled the functions always

- * return <code>ARM_MATH_SUCCESS</code>.

- */

-

-/**

- * @defgroup groupTransforms Transform Functions

- */

-

-/**

- * @defgroup groupController Controller Functions

- */

-

-/**

- * @defgroup groupStats Statistics Functions

- */

-/**

- * @defgroup groupSupport Support Functions

- */

-

-/**

- * @defgroup groupInterpolation Interpolation Functions

- * These functions perform 1- and 2-dimensional interpolation of data.

- * Linear interpolation is used for 1-dimensional data and

- * bilinear interpolation is used for 2-dimensional data.

- */

-

-/**

- * @defgroup groupExamples Examples

- */

-#ifndef _ARM_MATH_H

-#define _ARM_MATH_H

-

-#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */

-

-#if defined(ARM_MATH_CM7)

-  #include "core_cm7.h"

-#elif defined (ARM_MATH_CM4)

-  #include "core_cm4.h"

-#elif defined (ARM_MATH_CM3)

-  #include "core_cm3.h"

-#elif defined (ARM_MATH_CM0)

-  #include "core_cm0.h"

-#define ARM_MATH_CM0_FAMILY

-  #elif defined (ARM_MATH_CM0PLUS)

-#include "core_cm0plus.h"

-  #define ARM_MATH_CM0_FAMILY

-#else

-  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"

-#endif

-

-#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */

-#include "string.h"

-#include "math.h"

-#ifdef  __cplusplus

-extern "C"

-{

-#endif

-

-

-  /**

-   * @brief Macros required for reciprocal calculation in Normalized LMS

-   */

-

-#define DELTA_Q31    (0x100)

-#define DELTA_Q15    0x5

-#define INDEX_MASK   0x0000003F

-#ifndef PI

-#define PI           3.14159265358979f

-#endif

-

-  /**

-   * @brief Macros required for SINE and COSINE Fast math approximations

-   */

-

-#define FAST_MATH_TABLE_SIZE  512

-#define FAST_MATH_Q31_SHIFT   (32 - 10)

-#define FAST_MATH_Q15_SHIFT   (16 - 10)

-#define CONTROLLER_Q31_SHIFT  (32 - 9)

-#define TABLE_SIZE  256

-#define TABLE_SPACING_Q31     0x400000

-#define TABLE_SPACING_Q15     0x80

-

-  /**

-   * @brief Macros required for SINE and COSINE Controller functions

-   */

-  /* 1.31(q31) Fixed value of 2/360 */

-  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */

-#define INPUT_SPACING      0xB60B61

-

-  /**

-   * @brief Macro for Unaligned Support

-   */

-#ifndef UNALIGNED_SUPPORT_DISABLE

-    #define ALIGN4

-#else

-  #if defined  (__GNUC__)

-    #define ALIGN4 __attribute__((aligned(4)))

-  #else

-    #define ALIGN4 __align(4)

-  #endif

-#endif  /*  #ifndef UNALIGNED_SUPPORT_DISABLE  */

-

-  /**

-   * @brief Error status returned by some functions in the library.

-   */

-

-  typedef enum

-  {

-    ARM_MATH_SUCCESS = 0,                /**< No error */

-    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */

-    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */

-    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */

-    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */

-    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */

-    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */

-  } arm_status;

-

-  /**

-   * @brief 8-bit fractional data type in 1.7 format.

-   */

-  typedef int8_t q7_t;

-

-  /**

-   * @brief 16-bit fractional data type in 1.15 format.

-   */

-  typedef int16_t q15_t;

-

-  /**

-   * @brief 32-bit fractional data type in 1.31 format.

-   */

-  typedef int32_t q31_t;

-

-  /**

-   * @brief 64-bit fractional data type in 1.63 format.

-   */

-  typedef int64_t q63_t;

-

-  /**

-   * @brief 32-bit floating-point type definition.

-   */

-  typedef float float32_t;

-

-  /**

-   * @brief 64-bit floating-point type definition.

-   */

-  typedef double float64_t;

-

-  /**

-   * @brief definition to read/write two 16 bit values.

-   */

-#if defined __CC_ARM

-#define __SIMD32_TYPE int32_t __packed

-#define CMSIS_UNUSED __attribute__((unused))

-#elif defined __ICCARM__

-#define CMSIS_UNUSED

-#define __SIMD32_TYPE int32_t __packed

-#elif defined __GNUC__

-#define __SIMD32_TYPE int32_t

-#define CMSIS_UNUSED __attribute__((unused))

-#elif defined __CSMC__      /* Cosmic */

-#define CMSIS_UNUSED

-#define __SIMD32_TYPE int32_t

-#else

-#error Unknown compiler

-#endif

-

-#define __SIMD32(addr)  (*(__SIMD32_TYPE **) & (addr))

-#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))

-

-#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))

-

-#define __SIMD64(addr)  (*(int64_t **) & (addr))

-

-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)

-  /**

-   * @brief definition to pack two 16 bit values.

-   */

-#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \

-                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )

-#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \

-                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )

-

-#endif

-

-

-   /**

-   * @brief definition to pack four 8 bit values.

-   */

-#ifndef ARM_MATH_BIG_ENDIAN

-

-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \

-                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \

-                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \

-                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )

-#else

-

-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \

-                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \

-                                (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \

-                                (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )

-

-#endif

-

-

-  /**

-   * @brief Clips Q63 to Q31 values.

-   */

-  static __INLINE q31_t clip_q63_to_q31(

-  q63_t x)

-  {

-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?

-      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;

-  }

-

-  /**

-   * @brief Clips Q63 to Q15 values.

-   */

-  static __INLINE q15_t clip_q63_to_q15(

-  q63_t x)

-  {

-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?

-      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);

-  }

-

-  /**

-   * @brief Clips Q31 to Q7 values.

-   */

-  static __INLINE q7_t clip_q31_to_q7(

-  q31_t x)

-  {

-    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?

-      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;

-  }

-

-  /**

-   * @brief Clips Q31 to Q15 values.

-   */

-  static __INLINE q15_t clip_q31_to_q15(

-  q31_t x)

-  {

-    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?

-      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;

-  }

-

-  /**

-   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.

-   */

-

-  static __INLINE q63_t mult32x64(

-  q63_t x,

-  q31_t y)

-  {

-    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +

-            (((q63_t) (x >> 32) * y)));

-  }

-

-

-#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )

-#define __CLZ __clz

-#endif

-

-#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )

-

-  static __INLINE uint32_t __CLZ(

-  q31_t data);

-

-

-  static __INLINE uint32_t __CLZ(

-  q31_t data)

-  {

-    uint32_t count = 0;

-    uint32_t mask = 0x80000000;

-

-    while((data & mask) == 0)

-    {

-      count += 1u;

-      mask = mask >> 1u;

-    }

-

-    return (count);

-

-  }

-

-#endif

-

-  /**

-   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.

-   */

-

-  static __INLINE uint32_t arm_recip_q31(

-  q31_t in,

-  q31_t * dst,

-  q31_t * pRecipTable)

-  {

-

-    uint32_t out, tempVal;

-    uint32_t index, i;

-    uint32_t signBits;

-

-    if(in > 0)

-    {

-      signBits = __CLZ(in) - 1;

-    }

-    else

-    {

-      signBits = __CLZ(-in) - 1;

-    }

-

-    /* Convert input sample to 1.31 format */

-    in = in << signBits;

-

-    /* calculation of index for initial approximated Val */

-    index = (uint32_t) (in >> 24u);

-    index = (index & INDEX_MASK);

-

-    /* 1.31 with exp 1 */

-    out = pRecipTable[index];

-

-    /* calculation of reciprocal value */

-    /* running approximation for two iterations */

-    for (i = 0u; i < 2u; i++)

-    {

-      tempVal = (q31_t) (((q63_t) in * out) >> 31u);

-      tempVal = 0x7FFFFFFF - tempVal;

-      /*      1.31 with exp 1 */

-      //out = (q31_t) (((q63_t) out * tempVal) >> 30u);

-      out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);

-    }

-

-    /* write output */

-    *dst = out;

-

-    /* return num of signbits of out = 1/in value */

-    return (signBits + 1u);

-

-  }

-

-  /**

-   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.

-   */

-  static __INLINE uint32_t arm_recip_q15(

-  q15_t in,

-  q15_t * dst,

-  q15_t * pRecipTable)

-  {

-

-    uint32_t out = 0, tempVal = 0;

-    uint32_t index = 0, i = 0;

-    uint32_t signBits = 0;

-

-    if(in > 0)

-    {

-      signBits = __CLZ(in) - 17;

-    }

-    else

-    {

-      signBits = __CLZ(-in) - 17;

-    }

-

-    /* Convert input sample to 1.15 format */

-    in = in << signBits;

-

-    /* calculation of index for initial approximated Val */

-    index = in >> 8;

-    index = (index & INDEX_MASK);

-

-    /*      1.15 with exp 1  */

-    out = pRecipTable[index];

-

-    /* calculation of reciprocal value */

-    /* running approximation for two iterations */

-    for (i = 0; i < 2; i++)

-    {

-      tempVal = (q15_t) (((q31_t) in * out) >> 15);

-      tempVal = 0x7FFF - tempVal;

-      /*      1.15 with exp 1 */

-      out = (q15_t) (((q31_t) out * tempVal) >> 14);

-    }

-

-    /* write output */

-    *dst = out;

-

-    /* return num of signbits of out = 1/in value */

-    return (signBits + 1);

-

-  }

-

-

-  /*

-   * @brief C custom defined intrinisic function for only M0 processors

-   */

-#if defined(ARM_MATH_CM0_FAMILY)

-

-  static __INLINE q31_t __SSAT(

-  q31_t x,

-  uint32_t y)

-  {

-    int32_t posMax, negMin;

-    uint32_t i;

-

-    posMax = 1;

-    for (i = 0; i < (y - 1); i++)

-    {

-      posMax = posMax * 2;

-    }

-

-    if(x > 0)

-    {

-      posMax = (posMax - 1);

-

-      if(x > posMax)

-      {

-        x = posMax;

-      }

-    }

-    else

-    {

-      negMin = -posMax;

-

-      if(x < negMin)

-      {

-        x = negMin;

-      }

-    }

-    return (x);

-

-

-  }

-

-#endif /* end of ARM_MATH_CM0_FAMILY */

-

-

-

-  /*

-   * @brief C custom defined intrinsic function for M3 and M0 processors

-   */

-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)

-

-  /*

-   * @brief C custom defined QADD8 for M3 and M0 processors

-   */

-  static __INLINE q31_t __QADD8(

-  q31_t x,

-  q31_t y)

-  {

-

-    q31_t sum;

-    q7_t r, s, t, u;

-

-    r = (q7_t) x;

-    s = (q7_t) y;

-

-    r = __SSAT((q31_t) (r + s), 8);

-    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);

-    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);

-    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);

-

-    sum =

-      (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |

-      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);

-

-    return sum;

-

-  }

-

-  /*

-   * @brief C custom defined QSUB8 for M3 and M0 processors

-   */

-  static __INLINE q31_t __QSUB8(

-  q31_t x,

-  q31_t y)

-  {

-

-    q31_t sum;

-    q31_t r, s, t, u;

-

-    r = (q7_t) x;

-    s = (q7_t) y;

-

-    r = __SSAT((r - s), 8);

-    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;

-    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;

-    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;

-

-    sum =

-      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &

-                                                                0x000000FF);

-

-    return sum;

-  }

-

-  /*

-   * @brief C custom defined QADD16 for M3 and M0 processors

-   */

-

-  /*

-   * @brief C custom defined QADD16 for M3 and M0 processors

-   */

-  static __INLINE q31_t __QADD16(

-  q31_t x,

-  q31_t y)

-  {

-

-    q31_t sum;

-    q31_t r, s;

-

-    r = (q15_t) x;

-    s = (q15_t) y;

-

-    r = __SSAT(r + s, 16);

-    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;

-

-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);

-

-    return sum;

-

-  }

-

-  /*

-   * @brief C custom defined SHADD16 for M3 and M0 processors

-   */

-  static __INLINE q31_t __SHADD16(

-  q31_t x,

-  q31_t y)

-  {

-

-    q31_t sum;

-    q31_t r, s;

-

-    r = (q15_t) x;

-    s = (q15_t) y;

-

-    r = ((r >> 1) + (s >> 1));

-    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;

-

-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);

-

-    return sum;

-

-  }

-

-  /*

-   * @brief C custom defined QSUB16 for M3 and M0 processors

-   */

-  static __INLINE q31_t __QSUB16(

-  q31_t x,

-  q31_t y)

-  {

-

-    q31_t sum;

-    q31_t r, s;

-

-    r = (q15_t) x;

-    s = (q15_t) y;

-

-    r = __SSAT(r - s, 16);

-    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;

-

-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);

-

-    return sum;

-  }

-

-  /*

-   * @brief C custom defined SHSUB16 for M3 and M0 processors

-   */

-  static __INLINE q31_t __SHSUB16(

-  q31_t x,

-  q31_t y)

-  {

-

-    q31_t diff;

-    q31_t r, s;

-

-    r = (q15_t) x;

-    s = (q15_t) y;

-

-    r = ((r >> 1) - (s >> 1));

-    s = (((x >> 17) - (y >> 17)) << 16);

-

-    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);

-

-    return diff;

-  }

-

-  /*

-   * @brief C custom defined QASX for M3 and M0 processors

-   */

-  static __INLINE q31_t __QASX(

-  q31_t x,

-  q31_t y)

-  {

-

-    q31_t sum = 0;

-

-    sum =

-      ((sum +

-        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) +

-      clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16)));

-

-    return sum;

-  }

-

-  /*

-   * @brief C custom defined SHASX for M3 and M0 processors

-   */

-  static __INLINE q31_t __SHASX(

-  q31_t x,

-  q31_t y)

-  {

-

-    q31_t sum;

-    q31_t r, s;

-

-    r = (q15_t) x;

-    s = (q15_t) y;

-

-    r = ((r >> 1) - (y >> 17));

-    s = (((x >> 17) + (s >> 1)) << 16);

-

-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);

-

-    return sum;

-  }

-

-

-  /*

-   * @brief C custom defined QSAX for M3 and M0 processors

-   */

-  static __INLINE q31_t __QSAX(

-  q31_t x,

-  q31_t y)

-  {

-

-    q31_t sum = 0;

-

-    sum =

-      ((sum +

-        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) +

-      clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16)));

-

-    return sum;

-  }

-

-  /*

-   * @brief C custom defined SHSAX for M3 and M0 processors

-   */

-  static __INLINE q31_t __SHSAX(

-  q31_t x,

-  q31_t y)

-  {

-

-    q31_t sum;

-    q31_t r, s;

-

-    r = (q15_t) x;

-    s = (q15_t) y;

-

-    r = ((r >> 1) + (y >> 17));

-    s = (((x >> 17) - (s >> 1)) << 16);

-

-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);

-

-    return sum;

-  }

-

-  /*

-   * @brief C custom defined SMUSDX for M3 and M0 processors

-   */

-  static __INLINE q31_t __SMUSDX(

-  q31_t x,

-  q31_t y)

-  {

-

-    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) -

-                     ((q15_t) (x >> 16) * (q15_t) y)));

-  }

-

-  /*

-   * @brief C custom defined SMUADX for M3 and M0 processors

-   */

-  static __INLINE q31_t __SMUADX(

-  q31_t x,

-  q31_t y)

-  {

-

-    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) +

-                     ((q15_t) (x >> 16) * (q15_t) y)));

-  }

-

-  /*

-   * @brief C custom defined QADD for M3 and M0 processors

-   */

-  static __INLINE q31_t __QADD(

-  q31_t x,

-  q31_t y)

-  {

-    return clip_q63_to_q31((q63_t) x + y);

-  }

-

-  /*

-   * @brief C custom defined QSUB for M3 and M0 processors

-   */

-  static __INLINE q31_t __QSUB(

-  q31_t x,

-  q31_t y)

-  {

-    return clip_q63_to_q31((q63_t) x - y);

-  }

-

-  /*

-   * @brief C custom defined SMLAD for M3 and M0 processors

-   */

-  static __INLINE q31_t __SMLAD(

-  q31_t x,

-  q31_t y,

-  q31_t sum)

-  {

-

-    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +

-            ((q15_t) x * (q15_t) y));

-  }

-

-  /*

-   * @brief C custom defined SMLADX for M3 and M0 processors

-   */

-  static __INLINE q31_t __SMLADX(

-  q31_t x,

-  q31_t y,

-  q31_t sum)

-  {

-

-    return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) +

-            ((q15_t) x * (q15_t) (y >> 16)));

-  }

-

-  /*

-   * @brief C custom defined SMLSDX for M3 and M0 processors

-   */

-  static __INLINE q31_t __SMLSDX(

-  q31_t x,

-  q31_t y,

-  q31_t sum)

-  {

-

-    return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) +

-            ((q15_t) x * (q15_t) (y >> 16)));

-  }

-

-  /*

-   * @brief C custom defined SMLALD for M3 and M0 processors

-   */

-  static __INLINE q63_t __SMLALD(

-  q31_t x,

-  q31_t y,

-  q63_t sum)

-  {

-

-    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +

-            ((q15_t) x * (q15_t) y));

-  }

-

-  /*

-   * @brief C custom defined SMLALDX for M3 and M0 processors

-   */

-  static __INLINE q63_t __SMLALDX(

-  q31_t x,

-  q31_t y,

-  q63_t sum)

-  {

-

-    return (sum + ((q15_t) (x >> 16) * (q15_t) y)) +

-      ((q15_t) x * (q15_t) (y >> 16));

-  }

-

-  /*

-   * @brief C custom defined SMUAD for M3 and M0 processors

-   */

-  static __INLINE q31_t __SMUAD(

-  q31_t x,

-  q31_t y)

-  {

-

-    return (((x >> 16) * (y >> 16)) +

-            (((x << 16) >> 16) * ((y << 16) >> 16)));

-  }

-

-  /*

-   * @brief C custom defined SMUSD for M3 and M0 processors

-   */

-  static __INLINE q31_t __SMUSD(

-  q31_t x,

-  q31_t y)

-  {

-

-    return (-((x >> 16) * (y >> 16)) +

-            (((x << 16) >> 16) * ((y << 16) >> 16)));

-  }

-

-

-  /*

-   * @brief C custom defined SXTB16 for M3 and M0 processors

-   */

-  static __INLINE q31_t __SXTB16(

-  q31_t x)

-  {

-

-    return ((((x << 24) >> 24) & 0x0000FFFF) |

-            (((x << 8) >> 8) & 0xFFFF0000));

-  }

-

-

-#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */

-

-

-  /**

-   * @brief Instance structure for the Q7 FIR filter.

-   */

-  typedef struct

-  {

-    uint16_t numTaps;        /**< number of filter coefficients in the filter. */

-    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */

-    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/

-  } arm_fir_instance_q7;

-

-  /**

-   * @brief Instance structure for the Q15 FIR filter.

-   */

-  typedef struct

-  {

-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */

-    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */

-    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/

-  } arm_fir_instance_q15;

-

-  /**

-   * @brief Instance structure for the Q31 FIR filter.

-   */

-  typedef struct

-  {

-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */

-    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */

-    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */

-  } arm_fir_instance_q31;

-

-  /**

-   * @brief Instance structure for the floating-point FIR filter.

-   */

-  typedef struct

-  {

-    uint16_t numTaps;     /**< number of filter coefficients in the filter. */

-    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */

-    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */

-  } arm_fir_instance_f32;

-

-

-  /**

-   * @brief Processing function for the Q7 FIR filter.

-   * @param[in] *S points to an instance of the Q7 FIR filter structure.

-   * @param[in] *pSrc points to the block of input data.

-   * @param[out] *pDst points to the block of output data.

-   * @param[in] blockSize number of samples to process.

-   * @return none.

-   */

-  void arm_fir_q7(

-  const arm_fir_instance_q7 * S,

-  q7_t * pSrc,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Initialization function for the Q7 FIR filter.

-   * @param[in,out] *S points to an instance of the Q7 FIR structure.

-   * @param[in] numTaps  Number of filter coefficients in the filter.

-   * @param[in] *pCoeffs points to the filter coefficients.

-   * @param[in] *pState points to the state buffer.

-   * @param[in] blockSize number of samples that are processed.

-   * @return none

-   */

-  void arm_fir_init_q7(

-  arm_fir_instance_q7 * S,

-  uint16_t numTaps,

-  q7_t * pCoeffs,

-  q7_t * pState,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Processing function for the Q15 FIR filter.

-   * @param[in] *S points to an instance of the Q15 FIR structure.

-   * @param[in] *pSrc points to the block of input data.

-   * @param[out] *pDst points to the block of output data.

-   * @param[in] blockSize number of samples to process.

-   * @return none.

-   */

-  void arm_fir_q15(

-  const arm_fir_instance_q15 * S,

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.

-   * @param[in] *S points to an instance of the Q15 FIR filter structure.

-   * @param[in] *pSrc points to the block of input data.

-   * @param[out] *pDst points to the block of output data.

-   * @param[in] blockSize number of samples to process.

-   * @return none.

-   */

-  void arm_fir_fast_q15(

-  const arm_fir_instance_q15 * S,

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Initialization function for the Q15 FIR filter.

-   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.

-   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.

-   * @param[in] *pCoeffs points to the filter coefficients.

-   * @param[in] *pState points to the state buffer.

-   * @param[in] blockSize number of samples that are processed at a time.

-   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if

-   * <code>numTaps</code> is not a supported value.

-   */

-

-  arm_status arm_fir_init_q15(

-  arm_fir_instance_q15 * S,

-  uint16_t numTaps,

-  q15_t * pCoeffs,

-  q15_t * pState,

-  uint32_t blockSize);

-

-  /**

-   * @brief Processing function for the Q31 FIR filter.

-   * @param[in] *S points to an instance of the Q31 FIR filter structure.

-   * @param[in] *pSrc points to the block of input data.

-   * @param[out] *pDst points to the block of output data.

-   * @param[in] blockSize number of samples to process.

-   * @return none.

-   */

-  void arm_fir_q31(

-  const arm_fir_instance_q31 * S,

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.

-   * @param[in] *S points to an instance of the Q31 FIR structure.

-   * @param[in] *pSrc points to the block of input data.

-   * @param[out] *pDst points to the block of output data.

-   * @param[in] blockSize number of samples to process.

-   * @return none.

-   */

-  void arm_fir_fast_q31(

-  const arm_fir_instance_q31 * S,

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Initialization function for the Q31 FIR filter.

-   * @param[in,out] *S points to an instance of the Q31 FIR structure.

-   * @param[in]     numTaps  Number of filter coefficients in the filter.

-   * @param[in]     *pCoeffs points to the filter coefficients.

-   * @param[in]     *pState points to the state buffer.

-   * @param[in]     blockSize number of samples that are processed at a time.

-   * @return        none.

-   */

-  void arm_fir_init_q31(

-  arm_fir_instance_q31 * S,

-  uint16_t numTaps,

-  q31_t * pCoeffs,

-  q31_t * pState,

-  uint32_t blockSize);

-

-  /**

-   * @brief Processing function for the floating-point FIR filter.

-   * @param[in] *S points to an instance of the floating-point FIR structure.

-   * @param[in] *pSrc points to the block of input data.

-   * @param[out] *pDst points to the block of output data.

-   * @param[in] blockSize number of samples to process.

-   * @return none.

-   */

-  void arm_fir_f32(

-  const arm_fir_instance_f32 * S,

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Initialization function for the floating-point FIR filter.

-   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.

-   * @param[in]     numTaps  Number of filter coefficients in the filter.

-   * @param[in]     *pCoeffs points to the filter coefficients.

-   * @param[in]     *pState points to the state buffer.

-   * @param[in]     blockSize number of samples that are processed at a time.

-   * @return        none.

-   */

-  void arm_fir_init_f32(

-  arm_fir_instance_f32 * S,

-  uint16_t numTaps,

-  float32_t * pCoeffs,

-  float32_t * pState,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Instance structure for the Q15 Biquad cascade filter.

-   */

-  typedef struct

-  {

-    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */

-    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */

-    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */

-    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */

-

-  } arm_biquad_casd_df1_inst_q15;

-

-

-  /**

-   * @brief Instance structure for the Q31 Biquad cascade filter.

-   */

-  typedef struct

-  {

-    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */

-    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */

-    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */

-    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */

-

-  } arm_biquad_casd_df1_inst_q31;

-

-  /**

-   * @brief Instance structure for the floating-point Biquad cascade filter.

-   */

-  typedef struct

-  {

-    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */

-    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */

-    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */

-

-

-  } arm_biquad_casd_df1_inst_f32;

-

-

-

-  /**

-   * @brief Processing function for the Q15 Biquad cascade filter.

-   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.

-   * @param[in]  *pSrc points to the block of input data.

-   * @param[out] *pDst points to the block of output data.

-   * @param[in]  blockSize number of samples to process.

-   * @return     none.

-   */

-

-  void arm_biquad_cascade_df1_q15(

-  const arm_biquad_casd_df1_inst_q15 * S,

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Initialization function for the Q15 Biquad cascade filter.

-   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.

-   * @param[in]     numStages    number of 2nd order stages in the filter.

-   * @param[in]     *pCoeffs     points to the filter coefficients.

-   * @param[in]     *pState      points to the state buffer.

-   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format

-   * @return        none

-   */

-

-  void arm_biquad_cascade_df1_init_q15(

-  arm_biquad_casd_df1_inst_q15 * S,

-  uint8_t numStages,

-  q15_t * pCoeffs,

-  q15_t * pState,

-  int8_t postShift);

-

-

-  /**

-   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.

-   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.

-   * @param[in]  *pSrc points to the block of input data.

-   * @param[out] *pDst points to the block of output data.

-   * @param[in]  blockSize number of samples to process.

-   * @return     none.

-   */

-

-  void arm_biquad_cascade_df1_fast_q15(

-  const arm_biquad_casd_df1_inst_q15 * S,

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Processing function for the Q31 Biquad cascade filter

-   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.

-   * @param[in]  *pSrc      points to the block of input data.

-   * @param[out] *pDst      points to the block of output data.

-   * @param[in]  blockSize  number of samples to process.

-   * @return     none.

-   */

-

-  void arm_biquad_cascade_df1_q31(

-  const arm_biquad_casd_df1_inst_q31 * S,

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.

-   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.

-   * @param[in]  *pSrc      points to the block of input data.

-   * @param[out] *pDst      points to the block of output data.

-   * @param[in]  blockSize  number of samples to process.

-   * @return     none.

-   */

-

-  void arm_biquad_cascade_df1_fast_q31(

-  const arm_biquad_casd_df1_inst_q31 * S,

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Initialization function for the Q31 Biquad cascade filter.

-   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.

-   * @param[in]     numStages      number of 2nd order stages in the filter.

-   * @param[in]     *pCoeffs     points to the filter coefficients.

-   * @param[in]     *pState      points to the state buffer.

-   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format

-   * @return        none

-   */

-

-  void arm_biquad_cascade_df1_init_q31(

-  arm_biquad_casd_df1_inst_q31 * S,

-  uint8_t numStages,

-  q31_t * pCoeffs,

-  q31_t * pState,

-  int8_t postShift);

-

-  /**

-   * @brief Processing function for the floating-point Biquad cascade filter.

-   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.

-   * @param[in]  *pSrc      points to the block of input data.

-   * @param[out] *pDst      points to the block of output data.

-   * @param[in]  blockSize  number of samples to process.

-   * @return     none.

-   */

-

-  void arm_biquad_cascade_df1_f32(

-  const arm_biquad_casd_df1_inst_f32 * S,

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Initialization function for the floating-point Biquad cascade filter.

-   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.

-   * @param[in]     numStages    number of 2nd order stages in the filter.

-   * @param[in]     *pCoeffs     points to the filter coefficients.

-   * @param[in]     *pState      points to the state buffer.

-   * @return        none

-   */

-

-  void arm_biquad_cascade_df1_init_f32(

-  arm_biquad_casd_df1_inst_f32 * S,

-  uint8_t numStages,

-  float32_t * pCoeffs,

-  float32_t * pState);

-

-

-  /**

-   * @brief Instance structure for the floating-point matrix structure.

-   */

-

-  typedef struct

-  {

-    uint16_t numRows;     /**< number of rows of the matrix.     */

-    uint16_t numCols;     /**< number of columns of the matrix.  */

-    float32_t *pData;     /**< points to the data of the matrix. */

-  } arm_matrix_instance_f32;

-

-

-  /**

-   * @brief Instance structure for the floating-point matrix structure.

-   */

-

-  typedef struct

-  {

-    uint16_t numRows;     /**< number of rows of the matrix.     */

-    uint16_t numCols;     /**< number of columns of the matrix.  */

-    float64_t *pData;     /**< points to the data of the matrix. */

-  } arm_matrix_instance_f64;

-

-  /**

-   * @brief Instance structure for the Q15 matrix structure.

-   */

-

-  typedef struct

-  {

-    uint16_t numRows;     /**< number of rows of the matrix.     */

-    uint16_t numCols;     /**< number of columns of the matrix.  */

-    q15_t *pData;         /**< points to the data of the matrix. */

-

-  } arm_matrix_instance_q15;

-

-  /**

-   * @brief Instance structure for the Q31 matrix structure.

-   */

-

-  typedef struct

-  {

-    uint16_t numRows;     /**< number of rows of the matrix.     */

-    uint16_t numCols;     /**< number of columns of the matrix.  */

-    q31_t *pData;         /**< points to the data of the matrix. */

-

-  } arm_matrix_instance_q31;

-

-

-

-  /**

-   * @brief Floating-point matrix addition.

-   * @param[in]       *pSrcA points to the first input matrix structure

-   * @param[in]       *pSrcB points to the second input matrix structure

-   * @param[out]      *pDst points to output matrix structure

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-

-  arm_status arm_mat_add_f32(

-  const arm_matrix_instance_f32 * pSrcA,

-  const arm_matrix_instance_f32 * pSrcB,

-  arm_matrix_instance_f32 * pDst);

-

-  /**

-   * @brief Q15 matrix addition.

-   * @param[in]       *pSrcA points to the first input matrix structure

-   * @param[in]       *pSrcB points to the second input matrix structure

-   * @param[out]      *pDst points to output matrix structure

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-

-  arm_status arm_mat_add_q15(

-  const arm_matrix_instance_q15 * pSrcA,

-  const arm_matrix_instance_q15 * pSrcB,

-  arm_matrix_instance_q15 * pDst);

-

-  /**

-   * @brief Q31 matrix addition.

-   * @param[in]       *pSrcA points to the first input matrix structure

-   * @param[in]       *pSrcB points to the second input matrix structure

-   * @param[out]      *pDst points to output matrix structure

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-

-  arm_status arm_mat_add_q31(

-  const arm_matrix_instance_q31 * pSrcA,

-  const arm_matrix_instance_q31 * pSrcB,

-  arm_matrix_instance_q31 * pDst);

-

-  /**

-   * @brief Floating-point, complex, matrix multiplication.

-   * @param[in]       *pSrcA points to the first input matrix structure

-   * @param[in]       *pSrcB points to the second input matrix structure

-   * @param[out]      *pDst points to output matrix structure

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-

-  arm_status arm_mat_cmplx_mult_f32(

-  const arm_matrix_instance_f32 * pSrcA,

-  const arm_matrix_instance_f32 * pSrcB,

-  arm_matrix_instance_f32 * pDst);

-

-  /**

-   * @brief Q15, complex,  matrix multiplication.

-   * @param[in]       *pSrcA points to the first input matrix structure

-   * @param[in]       *pSrcB points to the second input matrix structure

-   * @param[out]      *pDst points to output matrix structure

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-

-  arm_status arm_mat_cmplx_mult_q15(

-  const arm_matrix_instance_q15 * pSrcA,

-  const arm_matrix_instance_q15 * pSrcB,

-  arm_matrix_instance_q15 * pDst,

-  q15_t * pScratch);

-

-  /**

-   * @brief Q31, complex, matrix multiplication.

-   * @param[in]       *pSrcA points to the first input matrix structure

-   * @param[in]       *pSrcB points to the second input matrix structure

-   * @param[out]      *pDst points to output matrix structure

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-

-  arm_status arm_mat_cmplx_mult_q31(

-  const arm_matrix_instance_q31 * pSrcA,

-  const arm_matrix_instance_q31 * pSrcB,

-  arm_matrix_instance_q31 * pDst);

-

-

-  /**

-   * @brief Floating-point matrix transpose.

-   * @param[in]  *pSrc points to the input matrix

-   * @param[out] *pDst points to the output matrix

-   * @return     The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>

-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-

-  arm_status arm_mat_trans_f32(

-  const arm_matrix_instance_f32 * pSrc,

-  arm_matrix_instance_f32 * pDst);

-

-

-  /**

-   * @brief Q15 matrix transpose.

-   * @param[in]  *pSrc points to the input matrix

-   * @param[out] *pDst points to the output matrix

-   * @return     The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>

-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-

-  arm_status arm_mat_trans_q15(

-  const arm_matrix_instance_q15 * pSrc,

-  arm_matrix_instance_q15 * pDst);

-

-  /**

-   * @brief Q31 matrix transpose.

-   * @param[in]  *pSrc points to the input matrix

-   * @param[out] *pDst points to the output matrix

-   * @return     The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>

-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-

-  arm_status arm_mat_trans_q31(

-  const arm_matrix_instance_q31 * pSrc,

-  arm_matrix_instance_q31 * pDst);

-

-

-  /**

-   * @brief Floating-point matrix multiplication

-   * @param[in]       *pSrcA points to the first input matrix structure

-   * @param[in]       *pSrcB points to the second input matrix structure

-   * @param[out]      *pDst points to output matrix structure

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-

-  arm_status arm_mat_mult_f32(

-  const arm_matrix_instance_f32 * pSrcA,

-  const arm_matrix_instance_f32 * pSrcB,

-  arm_matrix_instance_f32 * pDst);

-

-  /**

-   * @brief Q15 matrix multiplication

-   * @param[in]       *pSrcA points to the first input matrix structure

-   * @param[in]       *pSrcB points to the second input matrix structure

-   * @param[out]      *pDst points to output matrix structure

-   * @param[in]       *pState points to the array for storing intermediate results

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-

-  arm_status arm_mat_mult_q15(

-  const arm_matrix_instance_q15 * pSrcA,

-  const arm_matrix_instance_q15 * pSrcB,

-  arm_matrix_instance_q15 * pDst,

-  q15_t * pState);

-

-  /**

-   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4

-   * @param[in]       *pSrcA  points to the first input matrix structure

-   * @param[in]       *pSrcB  points to the second input matrix structure

-   * @param[out]      *pDst   points to output matrix structure

-   * @param[in]       *pState points to the array for storing intermediate results

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-

-  arm_status arm_mat_mult_fast_q15(

-  const arm_matrix_instance_q15 * pSrcA,

-  const arm_matrix_instance_q15 * pSrcB,

-  arm_matrix_instance_q15 * pDst,

-  q15_t * pState);

-

-  /**

-   * @brief Q31 matrix multiplication

-   * @param[in]       *pSrcA points to the first input matrix structure

-   * @param[in]       *pSrcB points to the second input matrix structure

-   * @param[out]      *pDst points to output matrix structure

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-

-  arm_status arm_mat_mult_q31(

-  const arm_matrix_instance_q31 * pSrcA,

-  const arm_matrix_instance_q31 * pSrcB,

-  arm_matrix_instance_q31 * pDst);

-

-  /**

-   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4

-   * @param[in]       *pSrcA points to the first input matrix structure

-   * @param[in]       *pSrcB points to the second input matrix structure

-   * @param[out]      *pDst points to output matrix structure

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-

-  arm_status arm_mat_mult_fast_q31(

-  const arm_matrix_instance_q31 * pSrcA,

-  const arm_matrix_instance_q31 * pSrcB,

-  arm_matrix_instance_q31 * pDst);

-

-

-  /**

-   * @brief Floating-point matrix subtraction

-   * @param[in]       *pSrcA points to the first input matrix structure

-   * @param[in]       *pSrcB points to the second input matrix structure

-   * @param[out]      *pDst points to output matrix structure

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-

-  arm_status arm_mat_sub_f32(

-  const arm_matrix_instance_f32 * pSrcA,

-  const arm_matrix_instance_f32 * pSrcB,

-  arm_matrix_instance_f32 * pDst);

-

-  /**

-   * @brief Q15 matrix subtraction

-   * @param[in]       *pSrcA points to the first input matrix structure

-   * @param[in]       *pSrcB points to the second input matrix structure

-   * @param[out]      *pDst points to output matrix structure

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-

-  arm_status arm_mat_sub_q15(

-  const arm_matrix_instance_q15 * pSrcA,

-  const arm_matrix_instance_q15 * pSrcB,

-  arm_matrix_instance_q15 * pDst);

-

-  /**

-   * @brief Q31 matrix subtraction

-   * @param[in]       *pSrcA points to the first input matrix structure

-   * @param[in]       *pSrcB points to the second input matrix structure

-   * @param[out]      *pDst points to output matrix structure

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-

-  arm_status arm_mat_sub_q31(

-  const arm_matrix_instance_q31 * pSrcA,

-  const arm_matrix_instance_q31 * pSrcB,

-  arm_matrix_instance_q31 * pDst);

-

-  /**

-   * @brief Floating-point matrix scaling.

-   * @param[in]  *pSrc points to the input matrix

-   * @param[in]  scale scale factor

-   * @param[out] *pDst points to the output matrix

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-

-  arm_status arm_mat_scale_f32(

-  const arm_matrix_instance_f32 * pSrc,

-  float32_t scale,

-  arm_matrix_instance_f32 * pDst);

-

-  /**

-   * @brief Q15 matrix scaling.

-   * @param[in]       *pSrc points to input matrix

-   * @param[in]       scaleFract fractional portion of the scale factor

-   * @param[in]       shift number of bits to shift the result by

-   * @param[out]      *pDst points to output matrix

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-

-  arm_status arm_mat_scale_q15(

-  const arm_matrix_instance_q15 * pSrc,

-  q15_t scaleFract,

-  int32_t shift,

-  arm_matrix_instance_q15 * pDst);

-

-  /**

-   * @brief Q31 matrix scaling.

-   * @param[in]       *pSrc points to input matrix

-   * @param[in]       scaleFract fractional portion of the scale factor

-   * @param[in]       shift number of bits to shift the result by

-   * @param[out]      *pDst points to output matrix structure

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-

-  arm_status arm_mat_scale_q31(

-  const arm_matrix_instance_q31 * pSrc,

-  q31_t scaleFract,

-  int32_t shift,

-  arm_matrix_instance_q31 * pDst);

-

-

-  /**

-   * @brief  Q31 matrix initialization.

-   * @param[in,out] *S             points to an instance of the floating-point matrix structure.

-   * @param[in]     nRows          number of rows in the matrix.

-   * @param[in]     nColumns       number of columns in the matrix.

-   * @param[in]     *pData         points to the matrix data array.

-   * @return        none

-   */

-

-  void arm_mat_init_q31(

-  arm_matrix_instance_q31 * S,

-  uint16_t nRows,

-  uint16_t nColumns,

-  q31_t * pData);

-

-  /**

-   * @brief  Q15 matrix initialization.

-   * @param[in,out] *S             points to an instance of the floating-point matrix structure.

-   * @param[in]     nRows          number of rows in the matrix.

-   * @param[in]     nColumns       number of columns in the matrix.

-   * @param[in]     *pData         points to the matrix data array.

-   * @return        none

-   */

-

-  void arm_mat_init_q15(

-  arm_matrix_instance_q15 * S,

-  uint16_t nRows,

-  uint16_t nColumns,

-  q15_t * pData);

-

-  /**

-   * @brief  Floating-point matrix initialization.

-   * @param[in,out] *S             points to an instance of the floating-point matrix structure.

-   * @param[in]     nRows          number of rows in the matrix.

-   * @param[in]     nColumns       number of columns in the matrix.

-   * @param[in]     *pData         points to the matrix data array.

-   * @return        none

-   */

-

-  void arm_mat_init_f32(

-  arm_matrix_instance_f32 * S,

-  uint16_t nRows,

-  uint16_t nColumns,

-  float32_t * pData);

-

-

-

-  /**

-   * @brief Instance structure for the Q15 PID Control.

-   */

-  typedef struct

-  {

-    q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */

-#ifdef ARM_MATH_CM0_FAMILY

-    q15_t A1;

-    q15_t A2;

-#else

-    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/

-#endif

-    q15_t state[3];       /**< The state array of length 3. */

-    q15_t Kp;           /**< The proportional gain. */

-    q15_t Ki;           /**< The integral gain. */

-    q15_t Kd;           /**< The derivative gain. */

-  } arm_pid_instance_q15;

-

-  /**

-   * @brief Instance structure for the Q31 PID Control.

-   */

-  typedef struct

-  {

-    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */

-    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */

-    q31_t A2;            /**< The derived gain, A2 = Kd . */

-    q31_t state[3];      /**< The state array of length 3. */

-    q31_t Kp;            /**< The proportional gain. */

-    q31_t Ki;            /**< The integral gain. */

-    q31_t Kd;            /**< The derivative gain. */

-

-  } arm_pid_instance_q31;

-

-  /**

-   * @brief Instance structure for the floating-point PID Control.

-   */

-  typedef struct

-  {

-    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */

-    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */

-    float32_t A2;          /**< The derived gain, A2 = Kd . */

-    float32_t state[3];    /**< The state array of length 3. */

-    float32_t Kp;               /**< The proportional gain. */

-    float32_t Ki;               /**< The integral gain. */

-    float32_t Kd;               /**< The derivative gain. */

-  } arm_pid_instance_f32;

-

-

-

-  /**

-   * @brief  Initialization function for the floating-point PID Control.

-   * @param[in,out] *S      points to an instance of the PID structure.

-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.

-   * @return none.

-   */

-  void arm_pid_init_f32(

-  arm_pid_instance_f32 * S,

-  int32_t resetStateFlag);

-

-  /**

-   * @brief  Reset function for the floating-point PID Control.

-   * @param[in,out] *S is an instance of the floating-point PID Control structure

-   * @return none

-   */

-  void arm_pid_reset_f32(

-  arm_pid_instance_f32 * S);

-

-

-  /**

-   * @brief  Initialization function for the Q31 PID Control.

-   * @param[in,out] *S points to an instance of the Q15 PID structure.

-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.

-   * @return none.

-   */

-  void arm_pid_init_q31(

-  arm_pid_instance_q31 * S,

-  int32_t resetStateFlag);

-

-

-  /**

-   * @brief  Reset function for the Q31 PID Control.

-   * @param[in,out] *S points to an instance of the Q31 PID Control structure

-   * @return none

-   */

-

-  void arm_pid_reset_q31(

-  arm_pid_instance_q31 * S);

-

-  /**

-   * @brief  Initialization function for the Q15 PID Control.

-   * @param[in,out] *S points to an instance of the Q15 PID structure.

-   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.

-   * @return none.

-   */

-  void arm_pid_init_q15(

-  arm_pid_instance_q15 * S,

-  int32_t resetStateFlag);

-

-  /**

-   * @brief  Reset function for the Q15 PID Control.

-   * @param[in,out] *S points to an instance of the q15 PID Control structure

-   * @return none

-   */

-  void arm_pid_reset_q15(

-  arm_pid_instance_q15 * S);

-

-

-  /**

-   * @brief Instance structure for the floating-point Linear Interpolate function.

-   */

-  typedef struct

-  {

-    uint32_t nValues;           /**< nValues */

-    float32_t x1;               /**< x1 */

-    float32_t xSpacing;         /**< xSpacing */

-    float32_t *pYData;          /**< pointer to the table of Y values */

-  } arm_linear_interp_instance_f32;

-

-  /**

-   * @brief Instance structure for the floating-point bilinear interpolation function.

-   */

-

-  typedef struct

-  {

-    uint16_t numRows;   /**< number of rows in the data table. */

-    uint16_t numCols;   /**< number of columns in the data table. */

-    float32_t *pData;   /**< points to the data table. */

-  } arm_bilinear_interp_instance_f32;

-

-   /**

-   * @brief Instance structure for the Q31 bilinear interpolation function.

-   */

-

-  typedef struct

-  {

-    uint16_t numRows;   /**< number of rows in the data table. */

-    uint16_t numCols;   /**< number of columns in the data table. */

-    q31_t *pData;       /**< points to the data table. */

-  } arm_bilinear_interp_instance_q31;

-

-   /**

-   * @brief Instance structure for the Q15 bilinear interpolation function.

-   */

-

-  typedef struct

-  {

-    uint16_t numRows;   /**< number of rows in the data table. */

-    uint16_t numCols;   /**< number of columns in the data table. */

-    q15_t *pData;       /**< points to the data table. */

-  } arm_bilinear_interp_instance_q15;

-

-   /**

-   * @brief Instance structure for the Q15 bilinear interpolation function.

-   */

-

-  typedef struct

-  {

-    uint16_t numRows;   /**< number of rows in the data table. */

-    uint16_t numCols;   /**< number of columns in the data table. */

-    q7_t *pData;                /**< points to the data table. */

-  } arm_bilinear_interp_instance_q7;

-

-

-  /**

-   * @brief Q7 vector multiplication.

-   * @param[in]       *pSrcA points to the first input vector

-   * @param[in]       *pSrcB points to the second input vector

-   * @param[out]      *pDst  points to the output vector

-   * @param[in]       blockSize number of samples in each vector

-   * @return none.

-   */

-

-  void arm_mult_q7(

-  q7_t * pSrcA,

-  q7_t * pSrcB,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Q15 vector multiplication.

-   * @param[in]       *pSrcA points to the first input vector

-   * @param[in]       *pSrcB points to the second input vector

-   * @param[out]      *pDst  points to the output vector

-   * @param[in]       blockSize number of samples in each vector

-   * @return none.

-   */

-

-  void arm_mult_q15(

-  q15_t * pSrcA,

-  q15_t * pSrcB,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Q31 vector multiplication.

-   * @param[in]       *pSrcA points to the first input vector

-   * @param[in]       *pSrcB points to the second input vector

-   * @param[out]      *pDst points to the output vector

-   * @param[in]       blockSize number of samples in each vector

-   * @return none.

-   */

-

-  void arm_mult_q31(

-  q31_t * pSrcA,

-  q31_t * pSrcB,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Floating-point vector multiplication.

-   * @param[in]       *pSrcA points to the first input vector

-   * @param[in]       *pSrcB points to the second input vector

-   * @param[out]      *pDst points to the output vector

-   * @param[in]       blockSize number of samples in each vector

-   * @return none.

-   */

-

-  void arm_mult_f32(

-  float32_t * pSrcA,

-  float32_t * pSrcB,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-

-

-

-

-

-  /**

-   * @brief Instance structure for the Q15 CFFT/CIFFT function.

-   */

-

-  typedef struct

-  {

-    uint16_t fftLen;                 /**< length of the FFT. */

-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */

-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */

-    q15_t *pTwiddle;                     /**< points to the Sin twiddle factor table. */

-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */

-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */

-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */

-  } arm_cfft_radix2_instance_q15;

-

-/* Deprecated */

-  arm_status arm_cfft_radix2_init_q15(

-  arm_cfft_radix2_instance_q15 * S,

-  uint16_t fftLen,

-  uint8_t ifftFlag,

-  uint8_t bitReverseFlag);

-

-/* Deprecated */

-  void arm_cfft_radix2_q15(

-  const arm_cfft_radix2_instance_q15 * S,

-  q15_t * pSrc);

-

-

-

-  /**

-   * @brief Instance structure for the Q15 CFFT/CIFFT function.

-   */

-

-  typedef struct

-  {

-    uint16_t fftLen;                 /**< length of the FFT. */

-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */

-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */

-    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */

-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */

-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */

-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */

-  } arm_cfft_radix4_instance_q15;

-

-/* Deprecated */

-  arm_status arm_cfft_radix4_init_q15(

-  arm_cfft_radix4_instance_q15 * S,

-  uint16_t fftLen,

-  uint8_t ifftFlag,

-  uint8_t bitReverseFlag);

-

-/* Deprecated */

-  void arm_cfft_radix4_q15(

-  const arm_cfft_radix4_instance_q15 * S,

-  q15_t * pSrc);

-

-  /**

-   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.

-   */

-

-  typedef struct

-  {

-    uint16_t fftLen;                 /**< length of the FFT. */

-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */

-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */

-    q31_t *pTwiddle;                     /**< points to the Twiddle factor table. */

-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */

-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */

-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */

-  } arm_cfft_radix2_instance_q31;

-

-/* Deprecated */

-  arm_status arm_cfft_radix2_init_q31(

-  arm_cfft_radix2_instance_q31 * S,

-  uint16_t fftLen,

-  uint8_t ifftFlag,

-  uint8_t bitReverseFlag);

-

-/* Deprecated */

-  void arm_cfft_radix2_q31(

-  const arm_cfft_radix2_instance_q31 * S,

-  q31_t * pSrc);

-

-  /**

-   * @brief Instance structure for the Q31 CFFT/CIFFT function.

-   */

-

-  typedef struct

-  {

-    uint16_t fftLen;                 /**< length of the FFT. */

-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */

-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */

-    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */

-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */

-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */

-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */

-  } arm_cfft_radix4_instance_q31;

-

-/* Deprecated */

-  void arm_cfft_radix4_q31(

-  const arm_cfft_radix4_instance_q31 * S,

-  q31_t * pSrc);

-

-/* Deprecated */

-  arm_status arm_cfft_radix4_init_q31(

-  arm_cfft_radix4_instance_q31 * S,

-  uint16_t fftLen,

-  uint8_t ifftFlag,

-  uint8_t bitReverseFlag);

-

-  /**

-   * @brief Instance structure for the floating-point CFFT/CIFFT function.

-   */

-

-  typedef struct

-  {

-    uint16_t fftLen;                   /**< length of the FFT. */

-    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */

-    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */

-    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */

-    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */

-    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */

-    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */

-    float32_t onebyfftLen;                 /**< value of 1/fftLen. */

-  } arm_cfft_radix2_instance_f32;

-

-/* Deprecated */

-  arm_status arm_cfft_radix2_init_f32(

-  arm_cfft_radix2_instance_f32 * S,

-  uint16_t fftLen,

-  uint8_t ifftFlag,

-  uint8_t bitReverseFlag);

-

-/* Deprecated */

-  void arm_cfft_radix2_f32(

-  const arm_cfft_radix2_instance_f32 * S,

-  float32_t * pSrc);

-

-  /**

-   * @brief Instance structure for the floating-point CFFT/CIFFT function.

-   */

-

-  typedef struct

-  {

-    uint16_t fftLen;                   /**< length of the FFT. */

-    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */

-    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */

-    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */

-    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */

-    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */

-    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */

-    float32_t onebyfftLen;                 /**< value of 1/fftLen. */

-  } arm_cfft_radix4_instance_f32;

-

-/* Deprecated */

-  arm_status arm_cfft_radix4_init_f32(

-  arm_cfft_radix4_instance_f32 * S,

-  uint16_t fftLen,

-  uint8_t ifftFlag,

-  uint8_t bitReverseFlag);

-

-/* Deprecated */

-  void arm_cfft_radix4_f32(

-  const arm_cfft_radix4_instance_f32 * S,

-  float32_t * pSrc);

-

-  /**

-   * @brief Instance structure for the fixed-point CFFT/CIFFT function.

-   */

-

-  typedef struct

-  {

-    uint16_t fftLen;                   /**< length of the FFT. */

-    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */

-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */

-    uint16_t bitRevLength;             /**< bit reversal table length. */

-  } arm_cfft_instance_q15;

-

-  void arm_cfft_q15(

-  const arm_cfft_instance_q15 * S,

-  q15_t * p1,

-  uint8_t ifftFlag,

-  uint8_t bitReverseFlag);

-

-  /**

-   * @brief Instance structure for the fixed-point CFFT/CIFFT function.

-   */

-

-  typedef struct

-  {

-    uint16_t fftLen;                   /**< length of the FFT. */

-    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */

-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */

-    uint16_t bitRevLength;             /**< bit reversal table length. */

-  } arm_cfft_instance_q31;

-

-  void arm_cfft_q31(

-  const arm_cfft_instance_q31 * S,

-  q31_t * p1,

-  uint8_t ifftFlag,

-  uint8_t bitReverseFlag);

-

-  /**

-   * @brief Instance structure for the floating-point CFFT/CIFFT function.

-   */

-

-  typedef struct

-  {

-    uint16_t fftLen;                   /**< length of the FFT. */

-    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */

-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */

-    uint16_t bitRevLength;             /**< bit reversal table length. */

-  } arm_cfft_instance_f32;

-

-  void arm_cfft_f32(

-  const arm_cfft_instance_f32 * S,

-  float32_t * p1,

-  uint8_t ifftFlag,

-  uint8_t bitReverseFlag);

-

-  /**

-   * @brief Instance structure for the Q15 RFFT/RIFFT function.

-   */

-

-  typedef struct

-  {

-    uint32_t fftLenReal;                      /**< length of the real FFT. */

-    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */

-    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */

-    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */

-    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */

-    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */

-    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */

-  } arm_rfft_instance_q15;

-

-  arm_status arm_rfft_init_q15(

-  arm_rfft_instance_q15 * S,

-  uint32_t fftLenReal,

-  uint32_t ifftFlagR,

-  uint32_t bitReverseFlag);

-

-  void arm_rfft_q15(

-  const arm_rfft_instance_q15 * S,

-  q15_t * pSrc,

-  q15_t * pDst);

-

-  /**

-   * @brief Instance structure for the Q31 RFFT/RIFFT function.

-   */

-

-  typedef struct

-  {

-    uint32_t fftLenReal;                        /**< length of the real FFT. */

-    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */

-    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */

-    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */

-    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */

-    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */

-    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */

-  } arm_rfft_instance_q31;

-

-  arm_status arm_rfft_init_q31(

-  arm_rfft_instance_q31 * S,

-  uint32_t fftLenReal,

-  uint32_t ifftFlagR,

-  uint32_t bitReverseFlag);

-

-  void arm_rfft_q31(

-  const arm_rfft_instance_q31 * S,

-  q31_t * pSrc,

-  q31_t * pDst);

-

-  /**

-   * @brief Instance structure for the floating-point RFFT/RIFFT function.

-   */

-

-  typedef struct

-  {

-    uint32_t fftLenReal;                        /**< length of the real FFT. */

-    uint16_t fftLenBy2;                         /**< length of the complex FFT. */

-    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */

-    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */

-    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */

-    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */

-    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */

-    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */

-  } arm_rfft_instance_f32;

-

-  arm_status arm_rfft_init_f32(

-  arm_rfft_instance_f32 * S,

-  arm_cfft_radix4_instance_f32 * S_CFFT,

-  uint32_t fftLenReal,

-  uint32_t ifftFlagR,

-  uint32_t bitReverseFlag);

-

-  void arm_rfft_f32(

-  const arm_rfft_instance_f32 * S,

-  float32_t * pSrc,

-  float32_t * pDst);

-

-  /**

-   * @brief Instance structure for the floating-point RFFT/RIFFT function.

-   */

-

-  typedef struct

-  {

-    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */

-    uint16_t fftLenRFFT;                        /**< length of the real sequence */

-    float32_t * pTwiddleRFFT;                   /**< Twiddle factors real stage  */

-  } arm_rfft_fast_instance_f32 ;

-

-  arm_status arm_rfft_fast_init_f32 (

-  arm_rfft_fast_instance_f32 * S,

-  uint16_t fftLen);

-

-  void arm_rfft_fast_f32(

-  arm_rfft_fast_instance_f32 * S,

-  float32_t * p, float32_t * pOut,

-  uint8_t ifftFlag);

-

-  /**

-   * @brief Instance structure for the floating-point DCT4/IDCT4 function.

-   */

-

-  typedef struct

-  {

-    uint16_t N;                         /**< length of the DCT4. */

-    uint16_t Nby2;                      /**< half of the length of the DCT4. */

-    float32_t normalize;                /**< normalizing factor. */

-    float32_t *pTwiddle;                /**< points to the twiddle factor table. */

-    float32_t *pCosFactor;              /**< points to the cosFactor table. */

-    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */

-    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */

-  } arm_dct4_instance_f32;

-

-  /**

-   * @brief  Initialization function for the floating-point DCT4/IDCT4.

-   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.

-   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.

-   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.

-   * @param[in]     N          length of the DCT4.

-   * @param[in]     Nby2       half of the length of the DCT4.

-   * @param[in]     normalize  normalizing factor.

-   * @return        arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.

-   */

-

-  arm_status arm_dct4_init_f32(

-  arm_dct4_instance_f32 * S,

-  arm_rfft_instance_f32 * S_RFFT,

-  arm_cfft_radix4_instance_f32 * S_CFFT,

-  uint16_t N,

-  uint16_t Nby2,

-  float32_t normalize);

-

-  /**

-   * @brief Processing function for the floating-point DCT4/IDCT4.

-   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.

-   * @param[in]       *pState        points to state buffer.

-   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.

-   * @return none.

-   */

-

-  void arm_dct4_f32(

-  const arm_dct4_instance_f32 * S,

-  float32_t * pState,

-  float32_t * pInlineBuffer);

-

-  /**

-   * @brief Instance structure for the Q31 DCT4/IDCT4 function.

-   */

-

-  typedef struct

-  {

-    uint16_t N;                         /**< length of the DCT4. */

-    uint16_t Nby2;                      /**< half of the length of the DCT4. */

-    q31_t normalize;                    /**< normalizing factor. */

-    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */

-    q31_t *pCosFactor;                  /**< points to the cosFactor table. */

-    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */

-    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */

-  } arm_dct4_instance_q31;

-

-  /**

-   * @brief  Initialization function for the Q31 DCT4/IDCT4.

-   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.

-   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure

-   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure

-   * @param[in]     N          length of the DCT4.

-   * @param[in]     Nby2       half of the length of the DCT4.

-   * @param[in]     normalize  normalizing factor.

-   * @return        arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.

-   */

-

-  arm_status arm_dct4_init_q31(

-  arm_dct4_instance_q31 * S,

-  arm_rfft_instance_q31 * S_RFFT,

-  arm_cfft_radix4_instance_q31 * S_CFFT,

-  uint16_t N,

-  uint16_t Nby2,

-  q31_t normalize);

-

-  /**

-   * @brief Processing function for the Q31 DCT4/IDCT4.

-   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.

-   * @param[in]       *pState        points to state buffer.

-   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.

-   * @return none.

-   */

-

-  void arm_dct4_q31(

-  const arm_dct4_instance_q31 * S,

-  q31_t * pState,

-  q31_t * pInlineBuffer);

-

-  /**

-   * @brief Instance structure for the Q15 DCT4/IDCT4 function.

-   */

-

-  typedef struct

-  {

-    uint16_t N;                         /**< length of the DCT4. */

-    uint16_t Nby2;                      /**< half of the length of the DCT4. */

-    q15_t normalize;                    /**< normalizing factor. */

-    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */

-    q15_t *pCosFactor;                  /**< points to the cosFactor table. */

-    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */

-    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */

-  } arm_dct4_instance_q15;

-

-  /**

-   * @brief  Initialization function for the Q15 DCT4/IDCT4.

-   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.

-   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.

-   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.

-   * @param[in]     N          length of the DCT4.

-   * @param[in]     Nby2       half of the length of the DCT4.

-   * @param[in]     normalize  normalizing factor.

-   * @return        arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.

-   */

-

-  arm_status arm_dct4_init_q15(

-  arm_dct4_instance_q15 * S,

-  arm_rfft_instance_q15 * S_RFFT,

-  arm_cfft_radix4_instance_q15 * S_CFFT,

-  uint16_t N,

-  uint16_t Nby2,

-  q15_t normalize);

-

-  /**

-   * @brief Processing function for the Q15 DCT4/IDCT4.

-   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.

-   * @param[in]       *pState        points to state buffer.

-   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.

-   * @return none.

-   */

-

-  void arm_dct4_q15(

-  const arm_dct4_instance_q15 * S,

-  q15_t * pState,

-  q15_t * pInlineBuffer);

-

-  /**

-   * @brief Floating-point vector addition.

-   * @param[in]       *pSrcA points to the first input vector

-   * @param[in]       *pSrcB points to the second input vector

-   * @param[out]      *pDst points to the output vector

-   * @param[in]       blockSize number of samples in each vector

-   * @return none.

-   */

-

-  void arm_add_f32(

-  float32_t * pSrcA,

-  float32_t * pSrcB,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Q7 vector addition.

-   * @param[in]       *pSrcA points to the first input vector

-   * @param[in]       *pSrcB points to the second input vector

-   * @param[out]      *pDst points to the output vector

-   * @param[in]       blockSize number of samples in each vector

-   * @return none.

-   */

-

-  void arm_add_q7(

-  q7_t * pSrcA,

-  q7_t * pSrcB,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Q15 vector addition.

-   * @param[in]       *pSrcA points to the first input vector

-   * @param[in]       *pSrcB points to the second input vector

-   * @param[out]      *pDst points to the output vector

-   * @param[in]       blockSize number of samples in each vector

-   * @return none.

-   */

-

-  void arm_add_q15(

-  q15_t * pSrcA,

-  q15_t * pSrcB,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Q31 vector addition.

-   * @param[in]       *pSrcA points to the first input vector

-   * @param[in]       *pSrcB points to the second input vector

-   * @param[out]      *pDst points to the output vector

-   * @param[in]       blockSize number of samples in each vector

-   * @return none.

-   */

-

-  void arm_add_q31(

-  q31_t * pSrcA,

-  q31_t * pSrcB,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Floating-point vector subtraction.

-   * @param[in]       *pSrcA points to the first input vector

-   * @param[in]       *pSrcB points to the second input vector

-   * @param[out]      *pDst points to the output vector

-   * @param[in]       blockSize number of samples in each vector

-   * @return none.

-   */

-

-  void arm_sub_f32(

-  float32_t * pSrcA,

-  float32_t * pSrcB,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Q7 vector subtraction.

-   * @param[in]       *pSrcA points to the first input vector

-   * @param[in]       *pSrcB points to the second input vector

-   * @param[out]      *pDst points to the output vector

-   * @param[in]       blockSize number of samples in each vector

-   * @return none.

-   */

-

-  void arm_sub_q7(

-  q7_t * pSrcA,

-  q7_t * pSrcB,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Q15 vector subtraction.

-   * @param[in]       *pSrcA points to the first input vector

-   * @param[in]       *pSrcB points to the second input vector

-   * @param[out]      *pDst points to the output vector

-   * @param[in]       blockSize number of samples in each vector

-   * @return none.

-   */

-

-  void arm_sub_q15(

-  q15_t * pSrcA,

-  q15_t * pSrcB,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Q31 vector subtraction.

-   * @param[in]       *pSrcA points to the first input vector

-   * @param[in]       *pSrcB points to the second input vector

-   * @param[out]      *pDst points to the output vector

-   * @param[in]       blockSize number of samples in each vector

-   * @return none.

-   */

-

-  void arm_sub_q31(

-  q31_t * pSrcA,

-  q31_t * pSrcB,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Multiplies a floating-point vector by a scalar.

-   * @param[in]       *pSrc points to the input vector

-   * @param[in]       scale scale factor to be applied

-   * @param[out]      *pDst points to the output vector

-   * @param[in]       blockSize number of samples in the vector

-   * @return none.

-   */

-

-  void arm_scale_f32(

-  float32_t * pSrc,

-  float32_t scale,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Multiplies a Q7 vector by a scalar.

-   * @param[in]       *pSrc points to the input vector

-   * @param[in]       scaleFract fractional portion of the scale value

-   * @param[in]       shift number of bits to shift the result by

-   * @param[out]      *pDst points to the output vector

-   * @param[in]       blockSize number of samples in the vector

-   * @return none.

-   */

-

-  void arm_scale_q7(

-  q7_t * pSrc,

-  q7_t scaleFract,

-  int8_t shift,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Multiplies a Q15 vector by a scalar.

-   * @param[in]       *pSrc points to the input vector

-   * @param[in]       scaleFract fractional portion of the scale value

-   * @param[in]       shift number of bits to shift the result by

-   * @param[out]      *pDst points to the output vector

-   * @param[in]       blockSize number of samples in the vector

-   * @return none.

-   */

-

-  void arm_scale_q15(

-  q15_t * pSrc,

-  q15_t scaleFract,

-  int8_t shift,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Multiplies a Q31 vector by a scalar.

-   * @param[in]       *pSrc points to the input vector

-   * @param[in]       scaleFract fractional portion of the scale value

-   * @param[in]       shift number of bits to shift the result by

-   * @param[out]      *pDst points to the output vector

-   * @param[in]       blockSize number of samples in the vector

-   * @return none.

-   */

-

-  void arm_scale_q31(

-  q31_t * pSrc,

-  q31_t scaleFract,

-  int8_t shift,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Q7 vector absolute value.

-   * @param[in]       *pSrc points to the input buffer

-   * @param[out]      *pDst points to the output buffer

-   * @param[in]       blockSize number of samples in each vector

-   * @return none.

-   */

-

-  void arm_abs_q7(

-  q7_t * pSrc,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Floating-point vector absolute value.

-   * @param[in]       *pSrc points to the input buffer

-   * @param[out]      *pDst points to the output buffer

-   * @param[in]       blockSize number of samples in each vector

-   * @return none.

-   */

-

-  void arm_abs_f32(

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Q15 vector absolute value.

-   * @param[in]       *pSrc points to the input buffer

-   * @param[out]      *pDst points to the output buffer

-   * @param[in]       blockSize number of samples in each vector

-   * @return none.

-   */

-

-  void arm_abs_q15(

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Q31 vector absolute value.

-   * @param[in]       *pSrc points to the input buffer

-   * @param[out]      *pDst points to the output buffer

-   * @param[in]       blockSize number of samples in each vector

-   * @return none.

-   */

-

-  void arm_abs_q31(

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Dot product of floating-point vectors.

-   * @param[in]       *pSrcA points to the first input vector

-   * @param[in]       *pSrcB points to the second input vector

-   * @param[in]       blockSize number of samples in each vector

-   * @param[out]      *result output result returned here

-   * @return none.

-   */

-

-  void arm_dot_prod_f32(

-  float32_t * pSrcA,

-  float32_t * pSrcB,

-  uint32_t blockSize,

-  float32_t * result);

-

-  /**

-   * @brief Dot product of Q7 vectors.

-   * @param[in]       *pSrcA points to the first input vector

-   * @param[in]       *pSrcB points to the second input vector

-   * @param[in]       blockSize number of samples in each vector

-   * @param[out]      *result output result returned here

-   * @return none.

-   */

-

-  void arm_dot_prod_q7(

-  q7_t * pSrcA,

-  q7_t * pSrcB,

-  uint32_t blockSize,

-  q31_t * result);

-

-  /**

-   * @brief Dot product of Q15 vectors.

-   * @param[in]       *pSrcA points to the first input vector

-   * @param[in]       *pSrcB points to the second input vector

-   * @param[in]       blockSize number of samples in each vector

-   * @param[out]      *result output result returned here

-   * @return none.

-   */

-

-  void arm_dot_prod_q15(

-  q15_t * pSrcA,

-  q15_t * pSrcB,

-  uint32_t blockSize,

-  q63_t * result);

-

-  /**

-   * @brief Dot product of Q31 vectors.

-   * @param[in]       *pSrcA points to the first input vector

-   * @param[in]       *pSrcB points to the second input vector

-   * @param[in]       blockSize number of samples in each vector

-   * @param[out]      *result output result returned here

-   * @return none.

-   */

-

-  void arm_dot_prod_q31(

-  q31_t * pSrcA,

-  q31_t * pSrcB,

-  uint32_t blockSize,

-  q63_t * result);

-

-  /**

-   * @brief  Shifts the elements of a Q7 vector a specified number of bits.

-   * @param[in]  *pSrc points to the input vector

-   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.

-   * @param[out]  *pDst points to the output vector

-   * @param[in]  blockSize number of samples in the vector

-   * @return none.

-   */

-

-  void arm_shift_q7(

-  q7_t * pSrc,

-  int8_t shiftBits,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Shifts the elements of a Q15 vector a specified number of bits.

-   * @param[in]  *pSrc points to the input vector

-   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.

-   * @param[out]  *pDst points to the output vector

-   * @param[in]  blockSize number of samples in the vector

-   * @return none.

-   */

-

-  void arm_shift_q15(

-  q15_t * pSrc,

-  int8_t shiftBits,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Shifts the elements of a Q31 vector a specified number of bits.

-   * @param[in]  *pSrc points to the input vector

-   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.

-   * @param[out]  *pDst points to the output vector

-   * @param[in]  blockSize number of samples in the vector

-   * @return none.

-   */

-

-  void arm_shift_q31(

-  q31_t * pSrc,

-  int8_t shiftBits,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Adds a constant offset to a floating-point vector.

-   * @param[in]  *pSrc points to the input vector

-   * @param[in]  offset is the offset to be added

-   * @param[out]  *pDst points to the output vector

-   * @param[in]  blockSize number of samples in the vector

-   * @return none.

-   */

-

-  void arm_offset_f32(

-  float32_t * pSrc,

-  float32_t offset,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Adds a constant offset to a Q7 vector.

-   * @param[in]  *pSrc points to the input vector

-   * @param[in]  offset is the offset to be added

-   * @param[out]  *pDst points to the output vector

-   * @param[in]  blockSize number of samples in the vector

-   * @return none.

-   */

-

-  void arm_offset_q7(

-  q7_t * pSrc,

-  q7_t offset,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Adds a constant offset to a Q15 vector.

-   * @param[in]  *pSrc points to the input vector

-   * @param[in]  offset is the offset to be added

-   * @param[out]  *pDst points to the output vector

-   * @param[in]  blockSize number of samples in the vector

-   * @return none.

-   */

-

-  void arm_offset_q15(

-  q15_t * pSrc,

-  q15_t offset,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Adds a constant offset to a Q31 vector.

-   * @param[in]  *pSrc points to the input vector

-   * @param[in]  offset is the offset to be added

-   * @param[out]  *pDst points to the output vector

-   * @param[in]  blockSize number of samples in the vector

-   * @return none.

-   */

-

-  void arm_offset_q31(

-  q31_t * pSrc,

-  q31_t offset,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Negates the elements of a floating-point vector.

-   * @param[in]  *pSrc points to the input vector

-   * @param[out]  *pDst points to the output vector

-   * @param[in]  blockSize number of samples in the vector

-   * @return none.

-   */

-

-  void arm_negate_f32(

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Negates the elements of a Q7 vector.

-   * @param[in]  *pSrc points to the input vector

-   * @param[out]  *pDst points to the output vector

-   * @param[in]  blockSize number of samples in the vector

-   * @return none.

-   */

-

-  void arm_negate_q7(

-  q7_t * pSrc,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Negates the elements of a Q15 vector.

-   * @param[in]  *pSrc points to the input vector

-   * @param[out]  *pDst points to the output vector

-   * @param[in]  blockSize number of samples in the vector

-   * @return none.

-   */

-

-  void arm_negate_q15(

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Negates the elements of a Q31 vector.

-   * @param[in]  *pSrc points to the input vector

-   * @param[out]  *pDst points to the output vector

-   * @param[in]  blockSize number of samples in the vector

-   * @return none.

-   */

-

-  void arm_negate_q31(

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-  /**

-   * @brief  Copies the elements of a floating-point vector.

-   * @param[in]  *pSrc input pointer

-   * @param[out]  *pDst output pointer

-   * @param[in]  blockSize number of samples to process

-   * @return none.

-   */

-  void arm_copy_f32(

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Copies the elements of a Q7 vector.

-   * @param[in]  *pSrc input pointer

-   * @param[out]  *pDst output pointer

-   * @param[in]  blockSize number of samples to process

-   * @return none.

-   */

-  void arm_copy_q7(

-  q7_t * pSrc,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Copies the elements of a Q15 vector.

-   * @param[in]  *pSrc input pointer

-   * @param[out]  *pDst output pointer

-   * @param[in]  blockSize number of samples to process

-   * @return none.

-   */

-  void arm_copy_q15(

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Copies the elements of a Q31 vector.

-   * @param[in]  *pSrc input pointer

-   * @param[out]  *pDst output pointer

-   * @param[in]  blockSize number of samples to process

-   * @return none.

-   */

-  void arm_copy_q31(

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-  /**

-   * @brief  Fills a constant value into a floating-point vector.

-   * @param[in]  value input value to be filled

-   * @param[out]  *pDst output pointer

-   * @param[in]  blockSize number of samples to process

-   * @return none.

-   */

-  void arm_fill_f32(

-  float32_t value,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Fills a constant value into a Q7 vector.

-   * @param[in]  value input value to be filled

-   * @param[out]  *pDst output pointer

-   * @param[in]  blockSize number of samples to process

-   * @return none.

-   */

-  void arm_fill_q7(

-  q7_t value,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Fills a constant value into a Q15 vector.

-   * @param[in]  value input value to be filled

-   * @param[out]  *pDst output pointer

-   * @param[in]  blockSize number of samples to process

-   * @return none.

-   */

-  void arm_fill_q15(

-  q15_t value,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Fills a constant value into a Q31 vector.

-   * @param[in]  value input value to be filled

-   * @param[out]  *pDst output pointer

-   * @param[in]  blockSize number of samples to process

-   * @return none.

-   */

-  void arm_fill_q31(

-  q31_t value,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-/**

- * @brief Convolution of floating-point sequences.

- * @param[in] *pSrcA points to the first input sequence.

- * @param[in] srcALen length of the first input sequence.

- * @param[in] *pSrcB points to the second input sequence.

- * @param[in] srcBLen length of the second input sequence.

- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.

- * @return none.

- */

-

-  void arm_conv_f32(

-  float32_t * pSrcA,

-  uint32_t srcALen,

-  float32_t * pSrcB,

-  uint32_t srcBLen,

-  float32_t * pDst);

-

-

-  /**

-   * @brief Convolution of Q15 sequences.

-   * @param[in] *pSrcA points to the first input sequence.

-   * @param[in] srcALen length of the first input sequence.

-   * @param[in] *pSrcB points to the second input sequence.

-   * @param[in] srcBLen length of the second input sequence.

-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.

-   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.

-   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).

-   * @return none.

-   */

-

-

-  void arm_conv_opt_q15(

-  q15_t * pSrcA,

-  uint32_t srcALen,

-  q15_t * pSrcB,

-  uint32_t srcBLen,

-  q15_t * pDst,

-  q15_t * pScratch1,

-  q15_t * pScratch2);

-

-

-/**

- * @brief Convolution of Q15 sequences.

- * @param[in] *pSrcA points to the first input sequence.

- * @param[in] srcALen length of the first input sequence.

- * @param[in] *pSrcB points to the second input sequence.

- * @param[in] srcBLen length of the second input sequence.

- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.

- * @return none.

- */

-

-  void arm_conv_q15(

-  q15_t * pSrcA,

-  uint32_t srcALen,

-  q15_t * pSrcB,

-  uint32_t srcBLen,

-  q15_t * pDst);

-

-  /**

-   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4

-   * @param[in] *pSrcA points to the first input sequence.

-   * @param[in] srcALen length of the first input sequence.

-   * @param[in] *pSrcB points to the second input sequence.

-   * @param[in] srcBLen length of the second input sequence.

-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.

-   * @return none.

-   */

-

-  void arm_conv_fast_q15(

-  q15_t * pSrcA,

-  uint32_t srcALen,

-  q15_t * pSrcB,

-  uint32_t srcBLen,

-  q15_t * pDst);

-

-  /**

-   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4

-   * @param[in] *pSrcA points to the first input sequence.

-   * @param[in] srcALen length of the first input sequence.

-   * @param[in] *pSrcB points to the second input sequence.

-   * @param[in] srcBLen length of the second input sequence.

-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.

-   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.

-   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).

-   * @return none.

-   */

-

-  void arm_conv_fast_opt_q15(

-  q15_t * pSrcA,

-  uint32_t srcALen,

-  q15_t * pSrcB,

-  uint32_t srcBLen,

-  q15_t * pDst,

-  q15_t * pScratch1,

-  q15_t * pScratch2);

-

-

-

-  /**

-   * @brief Convolution of Q31 sequences.

-   * @param[in] *pSrcA points to the first input sequence.

-   * @param[in] srcALen length of the first input sequence.

-   * @param[in] *pSrcB points to the second input sequence.

-   * @param[in] srcBLen length of the second input sequence.

-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.

-   * @return none.

-   */

-

-  void arm_conv_q31(

-  q31_t * pSrcA,

-  uint32_t srcALen,

-  q31_t * pSrcB,

-  uint32_t srcBLen,

-  q31_t * pDst);

-

-  /**

-   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4

-   * @param[in] *pSrcA points to the first input sequence.

-   * @param[in] srcALen length of the first input sequence.

-   * @param[in] *pSrcB points to the second input sequence.

-   * @param[in] srcBLen length of the second input sequence.

-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.

-   * @return none.

-   */

-

-  void arm_conv_fast_q31(

-  q31_t * pSrcA,

-  uint32_t srcALen,

-  q31_t * pSrcB,

-  uint32_t srcBLen,

-  q31_t * pDst);

-

-

-    /**

-   * @brief Convolution of Q7 sequences.

-   * @param[in] *pSrcA points to the first input sequence.

-   * @param[in] srcALen length of the first input sequence.

-   * @param[in] *pSrcB points to the second input sequence.

-   * @param[in] srcBLen length of the second input sequence.

-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.

-   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.

-   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).

-   * @return none.

-   */

-

-  void arm_conv_opt_q7(

-  q7_t * pSrcA,

-  uint32_t srcALen,

-  q7_t * pSrcB,

-  uint32_t srcBLen,

-  q7_t * pDst,

-  q15_t * pScratch1,

-  q15_t * pScratch2);

-

-

-

-  /**

-   * @brief Convolution of Q7 sequences.

-   * @param[in] *pSrcA points to the first input sequence.

-   * @param[in] srcALen length of the first input sequence.

-   * @param[in] *pSrcB points to the second input sequence.

-   * @param[in] srcBLen length of the second input sequence.

-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.

-   * @return none.

-   */

-

-  void arm_conv_q7(

-  q7_t * pSrcA,

-  uint32_t srcALen,

-  q7_t * pSrcB,

-  uint32_t srcBLen,

-  q7_t * pDst);

-

-

-  /**

-   * @brief Partial convolution of floating-point sequences.

-   * @param[in]       *pSrcA points to the first input sequence.

-   * @param[in]       srcALen length of the first input sequence.

-   * @param[in]       *pSrcB points to the second input sequence.

-   * @param[in]       srcBLen length of the second input sequence.

-   * @param[out]      *pDst points to the block of output data

-   * @param[in]       firstIndex is the first output sample to start with.

-   * @param[in]       numPoints is the number of output points to be computed.

-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

-   */

-

-  arm_status arm_conv_partial_f32(

-  float32_t * pSrcA,

-  uint32_t srcALen,

-  float32_t * pSrcB,

-  uint32_t srcBLen,

-  float32_t * pDst,

-  uint32_t firstIndex,

-  uint32_t numPoints);

-

-    /**

-   * @brief Partial convolution of Q15 sequences.

-   * @param[in]       *pSrcA points to the first input sequence.

-   * @param[in]       srcALen length of the first input sequence.

-   * @param[in]       *pSrcB points to the second input sequence.

-   * @param[in]       srcBLen length of the second input sequence.

-   * @param[out]      *pDst points to the block of output data

-   * @param[in]       firstIndex is the first output sample to start with.

-   * @param[in]       numPoints is the number of output points to be computed.

-   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.

-   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).

-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

-   */

-

-  arm_status arm_conv_partial_opt_q15(

-  q15_t * pSrcA,

-  uint32_t srcALen,

-  q15_t * pSrcB,

-  uint32_t srcBLen,

-  q15_t * pDst,

-  uint32_t firstIndex,

-  uint32_t numPoints,

-  q15_t * pScratch1,

-  q15_t * pScratch2);

-

-

-/**

-   * @brief Partial convolution of Q15 sequences.

-   * @param[in]       *pSrcA points to the first input sequence.

-   * @param[in]       srcALen length of the first input sequence.

-   * @param[in]       *pSrcB points to the second input sequence.

-   * @param[in]       srcBLen length of the second input sequence.

-   * @param[out]      *pDst points to the block of output data

-   * @param[in]       firstIndex is the first output sample to start with.

-   * @param[in]       numPoints is the number of output points to be computed.

-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

-   */

-

-  arm_status arm_conv_partial_q15(

-  q15_t * pSrcA,

-  uint32_t srcALen,

-  q15_t * pSrcB,

-  uint32_t srcBLen,

-  q15_t * pDst,

-  uint32_t firstIndex,

-  uint32_t numPoints);

-

-  /**

-   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4

-   * @param[in]       *pSrcA points to the first input sequence.

-   * @param[in]       srcALen length of the first input sequence.

-   * @param[in]       *pSrcB points to the second input sequence.

-   * @param[in]       srcBLen length of the second input sequence.

-   * @param[out]      *pDst points to the block of output data

-   * @param[in]       firstIndex is the first output sample to start with.

-   * @param[in]       numPoints is the number of output points to be computed.

-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

-   */

-

-  arm_status arm_conv_partial_fast_q15(

-  q15_t * pSrcA,

-  uint32_t srcALen,

-  q15_t * pSrcB,

-  uint32_t srcBLen,

-  q15_t * pDst,

-  uint32_t firstIndex,

-  uint32_t numPoints);

-

-

-  /**

-   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4

-   * @param[in]       *pSrcA points to the first input sequence.

-   * @param[in]       srcALen length of the first input sequence.

-   * @param[in]       *pSrcB points to the second input sequence.

-   * @param[in]       srcBLen length of the second input sequence.

-   * @param[out]      *pDst points to the block of output data

-   * @param[in]       firstIndex is the first output sample to start with.

-   * @param[in]       numPoints is the number of output points to be computed.

-   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.

-   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).

-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

-   */

-

-  arm_status arm_conv_partial_fast_opt_q15(

-  q15_t * pSrcA,

-  uint32_t srcALen,

-  q15_t * pSrcB,

-  uint32_t srcBLen,

-  q15_t * pDst,

-  uint32_t firstIndex,

-  uint32_t numPoints,

-  q15_t * pScratch1,

-  q15_t * pScratch2);

-

-

-  /**

-   * @brief Partial convolution of Q31 sequences.

-   * @param[in]       *pSrcA points to the first input sequence.

-   * @param[in]       srcALen length of the first input sequence.

-   * @param[in]       *pSrcB points to the second input sequence.

-   * @param[in]       srcBLen length of the second input sequence.

-   * @param[out]      *pDst points to the block of output data

-   * @param[in]       firstIndex is the first output sample to start with.

-   * @param[in]       numPoints is the number of output points to be computed.

-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

-   */

-

-  arm_status arm_conv_partial_q31(

-  q31_t * pSrcA,

-  uint32_t srcALen,

-  q31_t * pSrcB,

-  uint32_t srcBLen,

-  q31_t * pDst,

-  uint32_t firstIndex,

-  uint32_t numPoints);

-

-

-  /**

-   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4

-   * @param[in]       *pSrcA points to the first input sequence.

-   * @param[in]       srcALen length of the first input sequence.

-   * @param[in]       *pSrcB points to the second input sequence.

-   * @param[in]       srcBLen length of the second input sequence.

-   * @param[out]      *pDst points to the block of output data

-   * @param[in]       firstIndex is the first output sample to start with.

-   * @param[in]       numPoints is the number of output points to be computed.

-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

-   */

-

-  arm_status arm_conv_partial_fast_q31(

-  q31_t * pSrcA,

-  uint32_t srcALen,

-  q31_t * pSrcB,

-  uint32_t srcBLen,

-  q31_t * pDst,

-  uint32_t firstIndex,

-  uint32_t numPoints);

-

-

-  /**

-   * @brief Partial convolution of Q7 sequences

-   * @param[in]       *pSrcA points to the first input sequence.

-   * @param[in]       srcALen length of the first input sequence.

-   * @param[in]       *pSrcB points to the second input sequence.

-   * @param[in]       srcBLen length of the second input sequence.

-   * @param[out]      *pDst points to the block of output data

-   * @param[in]       firstIndex is the first output sample to start with.

-   * @param[in]       numPoints is the number of output points to be computed.

-   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.

-   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).

-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

-   */

-

-  arm_status arm_conv_partial_opt_q7(

-  q7_t * pSrcA,

-  uint32_t srcALen,

-  q7_t * pSrcB,

-  uint32_t srcBLen,

-  q7_t * pDst,

-  uint32_t firstIndex,

-  uint32_t numPoints,

-  q15_t * pScratch1,

-  q15_t * pScratch2);

-

-

-/**

-   * @brief Partial convolution of Q7 sequences.

-   * @param[in]       *pSrcA points to the first input sequence.

-   * @param[in]       srcALen length of the first input sequence.

-   * @param[in]       *pSrcB points to the second input sequence.

-   * @param[in]       srcBLen length of the second input sequence.

-   * @param[out]      *pDst points to the block of output data

-   * @param[in]       firstIndex is the first output sample to start with.

-   * @param[in]       numPoints is the number of output points to be computed.

-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

-   */

-

-  arm_status arm_conv_partial_q7(

-  q7_t * pSrcA,

-  uint32_t srcALen,

-  q7_t * pSrcB,

-  uint32_t srcBLen,

-  q7_t * pDst,

-  uint32_t firstIndex,

-  uint32_t numPoints);

-

-

-

-  /**

-   * @brief Instance structure for the Q15 FIR decimator.

-   */

-

-  typedef struct

-  {

-    uint8_t M;                      /**< decimation factor. */

-    uint16_t numTaps;               /**< number of coefficients in the filter. */

-    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/

-    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */

-  } arm_fir_decimate_instance_q15;

-

-  /**

-   * @brief Instance structure for the Q31 FIR decimator.

-   */

-

-  typedef struct

-  {

-    uint8_t M;                  /**< decimation factor. */

-    uint16_t numTaps;           /**< number of coefficients in the filter. */

-    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/

-    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */

-

-  } arm_fir_decimate_instance_q31;

-

-  /**

-   * @brief Instance structure for the floating-point FIR decimator.

-   */

-

-  typedef struct

-  {

-    uint8_t M;                          /**< decimation factor. */

-    uint16_t numTaps;                   /**< number of coefficients in the filter. */

-    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/

-    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */

-

-  } arm_fir_decimate_instance_f32;

-

-

-

-  /**

-   * @brief Processing function for the floating-point FIR decimator.

-   * @param[in] *S points to an instance of the floating-point FIR decimator structure.

-   * @param[in] *pSrc points to the block of input data.

-   * @param[out] *pDst points to the block of output data

-   * @param[in] blockSize number of input samples to process per call.

-   * @return none

-   */

-

-  void arm_fir_decimate_f32(

-  const arm_fir_decimate_instance_f32 * S,

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Initialization function for the floating-point FIR decimator.

-   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.

-   * @param[in] numTaps  number of coefficients in the filter.

-   * @param[in] M  decimation factor.

-   * @param[in] *pCoeffs points to the filter coefficients.

-   * @param[in] *pState points to the state buffer.

-   * @param[in] blockSize number of input samples to process per call.

-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if

-   * <code>blockSize</code> is not a multiple of <code>M</code>.

-   */

-

-  arm_status arm_fir_decimate_init_f32(

-  arm_fir_decimate_instance_f32 * S,

-  uint16_t numTaps,

-  uint8_t M,

-  float32_t * pCoeffs,

-  float32_t * pState,

-  uint32_t blockSize);

-

-  /**

-   * @brief Processing function for the Q15 FIR decimator.

-   * @param[in] *S points to an instance of the Q15 FIR decimator structure.

-   * @param[in] *pSrc points to the block of input data.

-   * @param[out] *pDst points to the block of output data

-   * @param[in] blockSize number of input samples to process per call.

-   * @return none

-   */

-

-  void arm_fir_decimate_q15(

-  const arm_fir_decimate_instance_q15 * S,

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.

-   * @param[in] *S points to an instance of the Q15 FIR decimator structure.

-   * @param[in] *pSrc points to the block of input data.

-   * @param[out] *pDst points to the block of output data

-   * @param[in] blockSize number of input samples to process per call.

-   * @return none

-   */

-

-  void arm_fir_decimate_fast_q15(

-  const arm_fir_decimate_instance_q15 * S,

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-

-

-  /**

-   * @brief  Initialization function for the Q15 FIR decimator.

-   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.

-   * @param[in] numTaps  number of coefficients in the filter.

-   * @param[in] M  decimation factor.

-   * @param[in] *pCoeffs points to the filter coefficients.

-   * @param[in] *pState points to the state buffer.

-   * @param[in] blockSize number of input samples to process per call.

-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if

-   * <code>blockSize</code> is not a multiple of <code>M</code>.

-   */

-

-  arm_status arm_fir_decimate_init_q15(

-  arm_fir_decimate_instance_q15 * S,

-  uint16_t numTaps,

-  uint8_t M,

-  q15_t * pCoeffs,

-  q15_t * pState,

-  uint32_t blockSize);

-

-  /**

-   * @brief Processing function for the Q31 FIR decimator.

-   * @param[in] *S points to an instance of the Q31 FIR decimator structure.

-   * @param[in] *pSrc points to the block of input data.

-   * @param[out] *pDst points to the block of output data

-   * @param[in] blockSize number of input samples to process per call.

-   * @return none

-   */

-

-  void arm_fir_decimate_q31(

-  const arm_fir_decimate_instance_q31 * S,

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.

-   * @param[in] *S points to an instance of the Q31 FIR decimator structure.

-   * @param[in] *pSrc points to the block of input data.

-   * @param[out] *pDst points to the block of output data

-   * @param[in] blockSize number of input samples to process per call.

-   * @return none

-   */

-

-  void arm_fir_decimate_fast_q31(

-  arm_fir_decimate_instance_q31 * S,

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Initialization function for the Q31 FIR decimator.

-   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.

-   * @param[in] numTaps  number of coefficients in the filter.

-   * @param[in] M  decimation factor.

-   * @param[in] *pCoeffs points to the filter coefficients.

-   * @param[in] *pState points to the state buffer.

-   * @param[in] blockSize number of input samples to process per call.

-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if

-   * <code>blockSize</code> is not a multiple of <code>M</code>.

-   */

-

-  arm_status arm_fir_decimate_init_q31(

-  arm_fir_decimate_instance_q31 * S,

-  uint16_t numTaps,

-  uint8_t M,

-  q31_t * pCoeffs,

-  q31_t * pState,

-  uint32_t blockSize);

-

-

-

-  /**

-   * @brief Instance structure for the Q15 FIR interpolator.

-   */

-

-  typedef struct

-  {

-    uint8_t L;                      /**< upsample factor. */

-    uint16_t phaseLength;           /**< length of each polyphase filter component. */

-    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */

-    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */

-  } arm_fir_interpolate_instance_q15;

-

-  /**

-   * @brief Instance structure for the Q31 FIR interpolator.

-   */

-

-  typedef struct

-  {

-    uint8_t L;                      /**< upsample factor. */

-    uint16_t phaseLength;           /**< length of each polyphase filter component. */

-    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */

-    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */

-  } arm_fir_interpolate_instance_q31;

-

-  /**

-   * @brief Instance structure for the floating-point FIR interpolator.

-   */

-

-  typedef struct

-  {

-    uint8_t L;                     /**< upsample factor. */

-    uint16_t phaseLength;          /**< length of each polyphase filter component. */

-    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */

-    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */

-  } arm_fir_interpolate_instance_f32;

-

-

-  /**

-   * @brief Processing function for the Q15 FIR interpolator.

-   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.

-   * @param[in] *pSrc     points to the block of input data.

-   * @param[out] *pDst    points to the block of output data.

-   * @param[in] blockSize number of input samples to process per call.

-   * @return none.

-   */

-

-  void arm_fir_interpolate_q15(

-  const arm_fir_interpolate_instance_q15 * S,

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Initialization function for the Q15 FIR interpolator.

-   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.

-   * @param[in]     L         upsample factor.

-   * @param[in]     numTaps   number of filter coefficients in the filter.

-   * @param[in]     *pCoeffs  points to the filter coefficient buffer.

-   * @param[in]     *pState   points to the state buffer.

-   * @param[in]     blockSize number of input samples to process per call.

-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if

-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.

-   */

-

-  arm_status arm_fir_interpolate_init_q15(

-  arm_fir_interpolate_instance_q15 * S,

-  uint8_t L,

-  uint16_t numTaps,

-  q15_t * pCoeffs,

-  q15_t * pState,

-  uint32_t blockSize);

-

-  /**

-   * @brief Processing function for the Q31 FIR interpolator.

-   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.

-   * @param[in] *pSrc     points to the block of input data.

-   * @param[out] *pDst    points to the block of output data.

-   * @param[in] blockSize number of input samples to process per call.

-   * @return none.

-   */

-

-  void arm_fir_interpolate_q31(

-  const arm_fir_interpolate_instance_q31 * S,

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Initialization function for the Q31 FIR interpolator.

-   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.

-   * @param[in]     L         upsample factor.

-   * @param[in]     numTaps   number of filter coefficients in the filter.

-   * @param[in]     *pCoeffs  points to the filter coefficient buffer.

-   * @param[in]     *pState   points to the state buffer.

-   * @param[in]     blockSize number of input samples to process per call.

-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if

-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.

-   */

-

-  arm_status arm_fir_interpolate_init_q31(

-  arm_fir_interpolate_instance_q31 * S,

-  uint8_t L,

-  uint16_t numTaps,

-  q31_t * pCoeffs,

-  q31_t * pState,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Processing function for the floating-point FIR interpolator.

-   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.

-   * @param[in] *pSrc     points to the block of input data.

-   * @param[out] *pDst    points to the block of output data.

-   * @param[in] blockSize number of input samples to process per call.

-   * @return none.

-   */

-

-  void arm_fir_interpolate_f32(

-  const arm_fir_interpolate_instance_f32 * S,

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Initialization function for the floating-point FIR interpolator.

-   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.

-   * @param[in]     L         upsample factor.

-   * @param[in]     numTaps   number of filter coefficients in the filter.

-   * @param[in]     *pCoeffs  points to the filter coefficient buffer.

-   * @param[in]     *pState   points to the state buffer.

-   * @param[in]     blockSize number of input samples to process per call.

-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if

-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.

-   */

-

-  arm_status arm_fir_interpolate_init_f32(

-  arm_fir_interpolate_instance_f32 * S,

-  uint8_t L,

-  uint16_t numTaps,

-  float32_t * pCoeffs,

-  float32_t * pState,

-  uint32_t blockSize);

-

-  /**

-   * @brief Instance structure for the high precision Q31 Biquad cascade filter.

-   */

-

-  typedef struct

-  {

-    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */

-    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */

-    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */

-    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */

-

-  } arm_biquad_cas_df1_32x64_ins_q31;

-

-

-  /**

-   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.

-   * @param[in]  *pSrc     points to the block of input data.

-   * @param[out] *pDst     points to the block of output data

-   * @param[in]  blockSize number of samples to process.

-   * @return none.

-   */

-

-  void arm_biquad_cas_df1_32x64_q31(

-  const arm_biquad_cas_df1_32x64_ins_q31 * S,

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.

-   * @param[in]     numStages    number of 2nd order stages in the filter.

-   * @param[in]     *pCoeffs     points to the filter coefficients.

-   * @param[in]     *pState      points to the state buffer.

-   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format

-   * @return        none

-   */

-

-  void arm_biquad_cas_df1_32x64_init_q31(

-  arm_biquad_cas_df1_32x64_ins_q31 * S,

-  uint8_t numStages,

-  q31_t * pCoeffs,

-  q63_t * pState,

-  uint8_t postShift);

-

-

-

-  /**

-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.

-   */

-

-  typedef struct

-  {

-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */

-    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */

-    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */

-  } arm_biquad_cascade_df2T_instance_f32;

-

-

-

-  /**

-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.

-   */

-

-  typedef struct

-  {

-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */

-    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */

-    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */

-  } arm_biquad_cascade_stereo_df2T_instance_f32;

-

-

-

-  /**

-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.

-   */

-

-  typedef struct

-  {

-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */

-    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */

-    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */

-  } arm_biquad_cascade_df2T_instance_f64;

-

-

-  /**

-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.

-   * @param[in]  *S        points to an instance of the filter data structure.

-   * @param[in]  *pSrc     points to the block of input data.

-   * @param[out] *pDst     points to the block of output data

-   * @param[in]  blockSize number of samples to process.

-   * @return none.

-   */

-

-  void arm_biquad_cascade_df2T_f32(

-  const arm_biquad_cascade_df2T_instance_f32 * S,

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels

-   * @param[in]  *S        points to an instance of the filter data structure.

-   * @param[in]  *pSrc     points to the block of input data.

-   * @param[out] *pDst     points to the block of output data

-   * @param[in]  blockSize number of samples to process.

-   * @return none.

-   */

-

-  void arm_biquad_cascade_stereo_df2T_f32(

-  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.

-   * @param[in]  *S        points to an instance of the filter data structure.

-   * @param[in]  *pSrc     points to the block of input data.

-   * @param[out] *pDst     points to the block of output data

-   * @param[in]  blockSize number of samples to process.

-   * @return none.

-   */

-

-  void arm_biquad_cascade_df2T_f64(

-  const arm_biquad_cascade_df2T_instance_f64 * S,

-  float64_t * pSrc,

-  float64_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.

-   * @param[in,out] *S           points to an instance of the filter data structure.

-   * @param[in]     numStages    number of 2nd order stages in the filter.

-   * @param[in]     *pCoeffs     points to the filter coefficients.

-   * @param[in]     *pState      points to the state buffer.

-   * @return        none

-   */

-

-  void arm_biquad_cascade_df2T_init_f32(

-  arm_biquad_cascade_df2T_instance_f32 * S,

-  uint8_t numStages,

-  float32_t * pCoeffs,

-  float32_t * pState);

-

-

-  /**

-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.

-   * @param[in,out] *S           points to an instance of the filter data structure.

-   * @param[in]     numStages    number of 2nd order stages in the filter.

-   * @param[in]     *pCoeffs     points to the filter coefficients.

-   * @param[in]     *pState      points to the state buffer.

-   * @return        none

-   */

-

-  void arm_biquad_cascade_stereo_df2T_init_f32(

-  arm_biquad_cascade_stereo_df2T_instance_f32 * S,

-  uint8_t numStages,

-  float32_t * pCoeffs,

-  float32_t * pState);

-

-

-  /**

-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.

-   * @param[in,out] *S           points to an instance of the filter data structure.

-   * @param[in]     numStages    number of 2nd order stages in the filter.

-   * @param[in]     *pCoeffs     points to the filter coefficients.

-   * @param[in]     *pState      points to the state buffer.

-   * @return        none

-   */

-

-  void arm_biquad_cascade_df2T_init_f64(

-  arm_biquad_cascade_df2T_instance_f64 * S,

-  uint8_t numStages,

-  float64_t * pCoeffs,

-  float64_t * pState);

-

-

-

-  /**

-   * @brief Instance structure for the Q15 FIR lattice filter.

-   */

-

-  typedef struct

-  {

-    uint16_t numStages;                          /**< number of filter stages. */

-    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */

-    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */

-  } arm_fir_lattice_instance_q15;

-

-  /**

-   * @brief Instance structure for the Q31 FIR lattice filter.

-   */

-

-  typedef struct

-  {

-    uint16_t numStages;                          /**< number of filter stages. */

-    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */

-    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */

-  } arm_fir_lattice_instance_q31;

-

-  /**

-   * @brief Instance structure for the floating-point FIR lattice filter.

-   */

-

-  typedef struct

-  {

-    uint16_t numStages;                  /**< number of filter stages. */

-    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */

-    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */

-  } arm_fir_lattice_instance_f32;

-

-  /**

-   * @brief Initialization function for the Q15 FIR lattice filter.

-   * @param[in] *S points to an instance of the Q15 FIR lattice structure.

-   * @param[in] numStages  number of filter stages.

-   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.

-   * @param[in] *pState points to the state buffer.  The array is of length numStages.

-   * @return none.

-   */

-

-  void arm_fir_lattice_init_q15(

-  arm_fir_lattice_instance_q15 * S,

-  uint16_t numStages,

-  q15_t * pCoeffs,

-  q15_t * pState);

-

-

-  /**

-   * @brief Processing function for the Q15 FIR lattice filter.

-   * @param[in] *S points to an instance of the Q15 FIR lattice structure.

-   * @param[in] *pSrc points to the block of input data.

-   * @param[out] *pDst points to the block of output data.

-   * @param[in] blockSize number of samples to process.

-   * @return none.

-   */

-  void arm_fir_lattice_q15(

-  const arm_fir_lattice_instance_q15 * S,

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Initialization function for the Q31 FIR lattice filter.

-   * @param[in] *S points to an instance of the Q31 FIR lattice structure.

-   * @param[in] numStages  number of filter stages.

-   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.

-   * @param[in] *pState points to the state buffer.   The array is of length numStages.

-   * @return none.

-   */

-

-  void arm_fir_lattice_init_q31(

-  arm_fir_lattice_instance_q31 * S,

-  uint16_t numStages,

-  q31_t * pCoeffs,

-  q31_t * pState);

-

-

-  /**

-   * @brief Processing function for the Q31 FIR lattice filter.

-   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.

-   * @param[in]  *pSrc     points to the block of input data.

-   * @param[out] *pDst     points to the block of output data

-   * @param[in]  blockSize number of samples to process.

-   * @return none.

-   */

-

-  void arm_fir_lattice_q31(

-  const arm_fir_lattice_instance_q31 * S,

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-/**

- * @brief Initialization function for the floating-point FIR lattice filter.

- * @param[in] *S points to an instance of the floating-point FIR lattice structure.

- * @param[in] numStages  number of filter stages.

- * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.

- * @param[in] *pState points to the state buffer.  The array is of length numStages.

- * @return none.

- */

-

-  void arm_fir_lattice_init_f32(

-  arm_fir_lattice_instance_f32 * S,

-  uint16_t numStages,

-  float32_t * pCoeffs,

-  float32_t * pState);

-

-  /**

-   * @brief Processing function for the floating-point FIR lattice filter.

-   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.

-   * @param[in]  *pSrc     points to the block of input data.

-   * @param[out] *pDst     points to the block of output data

-   * @param[in]  blockSize number of samples to process.

-   * @return none.

-   */

-

-  void arm_fir_lattice_f32(

-  const arm_fir_lattice_instance_f32 * S,

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Instance structure for the Q15 IIR lattice filter.

-   */

-  typedef struct

-  {

-    uint16_t numStages;                         /**< number of stages in the filter. */

-    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */

-    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */

-    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */

-  } arm_iir_lattice_instance_q15;

-

-  /**

-   * @brief Instance structure for the Q31 IIR lattice filter.

-   */

-  typedef struct

-  {

-    uint16_t numStages;                         /**< number of stages in the filter. */

-    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */

-    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */

-    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */

-  } arm_iir_lattice_instance_q31;

-

-  /**

-   * @brief Instance structure for the floating-point IIR lattice filter.

-   */

-  typedef struct

-  {

-    uint16_t numStages;                         /**< number of stages in the filter. */

-    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */

-    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */

-    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */

-  } arm_iir_lattice_instance_f32;

-

-  /**

-   * @brief Processing function for the floating-point IIR lattice filter.

-   * @param[in] *S points to an instance of the floating-point IIR lattice structure.

-   * @param[in] *pSrc points to the block of input data.

-   * @param[out] *pDst points to the block of output data.

-   * @param[in] blockSize number of samples to process.

-   * @return none.

-   */

-

-  void arm_iir_lattice_f32(

-  const arm_iir_lattice_instance_f32 * S,

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Initialization function for the floating-point IIR lattice filter.

-   * @param[in] *S points to an instance of the floating-point IIR lattice structure.

-   * @param[in] numStages number of stages in the filter.

-   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.

-   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.

-   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.

-   * @param[in] blockSize number of samples to process.

-   * @return none.

-   */

-

-  void arm_iir_lattice_init_f32(

-  arm_iir_lattice_instance_f32 * S,

-  uint16_t numStages,

-  float32_t * pkCoeffs,

-  float32_t * pvCoeffs,

-  float32_t * pState,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Processing function for the Q31 IIR lattice filter.

-   * @param[in] *S points to an instance of the Q31 IIR lattice structure.

-   * @param[in] *pSrc points to the block of input data.

-   * @param[out] *pDst points to the block of output data.

-   * @param[in] blockSize number of samples to process.

-   * @return none.

-   */

-

-  void arm_iir_lattice_q31(

-  const arm_iir_lattice_instance_q31 * S,

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Initialization function for the Q31 IIR lattice filter.

-   * @param[in] *S points to an instance of the Q31 IIR lattice structure.

-   * @param[in] numStages number of stages in the filter.

-   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.

-   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.

-   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.

-   * @param[in] blockSize number of samples to process.

-   * @return none.

-   */

-

-  void arm_iir_lattice_init_q31(

-  arm_iir_lattice_instance_q31 * S,

-  uint16_t numStages,

-  q31_t * pkCoeffs,

-  q31_t * pvCoeffs,

-  q31_t * pState,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Processing function for the Q15 IIR lattice filter.

-   * @param[in] *S points to an instance of the Q15 IIR lattice structure.

-   * @param[in] *pSrc points to the block of input data.

-   * @param[out] *pDst points to the block of output data.

-   * @param[in] blockSize number of samples to process.

-   * @return none.

-   */

-

-  void arm_iir_lattice_q15(

-  const arm_iir_lattice_instance_q15 * S,

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-

-/**

- * @brief Initialization function for the Q15 IIR lattice filter.

- * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.

- * @param[in] numStages  number of stages in the filter.

- * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.

- * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.

- * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.

- * @param[in] blockSize number of samples to process per call.

- * @return none.

- */

-

-  void arm_iir_lattice_init_q15(

-  arm_iir_lattice_instance_q15 * S,

-  uint16_t numStages,

-  q15_t * pkCoeffs,

-  q15_t * pvCoeffs,

-  q15_t * pState,

-  uint32_t blockSize);

-

-  /**

-   * @brief Instance structure for the floating-point LMS filter.

-   */

-

-  typedef struct

-  {

-    uint16_t numTaps;    /**< number of coefficients in the filter. */

-    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */

-    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */

-    float32_t mu;        /**< step size that controls filter coefficient updates. */

-  } arm_lms_instance_f32;

-

-  /**

-   * @brief Processing function for floating-point LMS filter.

-   * @param[in]  *S points to an instance of the floating-point LMS filter structure.

-   * @param[in]  *pSrc points to the block of input data.

-   * @param[in]  *pRef points to the block of reference data.

-   * @param[out] *pOut points to the block of output data.

-   * @param[out] *pErr points to the block of error data.

-   * @param[in]  blockSize number of samples to process.

-   * @return     none.

-   */

-

-  void arm_lms_f32(

-  const arm_lms_instance_f32 * S,

-  float32_t * pSrc,

-  float32_t * pRef,

-  float32_t * pOut,

-  float32_t * pErr,

-  uint32_t blockSize);

-

-  /**

-   * @brief Initialization function for floating-point LMS filter.

-   * @param[in] *S points to an instance of the floating-point LMS filter structure.

-   * @param[in] numTaps  number of filter coefficients.

-   * @param[in] *pCoeffs points to the coefficient buffer.

-   * @param[in] *pState points to state buffer.

-   * @param[in] mu step size that controls filter coefficient updates.

-   * @param[in] blockSize number of samples to process.

-   * @return none.

-   */

-

-  void arm_lms_init_f32(

-  arm_lms_instance_f32 * S,

-  uint16_t numTaps,

-  float32_t * pCoeffs,

-  float32_t * pState,

-  float32_t mu,

-  uint32_t blockSize);

-

-  /**

-   * @brief Instance structure for the Q15 LMS filter.

-   */

-

-  typedef struct

-  {

-    uint16_t numTaps;    /**< number of coefficients in the filter. */

-    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */

-    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */

-    q15_t mu;            /**< step size that controls filter coefficient updates. */

-    uint32_t postShift;  /**< bit shift applied to coefficients. */

-  } arm_lms_instance_q15;

-

-

-  /**

-   * @brief Initialization function for the Q15 LMS filter.

-   * @param[in] *S points to an instance of the Q15 LMS filter structure.

-   * @param[in] numTaps  number of filter coefficients.

-   * @param[in] *pCoeffs points to the coefficient buffer.

-   * @param[in] *pState points to the state buffer.

-   * @param[in] mu step size that controls filter coefficient updates.

-   * @param[in] blockSize number of samples to process.

-   * @param[in] postShift bit shift applied to coefficients.

-   * @return    none.

-   */

-

-  void arm_lms_init_q15(

-  arm_lms_instance_q15 * S,

-  uint16_t numTaps,

-  q15_t * pCoeffs,

-  q15_t * pState,

-  q15_t mu,

-  uint32_t blockSize,

-  uint32_t postShift);

-

-  /**

-   * @brief Processing function for Q15 LMS filter.

-   * @param[in] *S points to an instance of the Q15 LMS filter structure.

-   * @param[in] *pSrc points to the block of input data.

-   * @param[in] *pRef points to the block of reference data.

-   * @param[out] *pOut points to the block of output data.

-   * @param[out] *pErr points to the block of error data.

-   * @param[in] blockSize number of samples to process.

-   * @return none.

-   */

-

-  void arm_lms_q15(

-  const arm_lms_instance_q15 * S,

-  q15_t * pSrc,

-  q15_t * pRef,

-  q15_t * pOut,

-  q15_t * pErr,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Instance structure for the Q31 LMS filter.

-   */

-

-  typedef struct

-  {

-    uint16_t numTaps;    /**< number of coefficients in the filter. */

-    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */

-    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */

-    q31_t mu;            /**< step size that controls filter coefficient updates. */

-    uint32_t postShift;  /**< bit shift applied to coefficients. */

-

-  } arm_lms_instance_q31;

-

-  /**

-   * @brief Processing function for Q31 LMS filter.

-   * @param[in]  *S points to an instance of the Q15 LMS filter structure.

-   * @param[in]  *pSrc points to the block of input data.

-   * @param[in]  *pRef points to the block of reference data.

-   * @param[out] *pOut points to the block of output data.

-   * @param[out] *pErr points to the block of error data.

-   * @param[in]  blockSize number of samples to process.

-   * @return     none.

-   */

-

-  void arm_lms_q31(

-  const arm_lms_instance_q31 * S,

-  q31_t * pSrc,

-  q31_t * pRef,

-  q31_t * pOut,

-  q31_t * pErr,

-  uint32_t blockSize);

-

-  /**

-   * @brief Initialization function for Q31 LMS filter.

-   * @param[in] *S points to an instance of the Q31 LMS filter structure.

-   * @param[in] numTaps  number of filter coefficients.

-   * @param[in] *pCoeffs points to coefficient buffer.

-   * @param[in] *pState points to state buffer.

-   * @param[in] mu step size that controls filter coefficient updates.

-   * @param[in] blockSize number of samples to process.

-   * @param[in] postShift bit shift applied to coefficients.

-   * @return none.

-   */

-

-  void arm_lms_init_q31(

-  arm_lms_instance_q31 * S,

-  uint16_t numTaps,

-  q31_t * pCoeffs,

-  q31_t * pState,

-  q31_t mu,

-  uint32_t blockSize,

-  uint32_t postShift);

-

-  /**

-   * @brief Instance structure for the floating-point normalized LMS filter.

-   */

-

-  typedef struct

-  {

-    uint16_t numTaps;     /**< number of coefficients in the filter. */

-    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */

-    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */

-    float32_t mu;        /**< step size that control filter coefficient updates. */

-    float32_t energy;    /**< saves previous frame energy. */

-    float32_t x0;        /**< saves previous input sample. */

-  } arm_lms_norm_instance_f32;

-

-  /**

-   * @brief Processing function for floating-point normalized LMS filter.

-   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.

-   * @param[in] *pSrc points to the block of input data.

-   * @param[in] *pRef points to the block of reference data.

-   * @param[out] *pOut points to the block of output data.

-   * @param[out] *pErr points to the block of error data.

-   * @param[in] blockSize number of samples to process.

-   * @return none.

-   */

-

-  void arm_lms_norm_f32(

-  arm_lms_norm_instance_f32 * S,

-  float32_t * pSrc,

-  float32_t * pRef,

-  float32_t * pOut,

-  float32_t * pErr,

-  uint32_t blockSize);

-

-  /**

-   * @brief Initialization function for floating-point normalized LMS filter.

-   * @param[in] *S points to an instance of the floating-point LMS filter structure.

-   * @param[in] numTaps  number of filter coefficients.

-   * @param[in] *pCoeffs points to coefficient buffer.

-   * @param[in] *pState points to state buffer.

-   * @param[in] mu step size that controls filter coefficient updates.

-   * @param[in] blockSize number of samples to process.

-   * @return none.

-   */

-

-  void arm_lms_norm_init_f32(

-  arm_lms_norm_instance_f32 * S,

-  uint16_t numTaps,

-  float32_t * pCoeffs,

-  float32_t * pState,

-  float32_t mu,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Instance structure for the Q31 normalized LMS filter.

-   */

-  typedef struct

-  {

-    uint16_t numTaps;     /**< number of coefficients in the filter. */

-    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */

-    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */

-    q31_t mu;             /**< step size that controls filter coefficient updates. */

-    uint8_t postShift;    /**< bit shift applied to coefficients. */

-    q31_t *recipTable;    /**< points to the reciprocal initial value table. */

-    q31_t energy;         /**< saves previous frame energy. */

-    q31_t x0;             /**< saves previous input sample. */

-  } arm_lms_norm_instance_q31;

-

-  /**

-   * @brief Processing function for Q31 normalized LMS filter.

-   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.

-   * @param[in] *pSrc points to the block of input data.

-   * @param[in] *pRef points to the block of reference data.

-   * @param[out] *pOut points to the block of output data.

-   * @param[out] *pErr points to the block of error data.

-   * @param[in] blockSize number of samples to process.

-   * @return none.

-   */

-

-  void arm_lms_norm_q31(

-  arm_lms_norm_instance_q31 * S,

-  q31_t * pSrc,

-  q31_t * pRef,

-  q31_t * pOut,

-  q31_t * pErr,

-  uint32_t blockSize);

-

-  /**

-   * @brief Initialization function for Q31 normalized LMS filter.

-   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.

-   * @param[in] numTaps  number of filter coefficients.

-   * @param[in] *pCoeffs points to coefficient buffer.

-   * @param[in] *pState points to state buffer.

-   * @param[in] mu step size that controls filter coefficient updates.

-   * @param[in] blockSize number of samples to process.

-   * @param[in] postShift bit shift applied to coefficients.

-   * @return none.

-   */

-

-  void arm_lms_norm_init_q31(

-  arm_lms_norm_instance_q31 * S,

-  uint16_t numTaps,

-  q31_t * pCoeffs,

-  q31_t * pState,

-  q31_t mu,

-  uint32_t blockSize,

-  uint8_t postShift);

-

-  /**

-   * @brief Instance structure for the Q15 normalized LMS filter.

-   */

-

-  typedef struct

-  {

-    uint16_t numTaps;    /**< Number of coefficients in the filter. */

-    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */

-    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */

-    q15_t mu;            /**< step size that controls filter coefficient updates. */

-    uint8_t postShift;   /**< bit shift applied to coefficients. */

-    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */

-    q15_t energy;        /**< saves previous frame energy. */

-    q15_t x0;            /**< saves previous input sample. */

-  } arm_lms_norm_instance_q15;

-

-  /**

-   * @brief Processing function for Q15 normalized LMS filter.

-   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.

-   * @param[in] *pSrc points to the block of input data.

-   * @param[in] *pRef points to the block of reference data.

-   * @param[out] *pOut points to the block of output data.

-   * @param[out] *pErr points to the block of error data.

-   * @param[in] blockSize number of samples to process.

-   * @return none.

-   */

-

-  void arm_lms_norm_q15(

-  arm_lms_norm_instance_q15 * S,

-  q15_t * pSrc,

-  q15_t * pRef,

-  q15_t * pOut,

-  q15_t * pErr,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Initialization function for Q15 normalized LMS filter.

-   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.

-   * @param[in] numTaps  number of filter coefficients.

-   * @param[in] *pCoeffs points to coefficient buffer.

-   * @param[in] *pState points to state buffer.

-   * @param[in] mu step size that controls filter coefficient updates.

-   * @param[in] blockSize number of samples to process.

-   * @param[in] postShift bit shift applied to coefficients.

-   * @return none.

-   */

-

-  void arm_lms_norm_init_q15(

-  arm_lms_norm_instance_q15 * S,

-  uint16_t numTaps,

-  q15_t * pCoeffs,

-  q15_t * pState,

-  q15_t mu,

-  uint32_t blockSize,

-  uint8_t postShift);

-

-  /**

-   * @brief Correlation of floating-point sequences.

-   * @param[in] *pSrcA points to the first input sequence.

-   * @param[in] srcALen length of the first input sequence.

-   * @param[in] *pSrcB points to the second input sequence.

-   * @param[in] srcBLen length of the second input sequence.

-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.

-   * @return none.

-   */

-

-  void arm_correlate_f32(

-  float32_t * pSrcA,

-  uint32_t srcALen,

-  float32_t * pSrcB,

-  uint32_t srcBLen,

-  float32_t * pDst);

-

-

-   /**

-   * @brief Correlation of Q15 sequences

-   * @param[in] *pSrcA points to the first input sequence.

-   * @param[in] srcALen length of the first input sequence.

-   * @param[in] *pSrcB points to the second input sequence.

-   * @param[in] srcBLen length of the second input sequence.

-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.

-   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.

-   * @return none.

-   */

-  void arm_correlate_opt_q15(

-  q15_t * pSrcA,

-  uint32_t srcALen,

-  q15_t * pSrcB,

-  uint32_t srcBLen,

-  q15_t * pDst,

-  q15_t * pScratch);

-

-

-  /**

-   * @brief Correlation of Q15 sequences.

-   * @param[in] *pSrcA points to the first input sequence.

-   * @param[in] srcALen length of the first input sequence.

-   * @param[in] *pSrcB points to the second input sequence.

-   * @param[in] srcBLen length of the second input sequence.

-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.

-   * @return none.

-   */

-

-  void arm_correlate_q15(

-  q15_t * pSrcA,

-  uint32_t srcALen,

-  q15_t * pSrcB,

-  uint32_t srcBLen,

-  q15_t * pDst);

-

-  /**

-   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.

-   * @param[in] *pSrcA points to the first input sequence.

-   * @param[in] srcALen length of the first input sequence.

-   * @param[in] *pSrcB points to the second input sequence.

-   * @param[in] srcBLen length of the second input sequence.

-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.

-   * @return none.

-   */

-

-  void arm_correlate_fast_q15(

-  q15_t * pSrcA,

-  uint32_t srcALen,

-  q15_t * pSrcB,

-  uint32_t srcBLen,

-  q15_t * pDst);

-

-

-

-  /**

-   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.

-   * @param[in] *pSrcA points to the first input sequence.

-   * @param[in] srcALen length of the first input sequence.

-   * @param[in] *pSrcB points to the second input sequence.

-   * @param[in] srcBLen length of the second input sequence.

-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.

-   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.

-   * @return none.

-   */

-

-  void arm_correlate_fast_opt_q15(

-  q15_t * pSrcA,

-  uint32_t srcALen,

-  q15_t * pSrcB,

-  uint32_t srcBLen,

-  q15_t * pDst,

-  q15_t * pScratch);

-

-  /**

-   * @brief Correlation of Q31 sequences.

-   * @param[in] *pSrcA points to the first input sequence.

-   * @param[in] srcALen length of the first input sequence.

-   * @param[in] *pSrcB points to the second input sequence.

-   * @param[in] srcBLen length of the second input sequence.

-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.

-   * @return none.

-   */

-

-  void arm_correlate_q31(

-  q31_t * pSrcA,

-  uint32_t srcALen,

-  q31_t * pSrcB,

-  uint32_t srcBLen,

-  q31_t * pDst);

-

-  /**

-   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4

-   * @param[in] *pSrcA points to the first input sequence.

-   * @param[in] srcALen length of the first input sequence.

-   * @param[in] *pSrcB points to the second input sequence.

-   * @param[in] srcBLen length of the second input sequence.

-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.

-   * @return none.

-   */

-

-  void arm_correlate_fast_q31(

-  q31_t * pSrcA,

-  uint32_t srcALen,

-  q31_t * pSrcB,

-  uint32_t srcBLen,

-  q31_t * pDst);

-

-

-

- /**

-   * @brief Correlation of Q7 sequences.

-   * @param[in] *pSrcA points to the first input sequence.

-   * @param[in] srcALen length of the first input sequence.

-   * @param[in] *pSrcB points to the second input sequence.

-   * @param[in] srcBLen length of the second input sequence.

-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.

-   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.

-   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).

-   * @return none.

-   */

-

-  void arm_correlate_opt_q7(

-  q7_t * pSrcA,

-  uint32_t srcALen,

-  q7_t * pSrcB,

-  uint32_t srcBLen,

-  q7_t * pDst,

-  q15_t * pScratch1,

-  q15_t * pScratch2);

-

-

-  /**

-   * @brief Correlation of Q7 sequences.

-   * @param[in] *pSrcA points to the first input sequence.

-   * @param[in] srcALen length of the first input sequence.

-   * @param[in] *pSrcB points to the second input sequence.

-   * @param[in] srcBLen length of the second input sequence.

-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.

-   * @return none.

-   */

-

-  void arm_correlate_q7(

-  q7_t * pSrcA,

-  uint32_t srcALen,

-  q7_t * pSrcB,

-  uint32_t srcBLen,

-  q7_t * pDst);

-

-

-  /**

-   * @brief Instance structure for the floating-point sparse FIR filter.

-   */

-  typedef struct

-  {

-    uint16_t numTaps;             /**< number of coefficients in the filter. */

-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */

-    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */

-    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/

-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */

-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */

-  } arm_fir_sparse_instance_f32;

-

-  /**

-   * @brief Instance structure for the Q31 sparse FIR filter.

-   */

-

-  typedef struct

-  {

-    uint16_t numTaps;             /**< number of coefficients in the filter. */

-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */

-    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */

-    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/

-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */

-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */

-  } arm_fir_sparse_instance_q31;

-

-  /**

-   * @brief Instance structure for the Q15 sparse FIR filter.

-   */

-

-  typedef struct

-  {

-    uint16_t numTaps;             /**< number of coefficients in the filter. */

-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */

-    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */

-    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/

-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */

-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */

-  } arm_fir_sparse_instance_q15;

-

-  /**

-   * @brief Instance structure for the Q7 sparse FIR filter.

-   */

-

-  typedef struct

-  {

-    uint16_t numTaps;             /**< number of coefficients in the filter. */

-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */

-    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */

-    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/

-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */

-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */

-  } arm_fir_sparse_instance_q7;

-

-  /**

-   * @brief Processing function for the floating-point sparse FIR filter.

-   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.

-   * @param[in]  *pSrc       points to the block of input data.

-   * @param[out] *pDst       points to the block of output data

-   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.

-   * @param[in]  blockSize   number of input samples to process per call.

-   * @return none.

-   */

-

-  void arm_fir_sparse_f32(

-  arm_fir_sparse_instance_f32 * S,

-  float32_t * pSrc,

-  float32_t * pDst,

-  float32_t * pScratchIn,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Initialization function for the floating-point sparse FIR filter.

-   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.

-   * @param[in]     numTaps    number of nonzero coefficients in the filter.

-   * @param[in]     *pCoeffs   points to the array of filter coefficients.

-   * @param[in]     *pState    points to the state buffer.

-   * @param[in]     *pTapDelay points to the array of offset times.

-   * @param[in]     maxDelay   maximum offset time supported.

-   * @param[in]     blockSize  number of samples that will be processed per block.

-   * @return none

-   */

-

-  void arm_fir_sparse_init_f32(

-  arm_fir_sparse_instance_f32 * S,

-  uint16_t numTaps,

-  float32_t * pCoeffs,

-  float32_t * pState,

-  int32_t * pTapDelay,

-  uint16_t maxDelay,

-  uint32_t blockSize);

-

-  /**

-   * @brief Processing function for the Q31 sparse FIR filter.

-   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.

-   * @param[in]  *pSrc       points to the block of input data.

-   * @param[out] *pDst       points to the block of output data

-   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.

-   * @param[in]  blockSize   number of input samples to process per call.

-   * @return none.

-   */

-

-  void arm_fir_sparse_q31(

-  arm_fir_sparse_instance_q31 * S,

-  q31_t * pSrc,

-  q31_t * pDst,

-  q31_t * pScratchIn,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Initialization function for the Q31 sparse FIR filter.

-   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.

-   * @param[in]     numTaps    number of nonzero coefficients in the filter.

-   * @param[in]     *pCoeffs   points to the array of filter coefficients.

-   * @param[in]     *pState    points to the state buffer.

-   * @param[in]     *pTapDelay points to the array of offset times.

-   * @param[in]     maxDelay   maximum offset time supported.

-   * @param[in]     blockSize  number of samples that will be processed per block.

-   * @return none

-   */

-

-  void arm_fir_sparse_init_q31(

-  arm_fir_sparse_instance_q31 * S,

-  uint16_t numTaps,

-  q31_t * pCoeffs,

-  q31_t * pState,

-  int32_t * pTapDelay,

-  uint16_t maxDelay,

-  uint32_t blockSize);

-

-  /**

-   * @brief Processing function for the Q15 sparse FIR filter.

-   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.

-   * @param[in]  *pSrc        points to the block of input data.

-   * @param[out] *pDst        points to the block of output data

-   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.

-   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.

-   * @param[in]  blockSize    number of input samples to process per call.

-   * @return none.

-   */

-

-  void arm_fir_sparse_q15(

-  arm_fir_sparse_instance_q15 * S,

-  q15_t * pSrc,

-  q15_t * pDst,

-  q15_t * pScratchIn,

-  q31_t * pScratchOut,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Initialization function for the Q15 sparse FIR filter.

-   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.

-   * @param[in]     numTaps    number of nonzero coefficients in the filter.

-   * @param[in]     *pCoeffs   points to the array of filter coefficients.

-   * @param[in]     *pState    points to the state buffer.

-   * @param[in]     *pTapDelay points to the array of offset times.

-   * @param[in]     maxDelay   maximum offset time supported.

-   * @param[in]     blockSize  number of samples that will be processed per block.

-   * @return none

-   */

-

-  void arm_fir_sparse_init_q15(

-  arm_fir_sparse_instance_q15 * S,

-  uint16_t numTaps,

-  q15_t * pCoeffs,

-  q15_t * pState,

-  int32_t * pTapDelay,

-  uint16_t maxDelay,

-  uint32_t blockSize);

-

-  /**

-   * @brief Processing function for the Q7 sparse FIR filter.

-   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.

-   * @param[in]  *pSrc        points to the block of input data.

-   * @param[out] *pDst        points to the block of output data

-   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.

-   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.

-   * @param[in]  blockSize    number of input samples to process per call.

-   * @return none.

-   */

-

-  void arm_fir_sparse_q7(

-  arm_fir_sparse_instance_q7 * S,

-  q7_t * pSrc,

-  q7_t * pDst,

-  q7_t * pScratchIn,

-  q31_t * pScratchOut,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Initialization function for the Q7 sparse FIR filter.

-   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.

-   * @param[in]     numTaps    number of nonzero coefficients in the filter.

-   * @param[in]     *pCoeffs   points to the array of filter coefficients.

-   * @param[in]     *pState    points to the state buffer.

-   * @param[in]     *pTapDelay points to the array of offset times.

-   * @param[in]     maxDelay   maximum offset time supported.

-   * @param[in]     blockSize  number of samples that will be processed per block.

-   * @return none

-   */

-

-  void arm_fir_sparse_init_q7(

-  arm_fir_sparse_instance_q7 * S,

-  uint16_t numTaps,

-  q7_t * pCoeffs,

-  q7_t * pState,

-  int32_t * pTapDelay,

-  uint16_t maxDelay,

-  uint32_t blockSize);

-

-

-  /*

-   * @brief  Floating-point sin_cos function.

-   * @param[in]  theta    input value in degrees

-   * @param[out] *pSinVal points to the processed sine output.

-   * @param[out] *pCosVal points to the processed cos output.

-   * @return none.

-   */

-

-  void arm_sin_cos_f32(

-  float32_t theta,

-  float32_t * pSinVal,

-  float32_t * pCcosVal);

-

-  /*

-   * @brief  Q31 sin_cos function.

-   * @param[in]  theta    scaled input value in degrees

-   * @param[out] *pSinVal points to the processed sine output.

-   * @param[out] *pCosVal points to the processed cosine output.

-   * @return none.

-   */

-

-  void arm_sin_cos_q31(

-  q31_t theta,

-  q31_t * pSinVal,

-  q31_t * pCosVal);

-

-

-  /**

-   * @brief  Floating-point complex conjugate.

-   * @param[in]  *pSrc points to the input vector

-   * @param[out]  *pDst points to the output vector

-   * @param[in]  numSamples number of complex samples in each vector

-   * @return none.

-   */

-

-  void arm_cmplx_conj_f32(

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t numSamples);

-

-  /**

-   * @brief  Q31 complex conjugate.

-   * @param[in]  *pSrc points to the input vector

-   * @param[out]  *pDst points to the output vector

-   * @param[in]  numSamples number of complex samples in each vector

-   * @return none.

-   */

-

-  void arm_cmplx_conj_q31(

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t numSamples);

-

-  /**

-   * @brief  Q15 complex conjugate.

-   * @param[in]  *pSrc points to the input vector

-   * @param[out]  *pDst points to the output vector

-   * @param[in]  numSamples number of complex samples in each vector

-   * @return none.

-   */

-

-  void arm_cmplx_conj_q15(

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t numSamples);

-

-

-

-  /**

-   * @brief  Floating-point complex magnitude squared

-   * @param[in]  *pSrc points to the complex input vector

-   * @param[out]  *pDst points to the real output vector

-   * @param[in]  numSamples number of complex samples in the input vector

-   * @return none.

-   */

-

-  void arm_cmplx_mag_squared_f32(

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t numSamples);

-

-  /**

-   * @brief  Q31 complex magnitude squared

-   * @param[in]  *pSrc points to the complex input vector

-   * @param[out]  *pDst points to the real output vector

-   * @param[in]  numSamples number of complex samples in the input vector

-   * @return none.

-   */

-

-  void arm_cmplx_mag_squared_q31(

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t numSamples);

-

-  /**

-   * @brief  Q15 complex magnitude squared

-   * @param[in]  *pSrc points to the complex input vector

-   * @param[out]  *pDst points to the real output vector

-   * @param[in]  numSamples number of complex samples in the input vector

-   * @return none.

-   */

-

-  void arm_cmplx_mag_squared_q15(

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t numSamples);

-

-

- /**

-   * @ingroup groupController

-   */

-

-  /**

-   * @defgroup PID PID Motor Control

-   *

-   * A Proportional Integral Derivative (PID) controller is a generic feedback control

-   * loop mechanism widely used in industrial control systems.

-   * A PID controller is the most commonly used type of feedback controller.

-   *

-   * This set of functions implements (PID) controllers

-   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample

-   * of data and each call to the function returns a single processed value.

-   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>

-   * is the input sample value. The functions return the output value.

-   *

-   * \par Algorithm:

-   * <pre>

-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]

-   *    A0 = Kp + Ki + Kd

-   *    A1 = (-Kp ) - (2 * Kd )

-   *    A2 = Kd  </pre>

-   *

-   * \par

-   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant

-   *

-   * \par

-   * \image html PID.gif "Proportional Integral Derivative Controller"

-   *

-   * \par

-   * The PID controller calculates an "error" value as the difference between

-   * the measured output and the reference input.

-   * The controller attempts to minimize the error by adjusting the process control inputs.

-   * The proportional value determines the reaction to the current error,

-   * the integral value determines the reaction based on the sum of recent errors,

-   * and the derivative value determines the reaction based on the rate at which the error has been changing.

-   *

-   * \par Instance Structure

-   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.

-   * A separate instance structure must be defined for each PID Controller.

-   * There are separate instance structure declarations for each of the 3 supported data types.

-   *

-   * \par Reset Functions

-   * There is also an associated reset function for each data type which clears the state array.

-   *

-   * \par Initialization Functions

-   * There is also an associated initialization function for each data type.

-   * The initialization function performs the following operations:

-   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.

-   * - Zeros out the values in the state buffer.

-   *

-   * \par

-   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.

-   *

-   * \par Fixed-Point Behavior

-   * Care must be taken when using the fixed-point versions of the PID Controller functions.

-   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.

-   * Refer to the function specific documentation below for usage guidelines.

-   */

-

-  /**

-   * @addtogroup PID

-   * @{

-   */

-

-  /**

-   * @brief  Process function for the floating-point PID Control.

-   * @param[in,out] *S is an instance of the floating-point PID Control structure

-   * @param[in] in input sample to process

-   * @return out processed output sample.

-   */

-

-

-  static __INLINE float32_t arm_pid_f32(

-  arm_pid_instance_f32 * S,

-  float32_t in)

-  {

-    float32_t out;

-

-    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */

-    out = (S->A0 * in) +

-      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);

-

-    /* Update state */

-    S->state[1] = S->state[0];

-    S->state[0] = in;

-    S->state[2] = out;

-

-    /* return to application */

-    return (out);

-

-  }

-

-  /**

-   * @brief  Process function for the Q31 PID Control.

-   * @param[in,out] *S points to an instance of the Q31 PID Control structure

-   * @param[in] in input sample to process

-   * @return out processed output sample.

-   *

-   * <b>Scaling and Overflow Behavior:</b>

-   * \par

-   * The function is implemented using an internal 64-bit accumulator.

-   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.

-   * Thus, if the accumulator result overflows it wraps around rather than clip.

-   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.

-   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.

-   */

-

-  static __INLINE q31_t arm_pid_q31(

-  arm_pid_instance_q31 * S,

-  q31_t in)

-  {

-    q63_t acc;

-    q31_t out;

-

-    /* acc = A0 * x[n]  */

-    acc = (q63_t) S->A0 * in;

-

-    /* acc += A1 * x[n-1] */

-    acc += (q63_t) S->A1 * S->state[0];

-

-    /* acc += A2 * x[n-2]  */

-    acc += (q63_t) S->A2 * S->state[1];

-

-    /* convert output to 1.31 format to add y[n-1] */

-    out = (q31_t) (acc >> 31u);

-

-    /* out += y[n-1] */

-    out += S->state[2];

-

-    /* Update state */

-    S->state[1] = S->state[0];

-    S->state[0] = in;

-    S->state[2] = out;

-

-    /* return to application */

-    return (out);

-

-  }

-

-  /**

-   * @brief  Process function for the Q15 PID Control.

-   * @param[in,out] *S points to an instance of the Q15 PID Control structure

-   * @param[in] in input sample to process

-   * @return out processed output sample.

-   *

-   * <b>Scaling and Overflow Behavior:</b>

-   * \par

-   * The function is implemented using a 64-bit internal accumulator.

-   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.

-   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.

-   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.

-   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.

-   * Lastly, the accumulator is saturated to yield a result in 1.15 format.

-   */

-

-  static __INLINE q15_t arm_pid_q15(

-  arm_pid_instance_q15 * S,

-  q15_t in)

-  {

-    q63_t acc;

-    q15_t out;

-

-#ifndef ARM_MATH_CM0_FAMILY

-    __SIMD32_TYPE *vstate;

-

-    /* Implementation of PID controller */

-

-    /* acc = A0 * x[n]  */

-    acc = (q31_t) __SMUAD(S->A0, in);

-

-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */

-    vstate = __SIMD32_CONST(S->state);

-    acc = __SMLALD(S->A1, (q31_t) *vstate, acc);

-

-#else

-    /* acc = A0 * x[n]  */

-    acc = ((q31_t) S->A0) * in;

-

-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */

-    acc += (q31_t) S->A1 * S->state[0];

-    acc += (q31_t) S->A2 * S->state[1];

-

-#endif

-

-    /* acc += y[n-1] */

-    acc += (q31_t) S->state[2] << 15;

-

-    /* saturate the output */

-    out = (q15_t) (__SSAT((acc >> 15), 16));

-

-    /* Update state */

-    S->state[1] = S->state[0];

-    S->state[0] = in;

-    S->state[2] = out;

-

-    /* return to application */

-    return (out);

-

-  }

-

-  /**

-   * @} end of PID group

-   */

-

-

-  /**

-   * @brief Floating-point matrix inverse.

-   * @param[in]  *src points to the instance of the input floating-point matrix structure.

-   * @param[out] *dst points to the instance of the output floating-point matrix structure.

-   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.

-   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.

-   */

-

-  arm_status arm_mat_inverse_f32(

-  const arm_matrix_instance_f32 * src,

-  arm_matrix_instance_f32 * dst);

-

-

-  /**

-   * @brief Floating-point matrix inverse.

-   * @param[in]  *src points to the instance of the input floating-point matrix structure.

-   * @param[out] *dst points to the instance of the output floating-point matrix structure.

-   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.

-   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.

-   */

-

-  arm_status arm_mat_inverse_f64(

-  const arm_matrix_instance_f64 * src,

-  arm_matrix_instance_f64 * dst);

-

-

-

-  /**

-   * @ingroup groupController

-   */

-

-

-  /**

-   * @defgroup clarke Vector Clarke Transform

-   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.

-   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents

-   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.

-   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below

-   * \image html clarke.gif Stator current space vector and its components in (a,b).

-   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>

-   * can be calculated using only <code>Ia</code> and <code>Ib</code>.

-   *

-   * The function operates on a single sample of data and each call to the function returns the processed output.

-   * The library provides separate functions for Q31 and floating-point data types.

-   * \par Algorithm

-   * \image html clarkeFormula.gif

-   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and

-   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.

-   * \par Fixed-Point Behavior

-   * Care must be taken when using the Q31 version of the Clarke transform.

-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.

-   * Refer to the function specific documentation below for usage guidelines.

-   */

-

-  /**

-   * @addtogroup clarke

-   * @{

-   */

-

-  /**

-   *

-   * @brief  Floating-point Clarke transform

-   * @param[in]       Ia       input three-phase coordinate <code>a</code>

-   * @param[in]       Ib       input three-phase coordinate <code>b</code>

-   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha

-   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta

-   * @return none.

-   */

-

-  static __INLINE void arm_clarke_f32(

-  float32_t Ia,

-  float32_t Ib,

-  float32_t * pIalpha,

-  float32_t * pIbeta)

-  {

-    /* Calculate pIalpha using the equation, pIalpha = Ia */

-    *pIalpha = Ia;

-

-    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */

-    *pIbeta =

-      ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);

-

-  }

-

-  /**

-   * @brief  Clarke transform for Q31 version

-   * @param[in]       Ia       input three-phase coordinate <code>a</code>

-   * @param[in]       Ib       input three-phase coordinate <code>b</code>

-   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha

-   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta

-   * @return none.

-   *

-   * <b>Scaling and Overflow Behavior:</b>

-   * \par

-   * The function is implemented using an internal 32-bit accumulator.

-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.

-   * There is saturation on the addition, hence there is no risk of overflow.

-   */

-

-  static __INLINE void arm_clarke_q31(

-  q31_t Ia,

-  q31_t Ib,

-  q31_t * pIalpha,

-  q31_t * pIbeta)

-  {

-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */

-

-    /* Calculating pIalpha from Ia by equation pIalpha = Ia */

-    *pIalpha = Ia;

-

-    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */

-    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);

-

-    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */

-    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);

-

-    /* pIbeta is calculated by adding the intermediate products */

-    *pIbeta = __QADD(product1, product2);

-  }

-

-  /**

-   * @} end of clarke group

-   */

-

-  /**

-   * @brief  Converts the elements of the Q7 vector to Q31 vector.

-   * @param[in]  *pSrc     input pointer

-   * @param[out]  *pDst    output pointer

-   * @param[in]  blockSize number of samples to process

-   * @return none.

-   */

-  void arm_q7_to_q31(

-  q7_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-

-

-

-  /**

-   * @ingroup groupController

-   */

-

-  /**

-   * @defgroup inv_clarke Vector Inverse Clarke Transform

-   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.

-   *

-   * The function operates on a single sample of data and each call to the function returns the processed output.

-   * The library provides separate functions for Q31 and floating-point data types.

-   * \par Algorithm

-   * \image html clarkeInvFormula.gif

-   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and

-   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.

-   * \par Fixed-Point Behavior

-   * Care must be taken when using the Q31 version of the Clarke transform.

-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.

-   * Refer to the function specific documentation below for usage guidelines.

-   */

-

-  /**

-   * @addtogroup inv_clarke

-   * @{

-   */

-

-   /**

-   * @brief  Floating-point Inverse Clarke transform

-   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha

-   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta

-   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>

-   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>

-   * @return none.

-   */

-

-

-  static __INLINE void arm_inv_clarke_f32(

-  float32_t Ialpha,

-  float32_t Ibeta,

-  float32_t * pIa,

-  float32_t * pIb)

-  {

-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */

-    *pIa = Ialpha;

-

-    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */

-    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;

-

-  }

-

-  /**

-   * @brief  Inverse Clarke transform for Q31 version

-   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha

-   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta

-   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>

-   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>

-   * @return none.

-   *

-   * <b>Scaling and Overflow Behavior:</b>

-   * \par

-   * The function is implemented using an internal 32-bit accumulator.

-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.

-   * There is saturation on the subtraction, hence there is no risk of overflow.

-   */

-

-  static __INLINE void arm_inv_clarke_q31(

-  q31_t Ialpha,

-  q31_t Ibeta,

-  q31_t * pIa,

-  q31_t * pIb)

-  {

-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */

-

-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */

-    *pIa = Ialpha;

-

-    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */

-    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);

-

-    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */

-    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);

-

-    /* pIb is calculated by subtracting the products */

-    *pIb = __QSUB(product2, product1);

-

-  }

-

-  /**

-   * @} end of inv_clarke group

-   */

-

-  /**

-   * @brief  Converts the elements of the Q7 vector to Q15 vector.

-   * @param[in]  *pSrc     input pointer

-   * @param[out] *pDst     output pointer

-   * @param[in]  blockSize number of samples to process

-   * @return none.

-   */

-  void arm_q7_to_q15(

-  q7_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-

-

-  /**

-   * @ingroup groupController

-   */

-

-  /**

-   * @defgroup park Vector Park Transform

-   *

-   * Forward Park transform converts the input two-coordinate vector to flux and torque components.

-   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents

-   * from the stationary to the moving reference frame and control the spatial relationship between

-   * the stator vector current and rotor flux vector.

-   * If we consider the d axis aligned with the rotor flux, the diagram below shows the

-   * current vector and the relationship from the two reference frames:

-   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"

-   *

-   * The function operates on a single sample of data and each call to the function returns the processed output.

-   * The library provides separate functions for Q31 and floating-point data types.

-   * \par Algorithm

-   * \image html parkFormula.gif

-   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,

-   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the

-   * cosine and sine values of theta (rotor flux position).

-   * \par Fixed-Point Behavior

-   * Care must be taken when using the Q31 version of the Park transform.

-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.

-   * Refer to the function specific documentation below for usage guidelines.

-   */

-

-  /**

-   * @addtogroup park

-   * @{

-   */

-

-  /**

-   * @brief Floating-point Park transform

-   * @param[in]       Ialpha input two-phase vector coordinate alpha

-   * @param[in]       Ibeta  input two-phase vector coordinate beta

-   * @param[out]      *pId   points to output  rotor reference frame d

-   * @param[out]      *pIq   points to output  rotor reference frame q

-   * @param[in]       sinVal sine value of rotation angle theta

-   * @param[in]       cosVal cosine value of rotation angle theta

-   * @return none.

-   *

-   * The function implements the forward Park transform.

-   *

-   */

-

-  static __INLINE void arm_park_f32(

-  float32_t Ialpha,

-  float32_t Ibeta,

-  float32_t * pId,

-  float32_t * pIq,

-  float32_t sinVal,

-  float32_t cosVal)

-  {

-    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */

-    *pId = Ialpha * cosVal + Ibeta * sinVal;

-

-    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */

-    *pIq = -Ialpha * sinVal + Ibeta * cosVal;

-

-  }

-

-  /**

-   * @brief  Park transform for Q31 version

-   * @param[in]       Ialpha input two-phase vector coordinate alpha

-   * @param[in]       Ibeta  input two-phase vector coordinate beta

-   * @param[out]      *pId   points to output rotor reference frame d

-   * @param[out]      *pIq   points to output rotor reference frame q

-   * @param[in]       sinVal sine value of rotation angle theta

-   * @param[in]       cosVal cosine value of rotation angle theta

-   * @return none.

-   *

-   * <b>Scaling and Overflow Behavior:</b>

-   * \par

-   * The function is implemented using an internal 32-bit accumulator.

-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.

-   * There is saturation on the addition and subtraction, hence there is no risk of overflow.

-   */

-

-

-  static __INLINE void arm_park_q31(

-  q31_t Ialpha,

-  q31_t Ibeta,

-  q31_t * pId,

-  q31_t * pIq,

-  q31_t sinVal,

-  q31_t cosVal)

-  {

-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */

-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */

-

-    /* Intermediate product is calculated by (Ialpha * cosVal) */

-    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);

-

-    /* Intermediate product is calculated by (Ibeta * sinVal) */

-    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);

-

-

-    /* Intermediate product is calculated by (Ialpha * sinVal) */

-    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);

-

-    /* Intermediate product is calculated by (Ibeta * cosVal) */

-    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);

-

-    /* Calculate pId by adding the two intermediate products 1 and 2 */

-    *pId = __QADD(product1, product2);

-

-    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */

-    *pIq = __QSUB(product4, product3);

-  }

-

-  /**

-   * @} end of park group

-   */

-

-  /**

-   * @brief  Converts the elements of the Q7 vector to floating-point vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[out]  *pDst is output pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @return none.

-   */

-  void arm_q7_to_float(

-  q7_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @ingroup groupController

-   */

-

-  /**

-   * @defgroup inv_park Vector Inverse Park transform

-   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.

-   *

-   * The function operates on a single sample of data and each call to the function returns the processed output.

-   * The library provides separate functions for Q31 and floating-point data types.

-   * \par Algorithm

-   * \image html parkInvFormula.gif

-   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,

-   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the

-   * cosine and sine values of theta (rotor flux position).

-   * \par Fixed-Point Behavior

-   * Care must be taken when using the Q31 version of the Park transform.

-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.

-   * Refer to the function specific documentation below for usage guidelines.

-   */

-

-  /**

-   * @addtogroup inv_park

-   * @{

-   */

-

-   /**

-   * @brief  Floating-point Inverse Park transform

-   * @param[in]       Id        input coordinate of rotor reference frame d

-   * @param[in]       Iq        input coordinate of rotor reference frame q

-   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha

-   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta

-   * @param[in]       sinVal    sine value of rotation angle theta

-   * @param[in]       cosVal    cosine value of rotation angle theta

-   * @return none.

-   */

-

-  static __INLINE void arm_inv_park_f32(

-  float32_t Id,

-  float32_t Iq,

-  float32_t * pIalpha,

-  float32_t * pIbeta,

-  float32_t sinVal,

-  float32_t cosVal)

-  {

-    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */

-    *pIalpha = Id * cosVal - Iq * sinVal;

-

-    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */

-    *pIbeta = Id * sinVal + Iq * cosVal;

-

-  }

-

-

-  /**

-   * @brief  Inverse Park transform for Q31 version

-   * @param[in]       Id        input coordinate of rotor reference frame d

-   * @param[in]       Iq        input coordinate of rotor reference frame q

-   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha

-   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta

-   * @param[in]       sinVal    sine value of rotation angle theta

-   * @param[in]       cosVal    cosine value of rotation angle theta

-   * @return none.

-   *

-   * <b>Scaling and Overflow Behavior:</b>

-   * \par

-   * The function is implemented using an internal 32-bit accumulator.

-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.

-   * There is saturation on the addition, hence there is no risk of overflow.

-   */

-

-

-  static __INLINE void arm_inv_park_q31(

-  q31_t Id,

-  q31_t Iq,

-  q31_t * pIalpha,

-  q31_t * pIbeta,

-  q31_t sinVal,

-  q31_t cosVal)

-  {

-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */

-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */

-

-    /* Intermediate product is calculated by (Id * cosVal) */

-    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);

-

-    /* Intermediate product is calculated by (Iq * sinVal) */

-    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);

-

-

-    /* Intermediate product is calculated by (Id * sinVal) */

-    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);

-

-    /* Intermediate product is calculated by (Iq * cosVal) */

-    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);

-

-    /* Calculate pIalpha by using the two intermediate products 1 and 2 */

-    *pIalpha = __QSUB(product1, product2);

-

-    /* Calculate pIbeta by using the two intermediate products 3 and 4 */

-    *pIbeta = __QADD(product4, product3);

-

-  }

-

-  /**

-   * @} end of Inverse park group

-   */

-

-

-  /**

-   * @brief  Converts the elements of the Q31 vector to floating-point vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[out]  *pDst is output pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @return none.

-   */

-  void arm_q31_to_float(

-  q31_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @ingroup groupInterpolation

-   */

-

-  /**

-   * @defgroup LinearInterpolate Linear Interpolation

-   *

-   * Linear interpolation is a method of curve fitting using linear polynomials.

-   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line

-   *

-   * \par

-   * \image html LinearInterp.gif "Linear interpolation"

-   *

-   * \par

-   * A  Linear Interpolate function calculates an output value(y), for the input(x)

-   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)

-   *

-   * \par Algorithm:

-   * <pre>

-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))

-   *       where x0, x1 are nearest values of input x

-   *             y0, y1 are nearest values to output y

-   * </pre>

-   *

-   * \par

-   * This set of functions implements Linear interpolation process

-   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single

-   * sample of data and each call to the function returns a single processed value.

-   * <code>S</code> points to an instance of the Linear Interpolate function data structure.

-   * <code>x</code> is the input sample value. The functions returns the output value.

-   *

-   * \par

-   * if x is outside of the table boundary, Linear interpolation returns first value of the table

-   * if x is below input range and returns last value of table if x is above range.

-   */

-

-  /**

-   * @addtogroup LinearInterpolate

-   * @{

-   */

-

-  /**

-   * @brief  Process function for the floating-point Linear Interpolation Function.

-   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure

-   * @param[in] x input sample to process

-   * @return y processed output sample.

-   *

-   */

-

-  static __INLINE float32_t arm_linear_interp_f32(

-  arm_linear_interp_instance_f32 * S,

-  float32_t x)

-  {

-

-    float32_t y;

-    float32_t x0, x1;                            /* Nearest input values */

-    float32_t y0, y1;                            /* Nearest output values */

-    float32_t xSpacing = S->xSpacing;            /* spacing between input values */

-    int32_t i;                                   /* Index variable */

-    float32_t *pYData = S->pYData;               /* pointer to output table */

-

-    /* Calculation of index */

-    i = (int32_t) ((x - S->x1) / xSpacing);

-

-    if(i < 0)

-    {

-      /* Iniatilize output for below specified range as least output value of table */

-      y = pYData[0];

-    }

-    else if((uint32_t)i >= S->nValues)

-    {

-      /* Iniatilize output for above specified range as last output value of table */

-      y = pYData[S->nValues - 1];

-    }

-    else

-    {

-      /* Calculation of nearest input values */

-      x0 = S->x1 + i * xSpacing;

-      x1 = S->x1 + (i + 1) * xSpacing;

-

-      /* Read of nearest output values */

-      y0 = pYData[i];

-      y1 = pYData[i + 1];

-

-      /* Calculation of output */

-      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));

-

-    }

-

-    /* returns output value */

-    return (y);

-  }

-

-   /**

-   *

-   * @brief  Process function for the Q31 Linear Interpolation Function.

-   * @param[in] *pYData  pointer to Q31 Linear Interpolation table

-   * @param[in] x input sample to process

-   * @param[in] nValues number of table values

-   * @return y processed output sample.

-   *

-   * \par

-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.

-   * This function can support maximum of table size 2^12.

-   *

-   */

-

-

-  static __INLINE q31_t arm_linear_interp_q31(

-  q31_t * pYData,

-  q31_t x,

-  uint32_t nValues)

-  {

-    q31_t y;                                     /* output */

-    q31_t y0, y1;                                /* Nearest output values */

-    q31_t fract;                                 /* fractional part */

-    int32_t index;                               /* Index to read nearest output values */

-

-    /* Input is in 12.20 format */

-    /* 12 bits for the table index */

-    /* Index value calculation */

-    index = ((x & 0xFFF00000) >> 20);

-

-    if(index >= (int32_t)(nValues - 1))

-    {

-      return (pYData[nValues - 1]);

-    }

-    else if(index < 0)

-    {

-      return (pYData[0]);

-    }

-    else

-    {

-

-      /* 20 bits for the fractional part */

-      /* shift left by 11 to keep fract in 1.31 format */

-      fract = (x & 0x000FFFFF) << 11;

-

-      /* Read two nearest output values from the index in 1.31(q31) format */

-      y0 = pYData[index];

-      y1 = pYData[index + 1u];

-

-      /* Calculation of y0 * (1-fract) and y is in 2.30 format */

-      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));

-

-      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */

-      y += ((q31_t) (((q63_t) y1 * fract) >> 32));

-

-      /* Convert y to 1.31 format */

-      return (y << 1u);

-

-    }

-

-  }

-

-  /**

-   *

-   * @brief  Process function for the Q15 Linear Interpolation Function.

-   * @param[in] *pYData  pointer to Q15 Linear Interpolation table

-   * @param[in] x input sample to process

-   * @param[in] nValues number of table values

-   * @return y processed output sample.

-   *

-   * \par

-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.

-   * This function can support maximum of table size 2^12.

-   *

-   */

-

-

-  static __INLINE q15_t arm_linear_interp_q15(

-  q15_t * pYData,

-  q31_t x,

-  uint32_t nValues)

-  {

-    q63_t y;                                     /* output */

-    q15_t y0, y1;                                /* Nearest output values */

-    q31_t fract;                                 /* fractional part */

-    int32_t index;                               /* Index to read nearest output values */

-

-    /* Input is in 12.20 format */

-    /* 12 bits for the table index */

-    /* Index value calculation */

-    index = ((x & 0xFFF00000) >> 20u);

-

-    if(index >= (int32_t)(nValues - 1))

-    {

-      return (pYData[nValues - 1]);

-    }

-    else if(index < 0)

-    {

-      return (pYData[0]);

-    }

-    else

-    {

-      /* 20 bits for the fractional part */

-      /* fract is in 12.20 format */

-      fract = (x & 0x000FFFFF);

-

-      /* Read two nearest output values from the index */

-      y0 = pYData[index];

-      y1 = pYData[index + 1u];

-

-      /* Calculation of y0 * (1-fract) and y is in 13.35 format */

-      y = ((q63_t) y0 * (0xFFFFF - fract));

-

-      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */

-      y += ((q63_t) y1 * (fract));

-

-      /* convert y to 1.15 format */

-      return (y >> 20);

-    }

-

-

-  }

-

-  /**

-   *

-   * @brief  Process function for the Q7 Linear Interpolation Function.

-   * @param[in] *pYData  pointer to Q7 Linear Interpolation table

-   * @param[in] x input sample to process

-   * @param[in] nValues number of table values

-   * @return y processed output sample.

-   *

-   * \par

-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.

-   * This function can support maximum of table size 2^12.

-   */

-

-

-  static __INLINE q7_t arm_linear_interp_q7(

-  q7_t * pYData,

-  q31_t x,

-  uint32_t nValues)

-  {

-    q31_t y;                                     /* output */

-    q7_t y0, y1;                                 /* Nearest output values */

-    q31_t fract;                                 /* fractional part */

-    uint32_t index;                              /* Index to read nearest output values */

-

-    /* Input is in 12.20 format */

-    /* 12 bits for the table index */

-    /* Index value calculation */

-    if (x < 0)

-    {

-      return (pYData[0]);

-    }

-    index = (x >> 20) & 0xfff;

-

-

-    if(index >= (nValues - 1))

-    {

-      return (pYData[nValues - 1]);

-    }

-    else

-    {

-

-      /* 20 bits for the fractional part */

-      /* fract is in 12.20 format */

-      fract = (x & 0x000FFFFF);

-

-      /* Read two nearest output values from the index and are in 1.7(q7) format */

-      y0 = pYData[index];

-      y1 = pYData[index + 1u];

-

-      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */

-      y = ((y0 * (0xFFFFF - fract)));

-

-      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */

-      y += (y1 * fract);

-

-      /* convert y to 1.7(q7) format */

-      return (y >> 20u);

-

-    }

-

-  }

-  /**

-   * @} end of LinearInterpolate group

-   */

-

-  /**

-   * @brief  Fast approximation to the trigonometric sine function for floating-point data.

-   * @param[in] x input value in radians.

-   * @return  sin(x).

-   */

-

-  float32_t arm_sin_f32(

-  float32_t x);

-

-  /**

-   * @brief  Fast approximation to the trigonometric sine function for Q31 data.

-   * @param[in] x Scaled input value in radians.

-   * @return  sin(x).

-   */

-

-  q31_t arm_sin_q31(

-  q31_t x);

-

-  /**

-   * @brief  Fast approximation to the trigonometric sine function for Q15 data.

-   * @param[in] x Scaled input value in radians.

-   * @return  sin(x).

-   */

-

-  q15_t arm_sin_q15(

-  q15_t x);

-

-  /**

-   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.

-   * @param[in] x input value in radians.

-   * @return  cos(x).

-   */

-

-  float32_t arm_cos_f32(

-  float32_t x);

-

-  /**

-   * @brief Fast approximation to the trigonometric cosine function for Q31 data.

-   * @param[in] x Scaled input value in radians.

-   * @return  cos(x).

-   */

-

-  q31_t arm_cos_q31(

-  q31_t x);

-

-  /**

-   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.

-   * @param[in] x Scaled input value in radians.

-   * @return  cos(x).

-   */

-

-  q15_t arm_cos_q15(

-  q15_t x);

-

-

-  /**

-   * @ingroup groupFastMath

-   */

-

-

-  /**

-   * @defgroup SQRT Square Root

-   *

-   * Computes the square root of a number.

-   * There are separate functions for Q15, Q31, and floating-point data types.

-   * The square root function is computed using the Newton-Raphson algorithm.

-   * This is an iterative algorithm of the form:

-   * <pre>

-   *      x1 = x0 - f(x0)/f'(x0)

-   * </pre>

-   * where <code>x1</code> is the current estimate,

-   * <code>x0</code> is the previous estimate, and

-   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.

-   * For the square root function, the algorithm reduces to:

-   * <pre>

-   *     x0 = in/2                         [initial guess]

-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]

-   * </pre>

-   */

-

-

-  /**

-   * @addtogroup SQRT

-   * @{

-   */

-

-  /**

-   * @brief  Floating-point square root function.

-   * @param[in]  in     input value.

-   * @param[out] *pOut  square root of input value.

-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if

-   * <code>in</code> is negative value and returns zero output for negative values.

-   */

-

-  static __INLINE arm_status arm_sqrt_f32(

-  float32_t in,

-  float32_t * pOut)

-  {

-    if(in > 0)

-    {

-

-//      #if __FPU_USED

-#if (__FPU_USED == 1) && defined ( __CC_ARM   )

-      *pOut = __sqrtf(in);

-#else

-      *pOut = sqrtf(in);

-#endif

-

-      return (ARM_MATH_SUCCESS);

-    }

-    else

-    {

-      *pOut = 0.0f;

-      return (ARM_MATH_ARGUMENT_ERROR);

-    }

-

-  }

-

-

-  /**

-   * @brief Q31 square root function.

-   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.

-   * @param[out]  *pOut square root of input value.

-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if

-   * <code>in</code> is negative value and returns zero output for negative values.

-   */

-  arm_status arm_sqrt_q31(

-  q31_t in,

-  q31_t * pOut);

-

-  /**

-   * @brief  Q15 square root function.

-   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.

-   * @param[out]  *pOut  square root of input value.

-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if

-   * <code>in</code> is negative value and returns zero output for negative values.

-   */

-  arm_status arm_sqrt_q15(

-  q15_t in,

-  q15_t * pOut);

-

-  /**

-   * @} end of SQRT group

-   */

-

-

-

-

-

-

-  /**

-   * @brief floating-point Circular write function.

-   */

-

-  static __INLINE void arm_circularWrite_f32(

-  int32_t * circBuffer,

-  int32_t L,

-  uint16_t * writeOffset,

-  int32_t bufferInc,

-  const int32_t * src,

-  int32_t srcInc,

-  uint32_t blockSize)

-  {

-    uint32_t i = 0u;

-    int32_t wOffset;

-

-    /* Copy the value of Index pointer that points

-     * to the current location where the input samples to be copied */

-    wOffset = *writeOffset;

-

-    /* Loop over the blockSize */

-    i = blockSize;

-

-    while(i > 0u)

-    {

-      /* copy the input sample to the circular buffer */

-      circBuffer[wOffset] = *src;

-

-      /* Update the input pointer */

-      src += srcInc;

-

-      /* Circularly update wOffset.  Watch out for positive and negative value */

-      wOffset += bufferInc;

-      if(wOffset >= L)

-        wOffset -= L;

-

-      /* Decrement the loop counter */

-      i--;

-    }

-

-    /* Update the index pointer */

-    *writeOffset = wOffset;

-  }

-

-

-

-  /**

-   * @brief floating-point Circular Read function.

-   */

-  static __INLINE void arm_circularRead_f32(

-  int32_t * circBuffer,

-  int32_t L,

-  int32_t * readOffset,

-  int32_t bufferInc,

-  int32_t * dst,

-  int32_t * dst_base,

-  int32_t dst_length,

-  int32_t dstInc,

-  uint32_t blockSize)

-  {

-    uint32_t i = 0u;

-    int32_t rOffset, dst_end;

-

-    /* Copy the value of Index pointer that points

-     * to the current location from where the input samples to be read */

-    rOffset = *readOffset;

-    dst_end = (int32_t) (dst_base + dst_length);

-

-    /* Loop over the blockSize */

-    i = blockSize;

-

-    while(i > 0u)

-    {

-      /* copy the sample from the circular buffer to the destination buffer */

-      *dst = circBuffer[rOffset];

-

-      /* Update the input pointer */

-      dst += dstInc;

-

-      if(dst == (int32_t *) dst_end)

-      {

-        dst = dst_base;

-      }

-

-      /* Circularly update rOffset.  Watch out for positive and negative value  */

-      rOffset += bufferInc;

-

-      if(rOffset >= L)

-      {

-        rOffset -= L;

-      }

-

-      /* Decrement the loop counter */

-      i--;

-    }

-

-    /* Update the index pointer */

-    *readOffset = rOffset;

-  }

-

-  /**

-   * @brief Q15 Circular write function.

-   */

-

-  static __INLINE void arm_circularWrite_q15(

-  q15_t * circBuffer,

-  int32_t L,

-  uint16_t * writeOffset,

-  int32_t bufferInc,

-  const q15_t * src,

-  int32_t srcInc,

-  uint32_t blockSize)

-  {

-    uint32_t i = 0u;

-    int32_t wOffset;

-

-    /* Copy the value of Index pointer that points

-     * to the current location where the input samples to be copied */

-    wOffset = *writeOffset;

-

-    /* Loop over the blockSize */

-    i = blockSize;

-

-    while(i > 0u)

-    {

-      /* copy the input sample to the circular buffer */

-      circBuffer[wOffset] = *src;

-

-      /* Update the input pointer */

-      src += srcInc;

-

-      /* Circularly update wOffset.  Watch out for positive and negative value */

-      wOffset += bufferInc;

-      if(wOffset >= L)

-        wOffset -= L;

-

-      /* Decrement the loop counter */

-      i--;

-    }

-

-    /* Update the index pointer */

-    *writeOffset = wOffset;

-  }

-

-

-

-  /**

-   * @brief Q15 Circular Read function.

-   */

-  static __INLINE void arm_circularRead_q15(

-  q15_t * circBuffer,

-  int32_t L,

-  int32_t * readOffset,

-  int32_t bufferInc,

-  q15_t * dst,

-  q15_t * dst_base,

-  int32_t dst_length,

-  int32_t dstInc,

-  uint32_t blockSize)

-  {

-    uint32_t i = 0;

-    int32_t rOffset, dst_end;

-

-    /* Copy the value of Index pointer that points

-     * to the current location from where the input samples to be read */

-    rOffset = *readOffset;

-

-    dst_end = (int32_t) (dst_base + dst_length);

-

-    /* Loop over the blockSize */

-    i = blockSize;

-

-    while(i > 0u)

-    {

-      /* copy the sample from the circular buffer to the destination buffer */

-      *dst = circBuffer[rOffset];

-

-      /* Update the input pointer */

-      dst += dstInc;

-

-      if(dst == (q15_t *) dst_end)

-      {

-        dst = dst_base;

-      }

-

-      /* Circularly update wOffset.  Watch out for positive and negative value */

-      rOffset += bufferInc;

-

-      if(rOffset >= L)

-      {

-        rOffset -= L;

-      }

-

-      /* Decrement the loop counter */

-      i--;

-    }

-

-    /* Update the index pointer */

-    *readOffset = rOffset;

-  }

-

-

-  /**

-   * @brief Q7 Circular write function.

-   */

-

-  static __INLINE void arm_circularWrite_q7(

-  q7_t * circBuffer,

-  int32_t L,

-  uint16_t * writeOffset,

-  int32_t bufferInc,

-  const q7_t * src,

-  int32_t srcInc,

-  uint32_t blockSize)

-  {

-    uint32_t i = 0u;

-    int32_t wOffset;

-

-    /* Copy the value of Index pointer that points

-     * to the current location where the input samples to be copied */

-    wOffset = *writeOffset;

-

-    /* Loop over the blockSize */

-    i = blockSize;

-

-    while(i > 0u)

-    {

-      /* copy the input sample to the circular buffer */

-      circBuffer[wOffset] = *src;

-

-      /* Update the input pointer */

-      src += srcInc;

-

-      /* Circularly update wOffset.  Watch out for positive and negative value */

-      wOffset += bufferInc;

-      if(wOffset >= L)

-        wOffset -= L;

-

-      /* Decrement the loop counter */

-      i--;

-    }

-

-    /* Update the index pointer */

-    *writeOffset = wOffset;

-  }

-

-

-

-  /**

-   * @brief Q7 Circular Read function.

-   */

-  static __INLINE void arm_circularRead_q7(

-  q7_t * circBuffer,

-  int32_t L,

-  int32_t * readOffset,

-  int32_t bufferInc,

-  q7_t * dst,

-  q7_t * dst_base,

-  int32_t dst_length,

-  int32_t dstInc,

-  uint32_t blockSize)

-  {

-    uint32_t i = 0;

-    int32_t rOffset, dst_end;

-

-    /* Copy the value of Index pointer that points

-     * to the current location from where the input samples to be read */

-    rOffset = *readOffset;

-

-    dst_end = (int32_t) (dst_base + dst_length);

-

-    /* Loop over the blockSize */

-    i = blockSize;

-

-    while(i > 0u)

-    {

-      /* copy the sample from the circular buffer to the destination buffer */

-      *dst = circBuffer[rOffset];

-

-      /* Update the input pointer */

-      dst += dstInc;

-

-      if(dst == (q7_t *) dst_end)

-      {

-        dst = dst_base;

-      }

-

-      /* Circularly update rOffset.  Watch out for positive and negative value */

-      rOffset += bufferInc;

-

-      if(rOffset >= L)

-      {

-        rOffset -= L;

-      }

-

-      /* Decrement the loop counter */

-      i--;

-    }

-

-    /* Update the index pointer */

-    *readOffset = rOffset;

-  }

-

-

-  /**

-   * @brief  Sum of the squares of the elements of a Q31 vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @param[out]  *pResult is output value.

-   * @return none.

-   */

-

-  void arm_power_q31(

-  q31_t * pSrc,

-  uint32_t blockSize,

-  q63_t * pResult);

-

-  /**

-   * @brief  Sum of the squares of the elements of a floating-point vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @param[out]  *pResult is output value.

-   * @return none.

-   */

-

-  void arm_power_f32(

-  float32_t * pSrc,

-  uint32_t blockSize,

-  float32_t * pResult);

-

-  /**

-   * @brief  Sum of the squares of the elements of a Q15 vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @param[out]  *pResult is output value.

-   * @return none.

-   */

-

-  void arm_power_q15(

-  q15_t * pSrc,

-  uint32_t blockSize,

-  q63_t * pResult);

-

-  /**

-   * @brief  Sum of the squares of the elements of a Q7 vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @param[out]  *pResult is output value.

-   * @return none.

-   */

-

-  void arm_power_q7(

-  q7_t * pSrc,

-  uint32_t blockSize,

-  q31_t * pResult);

-

-  /**

-   * @brief  Mean value of a Q7 vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @param[out]  *pResult is output value.

-   * @return none.

-   */

-

-  void arm_mean_q7(

-  q7_t * pSrc,

-  uint32_t blockSize,

-  q7_t * pResult);

-

-  /**

-   * @brief  Mean value of a Q15 vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @param[out]  *pResult is output value.

-   * @return none.

-   */

-  void arm_mean_q15(

-  q15_t * pSrc,

-  uint32_t blockSize,

-  q15_t * pResult);

-

-  /**

-   * @brief  Mean value of a Q31 vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @param[out]  *pResult is output value.

-   * @return none.

-   */

-  void arm_mean_q31(

-  q31_t * pSrc,

-  uint32_t blockSize,

-  q31_t * pResult);

-

-  /**

-   * @brief  Mean value of a floating-point vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @param[out]  *pResult is output value.

-   * @return none.

-   */

-  void arm_mean_f32(

-  float32_t * pSrc,

-  uint32_t blockSize,

-  float32_t * pResult);

-

-  /**

-   * @brief  Variance of the elements of a floating-point vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @param[out]  *pResult is output value.

-   * @return none.

-   */

-

-  void arm_var_f32(

-  float32_t * pSrc,

-  uint32_t blockSize,

-  float32_t * pResult);

-

-  /**

-   * @brief  Variance of the elements of a Q31 vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @param[out]  *pResult is output value.

-   * @return none.

-   */

-

-  void arm_var_q31(

-  q31_t * pSrc,

-  uint32_t blockSize,

-  q31_t * pResult);

-

-  /**

-   * @brief  Variance of the elements of a Q15 vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @param[out]  *pResult is output value.

-   * @return none.

-   */

-

-  void arm_var_q15(

-  q15_t * pSrc,

-  uint32_t blockSize,

-  q15_t * pResult);

-

-  /**

-   * @brief  Root Mean Square of the elements of a floating-point vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @param[out]  *pResult is output value.

-   * @return none.

-   */

-

-  void arm_rms_f32(

-  float32_t * pSrc,

-  uint32_t blockSize,

-  float32_t * pResult);

-

-  /**

-   * @brief  Root Mean Square of the elements of a Q31 vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @param[out]  *pResult is output value.

-   * @return none.

-   */

-

-  void arm_rms_q31(

-  q31_t * pSrc,

-  uint32_t blockSize,

-  q31_t * pResult);

-

-  /**

-   * @brief  Root Mean Square of the elements of a Q15 vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @param[out]  *pResult is output value.

-   * @return none.

-   */

-

-  void arm_rms_q15(

-  q15_t * pSrc,

-  uint32_t blockSize,

-  q15_t * pResult);

-

-  /**

-   * @brief  Standard deviation of the elements of a floating-point vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @param[out]  *pResult is output value.

-   * @return none.

-   */

-

-  void arm_std_f32(

-  float32_t * pSrc,

-  uint32_t blockSize,

-  float32_t * pResult);

-

-  /**

-   * @brief  Standard deviation of the elements of a Q31 vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @param[out]  *pResult is output value.

-   * @return none.

-   */

-

-  void arm_std_q31(

-  q31_t * pSrc,

-  uint32_t blockSize,

-  q31_t * pResult);

-

-  /**

-   * @brief  Standard deviation of the elements of a Q15 vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @param[out]  *pResult is output value.

-   * @return none.

-   */

-

-  void arm_std_q15(

-  q15_t * pSrc,

-  uint32_t blockSize,

-  q15_t * pResult);

-

-  /**

-   * @brief  Floating-point complex magnitude

-   * @param[in]  *pSrc points to the complex input vector

-   * @param[out]  *pDst points to the real output vector

-   * @param[in]  numSamples number of complex samples in the input vector

-   * @return none.

-   */

-

-  void arm_cmplx_mag_f32(

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t numSamples);

-

-  /**

-   * @brief  Q31 complex magnitude

-   * @param[in]  *pSrc points to the complex input vector

-   * @param[out]  *pDst points to the real output vector

-   * @param[in]  numSamples number of complex samples in the input vector

-   * @return none.

-   */

-

-  void arm_cmplx_mag_q31(

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t numSamples);

-

-  /**

-   * @brief  Q15 complex magnitude

-   * @param[in]  *pSrc points to the complex input vector

-   * @param[out]  *pDst points to the real output vector

-   * @param[in]  numSamples number of complex samples in the input vector

-   * @return none.

-   */

-

-  void arm_cmplx_mag_q15(

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t numSamples);

-

-  /**

-   * @brief  Q15 complex dot product

-   * @param[in]  *pSrcA points to the first input vector

-   * @param[in]  *pSrcB points to the second input vector

-   * @param[in]  numSamples number of complex samples in each vector

-   * @param[out]  *realResult real part of the result returned here

-   * @param[out]  *imagResult imaginary part of the result returned here

-   * @return none.

-   */

-

-  void arm_cmplx_dot_prod_q15(

-  q15_t * pSrcA,

-  q15_t * pSrcB,

-  uint32_t numSamples,

-  q31_t * realResult,

-  q31_t * imagResult);

-

-  /**

-   * @brief  Q31 complex dot product

-   * @param[in]  *pSrcA points to the first input vector

-   * @param[in]  *pSrcB points to the second input vector

-   * @param[in]  numSamples number of complex samples in each vector

-   * @param[out]  *realResult real part of the result returned here

-   * @param[out]  *imagResult imaginary part of the result returned here

-   * @return none.

-   */

-

-  void arm_cmplx_dot_prod_q31(

-  q31_t * pSrcA,

-  q31_t * pSrcB,

-  uint32_t numSamples,

-  q63_t * realResult,

-  q63_t * imagResult);

-

-  /**

-   * @brief  Floating-point complex dot product

-   * @param[in]  *pSrcA points to the first input vector

-   * @param[in]  *pSrcB points to the second input vector

-   * @param[in]  numSamples number of complex samples in each vector

-   * @param[out]  *realResult real part of the result returned here

-   * @param[out]  *imagResult imaginary part of the result returned here

-   * @return none.

-   */

-

-  void arm_cmplx_dot_prod_f32(

-  float32_t * pSrcA,

-  float32_t * pSrcB,

-  uint32_t numSamples,

-  float32_t * realResult,

-  float32_t * imagResult);

-

-  /**

-   * @brief  Q15 complex-by-real multiplication

-   * @param[in]  *pSrcCmplx points to the complex input vector

-   * @param[in]  *pSrcReal points to the real input vector

-   * @param[out]  *pCmplxDst points to the complex output vector

-   * @param[in]  numSamples number of samples in each vector

-   * @return none.

-   */

-

-  void arm_cmplx_mult_real_q15(

-  q15_t * pSrcCmplx,

-  q15_t * pSrcReal,

-  q15_t * pCmplxDst,

-  uint32_t numSamples);

-

-  /**

-   * @brief  Q31 complex-by-real multiplication

-   * @param[in]  *pSrcCmplx points to the complex input vector

-   * @param[in]  *pSrcReal points to the real input vector

-   * @param[out]  *pCmplxDst points to the complex output vector

-   * @param[in]  numSamples number of samples in each vector

-   * @return none.

-   */

-

-  void arm_cmplx_mult_real_q31(

-  q31_t * pSrcCmplx,

-  q31_t * pSrcReal,

-  q31_t * pCmplxDst,

-  uint32_t numSamples);

-

-  /**

-   * @brief  Floating-point complex-by-real multiplication

-   * @param[in]  *pSrcCmplx points to the complex input vector

-   * @param[in]  *pSrcReal points to the real input vector

-   * @param[out]  *pCmplxDst points to the complex output vector

-   * @param[in]  numSamples number of samples in each vector

-   * @return none.

-   */

-

-  void arm_cmplx_mult_real_f32(

-  float32_t * pSrcCmplx,

-  float32_t * pSrcReal,

-  float32_t * pCmplxDst,

-  uint32_t numSamples);

-

-  /**

-   * @brief  Minimum value of a Q7 vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @param[out]  *result is output pointer

-   * @param[in]  index is the array index of the minimum value in the input buffer.

-   * @return none.

-   */

-

-  void arm_min_q7(

-  q7_t * pSrc,

-  uint32_t blockSize,

-  q7_t * result,

-  uint32_t * index);

-

-  /**

-   * @brief  Minimum value of a Q15 vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @param[out]  *pResult is output pointer

-   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.

-   * @return none.

-   */

-

-  void arm_min_q15(

-  q15_t * pSrc,

-  uint32_t blockSize,

-  q15_t * pResult,

-  uint32_t * pIndex);

-

-  /**

-   * @brief  Minimum value of a Q31 vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @param[out]  *pResult is output pointer

-   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.

-   * @return none.

-   */

-  void arm_min_q31(

-  q31_t * pSrc,

-  uint32_t blockSize,

-  q31_t * pResult,

-  uint32_t * pIndex);

-

-  /**

-   * @brief  Minimum value of a floating-point vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @param[out]  *pResult is output pointer

-   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.

-   * @return none.

-   */

-

-  void arm_min_f32(

-  float32_t * pSrc,

-  uint32_t blockSize,

-  float32_t * pResult,

-  uint32_t * pIndex);

-

-/**

- * @brief Maximum value of a Q7 vector.

- * @param[in]       *pSrc points to the input buffer

- * @param[in]       blockSize length of the input vector

- * @param[out]      *pResult maximum value returned here

- * @param[out]      *pIndex index of maximum value returned here

- * @return none.

- */

-

-  void arm_max_q7(

-  q7_t * pSrc,

-  uint32_t blockSize,

-  q7_t * pResult,

-  uint32_t * pIndex);

-

-/**

- * @brief Maximum value of a Q15 vector.

- * @param[in]       *pSrc points to the input buffer

- * @param[in]       blockSize length of the input vector

- * @param[out]      *pResult maximum value returned here

- * @param[out]      *pIndex index of maximum value returned here

- * @return none.

- */

-

-  void arm_max_q15(

-  q15_t * pSrc,

-  uint32_t blockSize,

-  q15_t * pResult,

-  uint32_t * pIndex);

-

-/**

- * @brief Maximum value of a Q31 vector.

- * @param[in]       *pSrc points to the input buffer

- * @param[in]       blockSize length of the input vector

- * @param[out]      *pResult maximum value returned here

- * @param[out]      *pIndex index of maximum value returned here

- * @return none.

- */

-

-  void arm_max_q31(

-  q31_t * pSrc,

-  uint32_t blockSize,

-  q31_t * pResult,

-  uint32_t * pIndex);

-

-/**

- * @brief Maximum value of a floating-point vector.

- * @param[in]       *pSrc points to the input buffer

- * @param[in]       blockSize length of the input vector

- * @param[out]      *pResult maximum value returned here

- * @param[out]      *pIndex index of maximum value returned here

- * @return none.

- */

-

-  void arm_max_f32(

-  float32_t * pSrc,

-  uint32_t blockSize,

-  float32_t * pResult,

-  uint32_t * pIndex);

-

-  /**

-   * @brief  Q15 complex-by-complex multiplication

-   * @param[in]  *pSrcA points to the first input vector

-   * @param[in]  *pSrcB points to the second input vector

-   * @param[out]  *pDst  points to the output vector

-   * @param[in]  numSamples number of complex samples in each vector

-   * @return none.

-   */

-

-  void arm_cmplx_mult_cmplx_q15(

-  q15_t * pSrcA,

-  q15_t * pSrcB,

-  q15_t * pDst,

-  uint32_t numSamples);

-

-  /**

-   * @brief  Q31 complex-by-complex multiplication

-   * @param[in]  *pSrcA points to the first input vector

-   * @param[in]  *pSrcB points to the second input vector

-   * @param[out]  *pDst  points to the output vector

-   * @param[in]  numSamples number of complex samples in each vector

-   * @return none.

-   */

-

-  void arm_cmplx_mult_cmplx_q31(

-  q31_t * pSrcA,

-  q31_t * pSrcB,

-  q31_t * pDst,

-  uint32_t numSamples);

-

-  /**

-   * @brief  Floating-point complex-by-complex multiplication

-   * @param[in]  *pSrcA points to the first input vector

-   * @param[in]  *pSrcB points to the second input vector

-   * @param[out]  *pDst  points to the output vector

-   * @param[in]  numSamples number of complex samples in each vector

-   * @return none.

-   */

-

-  void arm_cmplx_mult_cmplx_f32(

-  float32_t * pSrcA,

-  float32_t * pSrcB,

-  float32_t * pDst,

-  uint32_t numSamples);

-

-  /**

-   * @brief Converts the elements of the floating-point vector to Q31 vector.

-   * @param[in]       *pSrc points to the floating-point input vector

-   * @param[out]      *pDst points to the Q31 output vector

-   * @param[in]       blockSize length of the input vector

-   * @return none.

-   */

-  void arm_float_to_q31(

-  float32_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Converts the elements of the floating-point vector to Q15 vector.

-   * @param[in]       *pSrc points to the floating-point input vector

-   * @param[out]      *pDst points to the Q15 output vector

-   * @param[in]       blockSize length of the input vector

-   * @return          none

-   */

-  void arm_float_to_q15(

-  float32_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Converts the elements of the floating-point vector to Q7 vector.

-   * @param[in]       *pSrc points to the floating-point input vector

-   * @param[out]      *pDst points to the Q7 output vector

-   * @param[in]       blockSize length of the input vector

-   * @return          none

-   */

-  void arm_float_to_q7(

-  float32_t * pSrc,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Converts the elements of the Q31 vector to Q15 vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[out]  *pDst is output pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @return none.

-   */

-  void arm_q31_to_q15(

-  q31_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Converts the elements of the Q31 vector to Q7 vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[out]  *pDst is output pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @return none.

-   */

-  void arm_q31_to_q7(

-  q31_t * pSrc,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief  Converts the elements of the Q15 vector to floating-point vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[out]  *pDst is output pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @return none.

-   */

-  void arm_q15_to_float(

-  q15_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Converts the elements of the Q15 vector to Q31 vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[out]  *pDst is output pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @return none.

-   */

-  void arm_q15_to_q31(

-  q15_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Converts the elements of the Q15 vector to Q7 vector.

-   * @param[in]  *pSrc is input pointer

-   * @param[out]  *pDst is output pointer

-   * @param[in]  blockSize is the number of samples to process

-   * @return none.

-   */

-  void arm_q15_to_q7(

-  q15_t * pSrc,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @ingroup groupInterpolation

-   */

-

-  /**

-   * @defgroup BilinearInterpolate Bilinear Interpolation

-   *

-   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.

-   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process

-   * determines values between the grid points.

-   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.

-   * Bilinear interpolation is often used in image processing to rescale images.

-   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.

-   *

-   * <b>Algorithm</b>

-   * \par

-   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.

-   * For floating-point, the instance structure is defined as:

-   * <pre>

-   *   typedef struct

-   *   {

-   *     uint16_t numRows;

-   *     uint16_t numCols;

-   *     float32_t *pData;

-   * } arm_bilinear_interp_instance_f32;

-   * </pre>

-   *

-   * \par

-   * where <code>numRows</code> specifies the number of rows in the table;

-   * <code>numCols</code> specifies the number of columns in the table;

-   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.

-   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.

-   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.

-   *

-   * \par

-   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:

-   * <pre>

-   *     XF = floor(x)

-   *     YF = floor(y)

-   * </pre>

-   * \par

-   * The interpolated output point is computed as:

-   * <pre>

-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))

-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))

-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)

-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)

-   * </pre>

-   * Note that the coordinates (x, y) contain integer and fractional components.

-   * The integer components specify which portion of the table to use while the

-   * fractional components control the interpolation processor.

-   *

-   * \par

-   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.

-   */

-

-  /**

-   * @addtogroup BilinearInterpolate

-   * @{

-   */

-

-  /**

-  *

-  * @brief  Floating-point bilinear interpolation.

-  * @param[in,out] *S points to an instance of the interpolation structure.

-  * @param[in] X interpolation coordinate.

-  * @param[in] Y interpolation coordinate.

-  * @return out interpolated value.

-  */

-

-

-  static __INLINE float32_t arm_bilinear_interp_f32(

-  const arm_bilinear_interp_instance_f32 * S,

-  float32_t X,

-  float32_t Y)

-  {

-    float32_t out;

-    float32_t f00, f01, f10, f11;

-    float32_t *pData = S->pData;

-    int32_t xIndex, yIndex, index;

-    float32_t xdiff, ydiff;

-    float32_t b1, b2, b3, b4;

-

-    xIndex = (int32_t) X;

-    yIndex = (int32_t) Y;

-

-    /* Care taken for table outside boundary */

-    /* Returns zero output when values are outside table boundary */

-    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0

-       || yIndex > (S->numCols - 1))

-    {

-      return (0);

-    }

-

-    /* Calculation of index for two nearest points in X-direction */

-    index = (xIndex - 1) + (yIndex - 1) * S->numCols;

-

-

-    /* Read two nearest points in X-direction */

-    f00 = pData[index];

-    f01 = pData[index + 1];

-

-    /* Calculation of index for two nearest points in Y-direction */

-    index = (xIndex - 1) + (yIndex) * S->numCols;

-

-

-    /* Read two nearest points in Y-direction */

-    f10 = pData[index];

-    f11 = pData[index + 1];

-

-    /* Calculation of intermediate values */

-    b1 = f00;

-    b2 = f01 - f00;

-    b3 = f10 - f00;

-    b4 = f00 - f01 - f10 + f11;

-

-    /* Calculation of fractional part in X */

-    xdiff = X - xIndex;

-

-    /* Calculation of fractional part in Y */

-    ydiff = Y - yIndex;

-

-    /* Calculation of bi-linear interpolated output */

-    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;

-

-    /* return to application */

-    return (out);

-

-  }

-

-  /**

-  *

-  * @brief  Q31 bilinear interpolation.

-  * @param[in,out] *S points to an instance of the interpolation structure.

-  * @param[in] X interpolation coordinate in 12.20 format.

-  * @param[in] Y interpolation coordinate in 12.20 format.

-  * @return out interpolated value.

-  */

-

-  static __INLINE q31_t arm_bilinear_interp_q31(

-  arm_bilinear_interp_instance_q31 * S,

-  q31_t X,

-  q31_t Y)

-  {

-    q31_t out;                                   /* Temporary output */

-    q31_t acc = 0;                               /* output */

-    q31_t xfract, yfract;                        /* X, Y fractional parts */

-    q31_t x1, x2, y1, y2;                        /* Nearest output values */

-    int32_t rI, cI;                              /* Row and column indices */

-    q31_t *pYData = S->pData;                    /* pointer to output table values */

-    uint32_t nCols = S->numCols;                 /* num of rows */

-

-

-    /* Input is in 12.20 format */

-    /* 12 bits for the table index */

-    /* Index value calculation */

-    rI = ((X & 0xFFF00000) >> 20u);

-

-    /* Input is in 12.20 format */

-    /* 12 bits for the table index */

-    /* Index value calculation */

-    cI = ((Y & 0xFFF00000) >> 20u);

-

-    /* Care taken for table outside boundary */

-    /* Returns zero output when values are outside table boundary */

-    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))

-    {

-      return (0);

-    }

-

-    /* 20 bits for the fractional part */

-    /* shift left xfract by 11 to keep 1.31 format */

-    xfract = (X & 0x000FFFFF) << 11u;

-

-    /* Read two nearest output values from the index */

-    x1 = pYData[(rI) + nCols * (cI)];

-    x2 = pYData[(rI) + nCols * (cI) + 1u];

-

-    /* 20 bits for the fractional part */

-    /* shift left yfract by 11 to keep 1.31 format */

-    yfract = (Y & 0x000FFFFF) << 11u;

-

-    /* Read two nearest output values from the index */

-    y1 = pYData[(rI) + nCols * (cI + 1)];

-    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];

-

-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */

-    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));

-    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));

-

-    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */

-    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));

-    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));

-

-    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */

-    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));

-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));

-

-    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */

-    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));

-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));

-

-    /* Convert acc to 1.31(q31) format */

-    return (acc << 2u);

-

-  }

-

-  /**

-  * @brief  Q15 bilinear interpolation.

-  * @param[in,out] *S points to an instance of the interpolation structure.

-  * @param[in] X interpolation coordinate in 12.20 format.

-  * @param[in] Y interpolation coordinate in 12.20 format.

-  * @return out interpolated value.

-  */

-

-  static __INLINE q15_t arm_bilinear_interp_q15(

-  arm_bilinear_interp_instance_q15 * S,

-  q31_t X,

-  q31_t Y)

-  {

-    q63_t acc = 0;                               /* output */

-    q31_t out;                                   /* Temporary output */

-    q15_t x1, x2, y1, y2;                        /* Nearest output values */

-    q31_t xfract, yfract;                        /* X, Y fractional parts */

-    int32_t rI, cI;                              /* Row and column indices */

-    q15_t *pYData = S->pData;                    /* pointer to output table values */

-    uint32_t nCols = S->numCols;                 /* num of rows */

-

-    /* Input is in 12.20 format */

-    /* 12 bits for the table index */

-    /* Index value calculation */

-    rI = ((X & 0xFFF00000) >> 20);

-

-    /* Input is in 12.20 format */

-    /* 12 bits for the table index */

-    /* Index value calculation */

-    cI = ((Y & 0xFFF00000) >> 20);

-

-    /* Care taken for table outside boundary */

-    /* Returns zero output when values are outside table boundary */

-    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))

-    {

-      return (0);

-    }

-

-    /* 20 bits for the fractional part */

-    /* xfract should be in 12.20 format */

-    xfract = (X & 0x000FFFFF);

-

-    /* Read two nearest output values from the index */

-    x1 = pYData[(rI) + nCols * (cI)];

-    x2 = pYData[(rI) + nCols * (cI) + 1u];

-

-

-    /* 20 bits for the fractional part */

-    /* yfract should be in 12.20 format */

-    yfract = (Y & 0x000FFFFF);

-

-    /* Read two nearest output values from the index */

-    y1 = pYData[(rI) + nCols * (cI + 1)];

-    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];

-

-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */

-

-    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */

-    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */

-    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);

-    acc = ((q63_t) out * (0xFFFFF - yfract));

-

-    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */

-    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);

-    acc += ((q63_t) out * (xfract));

-

-    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */

-    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);

-    acc += ((q63_t) out * (yfract));

-

-    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */

-    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);

-    acc += ((q63_t) out * (yfract));

-

-    /* acc is in 13.51 format and down shift acc by 36 times */

-    /* Convert out to 1.15 format */

-    return (acc >> 36);

-

-  }

-

-  /**

-  * @brief  Q7 bilinear interpolation.

-  * @param[in,out] *S points to an instance of the interpolation structure.

-  * @param[in] X interpolation coordinate in 12.20 format.

-  * @param[in] Y interpolation coordinate in 12.20 format.

-  * @return out interpolated value.

-  */

-

-  static __INLINE q7_t arm_bilinear_interp_q7(

-  arm_bilinear_interp_instance_q7 * S,

-  q31_t X,

-  q31_t Y)

-  {

-    q63_t acc = 0;                               /* output */

-    q31_t out;                                   /* Temporary output */

-    q31_t xfract, yfract;                        /* X, Y fractional parts */

-    q7_t x1, x2, y1, y2;                         /* Nearest output values */

-    int32_t rI, cI;                              /* Row and column indices */

-    q7_t *pYData = S->pData;                     /* pointer to output table values */

-    uint32_t nCols = S->numCols;                 /* num of rows */

-

-    /* Input is in 12.20 format */

-    /* 12 bits for the table index */

-    /* Index value calculation */

-    rI = ((X & 0xFFF00000) >> 20);

-

-    /* Input is in 12.20 format */

-    /* 12 bits for the table index */

-    /* Index value calculation */

-    cI = ((Y & 0xFFF00000) >> 20);

-

-    /* Care taken for table outside boundary */

-    /* Returns zero output when values are outside table boundary */

-    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))

-    {

-      return (0);

-    }

-

-    /* 20 bits for the fractional part */

-    /* xfract should be in 12.20 format */

-    xfract = (X & 0x000FFFFF);

-

-    /* Read two nearest output values from the index */

-    x1 = pYData[(rI) + nCols * (cI)];

-    x2 = pYData[(rI) + nCols * (cI) + 1u];

-

-

-    /* 20 bits for the fractional part */

-    /* yfract should be in 12.20 format */

-    yfract = (Y & 0x000FFFFF);

-

-    /* Read two nearest output values from the index */

-    y1 = pYData[(rI) + nCols * (cI + 1)];

-    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];

-

-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */

-    out = ((x1 * (0xFFFFF - xfract)));

-    acc = (((q63_t) out * (0xFFFFF - yfract)));

-

-    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */

-    out = ((x2 * (0xFFFFF - yfract)));

-    acc += (((q63_t) out * (xfract)));

-

-    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */

-    out = ((y1 * (0xFFFFF - xfract)));

-    acc += (((q63_t) out * (yfract)));

-

-    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */

-    out = ((y2 * (yfract)));

-    acc += (((q63_t) out * (xfract)));

-

-    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */

-    return (acc >> 40);

-

-  }

-

-  /**

-   * @} end of BilinearInterpolate group

-   */

-   

-

-//SMMLAR

-#define multAcc_32x32_keep32_R(a, x, y) \

-    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)

-

-//SMMLSR

-#define multSub_32x32_keep32_R(a, x, y) \

-    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)

-

-//SMMULR

-#define mult_32x32_keep32_R(a, x, y) \

-    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)

-

-//SMMLA

-#define multAcc_32x32_keep32(a, x, y) \

-    a += (q31_t) (((q63_t) x * y) >> 32)

-

-//SMMLS

-#define multSub_32x32_keep32(a, x, y) \

-    a -= (q31_t) (((q63_t) x * y) >> 32)

-

-//SMMUL

-#define mult_32x32_keep32(a, x, y) \

-    a = (q31_t) (((q63_t) x * y ) >> 32)

-

-

-#if defined ( __CC_ARM ) //Keil

-

-//Enter low optimization region - place directly above function definition

-    #ifdef ARM_MATH_CM4

-      #define LOW_OPTIMIZATION_ENTER \

-         _Pragma ("push")         \

-         _Pragma ("O1")

-    #else

-      #define LOW_OPTIMIZATION_ENTER 

-    #endif

-

-//Exit low optimization region - place directly after end of function definition

-    #ifdef ARM_MATH_CM4

-      #define LOW_OPTIMIZATION_EXIT \

-         _Pragma ("pop")

-    #else

-      #define LOW_OPTIMIZATION_EXIT  

-    #endif

-

-//Enter low optimization region - place directly above function definition

-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER

-

-//Exit low optimization region - place directly after end of function definition

-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT

-

-#elif defined(__ICCARM__) //IAR

-

-//Enter low optimization region - place directly above function definition

-    #ifdef ARM_MATH_CM4

-      #define LOW_OPTIMIZATION_ENTER \

-         _Pragma ("optimize=low")

-    #else

-      #define LOW_OPTIMIZATION_ENTER   

-    #endif

-

-//Exit low optimization region - place directly after end of function definition

-  #define LOW_OPTIMIZATION_EXIT

-

-//Enter low optimization region - place directly above function definition

-    #ifdef ARM_MATH_CM4

-      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \

-         _Pragma ("optimize=low")

-    #else

-      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER   

-    #endif

-

-//Exit low optimization region - place directly after end of function definition

-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT

-

-#elif defined(__GNUC__)

-

-  #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))

-

-  #define LOW_OPTIMIZATION_EXIT

-

-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER

-

-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT

-

-#elif defined(__CSMC__)    // Cosmic

-

-#define LOW_OPTIMIZATION_ENTER

-#define LOW_OPTIMIZATION_EXIT

-#define IAR_ONLY_LOW_OPTIMIZATION_ENTER

-#define IAR_ONLY_LOW_OPTIMIZATION_EXIT

-

-#endif

-

-

-#ifdef  __cplusplus

-}

-#endif

-

-

-#endif /* _ARM_MATH_H */

-

-/**

- *

- * End of file.

- */

+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        12. March 2014
+* $Revision:    V1.4.4
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_math.h
+*
+* Description:  Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * Introduction
+   * ------------
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * Using the Library
+   * ------------
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
+   * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate pre processor MACRO ARM_MATH_CM4 or  ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   *
+   * Examples
+   * --------
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Toolchain Support
+   * ------------
+   *
+   * The library has been developed and tested with MDK-ARM version 4.60.
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * Building the Library
+   * ------------
+   *
+   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM_math.uvproj
+   *
+   *
+   * The libraries can be built by opening the arm_cortexM_math.uvproj project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+   *
+   * Pre-processor Macros
+   * ------------
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+   *
+   * <hr>
+   * CMSIS-DSP in ARM::CMSIS Pack
+   * -----------------------------
+   * 
+   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+   * |File/Folder                   |Content                                                                 |
+   * |------------------------------|------------------------------------------------------------------------|
+   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
+   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
+   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
+   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
+   * 
+   * <hr>
+   * Revision History of CMSIS-DSP
+   * ------------
+   * Please refer to \ref ChangeLog_pg.
+   *
+   * Copyright Notice
+   * ------------
+   *
+   * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+  #include "core_cm7.h"
+#elif defined (ARM_MATH_CM4)
+  #include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+  #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+  #include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+  #elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+  #define ARM_MATH_CM0_FAMILY
+#else
+  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31    (0x100)
+#define DELTA_Q15    0x5
+#define INDEX_MASK   0x0000003F
+#ifndef PI
+#define PI           3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define FAST_MATH_TABLE_SIZE  512
+#define FAST_MATH_Q31_SHIFT   (32 - 10)
+#define FAST_MATH_Q15_SHIFT   (16 - 10)
+#define CONTROLLER_Q31_SHIFT  (32 - 9)
+#define TABLE_SIZE  256
+#define TABLE_SPACING_Q31     0x400000
+#define TABLE_SPACING_Q15     0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING      0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif  /*  #ifndef UNALIGNED_SUPPORT_DISABLE  */
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if defined __CC_ARM
+#define __SIMD32_TYPE int32_t __packed
+#define CMSIS_UNUSED __attribute__((unused))
+#elif defined __ICCARM__
+#define CMSIS_UNUSED
+#define __SIMD32_TYPE int32_t __packed
+#elif defined __GNUC__
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#elif defined __CSMC__      /* Cosmic */
+#define CMSIS_UNUSED
+#define __SIMD32_TYPE int32_t
+#else
+#error Unknown compiler
+#endif
+
+#define __SIMD32(addr)  (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+
+#define __SIMD64(addr)  (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
+                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
+                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+#endif
+
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  static __INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  static __INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  static __INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  static __INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  static __INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+
+#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
+#define __CLZ __clz
+#endif
+
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data);
+
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data)
+  {
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while((data & mask) == 0)
+    {
+      count += 1u;
+      mask = mask >> 1u;
+    }
+
+    return (count);
+
+  }
+
+#endif
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+   */
+
+  static __INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+
+    uint32_t out, tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 1;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 1;
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t) (in >> 24u);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+      tempVal = 0x7FFFFFFF - tempVal;
+      /*      1.31 with exp 1 */
+      //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+      out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+
+  }
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+   */
+  static __INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+
+    uint32_t out = 0, tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 17;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 17;
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = in >> 8;
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0; i < 2; i++)
+    {
+      tempVal = (q15_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFF - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+
+  }
+
+
+  /*
+   * @brief C custom defined intrinisic function for only M0 processors
+   */
+#if defined(ARM_MATH_CM0_FAMILY)
+
+  static __INLINE q31_t __SSAT(
+  q31_t x,
+  uint32_t y)
+  {
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++)
+    {
+      posMax = posMax * 2;
+    }
+
+    if(x > 0)
+    {
+      posMax = (posMax - 1);
+
+      if(x > posMax)
+      {
+        x = posMax;
+      }
+    }
+    else
+    {
+      negMin = -posMax;
+
+      if(x < negMin)
+      {
+        x = negMin;
+      }
+    }
+    return (x);
+
+
+  }
+
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+
+  /*
+   * @brief C custom defined intrinsic function for M3 and M0 processors
+   */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q7_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((q31_t) (r + s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+    sum =
+      (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((r - s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+    sum =
+      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+                                                                0x000000FF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = __SSAT(r + s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) + (s >> 1));
+    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = __SSAT(r - s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t diff;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) - (s >> 1));
+    s = (((x >> 17) - (y >> 17)) << 16);
+
+    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return diff;
+  }
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) - (y >> 17));
+    s = (((x >> 17) + (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) + (y >> 17));
+    s = (((x >> 17) - (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSDX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) -
+                     ((q15_t) (x >> 16) * (q15_t) y)));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUADX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) +
+                     ((q15_t) (x >> 16) * (q15_t) y)));
+  }
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x + y);
+  }
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x - y);
+  }
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLAD(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+            ((q15_t) x * (q15_t) y));
+  }
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLADX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) +
+            ((q15_t) x * (q15_t) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLSDX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) +
+            ((q15_t) x * (q15_t) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALD(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+            ((q15_t) x * (q15_t) y));
+  }
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALDX(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) y)) +
+      ((q15_t) x * (q15_t) (y >> 16));
+  }
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUAD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (-((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SXTB16(
+  q31_t x)
+  {
+
+    return ((((x << 24) >> 24) & 0x0000FFFF) |
+            (((x << 8) >> 8) & 0xFFFF0000));
+  }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in] *S points to an instance of the Q7 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] *S points to an instance of the Q7 FIR structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed.
+   * @return none
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in] *S points to an instance of the Q15 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * <code>numTaps</code> is not a supported value.
+   */
+
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in] *S points to an instance of the Q31 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] *S points to an instance of the Q31 FIR structure.
+   * @param[in]     numTaps  Number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs points to the filter coefficients.
+   * @param[in]     *pState points to the state buffer.
+   * @param[in]     blockSize number of samples that are processed at a time.
+   * @return        none.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in] *S points to an instance of the floating-point FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+   * @param[in]     numTaps  Number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs points to the filter coefficients.
+   * @param[in]     *pState points to the state buffer.
+   * @param[in]     blockSize number of samples that are processed at a time.
+   * @return        none.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q15;
+
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+
+
+  } arm_biquad_casd_df1_inst_f32;
+
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages      number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float64_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f64;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q31;
+
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point, complex, matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15, complex,  matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Q31, complex, matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return     The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return     The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return     The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @param[in]       *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA  points to the first input matrix structure
+   * @param[in]       *pSrcB  points to the second input matrix structure
+   * @param[out]      *pDst   points to output matrix structure
+   * @param[in]       *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[in]  scale scale factor
+   * @param[out] *pDst points to the output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData         points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData         points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData         points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];       /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;               /**< The proportional gain. */
+    float32_t Ki;               /**< The integral gain. */
+    float32_t Kd;               /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] *S      points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @return none
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the q15 PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;                /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                     /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                     /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q15;
+
+  void arm_cfft_q15(
+  const arm_cfft_instance_q15 * S,
+  q15_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q31;
+
+  void arm_cfft_q31(
+  const arm_cfft_instance_q31 * S,
+  q31_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_f32;
+
+  void arm_cfft_f32(
+  const arm_cfft_instance_f32 * S,
+  float32_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;                        /**< length of the real sequence */
+    float32_t * pTwiddleRFFT;                   /**< Twiddle factors real stage  */
+  } arm_rfft_fast_instance_f32 ;
+
+  arm_status arm_rfft_fast_init_f32 (
+  arm_rfft_fast_instance_f32 * S,
+  uint16_t fftLen);
+
+  void arm_rfft_fast_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut,
+  uint8_t ifftFlag);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    float32_t normalize;                /**< normalizing factor. */
+    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;              /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return        arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q31_t normalize;                    /**< normalizing factor. */
+    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return        arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q15_t normalize;                    /**< normalizing factor. */
+    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return        arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scale scale factor to be applied
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Copies the elements of a floating-point vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q7 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q15 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q31 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Fills a constant value into a floating-point vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+    /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q7 sequences
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                      /**< decimation factor. */
+    uint16_t numTaps;               /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                          /**< decimation factor. */
+    uint16_t numTaps;                   /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_f32;
+
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f64;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_stereo_df2T_f32(
+  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f64(
+  const arm_biquad_cascade_df2T_instance_f64 * S,
+  float64_t * pSrc,
+  float64_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_stereo_df2T_init_f32(
+  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f64(
+  arm_biquad_cascade_df2T_instance_f64 * S,
+  uint8_t numStages,
+  float64_t * pCoeffs,
+  float64_t * pState);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return    none.
+   */
+
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+
+  } arm_lms_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that control filter coefficient updates. */
+    float32_t energy;    /**< saves previous frame energy. */
+    float32_t x0;        /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;   /**< bit shift applied to coefficients. */
+    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
+    q15_t energy;        /**< saves previous frame energy. */
+    q15_t x0;            /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**
+   * @brief Correlation of Q15 sequences
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+
+ /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /*
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta    input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cos output.
+   * @return none.
+   */
+
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCcosVal);
+
+  /*
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cosine output.
+   * @return none.
+   */
+
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * <pre>
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  </pre>
+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   *
+   * \par
+   * \image html PID.gif "Proportional Integral Derivative Controller"
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.
+   * The proportional value determines the reaction to the current error,
+   * the integral value determines the reaction based on the sum of recent errors,
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+   * A separate instance structure must be defined for each PID Controller.
+   * There are separate instance structure declarations for each of the 3 supported data types.
+   *
+   * \par Reset Functions
+   * There is also an associated reset function for each data type which clears the state array.
+   *
+   * \par Initialization Functions
+   * There is also an associated initialization function for each data type.
+   * The initialization function performs the following operations:
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.
+   *
+   * \par
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the fixed-point versions of the PID Controller functions.
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   */
+
+
+  static __INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 64-bit accumulator.
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+   * Thus, if the accumulator result overflows it wraps around rather than clip.
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+   */
+
+  static __INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using a 64-bit internal accumulator.
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+
+  static __INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+    __SIMD32_TYPE *vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD(S->A0, in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
+
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f64(
+  const arm_matrix_instance_f64 * src,
+  arm_matrix_instance_f64 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   */
+
+  static __INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta =
+      ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+  }
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out]  *pDst    output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   */
+
+
+  static __INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+  }
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out] *pDst     output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+   * from the stationary to the moving reference frame and control the spatial relationship between
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output  rotor reference frame d
+   * @param[out]      *pIq   points to output  rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+
+  static __INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+  }
+
+  /**
+   * @brief  Park transform for Q31 version
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output rotor reference frame d
+   * @param[out]      *pIq   points to output rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   */
+
+  static __INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for Q31 version
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * <pre>
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * </pre>
+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+   * <code>x</code> is the input sample value. The functions returns the output value.
+   *
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table
+   * if x is below input range and returns last value of table if x is above range.
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+   * @param[in] x input sample to process
+   * @return y processed output sample.
+   *
+   */
+
+  static __INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if(i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if((uint32_t)i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 + i * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1u);
+
+    }
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (y >> 20);
+    }
+
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+
+
+  static __INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0)
+    {
+      return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+
+    if(index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (y >> 20u);
+
+    }
+
+  }
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  sin(x).
+   */
+
+  float32_t arm_sin_f32(
+  float32_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q31_t arm_sin_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q15_t arm_sin_q15(
+  q15_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  cos(x).
+   */
+
+  float32_t arm_cos_f32(
+  float32_t x);
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q31_t arm_cos_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * <pre>
+   *      x1 = x0 - f(x0)/f'(x0)
+   * </pre>
+   * where <code>x1</code> is the current estimate,
+   * <code>x0</code> is the previous estimate, and
+   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+   * For the square root function, the algorithm reduces to:
+   * <pre>
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * </pre>
+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in     input value.
+   * @param[out] *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+
+  static __INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if(in > 0)
+    {
+
+//      #if __FPU_USED
+#if (__FPU_USED == 1) && defined ( __CC_ARM   )
+      *pOut = __sqrtf(in);
+#else
+      *pOut = sqrtf(in);
+#endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out]  *pOut square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out]  *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+
+
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  static __INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *result is output pointer
+   * @param[in]  index is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q31 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return none.
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q15 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q7 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * <b>Algorithm</b>
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * <pre>
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * </pre>
+   *
+   * \par
+   * where <code>numRows</code> specifies the number of rows in the table;
+   * <code>numCols</code> specifies the number of columns in the table;
+   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+   *
+   * \par
+   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+   * <pre>
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * </pre>
+   * \par
+   * The interpolated output point is computed as:
+   * <pre>
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * </pre>
+   * Note that the coordinates (x, y) contain integer and fractional components.
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate.
+  * @param[in] Y interpolation coordinate.
+  * @return out interpolated value.
+  */
+
+
+  static __INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+       || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20u);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20u);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return (acc << 2u);
+
+  }
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return (acc >> 36);
+
+  }
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return (acc >> 40);
+
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+   
+
+//SMMLAR
+#define multAcc_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMLSR
+#define multSub_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMULR
+#define mult_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+//SMMLA
+#define multAcc_32x32_keep32(a, x, y) \
+    a += (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMLS
+#define multSub_32x32_keep32(a, x, y) \
+    a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+#define mult_32x32_keep32(a, x, y) \
+    a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM ) //Keil
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_ENTER \
+         _Pragma ("push")         \
+         _Pragma ("O1")
+    #else
+      #define LOW_OPTIMIZATION_ENTER 
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_EXIT \
+         _Pragma ("pop")
+    #else
+      #define LOW_OPTIMIZATION_EXIT  
+    #endif
+
+//Enter low optimization region - place directly above function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__) //IAR
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_ENTER \
+         _Pragma ("optimize=low")
+    #else
+      #define LOW_OPTIMIZATION_ENTER   
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+  #define LOW_OPTIMIZATION_EXIT
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+         _Pragma ("optimize=low")
+    #else
+      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER   
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+
+  #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+
+  #define LOW_OPTIMIZATION_EXIT
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__CSMC__)    // Cosmic
+
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef  __cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/firmware/inc/platform/stm32f4xx/cmsis/core_cm0.h b/firmware/os/cpu/cortexm4/inc/cpu/cmsis/core_cm0.h
index dbc4e22d..5186cb48 100644
--- a/firmware/inc/platform/stm32f4xx/cmsis/core_cm0.h
+++ b/firmware/os/cpu/cortexm4/inc/cpu/cmsis/core_cm0.h
@@ -1,711 +1,711 @@
-/**************************************************************************//**

- * @file     core_cm0.h

- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File

- * @version  V4.00

- * @date     22. August 2014

- *

- * @note

- *

- ******************************************************************************/

-/* Copyright (c) 2009 - 2014 ARM LIMITED

-

-   All rights reserved.

-   Redistribution and use in source and binary forms, with or without

-   modification, are permitted provided that the following conditions are met:

-   - Redistributions of source code must retain the above copyright

-     notice, this list of conditions and the following disclaimer.

-   - Redistributions in binary form must reproduce the above copyright

-     notice, this list of conditions and the following disclaimer in the

-     documentation and/or other materials provided with the distribution.

-   - Neither the name of ARM nor the names of its contributors may be used

-     to endorse or promote products derived from this software without

-     specific prior written permission.

-   *

-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-   POSSIBILITY OF SUCH DAMAGE.

-   ---------------------------------------------------------------------------*/

-

-

-#if defined ( __ICCARM__ )

- #pragma system_include  /* treat file as system include file for MISRA check */

-#endif

-

-#ifndef __CORE_CM0_H_GENERIC

-#define __CORE_CM0_H_GENERIC

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions

-  CMSIS violates the following MISRA-C:2004 rules:

-

-   \li Required Rule 8.5, object/function definition in header file.<br>

-     Function definitions in header files are used to allow 'inlining'.

-

-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>

-     Unions are used for effective representation of core registers.

-

-   \li Advisory Rule 19.7, Function-like macro defined.<br>

-     Function-like macros are used to allow more efficient code.

- */

-

-

-/*******************************************************************************

- *                 CMSIS definitions

- ******************************************************************************/

-/** \ingroup Cortex_M0

-  @{

- */

-

-/*  CMSIS CM0 definitions */

-#define __CM0_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */

-#define __CM0_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */

-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \

-                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */

-

-#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */

-

-

-#if   defined ( __CC_ARM )

-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */

-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */

-  #define __STATIC_INLINE  static __inline

-

-#elif defined ( __GNUC__ )

-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */

-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __ICCARM__ )

-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */

-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TMS470__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TASKING__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */

-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __CSMC__ )

-  #define __packed

-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */

-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */

-  #define __STATIC_INLINE  static inline

-

-#endif

-

-/** __FPU_USED indicates whether an FPU is used or not.

-    This core does not support an FPU at all

-*/

-#define __FPU_USED       0

-

-#if defined ( __CC_ARM )

-  #if defined __TARGET_FPU_VFP

-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __GNUC__ )

-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __ICCARM__ )

-  #if defined __ARMVFP__

-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __TMS470__ )

-  #if defined __TI__VFP_SUPPORT____

-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __TASKING__ )

-  #if defined __FPU_VFP__

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __CSMC__ )		/* Cosmic */

-  #if ( __CSMC__ & 0x400)		// FPU present for parser

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-#endif

-

-#include <stdint.h>                      /* standard types definitions                      */

-#include <core_cmInstr.h>                /* Core Instruction Access                         */

-#include <core_cmFunc.h>                 /* Core Function Access                            */

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_CM0_H_GENERIC */

-

-#ifndef __CMSIS_GENERIC

-

-#ifndef __CORE_CM0_H_DEPENDANT

-#define __CORE_CM0_H_DEPENDANT

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/* check device defines and use defaults */

-#if defined __CHECK_DEVICE_DEFINES

-  #ifndef __CM0_REV

-    #define __CM0_REV               0x0000

-    #warning "__CM0_REV not defined in device header file; using default!"

-  #endif

-

-  #ifndef __NVIC_PRIO_BITS

-    #define __NVIC_PRIO_BITS          2

-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"

-  #endif

-

-  #ifndef __Vendor_SysTickConfig

-    #define __Vendor_SysTickConfig    0

-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"

-  #endif

-#endif

-

-/* IO definitions (access restrictions to peripheral registers) */

-/**

-    \defgroup CMSIS_glob_defs CMSIS Global Defines

-

-    <strong>IO Type Qualifiers</strong> are used

-    \li to specify the access to peripheral variables.

-    \li for automatic generation of peripheral register debug information.

-*/

-#ifdef __cplusplus

-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */

-#else

-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */

-#endif

-#define     __O     volatile             /*!< Defines 'write only' permissions                */

-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */

-

-/*@} end of group Cortex_M0 */

-

-

-

-/*******************************************************************************

- *                 Register Abstraction

-  Core Register contain:

-  - Core Register

-  - Core NVIC Register

-  - Core SCB Register

-  - Core SysTick Register

- ******************************************************************************/

-/** \defgroup CMSIS_core_register Defines and Type Definitions

-    \brief Type definitions and defines for Cortex-M processor based devices.

-*/

-

-/** \ingroup    CMSIS_core_register

-    \defgroup   CMSIS_CORE  Status and Control Registers

-    \brief  Core Register type definitions.

-  @{

- */

-

-/** \brief  Union type to access the Application Program Status Register (APSR).

- */

-typedef union

-{

-  struct

-  {

-#if (__CORTEX_M != 0x04)

-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */

-#else

-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */

-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */

-#endif

-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} APSR_Type;

-

-

-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} IPSR_Type;

-

-

-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

-#if (__CORTEX_M != 0x04)

-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */

-#else

-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */

-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */

-#endif

-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */

-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */

-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} xPSR_Type;

-

-

-/** \brief  Union type to access the Control Registers (CONTROL).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */

-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */

-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */

-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} CONTROL_Type;

-

-/*@} end of group CMSIS_CORE */

-

-

-/** \ingroup    CMSIS_core_register

-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)

-    \brief      Type definitions for the NVIC Registers

-  @{

- */

-

-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).

- */

-typedef struct

-{

-  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */

-       uint32_t RESERVED0[31];

-  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */

-       uint32_t RSERVED1[31];

-  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */

-       uint32_t RESERVED2[31];

-  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */

-       uint32_t RESERVED3[31];

-       uint32_t RESERVED4[64];

-  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */

-}  NVIC_Type;

-

-/*@} end of group CMSIS_NVIC */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_SCB     System Control Block (SCB)

-    \brief      Type definitions for the System Control Block Registers

-  @{

- */

-

-/** \brief  Structure type to access the System Control Block (SCB).

- */

-typedef struct

-{

-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */

-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */

-       uint32_t RESERVED0;

-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */

-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */

-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */

-       uint32_t RESERVED1;

-  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */

-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */

-} SCB_Type;

-

-/* SCB CPUID Register Definitions */

-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */

-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */

-

-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */

-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */

-

-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */

-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */

-

-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */

-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */

-

-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */

-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */

-

-/* SCB Interrupt Control State Register Definitions */

-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */

-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */

-

-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */

-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */

-

-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */

-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */

-

-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */

-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */

-

-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */

-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */

-

-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */

-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */

-

-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */

-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */

-

-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */

-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */

-

-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */

-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */

-

-/* SCB Application Interrupt and Reset Control Register Definitions */

-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */

-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */

-

-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */

-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */

-

-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */

-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */

-

-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */

-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */

-

-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */

-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */

-

-/* SCB System Control Register Definitions */

-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */

-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */

-

-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */

-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */

-

-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */

-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */

-

-/* SCB Configuration Control Register Definitions */

-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */

-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */

-

-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */

-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */

-

-/* SCB System Handler Control and State Register Definitions */

-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */

-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */

-

-/*@} end of group CMSIS_SCB */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)

-    \brief      Type definitions for the System Timer Registers.

-  @{

- */

-

-/** \brief  Structure type to access the System Timer (SysTick).

- */

-typedef struct

-{

-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */

-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */

-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */

-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */

-} SysTick_Type;

-

-/* SysTick Control / Status Register Definitions */

-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */

-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */

-

-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */

-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */

-

-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */

-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */

-

-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */

-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */

-

-/* SysTick Reload Register Definitions */

-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */

-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */

-

-/* SysTick Current Register Definitions */

-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */

-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */

-

-/* SysTick Calibration Register Definitions */

-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */

-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */

-

-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */

-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */

-

-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */

-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */

-

-/*@} end of group CMSIS_SysTick */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)

-    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)

-                are only accessible over DAP and not via processor. Therefore

-                they are not covered by the Cortex-M0 header file.

-  @{

- */

-/*@} end of group CMSIS_CoreDebug */

-

-

-/** \ingroup    CMSIS_core_register

-    \defgroup   CMSIS_core_base     Core Definitions

-    \brief      Definitions for base addresses, unions, and structures.

-  @{

- */

-

-/* Memory mapping of Cortex-M0 Hardware */

-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */

-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */

-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */

-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */

-

-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */

-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */

-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */

-

-

-/*@} */

-

-

-

-/*******************************************************************************

- *                Hardware Abstraction Layer

-  Core Function Interface contains:

-  - Core NVIC Functions

-  - Core SysTick Functions

-  - Core Register Access Functions

- ******************************************************************************/

-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference

-*/

-

-

-

-/* ##########################   NVIC functions  #################################### */

-/** \ingroup  CMSIS_Core_FunctionInterface

-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions

-    \brief      Functions that manage interrupts and exceptions via the NVIC.

-    @{

- */

-

-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */

-/* The following MACROS handle generation of the register offset and byte masks */

-#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )

-#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )

-#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )

-

-

-/** \brief  Enable External Interrupt

-

-    The function enables a device-specific interrupt in the NVIC interrupt controller.

-

-    \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)

-{

-  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));

-}

-

-

-/** \brief  Disable External Interrupt

-

-    The function disables a device-specific interrupt in the NVIC interrupt controller.

-

-    \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));

-}

-

-

-/** \brief  Get Pending Interrupt

-

-    The function reads the pending register in the NVIC and returns the pending bit

-    for the specified interrupt.

-

-    \param [in]      IRQn  Interrupt number.

-

-    \return             0  Interrupt status is not pending.

-    \return             1  Interrupt status is pending.

- */

-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)

-{

-  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));

-}

-

-

-/** \brief  Set Pending Interrupt

-

-    The function sets the pending bit of an external interrupt.

-

-    \param [in]      IRQn  Interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));

-}

-

-

-/** \brief  Clear Pending Interrupt

-

-    The function clears the pending bit of an external interrupt.

-

-    \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */

-}

-

-

-/** \brief  Set Interrupt Priority

-

-    The function sets the priority of an interrupt.

-

-    \note The priority cannot be set for every core interrupt.

-

-    \param [in]      IRQn  Interrupt number.

-    \param [in]  priority  Priority to set.

- */

-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

-{

-  if(IRQn < 0) {

-    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |

-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }

-  else {

-    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |

-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }

-}

-

-

-/** \brief  Get Interrupt Priority

-

-    The function reads the priority of an interrupt. The interrupt

-    number can be positive to specify an external (device specific)

-    interrupt, or negative to specify an internal (core) interrupt.

-

-

-    \param [in]   IRQn  Interrupt number.

-    \return             Interrupt Priority. Value is aligned automatically to the implemented

-                        priority bits of the microcontroller.

- */

-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)

-{

-

-  if(IRQn < 0) {

-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */

-  else {

-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */

-}

-

-

-/** \brief  System Reset

-

-    The function initiates a system reset request to reset the MCU.

- */

-__STATIC_INLINE void NVIC_SystemReset(void)

-{

-  __DSB();                                                     /* Ensure all outstanding memory accesses included

-                                                                  buffered write are completed before reset */

-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |

-                 SCB_AIRCR_SYSRESETREQ_Msk);

-  __DSB();                                                     /* Ensure completion of memory access */

-  while(1);                                                    /* wait until reset */

-}

-

-/*@} end of CMSIS_Core_NVICFunctions */

-

-

-

-/* ##################################    SysTick function  ############################################ */

-/** \ingroup  CMSIS_Core_FunctionInterface

-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions

-    \brief      Functions that configure the System.

-  @{

- */

-

-#if (__Vendor_SysTickConfig == 0)

-

-/** \brief  System Tick Configuration

-

-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.

-    Counter is in free running mode to generate periodic interrupts.

-

-    \param [in]  ticks  Number of ticks between two interrupts.

-

-    \return          0  Function succeeded.

-    \return          1  Function failed.

-

-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the

-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>

-    must contain a vendor-specific implementation of this function.

-

- */

-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

-{

-  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */

-

-  SysTick->LOAD  = ticks - 1;                                  /* set reload register */

-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */

-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */

-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |

-                   SysTick_CTRL_TICKINT_Msk   |

-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */

-  return (0);                                                  /* Function successful */

-}

-

-#endif

-

-/*@} end of CMSIS_Core_SysTickFunctions */

-

-

-

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_CM0_H_DEPENDANT */

-

-#endif /* __CMSIS_GENERIC */

+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM0_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+       uint32_t RESERVED0;
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/firmware/inc/platform/stm32f4xx/cmsis/core_cm0plus.h b/firmware/os/cpu/cortexm4/inc/cpu/cmsis/core_cm0plus.h
index 4d7facfa..17e43984 100644
--- a/firmware/inc/platform/stm32f4xx/cmsis/core_cm0plus.h
+++ b/firmware/os/cpu/cortexm4/inc/cpu/cmsis/core_cm0plus.h
@@ -1,822 +1,822 @@
-/**************************************************************************//**

- * @file     core_cm0plus.h

- * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File

- * @version  V4.00

- * @date     22. August 2014

- *

- * @note

- *

- ******************************************************************************/

-/* Copyright (c) 2009 - 2014 ARM LIMITED

-

-   All rights reserved.

-   Redistribution and use in source and binary forms, with or without

-   modification, are permitted provided that the following conditions are met:

-   - Redistributions of source code must retain the above copyright

-     notice, this list of conditions and the following disclaimer.

-   - Redistributions in binary form must reproduce the above copyright

-     notice, this list of conditions and the following disclaimer in the

-     documentation and/or other materials provided with the distribution.

-   - Neither the name of ARM nor the names of its contributors may be used

-     to endorse or promote products derived from this software without

-     specific prior written permission.

-   *

-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-   POSSIBILITY OF SUCH DAMAGE.

-   ---------------------------------------------------------------------------*/

-

-

-#if defined ( __ICCARM__ )

- #pragma system_include  /* treat file as system include file for MISRA check */

-#endif

-

-#ifndef __CORE_CM0PLUS_H_GENERIC

-#define __CORE_CM0PLUS_H_GENERIC

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions

-  CMSIS violates the following MISRA-C:2004 rules:

-

-   \li Required Rule 8.5, object/function definition in header file.<br>

-     Function definitions in header files are used to allow 'inlining'.

-

-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>

-     Unions are used for effective representation of core registers.

-

-   \li Advisory Rule 19.7, Function-like macro defined.<br>

-     Function-like macros are used to allow more efficient code.

- */

-

-

-/*******************************************************************************

- *                 CMSIS definitions

- ******************************************************************************/

-/** \ingroup Cortex-M0+

-  @{

- */

-

-/*  CMSIS CM0P definitions */

-#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04)                                /*!< [31:16] CMSIS HAL main version   */

-#define __CM0PLUS_CMSIS_VERSION_SUB  (0x00)                                /*!< [15:0]  CMSIS HAL sub version    */

-#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \

-                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */

-

-#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */

-

-

-#if   defined ( __CC_ARM )

-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */

-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */

-  #define __STATIC_INLINE  static __inline

-

-#elif defined ( __GNUC__ )

-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */

-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __ICCARM__ )

-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */

-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TMS470__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TASKING__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */

-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __CSMC__ )

-  #define __packed

-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */

-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */

-  #define __STATIC_INLINE  static inline

-

-#endif

-

-/** __FPU_USED indicates whether an FPU is used or not.

-    This core does not support an FPU at all

-*/

-#define __FPU_USED       0

-

-#if defined ( __CC_ARM )

-  #if defined __TARGET_FPU_VFP

-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __GNUC__ )

-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __ICCARM__ )

-  #if defined __ARMVFP__

-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __TMS470__ )

-  #if defined __TI__VFP_SUPPORT____

-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __TASKING__ )

-  #if defined __FPU_VFP__

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __CSMC__ )		/* Cosmic */

-  #if ( __CSMC__ & 0x400)		// FPU present for parser

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-#endif

-

-#include <stdint.h>                      /* standard types definitions                      */

-#include <core_cmInstr.h>                /* Core Instruction Access                         */

-#include <core_cmFunc.h>                 /* Core Function Access                            */

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_CM0PLUS_H_GENERIC */

-

-#ifndef __CMSIS_GENERIC

-

-#ifndef __CORE_CM0PLUS_H_DEPENDANT

-#define __CORE_CM0PLUS_H_DEPENDANT

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/* check device defines and use defaults */

-#if defined __CHECK_DEVICE_DEFINES

-  #ifndef __CM0PLUS_REV

-    #define __CM0PLUS_REV             0x0000

-    #warning "__CM0PLUS_REV not defined in device header file; using default!"

-  #endif

-

-  #ifndef __MPU_PRESENT

-    #define __MPU_PRESENT             0

-    #warning "__MPU_PRESENT not defined in device header file; using default!"

-  #endif

-

-  #ifndef __VTOR_PRESENT

-    #define __VTOR_PRESENT            0

-    #warning "__VTOR_PRESENT not defined in device header file; using default!"

-  #endif

-

-  #ifndef __NVIC_PRIO_BITS

-    #define __NVIC_PRIO_BITS          2

-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"

-  #endif

-

-  #ifndef __Vendor_SysTickConfig

-    #define __Vendor_SysTickConfig    0

-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"

-  #endif

-#endif

-

-/* IO definitions (access restrictions to peripheral registers) */

-/**

-    \defgroup CMSIS_glob_defs CMSIS Global Defines

-

-    <strong>IO Type Qualifiers</strong> are used

-    \li to specify the access to peripheral variables.

-    \li for automatic generation of peripheral register debug information.

-*/

-#ifdef __cplusplus

-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */

-#else

-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */

-#endif

-#define     __O     volatile             /*!< Defines 'write only' permissions                */

-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */

-

-/*@} end of group Cortex-M0+ */

-

-

-

-/*******************************************************************************

- *                 Register Abstraction

-  Core Register contain:

-  - Core Register

-  - Core NVIC Register

-  - Core SCB Register

-  - Core SysTick Register

-  - Core MPU Register

- ******************************************************************************/

-/** \defgroup CMSIS_core_register Defines and Type Definitions

-    \brief Type definitions and defines for Cortex-M processor based devices.

-*/

-

-/** \ingroup    CMSIS_core_register

-    \defgroup   CMSIS_CORE  Status and Control Registers

-    \brief  Core Register type definitions.

-  @{

- */

-

-/** \brief  Union type to access the Application Program Status Register (APSR).

- */

-typedef union

-{

-  struct

-  {

-#if (__CORTEX_M != 0x04)

-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */

-#else

-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */

-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */

-#endif

-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} APSR_Type;

-

-

-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} IPSR_Type;

-

-

-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

-#if (__CORTEX_M != 0x04)

-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */

-#else

-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */

-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */

-#endif

-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */

-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */

-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} xPSR_Type;

-

-

-/** \brief  Union type to access the Control Registers (CONTROL).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */

-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */

-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */

-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} CONTROL_Type;

-

-/*@} end of group CMSIS_CORE */

-

-

-/** \ingroup    CMSIS_core_register

-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)

-    \brief      Type definitions for the NVIC Registers

-  @{

- */

-

-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).

- */

-typedef struct

-{

-  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */

-       uint32_t RESERVED0[31];

-  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */

-       uint32_t RSERVED1[31];

-  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */

-       uint32_t RESERVED2[31];

-  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */

-       uint32_t RESERVED3[31];

-       uint32_t RESERVED4[64];

-  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */

-}  NVIC_Type;

-

-/*@} end of group CMSIS_NVIC */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_SCB     System Control Block (SCB)

-    \brief      Type definitions for the System Control Block Registers

-  @{

- */

-

-/** \brief  Structure type to access the System Control Block (SCB).

- */

-typedef struct

-{

-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */

-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */

-#if (__VTOR_PRESENT == 1)

-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */

-#else

-       uint32_t RESERVED0;

-#endif

-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */

-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */

-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */

-       uint32_t RESERVED1;

-  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */

-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */

-} SCB_Type;

-

-/* SCB CPUID Register Definitions */

-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */

-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */

-

-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */

-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */

-

-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */

-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */

-

-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */

-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */

-

-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */

-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */

-

-/* SCB Interrupt Control State Register Definitions */

-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */

-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */

-

-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */

-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */

-

-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */

-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */

-

-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */

-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */

-

-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */

-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */

-

-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */

-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */

-

-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */

-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */

-

-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */

-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */

-

-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */

-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */

-

-#if (__VTOR_PRESENT == 1)

-/* SCB Interrupt Control State Register Definitions */

-#define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */

-#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */

-#endif

-

-/* SCB Application Interrupt and Reset Control Register Definitions */

-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */

-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */

-

-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */

-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */

-

-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */

-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */

-

-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */

-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */

-

-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */

-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */

-

-/* SCB System Control Register Definitions */

-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */

-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */

-

-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */

-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */

-

-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */

-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */

-

-/* SCB Configuration Control Register Definitions */

-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */

-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */

-

-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */

-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */

-

-/* SCB System Handler Control and State Register Definitions */

-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */

-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */

-

-/*@} end of group CMSIS_SCB */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)

-    \brief      Type definitions for the System Timer Registers.

-  @{

- */

-

-/** \brief  Structure type to access the System Timer (SysTick).

- */

-typedef struct

-{

-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */

-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */

-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */

-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */

-} SysTick_Type;

-

-/* SysTick Control / Status Register Definitions */

-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */

-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */

-

-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */

-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */

-

-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */

-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */

-

-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */

-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */

-

-/* SysTick Reload Register Definitions */

-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */

-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */

-

-/* SysTick Current Register Definitions */

-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */

-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */

-

-/* SysTick Calibration Register Definitions */

-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */

-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */

-

-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */

-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */

-

-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */

-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */

-

-/*@} end of group CMSIS_SysTick */

-

-#if (__MPU_PRESENT == 1)

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)

-    \brief      Type definitions for the Memory Protection Unit (MPU)

-  @{

- */

-

-/** \brief  Structure type to access the Memory Protection Unit (MPU).

- */

-typedef struct

-{

-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */

-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */

-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */

-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */

-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */

-} MPU_Type;

-

-/* MPU Type Register */

-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */

-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */

-

-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */

-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */

-

-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */

-#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */

-

-/* MPU Control Register */

-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */

-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */

-

-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */

-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */

-

-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */

-#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */

-

-/* MPU Region Number Register */

-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */

-#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */

-

-/* MPU Region Base Address Register */

-#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */

-#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */

-

-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */

-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */

-

-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */

-#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */

-

-/* MPU Region Attribute and Size Register */

-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */

-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */

-

-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */

-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */

-

-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */

-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */

-

-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */

-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */

-

-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */

-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */

-

-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */

-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */

-

-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */

-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */

-

-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */

-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */

-

-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */

-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */

-

-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */

-#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */

-

-/*@} end of group CMSIS_MPU */

-#endif

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)

-    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)

-                are only accessible over DAP and not via processor. Therefore

-                they are not covered by the Cortex-M0 header file.

-  @{

- */

-/*@} end of group CMSIS_CoreDebug */

-

-

-/** \ingroup    CMSIS_core_register

-    \defgroup   CMSIS_core_base     Core Definitions

-    \brief      Definitions for base addresses, unions, and structures.

-  @{

- */

-

-/* Memory mapping of Cortex-M0+ Hardware */

-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */

-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */

-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */

-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */

-

-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */

-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */

-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */

-

-#if (__MPU_PRESENT == 1)

-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */

-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */

-#endif

-

-/*@} */

-

-

-

-/*******************************************************************************

- *                Hardware Abstraction Layer

-  Core Function Interface contains:

-  - Core NVIC Functions

-  - Core SysTick Functions

-  - Core Register Access Functions

- ******************************************************************************/

-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference

-*/

-

-

-

-/* ##########################   NVIC functions  #################################### */

-/** \ingroup  CMSIS_Core_FunctionInterface

-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions

-    \brief      Functions that manage interrupts and exceptions via the NVIC.

-    @{

- */

-

-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */

-/* The following MACROS handle generation of the register offset and byte masks */

-#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )

-#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )

-#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )

-

-

-/** \brief  Enable External Interrupt

-

-    The function enables a device-specific interrupt in the NVIC interrupt controller.

-

-    \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)

-{

-  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));

-}

-

-

-/** \brief  Disable External Interrupt

-

-    The function disables a device-specific interrupt in the NVIC interrupt controller.

-

-    \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));

-}

-

-

-/** \brief  Get Pending Interrupt

-

-    The function reads the pending register in the NVIC and returns the pending bit

-    for the specified interrupt.

-

-    \param [in]      IRQn  Interrupt number.

-

-    \return             0  Interrupt status is not pending.

-    \return             1  Interrupt status is pending.

- */

-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)

-{

-  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));

-}

-

-

-/** \brief  Set Pending Interrupt

-

-    The function sets the pending bit of an external interrupt.

-

-    \param [in]      IRQn  Interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));

-}

-

-

-/** \brief  Clear Pending Interrupt

-

-    The function clears the pending bit of an external interrupt.

-

-    \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */

-}

-

-

-/** \brief  Set Interrupt Priority

-

-    The function sets the priority of an interrupt.

-

-    \note The priority cannot be set for every core interrupt.

-

-    \param [in]      IRQn  Interrupt number.

-    \param [in]  priority  Priority to set.

- */

-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

-{

-  if(IRQn < 0) {

-    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |

-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }

-  else {

-    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |

-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }

-}

-

-

-/** \brief  Get Interrupt Priority

-

-    The function reads the priority of an interrupt. The interrupt

-    number can be positive to specify an external (device specific)

-    interrupt, or negative to specify an internal (core) interrupt.

-

-

-    \param [in]   IRQn  Interrupt number.

-    \return             Interrupt Priority. Value is aligned automatically to the implemented

-                        priority bits of the microcontroller.

- */

-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)

-{

-

-  if(IRQn < 0) {

-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */

-  else {

-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */

-}

-

-

-/** \brief  System Reset

-

-    The function initiates a system reset request to reset the MCU.

- */

-__STATIC_INLINE void NVIC_SystemReset(void)

-{

-  __DSB();                                                     /* Ensure all outstanding memory accesses included

-                                                                  buffered write are completed before reset */

-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |

-                 SCB_AIRCR_SYSRESETREQ_Msk);

-  __DSB();                                                     /* Ensure completion of memory access */

-  while(1);                                                    /* wait until reset */

-}

-

-/*@} end of CMSIS_Core_NVICFunctions */

-

-

-

-/* ##################################    SysTick function  ############################################ */

-/** \ingroup  CMSIS_Core_FunctionInterface

-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions

-    \brief      Functions that configure the System.

-  @{

- */

-

-#if (__Vendor_SysTickConfig == 0)

-

-/** \brief  System Tick Configuration

-

-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.

-    Counter is in free running mode to generate periodic interrupts.

-

-    \param [in]  ticks  Number of ticks between two interrupts.

-

-    \return          0  Function succeeded.

-    \return          1  Function failed.

-

-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the

-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>

-    must contain a vendor-specific implementation of this function.

-

- */

-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

-{

-  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */

-

-  SysTick->LOAD  = ticks - 1;                                  /* set reload register */

-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */

-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */

-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |

-                   SysTick_CTRL_TICKINT_Msk   |

-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */

-  return (0);                                                  /* Function successful */

-}

-

-#endif

-

-/*@} end of CMSIS_Core_SysTickFunctions */

-

-

-

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_CM0PLUS_H_DEPENDANT */

-

-#endif /* __CMSIS_GENERIC */

+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04)                                /*!< [31:16] CMSIS HAL main version   */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x00)                                /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+#if (__VTOR_PRESENT == 1)
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+#else
+       uint32_t RESERVED0;
+#endif
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/firmware/inc/platform/stm32f4xx/cmsis/core_cm3.h b/firmware/os/cpu/cortexm4/inc/cpu/cmsis/core_cm3.h
index d41ac3f0..e1357c67 100644
--- a/firmware/inc/platform/stm32f4xx/cmsis/core_cm3.h
+++ b/firmware/os/cpu/cortexm4/inc/cpu/cmsis/core_cm3.h
@@ -1,1650 +1,1650 @@
-/**************************************************************************//**

- * @file     core_cm3.h

- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File

- * @version  V4.00

- * @date     22. August 2014

- *

- * @note

- *

- ******************************************************************************/

-/* Copyright (c) 2009 - 2014 ARM LIMITED

-

-   All rights reserved.

-   Redistribution and use in source and binary forms, with or without

-   modification, are permitted provided that the following conditions are met:

-   - Redistributions of source code must retain the above copyright

-     notice, this list of conditions and the following disclaimer.

-   - Redistributions in binary form must reproduce the above copyright

-     notice, this list of conditions and the following disclaimer in the

-     documentation and/or other materials provided with the distribution.

-   - Neither the name of ARM nor the names of its contributors may be used

-     to endorse or promote products derived from this software without

-     specific prior written permission.

-   *

-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-   POSSIBILITY OF SUCH DAMAGE.

-   ---------------------------------------------------------------------------*/

-

-

-#if defined ( __ICCARM__ )

- #pragma system_include  /* treat file as system include file for MISRA check */

-#endif

-

-#ifndef __CORE_CM3_H_GENERIC

-#define __CORE_CM3_H_GENERIC

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions

-  CMSIS violates the following MISRA-C:2004 rules:

-

-   \li Required Rule 8.5, object/function definition in header file.<br>

-     Function definitions in header files are used to allow 'inlining'.

-

-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>

-     Unions are used for effective representation of core registers.

-

-   \li Advisory Rule 19.7, Function-like macro defined.<br>

-     Function-like macros are used to allow more efficient code.

- */

-

-

-/*******************************************************************************

- *                 CMSIS definitions

- ******************************************************************************/

-/** \ingroup Cortex_M3

-  @{

- */

-

-/*  CMSIS CM3 definitions */

-#define __CM3_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */

-#define __CM3_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */

-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \

-                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */

-

-#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */

-

-

-#if   defined ( __CC_ARM )

-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */

-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */

-  #define __STATIC_INLINE  static __inline

-

-#elif defined ( __GNUC__ )

-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */

-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __ICCARM__ )

-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */

-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TMS470__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TASKING__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */

-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __CSMC__ )

-  #define __packed

-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */

-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */

-  #define __STATIC_INLINE  static inline

-

-#endif

-

-/** __FPU_USED indicates whether an FPU is used or not.

-    This core does not support an FPU at all

-*/

-#define __FPU_USED       0

-

-#if defined ( __CC_ARM )

-  #if defined __TARGET_FPU_VFP

-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __GNUC__ )

-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __ICCARM__ )

-  #if defined __ARMVFP__

-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __TMS470__ )

-  #if defined __TI__VFP_SUPPORT____

-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __TASKING__ )

-  #if defined __FPU_VFP__

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __CSMC__ )		/* Cosmic */

-  #if ( __CSMC__ & 0x400)		// FPU present for parser

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-#endif

-

-#include <stdint.h>                      /* standard types definitions                      */

-#include <core_cmInstr.h>                /* Core Instruction Access                         */

-#include <core_cmFunc.h>                 /* Core Function Access                            */

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_CM3_H_GENERIC */

-

-#ifndef __CMSIS_GENERIC

-

-#ifndef __CORE_CM3_H_DEPENDANT

-#define __CORE_CM3_H_DEPENDANT

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/* check device defines and use defaults */

-#if defined __CHECK_DEVICE_DEFINES

-  #ifndef __CM3_REV

-    #define __CM3_REV               0x0200

-    #warning "__CM3_REV not defined in device header file; using default!"

-  #endif

-

-  #ifndef __MPU_PRESENT

-    #define __MPU_PRESENT             0

-    #warning "__MPU_PRESENT not defined in device header file; using default!"

-  #endif

-

-  #ifndef __NVIC_PRIO_BITS

-    #define __NVIC_PRIO_BITS          4

-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"

-  #endif

-

-  #ifndef __Vendor_SysTickConfig

-    #define __Vendor_SysTickConfig    0

-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"

-  #endif

-#endif

-

-/* IO definitions (access restrictions to peripheral registers) */

-/**

-    \defgroup CMSIS_glob_defs CMSIS Global Defines

-

-    <strong>IO Type Qualifiers</strong> are used

-    \li to specify the access to peripheral variables.

-    \li for automatic generation of peripheral register debug information.

-*/

-#ifdef __cplusplus

-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */

-#else

-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */

-#endif

-#define     __O     volatile             /*!< Defines 'write only' permissions                */

-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */

-

-/*@} end of group Cortex_M3 */

-

-

-

-/*******************************************************************************

- *                 Register Abstraction

-  Core Register contain:

-  - Core Register

-  - Core NVIC Register

-  - Core SCB Register

-  - Core SysTick Register

-  - Core Debug Register

-  - Core MPU Register

- ******************************************************************************/

-/** \defgroup CMSIS_core_register Defines and Type Definitions

-    \brief Type definitions and defines for Cortex-M processor based devices.

-*/

-

-/** \ingroup    CMSIS_core_register

-    \defgroup   CMSIS_CORE  Status and Control Registers

-    \brief  Core Register type definitions.

-  @{

- */

-

-/** \brief  Union type to access the Application Program Status Register (APSR).

- */

-typedef union

-{

-  struct

-  {

-#if (__CORTEX_M != 0x04)

-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */

-#else

-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */

-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */

-#endif

-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} APSR_Type;

-

-

-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} IPSR_Type;

-

-

-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

-#if (__CORTEX_M != 0x04)

-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */

-#else

-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */

-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */

-#endif

-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */

-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */

-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} xPSR_Type;

-

-

-/** \brief  Union type to access the Control Registers (CONTROL).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */

-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */

-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */

-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} CONTROL_Type;

-

-/*@} end of group CMSIS_CORE */

-

-

-/** \ingroup    CMSIS_core_register

-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)

-    \brief      Type definitions for the NVIC Registers

-  @{

- */

-

-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).

- */

-typedef struct

-{

-  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */

-       uint32_t RESERVED0[24];

-  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */

-       uint32_t RSERVED1[24];

-  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */

-       uint32_t RESERVED2[24];

-  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */

-       uint32_t RESERVED3[24];

-  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */

-       uint32_t RESERVED4[56];

-  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */

-       uint32_t RESERVED5[644];

-  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */

-}  NVIC_Type;

-

-/* Software Triggered Interrupt Register Definitions */

-#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */

-#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */

-

-/*@} end of group CMSIS_NVIC */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_SCB     System Control Block (SCB)

-    \brief      Type definitions for the System Control Block Registers

-  @{

- */

-

-/** \brief  Structure type to access the System Control Block (SCB).

- */

-typedef struct

-{

-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */

-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */

-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */

-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */

-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */

-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */

-  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */

-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */

-  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */

-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */

-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */

-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */

-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */

-  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */

-  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */

-  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */

-  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */

-  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */

-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */

-       uint32_t RESERVED0[5];

-  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */

-} SCB_Type;

-

-/* SCB CPUID Register Definitions */

-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */

-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */

-

-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */

-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */

-

-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */

-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */

-

-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */

-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */

-

-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */

-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */

-

-/* SCB Interrupt Control State Register Definitions */

-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */

-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */

-

-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */

-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */

-

-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */

-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */

-

-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */

-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */

-

-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */

-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */

-

-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */

-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */

-

-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */

-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */

-

-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */

-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */

-

-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */

-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */

-

-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */

-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */

-

-/* SCB Vector Table Offset Register Definitions */

-#if (__CM3_REV < 0x0201)                   /* core r2p1 */

-#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */

-#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */

-

-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */

-#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */

-#else

-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */

-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */

-#endif

-

-/* SCB Application Interrupt and Reset Control Register Definitions */

-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */

-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */

-

-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */

-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */

-

-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */

-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */

-

-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */

-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */

-

-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */

-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */

-

-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */

-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */

-

-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */

-#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */

-

-/* SCB System Control Register Definitions */

-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */

-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */

-

-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */

-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */

-

-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */

-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */

-

-/* SCB Configuration Control Register Definitions */

-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */

-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */

-

-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */

-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */

-

-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */

-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */

-

-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */

-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */

-

-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */

-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */

-

-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */

-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */

-

-/* SCB System Handler Control and State Register Definitions */

-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */

-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */

-

-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */

-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */

-

-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */

-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */

-

-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */

-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */

-

-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */

-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */

-

-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */

-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */

-

-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */

-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */

-

-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */

-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */

-

-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */

-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */

-

-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */

-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */

-

-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */

-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */

-

-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */

-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */

-

-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */

-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */

-

-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */

-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */

-

-/* SCB Configurable Fault Status Registers Definitions */

-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */

-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */

-

-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */

-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */

-

-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */

-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */

-

-/* SCB Hard Fault Status Registers Definitions */

-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */

-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */

-

-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */

-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */

-

-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */

-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */

-

-/* SCB Debug Fault Status Register Definitions */

-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */

-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */

-

-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */

-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */

-

-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */

-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */

-

-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */

-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */

-

-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */

-#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */

-

-/*@} end of group CMSIS_SCB */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)

-    \brief      Type definitions for the System Control and ID Register not in the SCB

-  @{

- */

-

-/** \brief  Structure type to access the System Control and ID Register not in the SCB.

- */

-typedef struct

-{

-       uint32_t RESERVED0[1];

-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */

-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))

-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */

-#else

-       uint32_t RESERVED1[1];

-#endif

-} SCnSCB_Type;

-

-/* Interrupt Controller Type Register Definitions */

-#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */

-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */

-

-/* Auxiliary Control Register Definitions */

-

-#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */

-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */

-

-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */

-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */

-

-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */

-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */

-

-/*@} end of group CMSIS_SCnotSCB */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)

-    \brief      Type definitions for the System Timer Registers.

-  @{

- */

-

-/** \brief  Structure type to access the System Timer (SysTick).

- */

-typedef struct

-{

-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */

-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */

-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */

-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */

-} SysTick_Type;

-

-/* SysTick Control / Status Register Definitions */

-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */

-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */

-

-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */

-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */

-

-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */

-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */

-

-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */

-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */

-

-/* SysTick Reload Register Definitions */

-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */

-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */

-

-/* SysTick Current Register Definitions */

-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */

-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */

-

-/* SysTick Calibration Register Definitions */

-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */

-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */

-

-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */

-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */

-

-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */

-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */

-

-/*@} end of group CMSIS_SysTick */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)

-    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)

-  @{

- */

-

-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).

- */

-typedef struct

-{

-  __O  union

-  {

-    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */

-    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */

-    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */

-  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */

-       uint32_t RESERVED0[864];

-  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */

-       uint32_t RESERVED1[15];

-  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */

-       uint32_t RESERVED2[15];

-  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */

-       uint32_t RESERVED3[29];

-  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */

-  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */

-  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */

-       uint32_t RESERVED4[43];

-  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */

-  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */

-       uint32_t RESERVED5[6];

-  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */

-  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */

-  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */

-  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */

-  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */

-  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */

-  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */

-  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */

-  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */

-  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */

-  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */

-  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */

-} ITM_Type;

-

-/* ITM Trace Privilege Register Definitions */

-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */

-#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */

-

-/* ITM Trace Control Register Definitions */

-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */

-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */

-

-#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */

-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */

-

-#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */

-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */

-

-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */

-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */

-

-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */

-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */

-

-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */

-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */

-

-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */

-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */

-

-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */

-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */

-

-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */

-#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */

-

-/* ITM Integration Write Register Definitions */

-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */

-#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */

-

-/* ITM Integration Read Register Definitions */

-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */

-#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */

-

-/* ITM Integration Mode Control Register Definitions */

-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */

-#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */

-

-/* ITM Lock Status Register Definitions */

-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */

-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */

-

-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */

-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */

-

-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */

-#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */

-

-/*@}*/ /* end of group CMSIS_ITM */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)

-    \brief      Type definitions for the Data Watchpoint and Trace (DWT)

-  @{

- */

-

-/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).

- */

-typedef struct

-{

-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */

-  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */

-  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */

-  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */

-  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */

-  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */

-  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */

-  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */

-  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */

-  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */

-  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */

-       uint32_t RESERVED0[1];

-  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */

-  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */

-  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */

-       uint32_t RESERVED1[1];

-  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */

-  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */

-  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */

-       uint32_t RESERVED2[1];

-  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */

-  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */

-  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */

-} DWT_Type;

-

-/* DWT Control Register Definitions */

-#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */

-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */

-

-#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */

-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */

-

-#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */

-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */

-

-#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */

-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */

-

-#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */

-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */

-

-#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */

-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */

-

-#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */

-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */

-

-#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */

-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */

-

-#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */

-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */

-

-#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */

-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */

-

-#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */

-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */

-

-#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */

-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */

-

-#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */

-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */

-

-#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */

-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */

-

-#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */

-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */

-

-#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */

-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */

-

-#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */

-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */

-

-#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */

-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */

-

-/* DWT CPI Count Register Definitions */

-#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */

-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */

-

-/* DWT Exception Overhead Count Register Definitions */

-#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */

-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */

-

-/* DWT Sleep Count Register Definitions */

-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */

-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */

-

-/* DWT LSU Count Register Definitions */

-#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */

-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */

-

-/* DWT Folded-instruction Count Register Definitions */

-#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */

-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */

-

-/* DWT Comparator Mask Register Definitions */

-#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */

-#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */

-

-/* DWT Comparator Function Register Definitions */

-#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */

-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */

-

-#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */

-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */

-

-#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */

-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */

-

-#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */

-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */

-

-#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */

-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */

-

-#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */

-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */

-

-#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */

-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */

-

-#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */

-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */

-

-#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */

-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */

-

-/*@}*/ /* end of group CMSIS_DWT */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_TPI     Trace Port Interface (TPI)

-    \brief      Type definitions for the Trace Port Interface (TPI)

-  @{

- */

-

-/** \brief  Structure type to access the Trace Port Interface Register (TPI).

- */

-typedef struct

-{

-  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */

-  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */

-       uint32_t RESERVED0[2];

-  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */

-       uint32_t RESERVED1[55];

-  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */

-       uint32_t RESERVED2[131];

-  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */

-  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */

-  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */

-       uint32_t RESERVED3[759];

-  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */

-  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */

-  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */

-       uint32_t RESERVED4[1];

-  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */

-  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */

-  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */

-       uint32_t RESERVED5[39];

-  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */

-  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */

-       uint32_t RESERVED7[8];

-  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */

-  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */

-} TPI_Type;

-

-/* TPI Asynchronous Clock Prescaler Register Definitions */

-#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */

-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */

-

-/* TPI Selected Pin Protocol Register Definitions */

-#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */

-#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */

-

-/* TPI Formatter and Flush Status Register Definitions */

-#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */

-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */

-

-#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */

-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */

-

-#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */

-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */

-

-#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */

-#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */

-

-/* TPI Formatter and Flush Control Register Definitions */

-#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */

-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */

-

-#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */

-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */

-

-/* TPI TRIGGER Register Definitions */

-#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */

-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */

-

-/* TPI Integration ETM Data Register Definitions (FIFO0) */

-#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */

-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */

-

-#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */

-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */

-

-#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */

-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */

-

-#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */

-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */

-

-#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */

-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */

-

-#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */

-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */

-

-#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */

-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */

-

-/* TPI ITATBCTR2 Register Definitions */

-#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */

-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */

-

-/* TPI Integration ITM Data Register Definitions (FIFO1) */

-#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */

-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */

-

-#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */

-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */

-

-#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */

-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */

-

-#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */

-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */

-

-#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */

-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */

-

-#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */

-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */

-

-#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */

-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */

-

-/* TPI ITATBCTR0 Register Definitions */

-#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */

-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */

-

-/* TPI Integration Mode Control Register Definitions */

-#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */

-#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */

-

-/* TPI DEVID Register Definitions */

-#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */

-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */

-

-#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */

-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */

-

-#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */

-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */

-

-#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */

-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */

-

-#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */

-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */

-

-#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */

-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */

-

-/* TPI DEVTYPE Register Definitions */

-#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */

-#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */

-

-#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */

-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */

-

-/*@}*/ /* end of group CMSIS_TPI */

-

-

-#if (__MPU_PRESENT == 1)

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)

-    \brief      Type definitions for the Memory Protection Unit (MPU)

-  @{

- */

-

-/** \brief  Structure type to access the Memory Protection Unit (MPU).

- */

-typedef struct

-{

-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */

-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */

-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */

-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */

-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */

-  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */

-  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */

-  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */

-  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */

-  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */

-  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */

-} MPU_Type;

-

-/* MPU Type Register */

-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */

-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */

-

-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */

-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */

-

-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */

-#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */

-

-/* MPU Control Register */

-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */

-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */

-

-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */

-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */

-

-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */

-#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */

-

-/* MPU Region Number Register */

-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */

-#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */

-

-/* MPU Region Base Address Register */

-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */

-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */

-

-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */

-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */

-

-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */

-#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */

-

-/* MPU Region Attribute and Size Register */

-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */

-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */

-

-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */

-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */

-

-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */

-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */

-

-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */

-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */

-

-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */

-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */

-

-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */

-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */

-

-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */

-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */

-

-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */

-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */

-

-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */

-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */

-

-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */

-#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */

-

-/*@} end of group CMSIS_MPU */

-#endif

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)

-    \brief      Type definitions for the Core Debug Registers

-  @{

- */

-

-/** \brief  Structure type to access the Core Debug Register (CoreDebug).

- */

-typedef struct

-{

-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */

-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */

-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */

-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */

-} CoreDebug_Type;

-

-/* Debug Halting Control and Status Register */

-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */

-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */

-

-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */

-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */

-

-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */

-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */

-

-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */

-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */

-

-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */

-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */

-

-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */

-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */

-

-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */

-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */

-

-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */

-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */

-

-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */

-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */

-

-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */

-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */

-

-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */

-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */

-

-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */

-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */

-

-/* Debug Core Register Selector Register */

-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */

-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */

-

-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */

-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */

-

-/* Debug Exception and Monitor Control Register */

-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */

-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */

-

-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */

-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */

-

-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */

-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */

-

-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */

-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */

-

-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */

-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */

-

-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */

-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */

-

-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */

-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */

-

-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */

-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */

-

-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */

-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */

-

-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */

-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */

-

-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */

-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */

-

-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */

-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */

-

-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */

-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */

-

-/*@} end of group CMSIS_CoreDebug */

-

-

-/** \ingroup    CMSIS_core_register

-    \defgroup   CMSIS_core_base     Core Definitions

-    \brief      Definitions for base addresses, unions, and structures.

-  @{

- */

-

-/* Memory mapping of Cortex-M3 Hardware */

-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */

-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */

-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */

-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */

-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */

-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */

-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */

-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */

-

-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */

-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */

-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */

-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */

-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */

-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */

-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */

-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */

-

-#if (__MPU_PRESENT == 1)

-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */

-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */

-#endif

-

-/*@} */

-

-

-

-/*******************************************************************************

- *                Hardware Abstraction Layer

-  Core Function Interface contains:

-  - Core NVIC Functions

-  - Core SysTick Functions

-  - Core Debug Functions

-  - Core Register Access Functions

- ******************************************************************************/

-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference

-*/

-

-

-

-/* ##########################   NVIC functions  #################################### */

-/** \ingroup  CMSIS_Core_FunctionInterface

-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions

-    \brief      Functions that manage interrupts and exceptions via the NVIC.

-    @{

- */

-

-/** \brief  Set Priority Grouping

-

-  The function sets the priority grouping field using the required unlock sequence.

-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.

-  Only values from 0..7 are used.

-  In case of a conflict between priority grouping and available

-  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

-

-    \param [in]      PriorityGroup  Priority grouping field.

- */

-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)

-{

-  uint32_t reg_value;

-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */

-

-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */

-  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */

-  reg_value  =  (reg_value                                 |

-                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |

-                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */

-  SCB->AIRCR =  reg_value;

-}

-

-

-/** \brief  Get Priority Grouping

-

-  The function reads the priority grouping field from the NVIC Interrupt Controller.

-

-    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).

- */

-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)

-{

-  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */

-}

-

-

-/** \brief  Enable External Interrupt

-

-    The function enables a device-specific interrupt in the NVIC interrupt controller.

-

-    \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)

-{

-  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */

-}

-

-

-/** \brief  Disable External Interrupt

-

-    The function disables a device-specific interrupt in the NVIC interrupt controller.

-

-    \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */

-}

-

-

-/** \brief  Get Pending Interrupt

-

-    The function reads the pending register in the NVIC and returns the pending bit

-    for the specified interrupt.

-

-    \param [in]      IRQn  Interrupt number.

-

-    \return             0  Interrupt status is not pending.

-    \return             1  Interrupt status is pending.

- */

-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)

-{

-  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */

-}

-

-

-/** \brief  Set Pending Interrupt

-

-    The function sets the pending bit of an external interrupt.

-

-    \param [in]      IRQn  Interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */

-}

-

-

-/** \brief  Clear Pending Interrupt

-

-    The function clears the pending bit of an external interrupt.

-

-    \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */

-}

-

-

-/** \brief  Get Active Interrupt

-

-    The function reads the active register in NVIC and returns the active bit.

-

-    \param [in]      IRQn  Interrupt number.

-

-    \return             0  Interrupt status is not active.

-    \return             1  Interrupt status is active.

- */

-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)

-{

-  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */

-}

-

-

-/** \brief  Set Interrupt Priority

-

-    The function sets the priority of an interrupt.

-

-    \note The priority cannot be set for every core interrupt.

-

-    \param [in]      IRQn  Interrupt number.

-    \param [in]  priority  Priority to set.

- */

-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

-{

-  if(IRQn < 0) {

-    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */

-  else {

-    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */

-}

-

-

-/** \brief  Get Interrupt Priority

-

-    The function reads the priority of an interrupt. The interrupt

-    number can be positive to specify an external (device specific)

-    interrupt, or negative to specify an internal (core) interrupt.

-

-

-    \param [in]   IRQn  Interrupt number.

-    \return             Interrupt Priority. Value is aligned automatically to the implemented

-                        priority bits of the microcontroller.

- */

-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)

-{

-

-  if(IRQn < 0) {

-    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */

-  else {

-    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */

-}

-

-

-/** \brief  Encode Priority

-

-    The function encodes the priority for an interrupt with the given priority group,

-    preemptive priority value, and subpriority value.

-    In case of a conflict between priority grouping and available

-    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

-

-    \param [in]     PriorityGroup  Used priority group.

-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).

-    \param [in]       SubPriority  Subpriority value (starting from 0).

-    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().

- */

-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)

-{

-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */

-  uint32_t PreemptPriorityBits;

-  uint32_t SubPriorityBits;

-

-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;

-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;

-

-  return (

-           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |

-           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))

-         );

-}

-

-

-/** \brief  Decode Priority

-

-    The function decodes an interrupt priority value with a given priority group to

-    preemptive priority value and subpriority value.

-    In case of a conflict between priority grouping and available

-    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.

-

-    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().

-    \param [in]     PriorityGroup  Used priority group.

-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).

-    \param [out]     pSubPriority  Subpriority value (starting from 0).

- */

-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)

-{

-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */

-  uint32_t PreemptPriorityBits;

-  uint32_t SubPriorityBits;

-

-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;

-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;

-

-  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);

-  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);

-}

-

-

-/** \brief  System Reset

-

-    The function initiates a system reset request to reset the MCU.

- */

-__STATIC_INLINE void NVIC_SystemReset(void)

-{

-  __DSB();                                                     /* Ensure all outstanding memory accesses included

-                                                                  buffered write are completed before reset */

-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |

-                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |

-                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */

-  __DSB();                                                     /* Ensure completion of memory access */

-  while(1);                                                    /* wait until reset */

-}

-

-/*@} end of CMSIS_Core_NVICFunctions */

-

-

-

-/* ##################################    SysTick function  ############################################ */

-/** \ingroup  CMSIS_Core_FunctionInterface

-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions

-    \brief      Functions that configure the System.

-  @{

- */

-

-#if (__Vendor_SysTickConfig == 0)

-

-/** \brief  System Tick Configuration

-

-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.

-    Counter is in free running mode to generate periodic interrupts.

-

-    \param [in]  ticks  Number of ticks between two interrupts.

-

-    \return          0  Function succeeded.

-    \return          1  Function failed.

-

-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the

-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>

-    must contain a vendor-specific implementation of this function.

-

- */

-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

-{

-  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */

-

-  SysTick->LOAD  = ticks - 1;                                  /* set reload register */

-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */

-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */

-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |

-                   SysTick_CTRL_TICKINT_Msk   |

-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */

-  return (0);                                                  /* Function successful */

-}

-

-#endif

-

-/*@} end of CMSIS_Core_SysTickFunctions */

-

-

-

-/* ##################################### Debug In/Output function ########################################### */

-/** \ingroup  CMSIS_Core_FunctionInterface

-    \defgroup CMSIS_core_DebugFunctions ITM Functions

-    \brief   Functions that access the ITM debug interface.

-  @{

- */

-

-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */

-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */

-

-

-/** \brief  ITM Send Character

-

-    The function transmits a character via the ITM channel 0, and

-    \li Just returns when no debugger is connected that has booked the output.

-    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.

-

-    \param [in]     ch  Character to transmit.

-

-    \returns            Character to transmit.

- */

-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)

-{

-  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */

-      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */

-  {

-    while (ITM->PORT[0].u32 == 0);

-    ITM->PORT[0].u8 = (uint8_t) ch;

-  }

-  return (ch);

-}

-

-

-/** \brief  ITM Receive Character

-

-    The function inputs a character via the external variable \ref ITM_RxBuffer.

-

-    \return             Received character.

-    \return         -1  No character pending.

- */

-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {

-  int32_t ch = -1;                           /* no character available */

-

-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {

-    ch = ITM_RxBuffer;

-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */

-  }

-

-  return (ch);

-}

-

-

-/** \brief  ITM Check Character

-

-    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.

-

-    \return          0  No character available.

-    \return          1  Character available.

- */

-__STATIC_INLINE int32_t ITM_CheckChar (void) {

-

-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {

-    return (0);                                 /* no character available */

-  } else {

-    return (1);                                 /*    character available */

-  }

-}

-

-/*@} end of CMSIS_core_DebugFunctions */

-

-

-

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_CM3_H_DEPENDANT */

-

-#endif /* __CMSIS_GENERIC */

+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+  @{
+ */
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM3_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/firmware/inc/platform/stm32f4xx/cmsis/core_cm4.h b/firmware/os/cpu/cortexm4/inc/cpu/cmsis/core_cm4.h
index 827dc384..fde301fd 100644
--- a/firmware/inc/platform/stm32f4xx/cmsis/core_cm4.h
+++ b/firmware/os/cpu/cortexm4/inc/cpu/cmsis/core_cm4.h
@@ -1,1802 +1,1802 @@
-/**************************************************************************//**

- * @file     core_cm4.h

- * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File

- * @version  V4.00

- * @date     22. August 2014

- *

- * @note

- *

- ******************************************************************************/

-/* Copyright (c) 2009 - 2014 ARM LIMITED

-

-   All rights reserved.

-   Redistribution and use in source and binary forms, with or without

-   modification, are permitted provided that the following conditions are met:

-   - Redistributions of source code must retain the above copyright

-     notice, this list of conditions and the following disclaimer.

-   - Redistributions in binary form must reproduce the above copyright

-     notice, this list of conditions and the following disclaimer in the

-     documentation and/or other materials provided with the distribution.

-   - Neither the name of ARM nor the names of its contributors may be used

-     to endorse or promote products derived from this software without

-     specific prior written permission.

-   *

-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-   POSSIBILITY OF SUCH DAMAGE.

-   ---------------------------------------------------------------------------*/

-

-

-#if defined ( __ICCARM__ )

- #pragma system_include  /* treat file as system include file for MISRA check */

-#endif

-

-#ifndef __CORE_CM4_H_GENERIC

-#define __CORE_CM4_H_GENERIC

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions

-  CMSIS violates the following MISRA-C:2004 rules:

-

-   \li Required Rule 8.5, object/function definition in header file.<br>

-     Function definitions in header files are used to allow 'inlining'.

-

-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>

-     Unions are used for effective representation of core registers.

-

-   \li Advisory Rule 19.7, Function-like macro defined.<br>

-     Function-like macros are used to allow more efficient code.

- */

-

-

-/*******************************************************************************

- *                 CMSIS definitions

- ******************************************************************************/

-/** \ingroup Cortex_M4

-  @{

- */

-

-/*  CMSIS CM4 definitions */

-#define __CM4_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */

-#define __CM4_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */

-#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \

-                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */

-

-#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */

-

-

-#if   defined ( __CC_ARM )

-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */

-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */

-  #define __STATIC_INLINE  static __inline

-

-#elif defined ( __GNUC__ )

-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */

-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __ICCARM__ )

-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */

-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TMS470__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TASKING__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */

-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __CSMC__ )

-  #define __packed

-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */

-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */

-  #define __STATIC_INLINE  static inline

-

-#endif

-

-/** __FPU_USED indicates whether an FPU is used or not.

-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.

-*/

-#if defined ( __CC_ARM )

-  #if defined __TARGET_FPU_VFP

-    #if (__FPU_PRESENT == 1)

-      #define __FPU_USED       1

-    #else

-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-      #define __FPU_USED       0

-    #endif

-  #else

-    #define __FPU_USED         0

-  #endif

-

-#elif defined ( __GNUC__ )

-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

-    #if (__FPU_PRESENT == 1)

-      #define __FPU_USED       1

-    #else

-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-      #define __FPU_USED       0

-    #endif

-  #else

-    #define __FPU_USED         0

-  #endif

-

-#elif defined ( __ICCARM__ )

-  #if defined __ARMVFP__

-    #if (__FPU_PRESENT == 1)

-      #define __FPU_USED       1

-    #else

-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-      #define __FPU_USED       0

-    #endif

-  #else

-    #define __FPU_USED         0

-  #endif

-

-#elif defined ( __TMS470__ )

-  #if defined __TI_VFP_SUPPORT__

-    #if (__FPU_PRESENT == 1)

-      #define __FPU_USED       1

-    #else

-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-      #define __FPU_USED       0

-    #endif

-  #else

-    #define __FPU_USED         0

-  #endif

-

-#elif defined ( __TASKING__ )

-  #if defined __FPU_VFP__

-    #if (__FPU_PRESENT == 1)

-      #define __FPU_USED       1

-    #else

-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-      #define __FPU_USED       0

-    #endif

-  #else

-    #define __FPU_USED         0

-  #endif

-

-#elif defined ( __CSMC__ )		/* Cosmic */

-  #if ( __CSMC__ & 0x400)		// FPU present for parser

-    #if (__FPU_PRESENT == 1)

-      #define __FPU_USED       1

-    #else

-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-      #define __FPU_USED       0

-    #endif

-  #else

-    #define __FPU_USED         0

-  #endif

-#endif

-

-#include <stdint.h>                      /* standard types definitions                      */

-#include <core_cmInstr.h>                /* Core Instruction Access                         */

-#include <core_cmFunc.h>                 /* Core Function Access                            */

-#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_CM4_H_GENERIC */

-

-#ifndef __CMSIS_GENERIC

-

-#ifndef __CORE_CM4_H_DEPENDANT

-#define __CORE_CM4_H_DEPENDANT

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/* check device defines and use defaults */

-#if defined __CHECK_DEVICE_DEFINES

-  #ifndef __CM4_REV

-    #define __CM4_REV               0x0000

-    #warning "__CM4_REV not defined in device header file; using default!"

-  #endif

-

-  #ifndef __FPU_PRESENT

-    #define __FPU_PRESENT             0

-    #warning "__FPU_PRESENT not defined in device header file; using default!"

-  #endif

-

-  #ifndef __MPU_PRESENT

-    #define __MPU_PRESENT             0

-    #warning "__MPU_PRESENT not defined in device header file; using default!"

-  #endif

-

-  #ifndef __NVIC_PRIO_BITS

-    #define __NVIC_PRIO_BITS          4

-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"

-  #endif

-

-  #ifndef __Vendor_SysTickConfig

-    #define __Vendor_SysTickConfig    0

-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"

-  #endif

-#endif

-

-/* IO definitions (access restrictions to peripheral registers) */

-/**

-    \defgroup CMSIS_glob_defs CMSIS Global Defines

-

-    <strong>IO Type Qualifiers</strong> are used

-    \li to specify the access to peripheral variables.

-    \li for automatic generation of peripheral register debug information.

-*/

-#ifdef __cplusplus

-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */

-#else

-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */

-#endif

-#define     __O     volatile             /*!< Defines 'write only' permissions                */

-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */

-

-/*@} end of group Cortex_M4 */

-

-

-

-/*******************************************************************************

- *                 Register Abstraction

-  Core Register contain:

-  - Core Register

-  - Core NVIC Register

-  - Core SCB Register

-  - Core SysTick Register

-  - Core Debug Register

-  - Core MPU Register

-  - Core FPU Register

- ******************************************************************************/

-/** \defgroup CMSIS_core_register Defines and Type Definitions

-    \brief Type definitions and defines for Cortex-M processor based devices.

-*/

-

-/** \ingroup    CMSIS_core_register

-    \defgroup   CMSIS_CORE  Status and Control Registers

-    \brief  Core Register type definitions.

-  @{

- */

-

-/** \brief  Union type to access the Application Program Status Register (APSR).

- */

-typedef union

-{

-  struct

-  {

-#if (__CORTEX_M != 0x04)

-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */

-#else

-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */

-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */

-#endif

-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} APSR_Type;

-

-

-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} IPSR_Type;

-

-

-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

-#if (__CORTEX_M != 0x04)

-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */

-#else

-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */

-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */

-#endif

-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */

-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */

-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} xPSR_Type;

-

-

-/** \brief  Union type to access the Control Registers (CONTROL).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */

-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */

-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */

-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} CONTROL_Type;

-

-/*@} end of group CMSIS_CORE */

-

-

-/** \ingroup    CMSIS_core_register

-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)

-    \brief      Type definitions for the NVIC Registers

-  @{

- */

-

-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).

- */

-typedef struct

-{

-  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */

-       uint32_t RESERVED0[24];

-  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */

-       uint32_t RSERVED1[24];

-  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */

-       uint32_t RESERVED2[24];

-  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */

-       uint32_t RESERVED3[24];

-  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */

-       uint32_t RESERVED4[56];

-  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */

-       uint32_t RESERVED5[644];

-  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */

-}  NVIC_Type;

-

-/* Software Triggered Interrupt Register Definitions */

-#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */

-#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */

-

-/*@} end of group CMSIS_NVIC */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_SCB     System Control Block (SCB)

-    \brief      Type definitions for the System Control Block Registers

-  @{

- */

-

-/** \brief  Structure type to access the System Control Block (SCB).

- */

-typedef struct

-{

-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */

-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */

-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */

-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */

-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */

-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */

-  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */

-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */

-  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */

-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */

-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */

-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */

-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */

-  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */

-  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */

-  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */

-  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */

-  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */

-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */

-       uint32_t RESERVED0[5];

-  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */

-} SCB_Type;

-

-/* SCB CPUID Register Definitions */

-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */

-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */

-

-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */

-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */

-

-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */

-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */

-

-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */

-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */

-

-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */

-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */

-

-/* SCB Interrupt Control State Register Definitions */

-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */

-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */

-

-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */

-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */

-

-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */

-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */

-

-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */

-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */

-

-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */

-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */

-

-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */

-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */

-

-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */

-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */

-

-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */

-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */

-

-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */

-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */

-

-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */

-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */

-

-/* SCB Vector Table Offset Register Definitions */

-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */

-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */

-

-/* SCB Application Interrupt and Reset Control Register Definitions */

-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */

-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */

-

-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */

-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */

-

-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */

-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */

-

-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */

-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */

-

-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */

-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */

-

-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */

-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */

-

-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */

-#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */

-

-/* SCB System Control Register Definitions */

-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */

-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */

-

-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */

-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */

-

-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */

-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */

-

-/* SCB Configuration Control Register Definitions */

-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */

-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */

-

-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */

-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */

-

-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */

-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */

-

-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */

-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */

-

-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */

-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */

-

-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */

-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */

-

-/* SCB System Handler Control and State Register Definitions */

-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */

-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */

-

-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */

-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */

-

-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */

-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */

-

-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */

-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */

-

-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */

-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */

-

-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */

-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */

-

-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */

-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */

-

-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */

-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */

-

-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */

-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */

-

-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */

-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */

-

-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */

-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */

-

-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */

-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */

-

-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */

-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */

-

-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */

-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */

-

-/* SCB Configurable Fault Status Registers Definitions */

-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */

-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */

-

-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */

-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */

-

-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */

-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */

-

-/* SCB Hard Fault Status Registers Definitions */

-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */

-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */

-

-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */

-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */

-

-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */

-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */

-

-/* SCB Debug Fault Status Register Definitions */

-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */

-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */

-

-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */

-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */

-

-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */

-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */

-

-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */

-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */

-

-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */

-#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */

-

-/*@} end of group CMSIS_SCB */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)

-    \brief      Type definitions for the System Control and ID Register not in the SCB

-  @{

- */

-

-/** \brief  Structure type to access the System Control and ID Register not in the SCB.

- */

-typedef struct

-{

-       uint32_t RESERVED0[1];

-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */

-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */

-} SCnSCB_Type;

-

-/* Interrupt Controller Type Register Definitions */

-#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */

-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */

-

-/* Auxiliary Control Register Definitions */

-#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */

-#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */

-

-#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */

-#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */

-

-#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */

-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */

-

-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */

-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */

-

-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */

-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */

-

-/*@} end of group CMSIS_SCnotSCB */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)

-    \brief      Type definitions for the System Timer Registers.

-  @{

- */

-

-/** \brief  Structure type to access the System Timer (SysTick).

- */

-typedef struct

-{

-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */

-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */

-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */

-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */

-} SysTick_Type;

-

-/* SysTick Control / Status Register Definitions */

-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */

-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */

-

-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */

-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */

-

-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */

-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */

-

-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */

-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */

-

-/* SysTick Reload Register Definitions */

-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */

-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */

-

-/* SysTick Current Register Definitions */

-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */

-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */

-

-/* SysTick Calibration Register Definitions */

-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */

-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */

-

-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */

-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */

-

-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */

-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */

-

-/*@} end of group CMSIS_SysTick */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)

-    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)

-  @{

- */

-

-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).

- */

-typedef struct

-{

-  __O  union

-  {

-    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */

-    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */

-    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */

-  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */

-       uint32_t RESERVED0[864];

-  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */

-       uint32_t RESERVED1[15];

-  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */

-       uint32_t RESERVED2[15];

-  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */

-       uint32_t RESERVED3[29];

-  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */

-  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */

-  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */

-       uint32_t RESERVED4[43];

-  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */

-  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */

-       uint32_t RESERVED5[6];

-  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */

-  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */

-  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */

-  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */

-  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */

-  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */

-  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */

-  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */

-  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */

-  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */

-  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */

-  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */

-} ITM_Type;

-

-/* ITM Trace Privilege Register Definitions */

-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */

-#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */

-

-/* ITM Trace Control Register Definitions */

-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */

-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */

-

-#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */

-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */

-

-#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */

-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */

-

-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */

-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */

-

-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */

-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */

-

-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */

-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */

-

-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */

-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */

-

-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */

-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */

-

-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */

-#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */

-

-/* ITM Integration Write Register Definitions */

-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */

-#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */

-

-/* ITM Integration Read Register Definitions */

-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */

-#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */

-

-/* ITM Integration Mode Control Register Definitions */

-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */

-#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */

-

-/* ITM Lock Status Register Definitions */

-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */

-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */

-

-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */

-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */

-

-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */

-#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */

-

-/*@}*/ /* end of group CMSIS_ITM */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)

-    \brief      Type definitions for the Data Watchpoint and Trace (DWT)

-  @{

- */

-

-/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).

- */

-typedef struct

-{

-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */

-  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */

-  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */

-  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */

-  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */

-  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */

-  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */

-  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */

-  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */

-  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */

-  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */

-       uint32_t RESERVED0[1];

-  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */

-  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */

-  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */

-       uint32_t RESERVED1[1];

-  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */

-  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */

-  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */

-       uint32_t RESERVED2[1];

-  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */

-  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */

-  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */

-} DWT_Type;

-

-/* DWT Control Register Definitions */

-#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */

-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */

-

-#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */

-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */

-

-#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */

-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */

-

-#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */

-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */

-

-#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */

-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */

-

-#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */

-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */

-

-#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */

-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */

-

-#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */

-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */

-

-#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */

-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */

-

-#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */

-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */

-

-#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */

-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */

-

-#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */

-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */

-

-#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */

-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */

-

-#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */

-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */

-

-#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */

-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */

-

-#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */

-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */

-

-#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */

-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */

-

-#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */

-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */

-

-/* DWT CPI Count Register Definitions */

-#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */

-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */

-

-/* DWT Exception Overhead Count Register Definitions */

-#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */

-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */

-

-/* DWT Sleep Count Register Definitions */

-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */

-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */

-

-/* DWT LSU Count Register Definitions */

-#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */

-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */

-

-/* DWT Folded-instruction Count Register Definitions */

-#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */

-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */

-

-/* DWT Comparator Mask Register Definitions */

-#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */

-#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */

-

-/* DWT Comparator Function Register Definitions */

-#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */

-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */

-

-#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */

-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */

-

-#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */

-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */

-

-#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */

-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */

-

-#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */

-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */

-

-#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */

-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */

-

-#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */

-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */

-

-#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */

-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */

-

-#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */

-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */

-

-/*@}*/ /* end of group CMSIS_DWT */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_TPI     Trace Port Interface (TPI)

-    \brief      Type definitions for the Trace Port Interface (TPI)

-  @{

- */

-

-/** \brief  Structure type to access the Trace Port Interface Register (TPI).

- */

-typedef struct

-{

-  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */

-  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */

-       uint32_t RESERVED0[2];

-  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */

-       uint32_t RESERVED1[55];

-  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */

-       uint32_t RESERVED2[131];

-  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */

-  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */

-  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */

-       uint32_t RESERVED3[759];

-  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */

-  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */

-  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */

-       uint32_t RESERVED4[1];

-  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */

-  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */

-  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */

-       uint32_t RESERVED5[39];

-  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */

-  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */

-       uint32_t RESERVED7[8];

-  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */

-  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */

-} TPI_Type;

-

-/* TPI Asynchronous Clock Prescaler Register Definitions */

-#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */

-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */

-

-/* TPI Selected Pin Protocol Register Definitions */

-#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */

-#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */

-

-/* TPI Formatter and Flush Status Register Definitions */

-#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */

-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */

-

-#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */

-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */

-

-#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */

-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */

-

-#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */

-#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */

-

-/* TPI Formatter and Flush Control Register Definitions */

-#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */

-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */

-

-#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */

-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */

-

-/* TPI TRIGGER Register Definitions */

-#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */

-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */

-

-/* TPI Integration ETM Data Register Definitions (FIFO0) */

-#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */

-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */

-

-#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */

-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */

-

-#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */

-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */

-

-#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */

-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */

-

-#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */

-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */

-

-#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */

-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */

-

-#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */

-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */

-

-/* TPI ITATBCTR2 Register Definitions */

-#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */

-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */

-

-/* TPI Integration ITM Data Register Definitions (FIFO1) */

-#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */

-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */

-

-#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */

-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */

-

-#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */

-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */

-

-#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */

-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */

-

-#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */

-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */

-

-#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */

-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */

-

-#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */

-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */

-

-/* TPI ITATBCTR0 Register Definitions */

-#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */

-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */

-

-/* TPI Integration Mode Control Register Definitions */

-#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */

-#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */

-

-/* TPI DEVID Register Definitions */

-#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */

-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */

-

-#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */

-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */

-

-#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */

-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */

-

-#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */

-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */

-

-#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */

-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */

-

-#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */

-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */

-

-/* TPI DEVTYPE Register Definitions */

-#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */

-#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */

-

-#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */

-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */

-

-/*@}*/ /* end of group CMSIS_TPI */

-

-

-#if (__MPU_PRESENT == 1)

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)

-    \brief      Type definitions for the Memory Protection Unit (MPU)

-  @{

- */

-

-/** \brief  Structure type to access the Memory Protection Unit (MPU).

- */

-typedef struct

-{

-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */

-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */

-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */

-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */

-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */

-  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */

-  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */

-  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */

-  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */

-  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */

-  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */

-} MPU_Type;

-

-/* MPU Type Register */

-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */

-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */

-

-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */

-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */

-

-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */

-#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */

-

-/* MPU Control Register */

-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */

-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */

-

-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */

-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */

-

-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */

-#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */

-

-/* MPU Region Number Register */

-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */

-#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */

-

-/* MPU Region Base Address Register */

-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */

-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */

-

-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */

-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */

-

-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */

-#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */

-

-/* MPU Region Attribute and Size Register */

-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */

-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */

-

-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */

-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */

-

-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */

-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */

-

-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */

-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */

-

-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */

-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */

-

-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */

-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */

-

-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */

-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */

-

-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */

-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */

-

-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */

-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */

-

-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */

-#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */

-

-/*@} end of group CMSIS_MPU */

-#endif

-

-

-#if (__FPU_PRESENT == 1)

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_FPU     Floating Point Unit (FPU)

-    \brief      Type definitions for the Floating Point Unit (FPU)

-  @{

- */

-

-/** \brief  Structure type to access the Floating Point Unit (FPU).

- */

-typedef struct

-{

-       uint32_t RESERVED0[1];

-  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */

-  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */

-  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */

-  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */

-  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */

-} FPU_Type;

-

-/* Floating-Point Context Control Register */

-#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */

-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */

-

-#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */

-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */

-

-#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */

-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */

-

-#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */

-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */

-

-#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */

-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */

-

-#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */

-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */

-

-#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */

-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */

-

-#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */

-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */

-

-#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */

-#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */

-

-/* Floating-Point Context Address Register */

-#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */

-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */

-

-/* Floating-Point Default Status Control Register */

-#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */

-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */

-

-#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */

-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */

-

-#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */

-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */

-

-#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */

-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */

-

-/* Media and FP Feature Register 0 */

-#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */

-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */

-

-#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */

-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */

-

-#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */

-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */

-

-#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */

-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */

-

-#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */

-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */

-

-#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */

-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */

-

-#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */

-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */

-

-#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */

-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */

-

-/* Media and FP Feature Register 1 */

-#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */

-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */

-

-#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */

-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */

-

-#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */

-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */

-

-#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */

-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */

-

-/*@} end of group CMSIS_FPU */

-#endif

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)

-    \brief      Type definitions for the Core Debug Registers

-  @{

- */

-

-/** \brief  Structure type to access the Core Debug Register (CoreDebug).

- */

-typedef struct

-{

-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */

-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */

-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */

-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */

-} CoreDebug_Type;

-

-/* Debug Halting Control and Status Register */

-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */

-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */

-

-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */

-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */

-

-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */

-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */

-

-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */

-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */

-

-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */

-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */

-

-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */

-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */

-

-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */

-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */

-

-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */

-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */

-

-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */

-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */

-

-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */

-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */

-

-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */

-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */

-

-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */

-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */

-

-/* Debug Core Register Selector Register */

-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */

-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */

-

-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */

-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */

-

-/* Debug Exception and Monitor Control Register */

-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */

-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */

-

-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */

-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */

-

-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */

-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */

-

-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */

-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */

-

-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */

-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */

-

-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */

-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */

-

-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */

-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */

-

-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */

-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */

-

-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */

-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */

-

-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */

-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */

-

-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */

-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */

-

-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */

-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */

-

-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */

-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */

-

-/*@} end of group CMSIS_CoreDebug */

-

-

-/** \ingroup    CMSIS_core_register

-    \defgroup   CMSIS_core_base     Core Definitions

-    \brief      Definitions for base addresses, unions, and structures.

-  @{

- */

-

-/* Memory mapping of Cortex-M4 Hardware */

-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */

-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */

-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */

-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */

-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */

-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */

-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */

-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */

-

-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */

-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */

-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */

-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */

-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */

-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */

-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */

-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */

-

-#if (__MPU_PRESENT == 1)

-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */

-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */

-#endif

-

-#if (__FPU_PRESENT == 1)

-  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */

-  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */

-#endif

-

-/*@} */

-

-

-

-/*******************************************************************************

- *                Hardware Abstraction Layer

-  Core Function Interface contains:

-  - Core NVIC Functions

-  - Core SysTick Functions

-  - Core Debug Functions

-  - Core Register Access Functions

- ******************************************************************************/

-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference

-*/

-

-

-

-/* ##########################   NVIC functions  #################################### */

-/** \ingroup  CMSIS_Core_FunctionInterface

-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions

-    \brief      Functions that manage interrupts and exceptions via the NVIC.

-    @{

- */

-

-/** \brief  Set Priority Grouping

-

-  The function sets the priority grouping field using the required unlock sequence.

-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.

-  Only values from 0..7 are used.

-  In case of a conflict between priority grouping and available

-  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

-

-    \param [in]      PriorityGroup  Priority grouping field.

- */

-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)

-{

-  uint32_t reg_value;

-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */

-

-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */

-  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */

-  reg_value  =  (reg_value                                 |

-                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |

-                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */

-  SCB->AIRCR =  reg_value;

-}

-

-

-/** \brief  Get Priority Grouping

-

-  The function reads the priority grouping field from the NVIC Interrupt Controller.

-

-    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).

- */

-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)

-{

-  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */

-}

-

-

-/** \brief  Enable External Interrupt

-

-    The function enables a device-specific interrupt in the NVIC interrupt controller.

-

-    \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)

-{

-/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */

-  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */

-}

-

-

-/** \brief  Disable External Interrupt

-

-    The function disables a device-specific interrupt in the NVIC interrupt controller.

-

-    \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */

-}

-

-

-/** \brief  Get Pending Interrupt

-

-    The function reads the pending register in the NVIC and returns the pending bit

-    for the specified interrupt.

-

-    \param [in]      IRQn  Interrupt number.

-

-    \return             0  Interrupt status is not pending.

-    \return             1  Interrupt status is pending.

- */

-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)

-{

-  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */

-}

-

-

-/** \brief  Set Pending Interrupt

-

-    The function sets the pending bit of an external interrupt.

-

-    \param [in]      IRQn  Interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */

-}

-

-

-/** \brief  Clear Pending Interrupt

-

-    The function clears the pending bit of an external interrupt.

-

-    \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */

-}

-

-

-/** \brief  Get Active Interrupt

-

-    The function reads the active register in NVIC and returns the active bit.

-

-    \param [in]      IRQn  Interrupt number.

-

-    \return             0  Interrupt status is not active.

-    \return             1  Interrupt status is active.

- */

-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)

-{

-  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */

-}

-

-

-/** \brief  Set Interrupt Priority

-

-    The function sets the priority of an interrupt.

-

-    \note The priority cannot be set for every core interrupt.

-

-    \param [in]      IRQn  Interrupt number.

-    \param [in]  priority  Priority to set.

- */

-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

-{

-  if(IRQn < 0) {

-    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */

-  else {

-    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */

-}

-

-

-/** \brief  Get Interrupt Priority

-

-    The function reads the priority of an interrupt. The interrupt

-    number can be positive to specify an external (device specific)

-    interrupt, or negative to specify an internal (core) interrupt.

-

-

-    \param [in]   IRQn  Interrupt number.

-    \return             Interrupt Priority. Value is aligned automatically to the implemented

-                        priority bits of the microcontroller.

- */

-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)

-{

-

-  if(IRQn < 0) {

-    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */

-  else {

-    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */

-}

-

-

-/** \brief  Encode Priority

-

-    The function encodes the priority for an interrupt with the given priority group,

-    preemptive priority value, and subpriority value.

-    In case of a conflict between priority grouping and available

-    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

-

-    \param [in]     PriorityGroup  Used priority group.

-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).

-    \param [in]       SubPriority  Subpriority value (starting from 0).

-    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().

- */

-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)

-{

-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */

-  uint32_t PreemptPriorityBits;

-  uint32_t SubPriorityBits;

-

-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;

-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;

-

-  return (

-           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |

-           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))

-         );

-}

-

-

-/** \brief  Decode Priority

-

-    The function decodes an interrupt priority value with a given priority group to

-    preemptive priority value and subpriority value.

-    In case of a conflict between priority grouping and available

-    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.

-

-    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().

-    \param [in]     PriorityGroup  Used priority group.

-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).

-    \param [out]     pSubPriority  Subpriority value (starting from 0).

- */

-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)

-{

-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */

-  uint32_t PreemptPriorityBits;

-  uint32_t SubPriorityBits;

-

-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;

-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;

-

-  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);

-  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);

-}

-

-

-/** \brief  System Reset

-

-    The function initiates a system reset request to reset the MCU.

- */

-__STATIC_INLINE void NVIC_SystemReset(void)

-{

-  __DSB();                                                     /* Ensure all outstanding memory accesses included

-                                                                  buffered write are completed before reset */

-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |

-                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |

-                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */

-  __DSB();                                                     /* Ensure completion of memory access */

-  while(1);                                                    /* wait until reset */

-}

-

-/*@} end of CMSIS_Core_NVICFunctions */

-

-

-

-/* ##################################    SysTick function  ############################################ */

-/** \ingroup  CMSIS_Core_FunctionInterface

-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions

-    \brief      Functions that configure the System.

-  @{

- */

-

-#if (__Vendor_SysTickConfig == 0)

-

-/** \brief  System Tick Configuration

-

-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.

-    Counter is in free running mode to generate periodic interrupts.

-

-    \param [in]  ticks  Number of ticks between two interrupts.

-

-    \return          0  Function succeeded.

-    \return          1  Function failed.

-

-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the

-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>

-    must contain a vendor-specific implementation of this function.

-

- */

-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

-{

-  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */

-

-  SysTick->LOAD  = ticks - 1;                                  /* set reload register */

-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */

-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */

-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |

-                   SysTick_CTRL_TICKINT_Msk   |

-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */

-  return (0);                                                  /* Function successful */

-}

-

-#endif

-

-/*@} end of CMSIS_Core_SysTickFunctions */

-

-

-

-/* ##################################### Debug In/Output function ########################################### */

-/** \ingroup  CMSIS_Core_FunctionInterface

-    \defgroup CMSIS_core_DebugFunctions ITM Functions

-    \brief   Functions that access the ITM debug interface.

-  @{

- */

-

-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */

-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */

-

-

-/** \brief  ITM Send Character

-

-    The function transmits a character via the ITM channel 0, and

-    \li Just returns when no debugger is connected that has booked the output.

-    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.

-

-    \param [in]     ch  Character to transmit.

-

-    \returns            Character to transmit.

- */

-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)

-{

-  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */

-      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */

-  {

-    while (ITM->PORT[0].u32 == 0);

-    ITM->PORT[0].u8 = (uint8_t) ch;

-  }

-  return (ch);

-}

-

-

-/** \brief  ITM Receive Character

-

-    The function inputs a character via the external variable \ref ITM_RxBuffer.

-

-    \return             Received character.

-    \return         -1  No character pending.

- */

-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {

-  int32_t ch = -1;                           /* no character available */

-

-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {

-    ch = ITM_RxBuffer;

-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */

-  }

-

-  return (ch);

-}

-

-

-/** \brief  ITM Check Character

-

-    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.

-

-    \return          0  No character available.

-    \return          1  Character available.

- */

-__STATIC_INLINE int32_t ITM_CheckChar (void) {

-

-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {

-    return (0);                                 /* no character available */

-  } else {

-    return (1);                                 /*    character available */

-  }

-}

-

-/*@} end of CMSIS_core_DebugFunctions */

-

-

-

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_CM4_H_DEPENDANT */

-

-#endif /* __CMSIS_GENERIC */

+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include "core_cmInstr.h"                /* Core Instruction Access                         */
+#include "core_cmFunc.h"                 /* Core Function Access                            */
+#include "core_cmSimd.h"                 /* Compiler specific SIMD Intrinsics               */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/firmware/inc/platform/stm32f4xx/cmsis/core_cm7.h b/firmware/os/cpu/cortexm4/inc/cpu/cmsis/core_cm7.h
index 64436103..242540f8 100644
--- a/firmware/inc/platform/stm32f4xx/cmsis/core_cm7.h
+++ b/firmware/os/cpu/cortexm4/inc/cpu/cmsis/core_cm7.h
@@ -1,2221 +1,2221 @@
-/**************************************************************************//**

- * @file     core_cm7.h

- * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File

- * @version  V4.00

- * @date     01. September 2014

- *

- * @note

- *

- ******************************************************************************/

-/* Copyright (c) 2009 - 2014 ARM LIMITED

-

-   All rights reserved.

-   Redistribution and use in source and binary forms, with or without

-   modification, are permitted provided that the following conditions are met:

-   - Redistributions of source code must retain the above copyright

-     notice, this list of conditions and the following disclaimer.

-   - Redistributions in binary form must reproduce the above copyright

-     notice, this list of conditions and the following disclaimer in the

-     documentation and/or other materials provided with the distribution.

-   - Neither the name of ARM nor the names of its contributors may be used

-     to endorse or promote products derived from this software without

-     specific prior written permission.

-   *

-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-   POSSIBILITY OF SUCH DAMAGE.

-   ---------------------------------------------------------------------------*/

-

-

-#if defined ( __ICCARM__ )

- #pragma system_include  /* treat file as system include file for MISRA check */

-#endif

-

-#ifndef __CORE_CM7_H_GENERIC

-#define __CORE_CM7_H_GENERIC

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions

-  CMSIS violates the following MISRA-C:2004 rules:

-

-   \li Required Rule 8.5, object/function definition in header file.<br>

-     Function definitions in header files are used to allow 'inlining'.

-

-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>

-     Unions are used for effective representation of core registers.

-

-   \li Advisory Rule 19.7, Function-like macro defined.<br>

-     Function-like macros are used to allow more efficient code.

- */

-

-

-/*******************************************************************************

- *                 CMSIS definitions

- ******************************************************************************/

-/** \ingroup Cortex_M7

-  @{

- */

-

-/*  CMSIS CM7 definitions */

-#define __CM7_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */

-#define __CM7_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */

-#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16) | \

-                                    __CM7_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */

-

-#define __CORTEX_M                (0x07)                                   /*!< Cortex-M Core                    */

-

-

-#if   defined ( __CC_ARM )

-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */

-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */

-  #define __STATIC_INLINE  static __inline

-

-#elif defined ( __GNUC__ )

-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */

-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __ICCARM__ )

-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */

-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TMS470__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TASKING__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */

-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __CSMC__ )

-  #define __packed

-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */

-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */

-  #define __STATIC_INLINE  static inline

-

-#endif

-

-/** __FPU_USED indicates whether an FPU is used or not.

-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.

-*/

-#if defined ( __CC_ARM )

-  #if defined __TARGET_FPU_VFP

-    #if (__FPU_PRESENT == 1)

-      #define __FPU_USED       1

-    #else

-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-      #define __FPU_USED       0

-    #endif

-  #else

-    #define __FPU_USED         0

-  #endif

-

-#elif defined ( __GNUC__ )

-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

-    #if (__FPU_PRESENT == 1)

-      #define __FPU_USED       1

-    #else

-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-      #define __FPU_USED       0

-    #endif

-  #else

-    #define __FPU_USED         0

-  #endif

-

-#elif defined ( __ICCARM__ )

-  #if defined __ARMVFP__

-    #if (__FPU_PRESENT == 1)

-      #define __FPU_USED       1

-    #else

-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-      #define __FPU_USED       0

-    #endif

-  #else

-    #define __FPU_USED         0

-  #endif

-

-#elif defined ( __TMS470__ )

-  #if defined __TI_VFP_SUPPORT__

-    #if (__FPU_PRESENT == 1)

-      #define __FPU_USED       1

-    #else

-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-      #define __FPU_USED       0

-    #endif

-  #else

-    #define __FPU_USED         0

-  #endif

-

-#elif defined ( __TASKING__ )

-  #if defined __FPU_VFP__

-    #if (__FPU_PRESENT == 1)

-      #define __FPU_USED       1

-    #else

-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-      #define __FPU_USED       0

-    #endif

-  #else

-    #define __FPU_USED         0

-  #endif

-

-#elif defined ( __CSMC__ )		/* Cosmic */

-  #if ( __CSMC__ & 0x400)		// FPU present for parser

-    #if (__FPU_PRESENT == 1)

-      #define __FPU_USED       1

-    #else

-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-      #define __FPU_USED       0

-    #endif

-  #else

-    #define __FPU_USED         0

-  #endif

-#endif

-

-#include <stdint.h>                      /* standard types definitions                      */

-#include <core_cmInstr.h>                /* Core Instruction Access                         */

-#include <core_cmFunc.h>                 /* Core Function Access                            */

-#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_CM7_H_GENERIC */

-

-#ifndef __CMSIS_GENERIC

-

-#ifndef __CORE_CM7_H_DEPENDANT

-#define __CORE_CM7_H_DEPENDANT

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/* check device defines and use defaults */

-#if defined __CHECK_DEVICE_DEFINES

-  #ifndef __CM7_REV

-    #define __CM7_REV               0x0000

-    #warning "__CM7_REV not defined in device header file; using default!"

-  #endif

-

-  #ifndef __FPU_PRESENT

-    #define __FPU_PRESENT             0

-    #warning "__FPU_PRESENT not defined in device header file; using default!"

-  #endif

-

-  #ifndef __MPU_PRESENT

-    #define __MPU_PRESENT             0

-    #warning "__MPU_PRESENT not defined in device header file; using default!"

-  #endif

-

-  #ifndef __ICACHE_PRESENT

-    #define __ICACHE_PRESENT          0

-    #warning "__ICACHE_PRESENT not defined in device header file; using default!"

-  #endif

-

-  #ifndef __DCACHE_PRESENT

-    #define __DCACHE_PRESENT          0

-    #warning "__DCACHE_PRESENT not defined in device header file; using default!"

-  #endif

-

-  #ifndef __DTCM_PRESENT

-    #define __DTCM_PRESENT            0

-    #warning "__DTCM_PRESENT        not defined in device header file; using default!"

-  #endif

-

-  #ifndef __NVIC_PRIO_BITS

-    #define __NVIC_PRIO_BITS          3

-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"

-  #endif

-

-  #ifndef __Vendor_SysTickConfig

-    #define __Vendor_SysTickConfig    0

-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"

-  #endif

-#endif

-

-/* IO definitions (access restrictions to peripheral registers) */

-/**

-    \defgroup CMSIS_glob_defs CMSIS Global Defines

-

-    <strong>IO Type Qualifiers</strong> are used

-    \li to specify the access to peripheral variables.

-    \li for automatic generation of peripheral register debug information.

-*/

-#ifdef __cplusplus

-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */

-#else

-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */

-#endif

-#define     __O     volatile             /*!< Defines 'write only' permissions                */

-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */

-

-/*@} end of group Cortex_M7 */

-

-

-

-/*******************************************************************************

- *                 Register Abstraction

-  Core Register contain:

-  - Core Register

-  - Core NVIC Register

-  - Core SCB Register

-  - Core SysTick Register

-  - Core Debug Register

-  - Core MPU Register

-  - Core FPU Register

- ******************************************************************************/

-/** \defgroup CMSIS_core_register Defines and Type Definitions

-    \brief Type definitions and defines for Cortex-M processor based devices.

-*/

-

-/** \ingroup    CMSIS_core_register

-    \defgroup   CMSIS_CORE  Status and Control Registers

-    \brief  Core Register type definitions.

-  @{

- */

-

-/** \brief  Union type to access the Application Program Status Register (APSR).

- */

-typedef union

-{

-  struct

-  {

-#if (__CORTEX_M != 0x07)

-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */

-#else

-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */

-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */

-#endif

-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} APSR_Type;

-

-

-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} IPSR_Type;

-

-

-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

-#if (__CORTEX_M != 0x07)

-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */

-#else

-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */

-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */

-#endif

-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */

-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */

-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} xPSR_Type;

-

-

-/** \brief  Union type to access the Control Registers (CONTROL).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */

-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */

-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */

-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} CONTROL_Type;

-

-/*@} end of group CMSIS_CORE */

-

-

-/** \ingroup    CMSIS_core_register

-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)

-    \brief      Type definitions for the NVIC Registers

-  @{

- */

-

-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).

- */

-typedef struct

-{

-  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */

-       uint32_t RESERVED0[24];

-  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */

-       uint32_t RSERVED1[24];

-  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */

-       uint32_t RESERVED2[24];

-  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */

-       uint32_t RESERVED3[24];

-  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */

-       uint32_t RESERVED4[56];

-  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */

-       uint32_t RESERVED5[644];

-  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */

-}  NVIC_Type;

-

-/* Software Triggered Interrupt Register Definitions */

-#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */

-#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */

-

-/*@} end of group CMSIS_NVIC */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_SCB     System Control Block (SCB)

-    \brief      Type definitions for the System Control Block Registers

-  @{

- */

-

-/** \brief  Structure type to access the System Control Block (SCB).

- */

-typedef struct

-{

-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */

-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */

-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */

-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */

-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */

-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */

-  __IO uint8_t  SHPR[12];                /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */

-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */

-  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */

-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */

-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */

-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */

-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */

-  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */

-  __I  uint32_t ID_PFR[2];               /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */

-  __I  uint32_t ID_DFR;                  /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */

-  __I  uint32_t ID_AFR;                  /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */

-  __I  uint32_t ID_MFR[4];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */

-  __I  uint32_t ID_ISAR[5];              /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */

-       uint32_t RESERVED0[1];

-  __I  uint32_t CLIDR;                   /*!< Offset: 0x078 (R/ )  Cache Level ID register                               */

-  __I  uint32_t CTR;                     /*!< Offset: 0x07C (R/ )  Cache Type register                                   */

-  __I  uint32_t CCSIDR;                  /*!< Offset: 0x080 (R/ )  Cache Size ID Register                                */

-  __IO uint32_t CSSELR;                  /*!< Offset: 0x084 (R/W)  Cache Size Selection Register                         */

-  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */

-       uint32_t RESERVED3[93];

-  __O  uint32_t STIR;                    /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register                 */

-       uint32_t RESERVED4[15];

-  __I  uint32_t MVFR0;                   /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0                      */

-  __I  uint32_t MVFR1;                   /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1                      */

-  __I  uint32_t MVFR2;                   /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1                      */

-       uint32_t RESERVED5[1];

-  __O  uint32_t ICIALLU;                 /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU                         */

-       uint32_t RESERVED6[1];

-  __O  uint32_t ICIMVAU;                 /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU                      */

-  __O  uint32_t DCIMVAU;                 /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC                      */

-  __O  uint32_t DCISW;                   /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way                         */

-  __O  uint32_t DCCMVAU;                 /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU                           */

-  __O  uint32_t DCCMVAC;                 /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC                           */

-  __O  uint32_t DCCSW;                   /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way                              */

-  __O  uint32_t DCCIMVAC;                /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC            */

-  __O  uint32_t DCCISW;                  /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way               */

-       uint32_t RESERVED7[6];

-  __IO uint32_t ITCMCR;                  /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register   */

-  __IO uint32_t DTCMCR;                  /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers         */

-  __IO uint32_t AHBPCR;                  /*!< Offset: 0x298 (R/W)  AHBP Control Register                                 */

-  __IO uint32_t CACR;                    /*!< Offset: 0x29C (R/W)  L1 Cache Control Register                             */

-  __IO uint32_t AHBSCR;                  /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register                            */

-       uint32_t RESERVED8[1];

-  __IO uint32_t ABFSR;                   /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register                   */

-} SCB_Type;

-

-/* SCB CPUID Register Definitions */

-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */

-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */

-

-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */

-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */

-

-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */

-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */

-

-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */

-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */

-

-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */

-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */

-

-/* SCB Interrupt Control State Register Definitions */

-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */

-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */

-

-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */

-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */

-

-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */

-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */

-

-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */

-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */

-

-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */

-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */

-

-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */

-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */

-

-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */

-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */

-

-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */

-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */

-

-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */

-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */

-

-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */

-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */

-

-/* SCB Vector Table Offset Register Definitions */

-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */

-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */

-

-/* SCB Application Interrupt and Reset Control Register Definitions */

-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */

-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */

-

-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */

-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */

-

-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */

-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */

-

-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */

-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */

-

-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */

-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */

-

-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */

-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */

-

-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */

-#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */

-

-/* SCB System Control Register Definitions */

-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */

-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */

-

-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */

-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */

-

-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */

-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */

-

-/* SCB Configuration Control Register Definitions */

-#define SCB_CCR_BP_Pos                      18                                            /*!< SCB CCR: Branch prediction enable bit Position */

-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */

-

-#define SCB_CCR_IC_Pos                      17                                            /*!< SCB CCR: Instruction cache enable bit Position */

-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */

-

-#define SCB_CCR_DC_Pos                      16                                            /*!< SCB CCR: Cache enable bit Position */

-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */

-

-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */

-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */

-

-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */

-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */

-

-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */

-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */

-

-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */

-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */

-

-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */

-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */

-

-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */

-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */

-

-/* SCB System Handler Control and State Register Definitions */

-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */

-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */

-

-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */

-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */

-

-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */

-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */

-

-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */

-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */

-

-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */

-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */

-

-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */

-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */

-

-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */

-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */

-

-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */

-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */

-

-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */

-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */

-

-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */

-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */

-

-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */

-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */

-

-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */

-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */

-

-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */

-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */

-

-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */

-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */

-

-/* SCB Configurable Fault Status Registers Definitions */

-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */

-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */

-

-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */

-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */

-

-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */

-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */

-

-/* SCB Hard Fault Status Registers Definitions */

-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */

-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */

-

-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */

-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */

-

-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */

-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */

-

-/* SCB Debug Fault Status Register Definitions */

-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */

-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */

-

-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */

-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */

-

-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */

-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */

-

-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */

-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */

-

-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */

-#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */

-

-/* Cache Level ID register */

-#define SCB_CLIDR_LOUU_Pos                 27                                             /*!< SCB CLIDR: LoUU Position */

-#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */

-

-#define SCB_CLIDR_LOC_Pos                  24                                             /*!< SCB CLIDR: LoC Position */

-#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_FORMAT_Pos)                  /*!< SCB CLIDR: LoC Mask */

-

-/* Cache Type register */

-#define SCB_CTR_FORMAT_Pos                 29                                             /*!< SCB CTR: Format Position */

-#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */

-

-#define SCB_CTR_CWG_Pos                    24                                             /*!< SCB CTR: CWG Position */

-#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */

-

-#define SCB_CTR_ERG_Pos                    20                                             /*!< SCB CTR: ERG Position */

-#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */

-

-#define SCB_CTR_DMINLINE_Pos               16                                             /*!< SCB CTR: DminLine Position */

-#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */

-

-#define SCB_CTR_IMINLINE_Pos                0                                             /*!< SCB CTR: ImInLine Position */

-#define SCB_CTR_IMINLINE_Msk               (0xFUL << SCB_CTR_IMINLINE_Pos)                /*!< SCB CTR: ImInLine Mask */

-

-/* Cache Size ID Register */

-#define SCB_CCSIDR_WT_Pos                  31                                             /*!< SCB CCSIDR: WT Position */

-#define SCB_CCSIDR_WT_Msk                  (7UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */

-

-#define SCB_CCSIDR_WB_Pos                  30                                             /*!< SCB CCSIDR: WB Position */

-#define SCB_CCSIDR_WB_Msk                  (7UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */

-

-#define SCB_CCSIDR_RA_Pos                  29                                             /*!< SCB CCSIDR: RA Position */

-#define SCB_CCSIDR_RA_Msk                  (7UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */

-

-#define SCB_CCSIDR_WA_Pos                  28                                             /*!< SCB CCSIDR: WA Position */

-#define SCB_CCSIDR_WA_Msk                  (7UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */

-

-#define SCB_CCSIDR_NUMSETS_Pos             13                                             /*!< SCB CCSIDR: NumSets Position */

-#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */

-

-#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3                                             /*!< SCB CCSIDR: Associativity Position */

-#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */

-

-#define SCB_CCSIDR_LINESIZE_Pos             0                                             /*!< SCB CCSIDR: LineSize Position */

-#define SCB_CCSIDR_LINESIZE_Msk            (7UL << SCB_CCSIDR_LINESIZE_Pos)               /*!< SCB CCSIDR: LineSize Mask */

-

-/* Cache Size Selection Register */

-#define SCB_CSSELR_LEVEL_Pos                0                                             /*!< SCB CSSELR: Level Position */

-#define SCB_CSSELR_LEVEL_Msk               (1UL << SCB_CSSELR_LEVEL_Pos)                    /*!< SCB CSSELR: Level Mask */

-

-#define SCB_CSSELR_IND_Pos                  0                                             /*!< SCB CSSELR: InD Position */

-#define SCB_CSSELR_IND_Msk                 (1UL << SCB_CSSELR_IND_Pos)                    /*!< SCB CSSELR: InD Mask */

-

-/* SCB Software Triggered Interrupt Register */

-#define SCB_STIR_INTID_Pos                  0                                             /*!< SCB STIR: INTID Position */

-#define SCB_STIR_INTID_Msk                 (0x1FFUL << SCB_STIR_INTID_Pos)                /*!< SCB STIR: INTID Mask */

-

-/* Instruction Tightly-Coupled Memory Control Register*/

-#define SCB_ITCMCR_SZ_Pos                   3                                             /*!< SCB ITCMCR: SZ Position */

-#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */

-

-#define SCB_ITCMCR_RETEN_Pos                2                                             /*!< SCB ITCMCR: RETEN Position */

-#define SCB_ITCMCR_RETEN_Msk               (1FFUL << SCB_ITCMCR_RETEN_Pos)                /*!< SCB ITCMCR: RETEN Mask */

-

-#define SCB_ITCMCR_RMW_Pos                  1                                             /*!< SCB ITCMCR: RMW Position */

-#define SCB_ITCMCR_RMW_Msk                 (1FFUL << SCB_ITCMCR_RMW_Pos)                  /*!< SCB ITCMCR: RMW Mask */

-

-#define SCB_ITCMCR_EN_Pos                   0                                             /*!< SCB ITCMCR: EN Position */

-#define SCB_ITCMCR_EN_Msk                  (1FFUL << SCB_ITCMCR_EN_Pos)                   /*!< SCB ITCMCR: EN Mask */

-

-/* Data Tightly-Coupled Memory Control Registers */

-#define SCB_DTCMCR_SZ_Pos                   3                                             /*!< SCB DTCMCR: SZ Position */

-#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */

-

-#define SCB_DTCMCR_RETEN_Pos                2                                             /*!< SCB DTCMCR: RETEN Position */

-#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */

-

-#define SCB_DTCMCR_RMW_Pos                  1                                             /*!< SCB DTCMCR: RMW Position */

-#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */

-

-#define SCB_DTCMCR_EN_Pos                   0                                             /*!< SCB DTCMCR: EN Position */

-#define SCB_DTCMCR_EN_Msk                  (1UL << SCB_DTCMCR_EN_Pos)                     /*!< SCB DTCMCR: EN Mask */

-

-/* AHBP Control Register */

-#define SCB_AHBPCR_SZ_Pos                   1                                             /*!< SCB AHBPCR: SZ Position */

-#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */

-

-#define SCB_AHBPCR_EN_Pos                   0                                             /*!< SCB AHBPCR: EN Position */

-#define SCB_AHBPCR_EN_Msk                  (1UL << SCB_AHBPCR_EN_Pos)                     /*!< SCB AHBPCR: EN Mask */

-

-/* L1 Cache Control Register */

-#define SCB_CACR_FORCEWT_Pos                2                                             /*!< SCB CACR: FORCEWT Position */

-#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */

-

-#define SCB_CACR_ECCEN_Pos                  1                                             /*!< SCB CACR: ECCEN Position */

-#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */

-

-#define SCB_CACR_SIWT_Pos                   0                                             /*!< SCB CACR: SIWT Position */

-#define SCB_CACR_SIWT_Msk                  (1UL << SCB_CACR_SIWT_Pos)                     /*!< SCB CACR: SIWT Mask */

-

-/* AHBS control register */

-#define SCB_AHBSCR_INITCOUNT_Pos           11                                             /*!< SCB AHBSCR: INITCOUNT Position */

-#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */

-

-#define SCB_AHBSCR_TPRI_Pos                 2                                             /*!< SCB AHBSCR: TPRI Position */

-#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */

-

-#define SCB_AHBSCR_CTL_Pos                  0                                             /*!< SCB AHBSCR: CTL Position*/

-#define SCB_AHBSCR_CTL_Msk                 (3UL << SCB_AHBPCR_CTL_Pos)                    /*!< SCB AHBSCR: CTL Mask */

-

-/* Auxiliary Bus Fault Status Register */

-#define SCB_ABFSR_AXIMTYPE_Pos              8                                             /*!< SCB ABFSR: AXIMTYPE Position*/

-#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */

-

-#define SCB_ABFSR_EPPB_Pos                  4                                             /*!< SCB ABFSR: EPPB Position*/

-#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */

-

-#define SCB_ABFSR_AXIM_Pos                  3                                             /*!< SCB ABFSR: AXIM Position*/

-#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */

-

-#define SCB_ABFSR_AHBP_Pos                  2                                             /*!< SCB ABFSR: AHBP Position*/

-#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */

-

-#define SCB_ABFSR_DTCM_Pos                  1                                             /*!< SCB ABFSR: DTCM Position*/

-#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */

-

-#define SCB_ABFSR_ITCM_Pos                  0                                             /*!< SCB ABFSR: ITCM Position*/

-#define SCB_ABFSR_ITCM_Msk                 (1UL << SCB_ABFSR_ITCM_Pos)                    /*!< SCB ABFSR: ITCM Mask */

-

-/*@} end of group CMSIS_SCB */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)

-    \brief      Type definitions for the System Control and ID Register not in the SCB

-  @{

- */

-

-/** \brief  Structure type to access the System Control and ID Register not in the SCB.

- */

-typedef struct

-{

-       uint32_t RESERVED0[1];

-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */

-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */

-} SCnSCB_Type;

-

-/* Interrupt Controller Type Register Definitions */

-#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */

-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */

-

-/* Auxiliary Control Register Definitions */

-#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12                                          /*!< ACTLR: DISITMATBFLUSH Position */

-#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */

-

-#define SCnSCB_ACTLR_DISRAMODE_Pos         11                                          /*!< ACTLR: DISRAMODE Position */

-#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */

-

-#define SCnSCB_ACTLR_FPEXCODIS_Pos         10                                          /*!< ACTLR: FPEXCODIS Position */

-#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */

-

-#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */

-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */

-

-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */

-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */

-

-/*@} end of group CMSIS_SCnotSCB */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)

-    \brief      Type definitions for the System Timer Registers.

-  @{

- */

-

-/** \brief  Structure type to access the System Timer (SysTick).

- */

-typedef struct

-{

-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */

-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */

-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */

-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */

-} SysTick_Type;

-

-/* SysTick Control / Status Register Definitions */

-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */

-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */

-

-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */

-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */

-

-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */

-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */

-

-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */

-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */

-

-/* SysTick Reload Register Definitions */

-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */

-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */

-

-/* SysTick Current Register Definitions */

-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */

-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */

-

-/* SysTick Calibration Register Definitions */

-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */

-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */

-

-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */

-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */

-

-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */

-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */

-

-/*@} end of group CMSIS_SysTick */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)

-    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)

-  @{

- */

-

-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).

- */

-typedef struct

-{

-  __O  union

-  {

-    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */

-    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */

-    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */

-  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */

-       uint32_t RESERVED0[864];

-  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */

-       uint32_t RESERVED1[15];

-  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */

-       uint32_t RESERVED2[15];

-  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */

-       uint32_t RESERVED3[29];

-  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */

-  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */

-  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */

-       uint32_t RESERVED4[43];

-  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */

-  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */

-       uint32_t RESERVED5[6];

-  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */

-  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */

-  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */

-  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */

-  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */

-  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */

-  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */

-  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */

-  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */

-  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */

-  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */

-  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */

-} ITM_Type;

-

-/* ITM Trace Privilege Register Definitions */

-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */

-#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */

-

-/* ITM Trace Control Register Definitions */

-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */

-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */

-

-#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */

-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */

-

-#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */

-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */

-

-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */

-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */

-

-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */

-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */

-

-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */

-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */

-

-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */

-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */

-

-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */

-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */

-

-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */

-#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */

-

-/* ITM Integration Write Register Definitions */

-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */

-#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */

-

-/* ITM Integration Read Register Definitions */

-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */

-#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */

-

-/* ITM Integration Mode Control Register Definitions */

-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */

-#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */

-

-/* ITM Lock Status Register Definitions */

-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */

-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */

-

-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */

-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */

-

-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */

-#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */

-

-/*@}*/ /* end of group CMSIS_ITM */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)

-    \brief      Type definitions for the Data Watchpoint and Trace (DWT)

-  @{

- */

-

-/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).

- */

-typedef struct

-{

-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */

-  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */

-  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */

-  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */

-  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */

-  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */

-  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */

-  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */

-  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */

-  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */

-  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */

-       uint32_t RESERVED0[1];

-  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */

-  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */

-  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */

-       uint32_t RESERVED1[1];

-  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */

-  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */

-  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */

-       uint32_t RESERVED2[1];

-  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */

-  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */

-  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */

-       uint32_t RESERVED3[981];

-  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 (  W)  Lock Access Register                      */

-  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R  )  Lock Status Register                      */

-} DWT_Type;

-

-/* DWT Control Register Definitions */

-#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */

-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */

-

-#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */

-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */

-

-#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */

-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */

-

-#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */

-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */

-

-#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */

-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */

-

-#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */

-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */

-

-#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */

-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */

-

-#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */

-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */

-

-#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */

-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */

-

-#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */

-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */

-

-#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */

-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */

-

-#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */

-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */

-

-#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */

-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */

-

-#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */

-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */

-

-#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */

-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */

-

-#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */

-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */

-

-#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */

-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */

-

-#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */

-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */

-

-/* DWT CPI Count Register Definitions */

-#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */

-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */

-

-/* DWT Exception Overhead Count Register Definitions */

-#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */

-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */

-

-/* DWT Sleep Count Register Definitions */

-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */

-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */

-

-/* DWT LSU Count Register Definitions */

-#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */

-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */

-

-/* DWT Folded-instruction Count Register Definitions */

-#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */

-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */

-

-/* DWT Comparator Mask Register Definitions */

-#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */

-#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */

-

-/* DWT Comparator Function Register Definitions */

-#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */

-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */

-

-#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */

-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */

-

-#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */

-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */

-

-#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */

-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */

-

-#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */

-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */

-

-#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */

-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */

-

-#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */

-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */

-

-#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */

-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */

-

-#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */

-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */

-

-/*@}*/ /* end of group CMSIS_DWT */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_TPI     Trace Port Interface (TPI)

-    \brief      Type definitions for the Trace Port Interface (TPI)

-  @{

- */

-

-/** \brief  Structure type to access the Trace Port Interface Register (TPI).

- */

-typedef struct

-{

-  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */

-  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */

-       uint32_t RESERVED0[2];

-  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */

-       uint32_t RESERVED1[55];

-  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */

-       uint32_t RESERVED2[131];

-  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */

-  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */

-  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */

-       uint32_t RESERVED3[759];

-  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */

-  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */

-  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */

-       uint32_t RESERVED4[1];

-  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */

-  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */

-  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */

-       uint32_t RESERVED5[39];

-  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */

-  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */

-       uint32_t RESERVED7[8];

-  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */

-  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */

-} TPI_Type;

-

-/* TPI Asynchronous Clock Prescaler Register Definitions */

-#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */

-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */

-

-/* TPI Selected Pin Protocol Register Definitions */

-#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */

-#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */

-

-/* TPI Formatter and Flush Status Register Definitions */

-#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */

-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */

-

-#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */

-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */

-

-#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */

-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */

-

-#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */

-#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */

-

-/* TPI Formatter and Flush Control Register Definitions */

-#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */

-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */

-

-#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */

-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */

-

-/* TPI TRIGGER Register Definitions */

-#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */

-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */

-

-/* TPI Integration ETM Data Register Definitions (FIFO0) */

-#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */

-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */

-

-#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */

-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */

-

-#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */

-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */

-

-#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */

-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */

-

-#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */

-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */

-

-#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */

-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */

-

-#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */

-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */

-

-/* TPI ITATBCTR2 Register Definitions */

-#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */

-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */

-

-/* TPI Integration ITM Data Register Definitions (FIFO1) */

-#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */

-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */

-

-#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */

-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */

-

-#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */

-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */

-

-#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */

-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */

-

-#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */

-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */

-

-#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */

-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */

-

-#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */

-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */

-

-/* TPI ITATBCTR0 Register Definitions */

-#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */

-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */

-

-/* TPI Integration Mode Control Register Definitions */

-#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */

-#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */

-

-/* TPI DEVID Register Definitions */

-#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */

-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */

-

-#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */

-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */

-

-#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */

-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */

-

-#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */

-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */

-

-#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */

-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */

-

-#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */

-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */

-

-/* TPI DEVTYPE Register Definitions */

-#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */

-#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */

-

-#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */

-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */

-

-/*@}*/ /* end of group CMSIS_TPI */

-

-

-#if (__MPU_PRESENT == 1)

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)

-    \brief      Type definitions for the Memory Protection Unit (MPU)

-  @{

- */

-

-/** \brief  Structure type to access the Memory Protection Unit (MPU).

- */

-typedef struct

-{

-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */

-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */

-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */

-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */

-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */

-  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */

-  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */

-  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */

-  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */

-  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */

-  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */

-} MPU_Type;

-

-/* MPU Type Register */

-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */

-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */

-

-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */

-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */

-

-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */

-#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */

-

-/* MPU Control Register */

-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */

-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */

-

-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */

-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */

-

-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */

-#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */

-

-/* MPU Region Number Register */

-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */

-#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */

-

-/* MPU Region Base Address Register */

-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */

-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */

-

-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */

-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */

-

-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */

-#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */

-

-/* MPU Region Attribute and Size Register */

-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */

-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */

-

-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */

-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */

-

-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */

-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */

-

-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */

-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */

-

-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */

-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */

-

-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */

-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */

-

-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */

-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */

-

-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */

-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */

-

-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */

-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */

-

-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */

-#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */

-

-/*@} end of group CMSIS_MPU */

-#endif

-

-

-#if (__FPU_PRESENT == 1)

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_FPU     Floating Point Unit (FPU)

-    \brief      Type definitions for the Floating Point Unit (FPU)

-  @{

- */

-

-/** \brief  Structure type to access the Floating Point Unit (FPU).

- */

-typedef struct

-{

-       uint32_t RESERVED0[1];

-  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */

-  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */

-  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */

-  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */

-  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */

-  __I  uint32_t MVFR2;                   /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2                       */

-} FPU_Type;

-

-/* Floating-Point Context Control Register */

-#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */

-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */

-

-#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */

-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */

-

-#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */

-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */

-

-#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */

-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */

-

-#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */

-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */

-

-#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */

-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */

-

-#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */

-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */

-

-#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */

-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */

-

-#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */

-#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */

-

-/* Floating-Point Context Address Register */

-#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */

-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */

-

-/* Floating-Point Default Status Control Register */

-#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */

-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */

-

-#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */

-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */

-

-#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */

-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */

-

-#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */

-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */

-

-/* Media and FP Feature Register 0 */

-#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */

-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */

-

-#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */

-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */

-

-#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */

-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */

-

-#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */

-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */

-

-#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */

-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */

-

-#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */

-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */

-

-#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */

-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */

-

-#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */

-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */

-

-/* Media and FP Feature Register 1 */

-#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */

-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */

-

-#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */

-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */

-

-#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */

-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */

-

-#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */

-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */

-

-/* Media and FP Feature Register 2 */

-

-/*@} end of group CMSIS_FPU */

-#endif

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)

-    \brief      Type definitions for the Core Debug Registers

-  @{

- */

-

-/** \brief  Structure type to access the Core Debug Register (CoreDebug).

- */

-typedef struct

-{

-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */

-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */

-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */

-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */

-} CoreDebug_Type;

-

-/* Debug Halting Control and Status Register */

-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */

-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */

-

-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */

-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */

-

-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */

-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */

-

-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */

-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */

-

-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */

-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */

-

-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */

-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */

-

-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */

-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */

-

-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */

-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */

-

-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */

-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */

-

-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */

-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */

-

-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */

-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */

-

-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */

-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */

-

-/* Debug Core Register Selector Register */

-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */

-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */

-

-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */

-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */

-

-/* Debug Exception and Monitor Control Register */

-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */

-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */

-

-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */

-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */

-

-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */

-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */

-

-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */

-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */

-

-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */

-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */

-

-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */

-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */

-

-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */

-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */

-

-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */

-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */

-

-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */

-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */

-

-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */

-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */

-

-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */

-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */

-

-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */

-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */

-

-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */

-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */

-

-/*@} end of group CMSIS_CoreDebug */

-

-

-/** \ingroup    CMSIS_core_register

-    \defgroup   CMSIS_core_base     Core Definitions

-    \brief      Definitions for base addresses, unions, and structures.

-  @{

- */

-

-/* Memory mapping of Cortex-M4 Hardware */

-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */

-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */

-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */

-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */

-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */

-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */

-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */

-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */

-

-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */

-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */

-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */

-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */

-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */

-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */

-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */

-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */

-

-#if (__MPU_PRESENT == 1)

-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */

-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */

-#endif

-

-#if (__FPU_PRESENT == 1)

-  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */

-  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */

-#endif

-

-/*@} */

-

-

-

-/*******************************************************************************

- *                Hardware Abstraction Layer

-  Core Function Interface contains:

-  - Core NVIC Functions

-  - Core SysTick Functions

-  - Core Debug Functions

-  - Core Register Access Functions

- ******************************************************************************/

-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference

-*/

-

-

-

-/* ##########################   NVIC functions  #################################### */

-/** \ingroup  CMSIS_Core_FunctionInterface

-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions

-    \brief      Functions that manage interrupts and exceptions via the NVIC.

-    @{

- */

-

-/** \brief  Set Priority Grouping

-

-  The function sets the priority grouping field using the required unlock sequence.

-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.

-  Only values from 0..7 are used.

-  In case of a conflict between priority grouping and available

-  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

-

-    \param [in]      PriorityGroup  Priority grouping field.

- */

-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)

-{

-  uint32_t reg_value;

-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */

-

-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */

-  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */

-  reg_value  =  (reg_value                                 |

-                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |

-                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */

-  SCB->AIRCR =  reg_value;

-}

-

-

-/** \brief  Get Priority Grouping

-

-  The function reads the priority grouping field from the NVIC Interrupt Controller.

-

-    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).

- */

-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)

-{

-  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */

-}

-

-

-/** \brief  Enable External Interrupt

-

-    The function enables a device-specific interrupt in the NVIC interrupt controller.

-

-    \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)

-{

-/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */

-  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */

-}

-

-

-/** \brief  Disable External Interrupt

-

-    The function disables a device-specific interrupt in the NVIC interrupt controller.

-

-    \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */

-}

-

-

-/** \brief  Get Pending Interrupt

-

-    The function reads the pending register in the NVIC and returns the pending bit

-    for the specified interrupt.

-

-    \param [in]      IRQn  Interrupt number.

-

-    \return             0  Interrupt status is not pending.

-    \return             1  Interrupt status is pending.

- */

-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)

-{

-  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */

-}

-

-

-/** \brief  Set Pending Interrupt

-

-    The function sets the pending bit of an external interrupt.

-

-    \param [in]      IRQn  Interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */

-}

-

-

-/** \brief  Clear Pending Interrupt

-

-    The function clears the pending bit of an external interrupt.

-

-    \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */

-}

-

-

-/** \brief  Get Active Interrupt

-

-    The function reads the active register in NVIC and returns the active bit.

-

-    \param [in]      IRQn  Interrupt number.

-

-    \return             0  Interrupt status is not active.

-    \return             1  Interrupt status is active.

- */

-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)

-{

-  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */

-}

-

-

-/** \brief  Set Interrupt Priority

-

-    The function sets the priority of an interrupt.

-

-    \note The priority cannot be set for every core interrupt.

-

-    \param [in]      IRQn  Interrupt number.

-    \param [in]  priority  Priority to set.

- */

-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

-{

-  if(IRQn < 0) {

-    SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */

-  else {

-    NVIC->IP[(uint32_t)(IRQn)]            = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts  */

-}

-

-

-/** \brief  Get Interrupt Priority

-

-    The function reads the priority of an interrupt. The interrupt

-    number can be positive to specify an external (device specific)

-    interrupt, or negative to specify an internal (core) interrupt.

-

-

-    \param [in]   IRQn  Interrupt number.

-    \return             Interrupt Priority. Value is aligned automatically to the implemented

-                        priority bits of the microcontroller.

- */

-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)

-{

-

-  if(IRQn < 0) {

-    return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */

-  else {

-    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]            >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */

-}

-

-

-/** \brief  Encode Priority

-

-    The function encodes the priority for an interrupt with the given priority group,

-    preemptive priority value, and subpriority value.

-    In case of a conflict between priority grouping and available

-    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

-

-    \param [in]     PriorityGroup  Used priority group.

-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).

-    \param [in]       SubPriority  Subpriority value (starting from 0).

-    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().

- */

-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)

-{

-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */

-  uint32_t PreemptPriorityBits;

-  uint32_t SubPriorityBits;

-

-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;

-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;

-

-  return (

-           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |

-           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))

-         );

-}

-

-

-/** \brief  Decode Priority

-

-    The function decodes an interrupt priority value with a given priority group to

-    preemptive priority value and subpriority value.

-    In case of a conflict between priority grouping and available

-    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.

-

-    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().

-    \param [in]     PriorityGroup  Used priority group.

-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).

-    \param [out]     pSubPriority  Subpriority value (starting from 0).

- */

-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)

-{

-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */

-  uint32_t PreemptPriorityBits;

-  uint32_t SubPriorityBits;

-

-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;

-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;

-

-  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);

-  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);

-}

-

-

-/** \brief  System Reset

-

-    The function initiates a system reset request to reset the MCU.

- */

-__STATIC_INLINE void NVIC_SystemReset(void)

-{

-  __DSB();                                                     /* Ensure all outstanding memory accesses included

-                                                                  buffered write are completed before reset */

-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |

-                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |

-                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */

-  __DSB();                                                     /* Ensure completion of memory access */

-  while(1);                                                    /* wait until reset */

-}

-

-/*@} end of CMSIS_Core_NVICFunctions */

-

-

-/* ##########################  Cache functions  #################################### */

-/** \ingroup  CMSIS_Core_FunctionInterface

-    \defgroup CMSIS_Core_CacheFunctions Cache Functions

-    \brief      Functions that configure Instruction and Data cache.

-    @{

- */

-

-/* Cache Size ID Register Macros */

-#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)

-#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )

-#define CCSIDR_LSSHIFT(x)      (((x) & SCB_CCSIDR_LINESIZE_Msk     ) >> SCB_CCSIDR_LINESIZE_Pos     )

-

-

-/** \brief Enable I-Cache

-

-    The function turns on I-Cache

-  */

-__STATIC_INLINE void SCB_EnableICache(void)

-{

-  #if (__ICACHE_PRESENT == 1)

-    __DSB();

-    __ISB();

-    SCB->ICIALLU = 0;                       // invalidate I-Cache

-    SCB->CCR |=  SCB_CCR_IC_Msk;            // enable I-Cache

-    __DSB();

-    __ISB();

-  #endif

-}

-

-

-/** \brief Disable I-Cache

-

-    The function turns off I-Cache

-  */

-__STATIC_INLINE void SCB_DisableICache(void)

-{

-  #if (__ICACHE_PRESENT == 1)

-    __DSB();

-    __ISB();

-    SCB->CCR &= ~SCB_CCR_IC_Msk;            // disable I-Cache

-    SCB->ICIALLU = 0;                       // invalidate I-Cache

-    __DSB();

-    __ISB();

-  #endif

-}

-

-

-/** \brief Invalidate I-Cache

-

-    The function invalidates I-Cache

-  */

-__STATIC_INLINE void SCB_InvalidateICache(void)

-{

-  #if (__ICACHE_PRESENT == 1)

-    __DSB();

-    __ISB();

-    SCB->ICIALLU = 0;

-    __DSB();

-    __ISB();

-  #endif

-}

-

-

-/** \brief Enable D-Cache

-

-    The function turns on D-Cache

-  */

-__STATIC_INLINE void SCB_EnableDCache(void)

-{

-  #if (__DCACHE_PRESENT == 1)

-    uint32_t ccsidr, sshift, wshift, sw;

-    uint32_t sets, ways;

-

-    ccsidr  = SCB->CCSIDR;

-    sets    = CCSIDR_SETS(ccsidr);

-    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;

-    ways    = CCSIDR_WAYS(ccsidr);

-    wshift  = __CLZ(ways) & 0x1f;

-

-    __DSB();

-

-    do {                                    // invalidate D-Cache

-         int32_t tmpways = ways;

-         do {

-              sw = ((tmpways << wshift) | (sets << sshift));

-              SCB->DCISW = sw;

-            } while(tmpways--);

-        } while(sets--);

-    __DSB();

-

-    SCB->CCR |=  SCB_CCR_DC_Msk;            // enable D-Cache

-

-    __DSB();

-    __ISB();

-  #endif

-}

-

-

-/** \brief Disable D-Cache

-

-    The function turns off D-Cache

-  */

-__STATIC_INLINE void SCB_DisableDCache(void)

-{

-  #if (__DCACHE_PRESENT == 1)

-    uint32_t ccsidr, sshift, wshift, sw;

-    uint32_t sets, ways;

-

-    ccsidr  = SCB->CCSIDR;

-    sets    = CCSIDR_SETS(ccsidr);

-    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;

-    ways    = CCSIDR_WAYS(ccsidr);

-    wshift  = __CLZ(ways) & 0x1f;

-

-    __DSB();

-

-    SCB->CCR &= ~SCB_CCR_DC_Msk;            // disable D-Cache

-

-    do {                                    // clean & invalidate D-Cache

-         int32_t tmpways = ways;

-         do {

-              sw = ((tmpways << wshift) | (sets << sshift));

-              SCB->DCCISW = sw;

-            } while(tmpways--);

-        } while(sets--);

-

-

-    __DSB();

-    __ISB();

- #endif

-}

-

-

-/** \brief Invalidate D-Cache

-

-    The function invalidates D-Cache

-  */

-__STATIC_INLINE void SCB_InvalidateDCache(void)

-{

-  #if (__DCACHE_PRESENT == 1)

-    uint32_t ccsidr, sshift, wshift, sw;

-    uint32_t sets, ways;

-

-    ccsidr  = SCB->CCSIDR;

-    sets    = CCSIDR_SETS(ccsidr);

-    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;

-    ways    = CCSIDR_WAYS(ccsidr);

-    wshift  = __CLZ(ways) & 0x1f;

-

-    __DSB();

-

-    do {                                    // invalidate D-Cache

-         int32_t tmpways = ways;

-         do {

-              sw = ((tmpways << wshift) | (sets << sshift));

-              SCB->DCISW = sw;

-            } while(tmpways--);

-        } while(sets--);

-

-    __DSB();

-    __ISB();

- #endif

-}

-

-

-/** \brief Clean D-Cache

-

-    The function cleans D-Cache

-  */

-__STATIC_INLINE void SCB_CleanDCache(void)

-{

-  #if (__DCACHE_PRESENT == 1)

-    uint32_t ccsidr, sshift, wshift, sw;

-    uint32_t sets, ways;

-

-    ccsidr  = SCB->CCSIDR;

-    sets    = CCSIDR_SETS(ccsidr);

-    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;

-    ways    = CCSIDR_WAYS(ccsidr);

-    wshift  = __CLZ(ways) & 0x1f;

-

-    __DSB();

-

-    do {                                    // clean D-Cache

-         int32_t tmpways = ways;

-         do {

-              sw = ((tmpways << wshift) | (sets << sshift));

-              SCB->DCCSW = sw;

-            } while(tmpways--);

-        } while(sets--);

-

-    __DSB();

-    __ISB();

- #endif

-}

-

-

-/** \brief Clean & Invalidate D-Cache

-

-    The function cleans and Invalidates D-Cache

-  */

-__STATIC_INLINE void SCB_CleanInvalidateDCache(void)

-{

-  #if (__DCACHE_PRESENT == 1)

-    uint32_t ccsidr, sshift, wshift, sw;

-    uint32_t sets, ways;

-

-    ccsidr  = SCB->CCSIDR;

-    sets    = CCSIDR_SETS(ccsidr);

-    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;

-    ways    = CCSIDR_WAYS(ccsidr);

-    wshift  = __CLZ(ways) & 0x1f;

-

-    __DSB();

-

-    do {                                    // clean & invalidate D-Cache

-         int32_t tmpways = ways;

-         do {

-              sw = ((tmpways << wshift) | (sets << sshift));

-              SCB->DCCISW = sw;

-            } while(tmpways--);

-        } while(sets--);

-

-    __DSB();

-    __ISB();

- #endif

-}

-

-

-/*@} end of CMSIS_Core_CacheFunctions */

-

-

-

-/* ##################################    SysTick function  ############################################ */

-/** \ingroup  CMSIS_Core_FunctionInterface

-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions

-    \brief      Functions that configure the System.

-  @{

- */

-

-#if (__Vendor_SysTickConfig == 0)

-

-/** \brief  System Tick Configuration

-

-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.

-    Counter is in free running mode to generate periodic interrupts.

-

-    \param [in]  ticks  Number of ticks between two interrupts.

-

-    \return          0  Function succeeded.

-    \return          1  Function failed.

-

-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the

-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>

-    must contain a vendor-specific implementation of this function.

-

- */

-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

-{

-  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */

-

-  SysTick->LOAD  = ticks - 1;                                  /* set reload register */

-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */

-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */

-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |

-                   SysTick_CTRL_TICKINT_Msk   |

-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */

-  return (0);                                                  /* Function successful */

-}

-

-#endif

-

-/*@} end of CMSIS_Core_SysTickFunctions */

-

-

-

-/* ##################################### Debug In/Output function ########################################### */

-/** \ingroup  CMSIS_Core_FunctionInterface

-    \defgroup CMSIS_core_DebugFunctions ITM Functions

-    \brief   Functions that access the ITM debug interface.

-  @{

- */

-

-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */

-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */

-

-

-/** \brief  ITM Send Character

-

-    The function transmits a character via the ITM channel 0, and

-    \li Just returns when no debugger is connected that has booked the output.

-    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.

-

-    \param [in]     ch  Character to transmit.

-

-    \returns            Character to transmit.

- */

-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)

-{

-  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */

-      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */

-  {

-    while (ITM->PORT[0].u32 == 0);

-    ITM->PORT[0].u8 = (uint8_t) ch;

-  }

-  return (ch);

-}

-

-

-/** \brief  ITM Receive Character

-

-    The function inputs a character via the external variable \ref ITM_RxBuffer.

-

-    \return             Received character.

-    \return         -1  No character pending.

- */

-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {

-  int32_t ch = -1;                           /* no character available */

-

-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {

-    ch = ITM_RxBuffer;

-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */

-  }

-

-  return (ch);

-}

-

-

-/** \brief  ITM Check Character

-

-    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.

-

-    \return          0  No character available.

-    \return          1  Character available.

- */

-__STATIC_INLINE int32_t ITM_CheckChar (void) {

-

-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {

-    return (0);                                 /* no character available */

-  } else {

-    return (1);                                 /*    character available */

-  }

-}

-

-/*@} end of CMSIS_core_DebugFunctions */

-

-

-

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_CM7_H_DEPENDANT */

-

-#endif /* __CMSIS_GENERIC */

+/**************************************************************************//**
+ * @file     core_cm7.h
+ * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     01. September 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M7
+  @{
+ */
+
+/*  CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM7_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM7_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x07)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM7_REV
+    #define __CM7_REV               0x0000
+    #warning "__CM7_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ICACHE_PRESENT
+    #define __ICACHE_PRESENT          0
+    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DCACHE_PRESENT
+    #define __DCACHE_PRESENT          0
+    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DTCM_PRESENT
+    #define __DTCM_PRESENT            0
+    #warning "__DTCM_PRESENT        not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x07)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x07)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHPR[12];                /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t ID_PFR[2];               /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t ID_DFR;                  /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ID_AFR;                  /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t ID_MFR[4];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ID_ISAR[5];              /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[1];
+  __I  uint32_t CLIDR;                   /*!< Offset: 0x078 (R/ )  Cache Level ID register                               */
+  __I  uint32_t CTR;                     /*!< Offset: 0x07C (R/ )  Cache Type register                                   */
+  __I  uint32_t CCSIDR;                  /*!< Offset: 0x080 (R/ )  Cache Size ID Register                                */
+  __IO uint32_t CSSELR;                  /*!< Offset: 0x084 (R/W)  Cache Size Selection Register                         */
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+       uint32_t RESERVED3[93];
+  __O  uint32_t STIR;                    /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register                 */
+       uint32_t RESERVED4[15];
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0                      */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1                      */
+  __I  uint32_t MVFR2;                   /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1                      */
+       uint32_t RESERVED5[1];
+  __O  uint32_t ICIALLU;                 /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU                         */
+       uint32_t RESERVED6[1];
+  __O  uint32_t ICIMVAU;                 /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU                      */
+  __O  uint32_t DCIMVAU;                 /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC                      */
+  __O  uint32_t DCISW;                   /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way                         */
+  __O  uint32_t DCCMVAU;                 /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU                           */
+  __O  uint32_t DCCMVAC;                 /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC                           */
+  __O  uint32_t DCCSW;                   /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way                              */
+  __O  uint32_t DCCIMVAC;                /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC            */
+  __O  uint32_t DCCISW;                  /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way               */
+       uint32_t RESERVED7[6];
+  __IO uint32_t ITCMCR;                  /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register   */
+  __IO uint32_t DTCMCR;                  /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers         */
+  __IO uint32_t AHBPCR;                  /*!< Offset: 0x298 (R/W)  AHBP Control Register                                 */
+  __IO uint32_t CACR;                    /*!< Offset: 0x29C (R/W)  L1 Cache Control Register                             */
+  __IO uint32_t AHBSCR;                  /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register                            */
+       uint32_t RESERVED8[1];
+  __IO uint32_t ABFSR;                   /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                      18                                            /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos                      17                                            /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos                      16                                            /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/* Cache Level ID register */
+#define SCB_CLIDR_LOUU_Pos                 27                                             /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24                                             /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_FORMAT_Pos)                  /*!< SCB CLIDR: LoC Mask */
+
+/* Cache Type register */
+#define SCB_CTR_FORMAT_Pos                 29                                             /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24                                             /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20                                             /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16                                             /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0                                             /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL << SCB_CTR_IMINLINE_Pos)                /*!< SCB CTR: ImInLine Mask */
+
+/* Cache Size ID Register */
+#define SCB_CCSIDR_WT_Pos                  31                                             /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (7UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30                                             /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (7UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29                                             /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (7UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28                                             /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (7UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13                                             /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3                                             /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0                                             /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL << SCB_CCSIDR_LINESIZE_Pos)               /*!< SCB CCSIDR: LineSize Mask */
+
+/* Cache Size Selection Register */
+#define SCB_CSSELR_LEVEL_Pos                0                                             /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (1UL << SCB_CSSELR_LEVEL_Pos)                    /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0                                             /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL << SCB_CSSELR_IND_Pos)                    /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register */
+#define SCB_STIR_INTID_Pos                  0                                             /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL << SCB_STIR_INTID_Pos)                /*!< SCB STIR: INTID Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register*/
+#define SCB_ITCMCR_SZ_Pos                   3                                             /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2                                             /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1FFUL << SCB_ITCMCR_RETEN_Pos)                /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1                                             /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1FFUL << SCB_ITCMCR_RMW_Pos)                  /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0                                             /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1FFUL << SCB_ITCMCR_EN_Pos)                   /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Registers */
+#define SCB_DTCMCR_SZ_Pos                   3                                             /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2                                             /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1                                             /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0                                             /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL << SCB_DTCMCR_EN_Pos)                     /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register */
+#define SCB_AHBPCR_SZ_Pos                   1                                             /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0                                             /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL << SCB_AHBPCR_EN_Pos)                     /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register */
+#define SCB_CACR_FORCEWT_Pos                2                                             /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1                                             /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0                                             /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL << SCB_CACR_SIWT_Pos)                     /*!< SCB CACR: SIWT Mask */
+
+/* AHBS control register */
+#define SCB_AHBSCR_INITCOUNT_Pos           11                                             /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2                                             /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0                                             /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL << SCB_AHBPCR_CTL_Pos)                    /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register */
+#define SCB_ABFSR_AXIMTYPE_Pos              8                                             /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4                                             /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3                                             /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2                                             /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1                                             /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0                                             /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL << SCB_ABFSR_ITCM_Pos)                    /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12                                          /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos         11                                          /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos         10                                          /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+       uint32_t RESERVED3[981];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 (  W)  Lock Access Register                      */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R  )  Lock Status Register                      */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+  __I  uint32_t MVFR2;                   /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)]            = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]            >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  Cache functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_CacheFunctions Cache Functions
+    \brief      Functions that configure Instruction and Data cache.
+    @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+#define CCSIDR_LSSHIFT(x)      (((x) & SCB_CCSIDR_LINESIZE_Msk     ) >> SCB_CCSIDR_LINESIZE_Pos     )
+
+
+/** \brief Enable I-Cache
+
+    The function turns on I-Cache
+  */
+__STATIC_INLINE void SCB_EnableICache(void)
+{
+  #if (__ICACHE_PRESENT == 1)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0;                       // invalidate I-Cache
+    SCB->CCR |=  SCB_CCR_IC_Msk;            // enable I-Cache
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Disable I-Cache
+
+    The function turns off I-Cache
+  */
+__STATIC_INLINE void SCB_DisableICache(void)
+{
+  #if (__ICACHE_PRESENT == 1)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~SCB_CCR_IC_Msk;            // disable I-Cache
+    SCB->ICIALLU = 0;                       // invalidate I-Cache
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Invalidate I-Cache
+
+    The function invalidates I-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateICache(void)
+{
+  #if (__ICACHE_PRESENT == 1)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0;
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Enable D-Cache
+
+    The function turns on D-Cache
+  */
+__STATIC_INLINE void SCB_EnableDCache(void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    ccsidr  = SCB->CCSIDR;
+    sets    = CCSIDR_SETS(ccsidr);
+    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;
+    ways    = CCSIDR_WAYS(ccsidr);
+    wshift  = __CLZ(ways) & 0x1f;
+
+    __DSB();
+
+    do {                                    // invalidate D-Cache
+         int32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCISW = sw;
+            } while(tmpways--);
+        } while(sets--);
+    __DSB();
+
+    SCB->CCR |=  SCB_CCR_DC_Msk;            // enable D-Cache
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Disable D-Cache
+
+    The function turns off D-Cache
+  */
+__STATIC_INLINE void SCB_DisableDCache(void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    ccsidr  = SCB->CCSIDR;
+    sets    = CCSIDR_SETS(ccsidr);
+    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;
+    ways    = CCSIDR_WAYS(ccsidr);
+    wshift  = __CLZ(ways) & 0x1f;
+
+    __DSB();
+
+    SCB->CCR &= ~SCB_CCR_DC_Msk;            // disable D-Cache
+
+    do {                                    // clean & invalidate D-Cache
+         int32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCCISW = sw;
+            } while(tmpways--);
+        } while(sets--);
+
+
+    __DSB();
+    __ISB();
+ #endif
+}
+
+
+/** \brief Invalidate D-Cache
+
+    The function invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateDCache(void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    ccsidr  = SCB->CCSIDR;
+    sets    = CCSIDR_SETS(ccsidr);
+    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;
+    ways    = CCSIDR_WAYS(ccsidr);
+    wshift  = __CLZ(ways) & 0x1f;
+
+    __DSB();
+
+    do {                                    // invalidate D-Cache
+         int32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCISW = sw;
+            } while(tmpways--);
+        } while(sets--);
+
+    __DSB();
+    __ISB();
+ #endif
+}
+
+
+/** \brief Clean D-Cache
+
+    The function cleans D-Cache
+  */
+__STATIC_INLINE void SCB_CleanDCache(void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    ccsidr  = SCB->CCSIDR;
+    sets    = CCSIDR_SETS(ccsidr);
+    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;
+    ways    = CCSIDR_WAYS(ccsidr);
+    wshift  = __CLZ(ways) & 0x1f;
+
+    __DSB();
+
+    do {                                    // clean D-Cache
+         int32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCCSW = sw;
+            } while(tmpways--);
+        } while(sets--);
+
+    __DSB();
+    __ISB();
+ #endif
+}
+
+
+/** \brief Clean & Invalidate D-Cache
+
+    The function cleans and Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_CleanInvalidateDCache(void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    ccsidr  = SCB->CCSIDR;
+    sets    = CCSIDR_SETS(ccsidr);
+    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;
+    ways    = CCSIDR_WAYS(ccsidr);
+    wshift  = __CLZ(ways) & 0x1f;
+
+    __DSB();
+
+    do {                                    // clean & invalidate D-Cache
+         int32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCCISW = sw;
+            } while(tmpways--);
+        } while(sets--);
+
+    __DSB();
+    __ISB();
+ #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/firmware/inc/platform/stm32f4xx/cmsis/core_cmFunc.h b/firmware/os/cpu/cortexm4/inc/cpu/cmsis/core_cmFunc.h
index a1bd88c2..01089f13 100644
--- a/firmware/inc/platform/stm32f4xx/cmsis/core_cmFunc.h
+++ b/firmware/os/cpu/cortexm4/inc/cpu/cmsis/core_cmFunc.h
@@ -1,637 +1,637 @@
-/**************************************************************************//**

- * @file     core_cmFunc.h

- * @brief    CMSIS Cortex-M Core Function Access Header File

- * @version  V4.00

- * @date     28. August 2014

- *

- * @note

- *

- ******************************************************************************/

-/* Copyright (c) 2009 - 2014 ARM LIMITED

-

-   All rights reserved.

-   Redistribution and use in source and binary forms, with or without

-   modification, are permitted provided that the following conditions are met:

-   - Redistributions of source code must retain the above copyright

-     notice, this list of conditions and the following disclaimer.

-   - Redistributions in binary form must reproduce the above copyright

-     notice, this list of conditions and the following disclaimer in the

-     documentation and/or other materials provided with the distribution.

-   - Neither the name of ARM nor the names of its contributors may be used

-     to endorse or promote products derived from this software without

-     specific prior written permission.

-   *

-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-   POSSIBILITY OF SUCH DAMAGE.

-   ---------------------------------------------------------------------------*/

-

-

-#ifndef __CORE_CMFUNC_H

-#define __CORE_CMFUNC_H

-

-

-/* ###########################  Core Function Access  ########################### */

-/** \ingroup  CMSIS_Core_FunctionInterface

-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions

-  @{

- */

-

-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/

-/* ARM armcc specific functions */

-

-#if (__ARMCC_VERSION < 400677)

-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"

-#endif

-

-/* intrinsic void __enable_irq();     */

-/* intrinsic void __disable_irq();    */

-

-/** \brief  Get Control Register

-

-    This function returns the content of the Control Register.

-

-    \return               Control Register value

- */

-__STATIC_INLINE uint32_t __get_CONTROL(void)

-{

-  register uint32_t __regControl         __ASM("control");

-  return(__regControl);

-}

-

-

-/** \brief  Set Control Register

-

-    This function writes the given value to the Control Register.

-

-    \param [in]    control  Control Register value to set

- */

-__STATIC_INLINE void __set_CONTROL(uint32_t control)

-{

-  register uint32_t __regControl         __ASM("control");

-  __regControl = control;

-}

-

-

-/** \brief  Get IPSR Register

-

-    This function returns the content of the IPSR Register.

-

-    \return               IPSR Register value

- */

-__STATIC_INLINE uint32_t __get_IPSR(void)

-{

-  register uint32_t __regIPSR          __ASM("ipsr");

-  return(__regIPSR);

-}

-

-

-/** \brief  Get APSR Register

-

-    This function returns the content of the APSR Register.

-

-    \return               APSR Register value

- */

-__STATIC_INLINE uint32_t __get_APSR(void)

-{

-  register uint32_t __regAPSR          __ASM("apsr");

-  return(__regAPSR);

-}

-

-

-/** \brief  Get xPSR Register

-

-    This function returns the content of the xPSR Register.

-

-    \return               xPSR Register value

- */

-__STATIC_INLINE uint32_t __get_xPSR(void)

-{

-  register uint32_t __regXPSR          __ASM("xpsr");

-  return(__regXPSR);

-}

-

-

-/** \brief  Get Process Stack Pointer

-

-    This function returns the current value of the Process Stack Pointer (PSP).

-

-    \return               PSP Register value

- */

-__STATIC_INLINE uint32_t __get_PSP(void)

-{

-  register uint32_t __regProcessStackPointer  __ASM("psp");

-  return(__regProcessStackPointer);

-}

-

-

-/** \brief  Set Process Stack Pointer

-

-    This function assigns the given value to the Process Stack Pointer (PSP).

-

-    \param [in]    topOfProcStack  Process Stack Pointer value to set

- */

-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)

-{

-  register uint32_t __regProcessStackPointer  __ASM("psp");

-  __regProcessStackPointer = topOfProcStack;

-}

-

-

-/** \brief  Get Main Stack Pointer

-

-    This function returns the current value of the Main Stack Pointer (MSP).

-

-    \return               MSP Register value

- */

-__STATIC_INLINE uint32_t __get_MSP(void)

-{

-  register uint32_t __regMainStackPointer     __ASM("msp");

-  return(__regMainStackPointer);

-}

-

-

-/** \brief  Set Main Stack Pointer

-

-    This function assigns the given value to the Main Stack Pointer (MSP).

-

-    \param [in]    topOfMainStack  Main Stack Pointer value to set

- */

-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)

-{

-  register uint32_t __regMainStackPointer     __ASM("msp");

-  __regMainStackPointer = topOfMainStack;

-}

-

-

-/** \brief  Get Priority Mask

-

-    This function returns the current state of the priority mask bit from the Priority Mask Register.

-

-    \return               Priority Mask value

- */

-__STATIC_INLINE uint32_t __get_PRIMASK(void)

-{

-  register uint32_t __regPriMask         __ASM("primask");

-  return(__regPriMask);

-}

-

-

-/** \brief  Set Priority Mask

-

-    This function assigns the given value to the Priority Mask Register.

-

-    \param [in]    priMask  Priority Mask

- */

-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)

-{

-  register uint32_t __regPriMask         __ASM("primask");

-  __regPriMask = (priMask);

-}

-

-

-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)

-

-/** \brief  Enable FIQ

-

-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.

-    Can only be executed in Privileged modes.

- */

-#define __enable_fault_irq                __enable_fiq

-

-

-/** \brief  Disable FIQ

-

-    This function disables FIQ interrupts by setting the F-bit in the CPSR.

-    Can only be executed in Privileged modes.

- */

-#define __disable_fault_irq               __disable_fiq

-

-

-/** \brief  Get Base Priority

-

-    This function returns the current value of the Base Priority register.

-

-    \return               Base Priority register value

- */

-__STATIC_INLINE uint32_t  __get_BASEPRI(void)

-{

-  register uint32_t __regBasePri         __ASM("basepri");

-  return(__regBasePri);

-}

-

-

-/** \brief  Set Base Priority

-

-    This function assigns the given value to the Base Priority register.

-

-    \param [in]    basePri  Base Priority value to set

- */

-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)

-{

-  register uint32_t __regBasePri         __ASM("basepri");

-  __regBasePri = (basePri & 0xff);

-}

-

-

-/** \brief  Get Fault Mask

-

-    This function returns the current value of the Fault Mask register.

-

-    \return               Fault Mask register value

- */

-__STATIC_INLINE uint32_t __get_FAULTMASK(void)

-{

-  register uint32_t __regFaultMask       __ASM("faultmask");

-  return(__regFaultMask);

-}

-

-

-/** \brief  Set Fault Mask

-

-    This function assigns the given value to the Fault Mask register.

-

-    \param [in]    faultMask  Fault Mask value to set

- */

-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)

-{

-  register uint32_t __regFaultMask       __ASM("faultmask");

-  __regFaultMask = (faultMask & (uint32_t)1);

-}

-

-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */

-

-

-#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)

-

-/** \brief  Get FPSCR

-

-    This function returns the current value of the Floating Point Status/Control register.

-

-    \return               Floating Point Status/Control register value

- */

-__STATIC_INLINE uint32_t __get_FPSCR(void)

-{

-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)

-  register uint32_t __regfpscr         __ASM("fpscr");

-  return(__regfpscr);

-#else

-   return(0);

-#endif

-}

-

-

-/** \brief  Set FPSCR

-

-    This function assigns the given value to the Floating Point Status/Control register.

-

-    \param [in]    fpscr  Floating Point Status/Control value to set

- */

-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)

-{

-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)

-  register uint32_t __regfpscr         __ASM("fpscr");

-  __regfpscr = (fpscr);

-#endif

-}

-

-#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */

-

-

-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/

-/* GNU gcc specific functions */

-

-/** \brief  Enable IRQ Interrupts

-

-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.

-  Can only be executed in Privileged modes.

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)

-{

-  __ASM volatile ("cpsie i" : : : "memory");

-}

-

-

-/** \brief  Disable IRQ Interrupts

-

-  This function disables IRQ interrupts by setting the I-bit in the CPSR.

-  Can only be executed in Privileged modes.

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)

-{

-  __ASM volatile ("cpsid i" : : : "memory");

-}

-

-

-/** \brief  Get Control Register

-

-    This function returns the content of the Control Register.

-

-    \return               Control Register value

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, control" : "=r" (result) );

-  return(result);

-}

-

-

-/** \brief  Set Control Register

-

-    This function writes the given value to the Control Register.

-

-    \param [in]    control  Control Register value to set

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)

-{

-  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");

-}

-

-

-/** \brief  Get IPSR Register

-

-    This function returns the content of the IPSR Register.

-

-    \return               IPSR Register value

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );

-  return(result);

-}

-

-

-/** \brief  Get APSR Register

-

-    This function returns the content of the APSR Register.

-

-    \return               APSR Register value

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );

-  return(result);

-}

-

-

-/** \brief  Get xPSR Register

-

-    This function returns the content of the xPSR Register.

-

-    \return               xPSR Register value

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );

-  return(result);

-}

-

-

-/** \brief  Get Process Stack Pointer

-

-    This function returns the current value of the Process Stack Pointer (PSP).

-

-    \return               PSP Register value

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)

-{

-  register uint32_t result;

-

-  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );

-  return(result);

-}

-

-

-/** \brief  Set Process Stack Pointer

-

-    This function assigns the given value to the Process Stack Pointer (PSP).

-

-    \param [in]    topOfProcStack  Process Stack Pointer value to set

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)

-{

-  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");

-}

-

-

-/** \brief  Get Main Stack Pointer

-

-    This function returns the current value of the Main Stack Pointer (MSP).

-

-    \return               MSP Register value

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)

-{

-  register uint32_t result;

-

-  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );

-  return(result);

-}

-

-

-/** \brief  Set Main Stack Pointer

-

-    This function assigns the given value to the Main Stack Pointer (MSP).

-

-    \param [in]    topOfMainStack  Main Stack Pointer value to set

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)

-{

-  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");

-}

-

-

-/** \brief  Get Priority Mask

-

-    This function returns the current state of the priority mask bit from the Priority Mask Register.

-

-    \return               Priority Mask value

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, primask" : "=r" (result) );

-  return(result);

-}

-

-

-/** \brief  Set Priority Mask

-

-    This function assigns the given value to the Priority Mask Register.

-

-    \param [in]    priMask  Priority Mask

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)

-{

-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");

-}

-

-

-#if       (__CORTEX_M >= 0x03)

-

-/** \brief  Enable FIQ

-

-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.

-    Can only be executed in Privileged modes.

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)

-{

-  __ASM volatile ("cpsie f" : : : "memory");

-}

-

-

-/** \brief  Disable FIQ

-

-    This function disables FIQ interrupts by setting the F-bit in the CPSR.

-    Can only be executed in Privileged modes.

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)

-{

-  __ASM volatile ("cpsid f" : : : "memory");

-}

-

-

-/** \brief  Get Base Priority

-

-    This function returns the current value of the Base Priority register.

-

-    \return               Base Priority register value

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );

-  return(result);

-}

-

-

-/** \brief  Set Base Priority

-

-    This function assigns the given value to the Base Priority register.

-

-    \param [in]    basePri  Base Priority value to set

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)

-{

-  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");

-}

-

-

-/** \brief  Get Fault Mask

-

-    This function returns the current value of the Fault Mask register.

-

-    \return               Fault Mask register value

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );

-  return(result);

-}

-

-

-/** \brief  Set Fault Mask

-

-    This function assigns the given value to the Fault Mask register.

-

-    \param [in]    faultMask  Fault Mask value to set

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)

-{

-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");

-}

-

-#endif /* (__CORTEX_M >= 0x03) */

-

-

-#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)

-

-/** \brief  Get FPSCR

-

-    This function returns the current value of the Floating Point Status/Control register.

-

-    \return               Floating Point Status/Control register value

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)

-{

-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)

-  uint32_t result;

-

-  /* Empty asm statement works as a scheduling barrier */

-  __ASM volatile ("");

-  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );

-  __ASM volatile ("");

-  return(result);

-#else

-   return(0);

-#endif

-}

-

-

-/** \brief  Set FPSCR

-

-    This function assigns the given value to the Floating Point Status/Control register.

-

-    \param [in]    fpscr  Floating Point Status/Control value to set

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)

-{

-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)

-  /* Empty asm statement works as a scheduling barrier */

-  __ASM volatile ("");

-  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");

-  __ASM volatile ("");

-#endif

-}

-

-#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */

-

-

-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/

-/* IAR iccarm specific functions */

-#include <cmsis_iar.h>

-

-

-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/

-/* TI CCS specific functions */

-#include <cmsis_ccs.h>

-

-

-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/

-/* TASKING carm specific functions */

-/*

- * The CMSIS functions have been implemented as intrinsics in the compiler.

- * Please use "carm -?i" to get an up to date list of all intrinsics,

- * Including the CMSIS ones.

- */

-

-

-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/

-/* Cosmic specific functions */

-#include <cmsis_csm.h>

-

-#endif

-

-/*@} end of CMSIS_Core_RegAccFunctions */

-

-#endif /* __CORE_CMFUNC_H */

+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.00
+ * @date     28. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/firmware/inc/platform/stm32f4xx/cmsis/core_cmInstr.h b/firmware/os/cpu/cortexm4/inc/cpu/cmsis/core_cmInstr.h
index cabf4a02..d14110b2 100644
--- a/firmware/inc/platform/stm32f4xx/cmsis/core_cmInstr.h
+++ b/firmware/os/cpu/cortexm4/inc/cpu/cmsis/core_cmInstr.h
@@ -1,880 +1,880 @@
-/**************************************************************************//**

- * @file     core_cmInstr.h

- * @brief    CMSIS Cortex-M Core Instruction Access Header File

- * @version  V4.00

- * @date     28. August 2014

- *

- * @note

- *

- ******************************************************************************/

-/* Copyright (c) 2009 - 2014 ARM LIMITED

-

-   All rights reserved.

-   Redistribution and use in source and binary forms, with or without

-   modification, are permitted provided that the following conditions are met:

-   - Redistributions of source code must retain the above copyright

-     notice, this list of conditions and the following disclaimer.

-   - Redistributions in binary form must reproduce the above copyright

-     notice, this list of conditions and the following disclaimer in the

-     documentation and/or other materials provided with the distribution.

-   - Neither the name of ARM nor the names of its contributors may be used

-     to endorse or promote products derived from this software without

-     specific prior written permission.

-   *

-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-   POSSIBILITY OF SUCH DAMAGE.

-   ---------------------------------------------------------------------------*/

-

-

-#ifndef __CORE_CMINSTR_H

-#define __CORE_CMINSTR_H

-

-

-/* ##########################  Core Instruction Access  ######################### */

-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface

-  Access to dedicated instructions

-  @{

-*/

-

-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/

-/* ARM armcc specific functions */

-

-#if (__ARMCC_VERSION < 400677)

-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"

-#endif

-

-

-/** \brief  No Operation

-

-    No Operation does nothing. This instruction can be used for code alignment purposes.

- */

-#define __NOP                             __nop

-

-

-/** \brief  Wait For Interrupt

-

-    Wait For Interrupt is a hint instruction that suspends execution

-    until one of a number of events occurs.

- */

-#define __WFI                             __wfi

-

-

-/** \brief  Wait For Event

-

-    Wait For Event is a hint instruction that permits the processor to enter

-    a low-power state until one of a number of events occurs.

- */

-#define __WFE                             __wfe

-

-

-/** \brief  Send Event

-

-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.

- */

-#define __SEV                             __sev

-

-

-/** \brief  Instruction Synchronization Barrier

-

-    Instruction Synchronization Barrier flushes the pipeline in the processor,

-    so that all instructions following the ISB are fetched from cache or

-    memory, after the instruction has been completed.

- */

-#define __ISB()                           __isb(0xF)

-

-

-/** \brief  Data Synchronization Barrier

-

-    This function acts as a special kind of Data Memory Barrier.

-    It completes when all explicit memory accesses before this instruction complete.

- */

-#define __DSB()                           __dsb(0xF)

-

-

-/** \brief  Data Memory Barrier

-

-    This function ensures the apparent order of the explicit memory operations before

-    and after the instruction, without ensuring their completion.

- */

-#define __DMB()                           __dmb(0xF)

-

-

-/** \brief  Reverse byte order (32 bit)

-

-    This function reverses the byte order in integer value.

-

-    \param [in]    value  Value to reverse

-    \return               Reversed value

- */

-#define __REV                             __rev

-

-

-/** \brief  Reverse byte order (16 bit)

-

-    This function reverses the byte order in two unsigned short values.

-

-    \param [in]    value  Value to reverse

-    \return               Reversed value

- */

-#ifndef __NO_EMBEDDED_ASM

-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)

-{

-  rev16 r0, r0

-  bx lr

-}

-#endif

-

-/** \brief  Reverse byte order in signed short value

-

-    This function reverses the byte order in a signed short value with sign extension to integer.

-

-    \param [in]    value  Value to reverse

-    \return               Reversed value

- */

-#ifndef __NO_EMBEDDED_ASM

-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)

-{

-  revsh r0, r0

-  bx lr

-}

-#endif

-

-

-/** \brief  Rotate Right in unsigned value (32 bit)

-

-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.

-

-    \param [in]    value  Value to rotate

-    \param [in]    value  Number of Bits to rotate

-    \return               Rotated value

- */

-#define __ROR                             __ror

-

-

-/** \brief  Breakpoint

-

-    This function causes the processor to enter Debug state.

-    Debug tools can use this to investigate system state when the instruction at a particular address is reached.

-

-    \param [in]    value  is ignored by the processor.

-                   If required, a debugger can use it to store additional information about the breakpoint.

- */

-#define __BKPT(value)                       __breakpoint(value)

-

-

-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)

-

-/** \brief  Reverse bit order of value

-

-    This function reverses the bit order of the given value.

-

-    \param [in]    value  Value to reverse

-    \return               Reversed value

- */

-#define __RBIT                            __rbit

-

-

-/** \brief  LDR Exclusive (8 bit)

-

-    This function executes a exclusive LDR instruction for 8 bit value.

-

-    \param [in]    ptr  Pointer to data

-    \return             value of type uint8_t at (*ptr)

- */

-#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))

-

-

-/** \brief  LDR Exclusive (16 bit)

-

-    This function executes a exclusive LDR instruction for 16 bit values.

-

-    \param [in]    ptr  Pointer to data

-    \return        value of type uint16_t at (*ptr)

- */

-#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))

-

-

-/** \brief  LDR Exclusive (32 bit)

-

-    This function executes a exclusive LDR instruction for 32 bit values.

-

-    \param [in]    ptr  Pointer to data

-    \return        value of type uint32_t at (*ptr)

- */

-#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))

-

-

-/** \brief  STR Exclusive (8 bit)

-

-    This function executes a exclusive STR instruction for 8 bit values.

-

-    \param [in]  value  Value to store

-    \param [in]    ptr  Pointer to location

-    \return          0  Function succeeded

-    \return          1  Function failed

- */

-#define __STREXB(value, ptr)              __strex(value, ptr)

-

-

-/** \brief  STR Exclusive (16 bit)

-

-    This function executes a exclusive STR instruction for 16 bit values.

-

-    \param [in]  value  Value to store

-    \param [in]    ptr  Pointer to location

-    \return          0  Function succeeded

-    \return          1  Function failed

- */

-#define __STREXH(value, ptr)              __strex(value, ptr)

-

-

-/** \brief  STR Exclusive (32 bit)

-

-    This function executes a exclusive STR instruction for 32 bit values.

-

-    \param [in]  value  Value to store

-    \param [in]    ptr  Pointer to location

-    \return          0  Function succeeded

-    \return          1  Function failed

- */

-#define __STREXW(value, ptr)              __strex(value, ptr)

-

-

-/** \brief  Remove the exclusive lock

-

-    This function removes the exclusive lock which is created by LDREX.

-

- */

-#define __CLREX                           __clrex

-

-

-/** \brief  Signed Saturate

-

-    This function saturates a signed value.

-

-    \param [in]  value  Value to be saturated

-    \param [in]    sat  Bit position to saturate to (1..32)

-    \return             Saturated value

- */

-#define __SSAT                            __ssat

-

-

-/** \brief  Unsigned Saturate

-

-    This function saturates an unsigned value.

-

-    \param [in]  value  Value to be saturated

-    \param [in]    sat  Bit position to saturate to (0..31)

-    \return             Saturated value

- */

-#define __USAT                            __usat

-

-

-/** \brief  Count leading zeros

-

-    This function counts the number of leading zeros of a data value.

-

-    \param [in]  value  Value to count the leading zeros

-    \return             number of leading zeros in value

- */

-#define __CLZ                             __clz

-

-

-/** \brief  Rotate Right with Extend (32 bit)

-

-    This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.

-

-    \param [in]    value  Value to rotate

-    \return               Rotated value

- */

-#ifndef __NO_EMBEDDED_ASM

-__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)

-{

-  rrx r0, r0

-  bx lr

-}

-#endif

-

-

-/** \brief  LDRT Unprivileged (8 bit)

-

-    This function executes a Unprivileged LDRT instruction for 8 bit value.

-

-    \param [in]    ptr  Pointer to data

-    \return             value of type uint8_t at (*ptr)

- */

-#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))

-

-

-/** \brief  LDRT Unprivileged (16 bit)

-

-    This function executes a Unprivileged LDRT instruction for 16 bit values.

-

-    \param [in]    ptr  Pointer to data

-    \return        value of type uint16_t at (*ptr)

- */

-#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))

-

-

-/** \brief  LDRT Unprivileged (32 bit)

-

-    This function executes a Unprivileged LDRT instruction for 32 bit values.

-

-    \param [in]    ptr  Pointer to data

-    \return        value of type uint32_t at (*ptr)

- */

-#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))

-

-

-/** \brief  STRT Unprivileged (8 bit)

-

-    This function executes a Unprivileged STRT instruction for 8 bit values.

-

-    \param [in]  value  Value to store

-    \param [in]    ptr  Pointer to location

- */

-#define __STRBT(value, ptr)               __strt(value, ptr)

-

-

-/** \brief  STRT Unprivileged (16 bit)

-

-    This function executes a Unprivileged STRT instruction for 16 bit values.

-

-    \param [in]  value  Value to store

-    \param [in]    ptr  Pointer to location

- */

-#define __STRHT(value, ptr)               __strt(value, ptr)

-

-

-/** \brief  STRT Unprivileged (32 bit)

-

-    This function executes a Unprivileged STRT instruction for 32 bit values.

-

-    \param [in]  value  Value to store

-    \param [in]    ptr  Pointer to location

- */

-#define __STRT(value, ptr)                __strt(value, ptr)

-

-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */

-

-

-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/

-/* GNU gcc specific functions */

-

-/* Define macros for porting to both thumb1 and thumb2.

- * For thumb1, use low register (r0-r7), specified by constrant "l"

- * Otherwise, use general registers, specified by constrant "r" */

-#if defined (__thumb__) && !defined (__thumb2__)

-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)

-#define __CMSIS_GCC_USE_REG(r) "l" (r)

-#else

-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)

-#define __CMSIS_GCC_USE_REG(r) "r" (r)

-#endif

-

-/** \brief  No Operation

-

-    No Operation does nothing. This instruction can be used for code alignment purposes.

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)

-{

-  __ASM volatile ("nop");

-}

-

-

-/** \brief  Wait For Interrupt

-

-    Wait For Interrupt is a hint instruction that suspends execution

-    until one of a number of events occurs.

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)

-{

-  __ASM volatile ("wfi");

-}

-

-

-/** \brief  Wait For Event

-

-    Wait For Event is a hint instruction that permits the processor to enter

-    a low-power state until one of a number of events occurs.

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)

-{

-  __ASM volatile ("wfe");

-}

-

-

-/** \brief  Send Event

-

-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)

-{

-  __ASM volatile ("sev");

-}

-

-

-/** \brief  Instruction Synchronization Barrier

-

-    Instruction Synchronization Barrier flushes the pipeline in the processor,

-    so that all instructions following the ISB are fetched from cache or

-    memory, after the instruction has been completed.

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)

-{

-  __ASM volatile ("isb");

-}

-

-

-/** \brief  Data Synchronization Barrier

-

-    This function acts as a special kind of Data Memory Barrier.

-    It completes when all explicit memory accesses before this instruction complete.

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)

-{

-  __ASM volatile ("dsb");

-}

-

-

-/** \brief  Data Memory Barrier

-

-    This function ensures the apparent order of the explicit memory operations before

-    and after the instruction, without ensuring their completion.

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)

-{

-  __ASM volatile ("dmb");

-}

-

-

-/** \brief  Reverse byte order (32 bit)

-

-    This function reverses the byte order in integer value.

-

-    \param [in]    value  Value to reverse

-    \return               Reversed value

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)

-{

-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)

-  return __builtin_bswap32(value);

-#else

-  uint32_t result;

-

-  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

-  return(result);

-#endif

-}

-

-

-/** \brief  Reverse byte order (16 bit)

-

-    This function reverses the byte order in two unsigned short values.

-

-    \param [in]    value  Value to reverse

-    \return               Reversed value

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)

-{

-  uint32_t result;

-

-  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

-  return(result);

-}

-

-

-/** \brief  Reverse byte order in signed short value

-

-    This function reverses the byte order in a signed short value with sign extension to integer.

-

-    \param [in]    value  Value to reverse

-    \return               Reversed value

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)

-{

-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

-  return (short)__builtin_bswap16(value);

-#else

-  uint32_t result;

-

-  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

-  return(result);

-#endif

-}

-

-

-/** \brief  Rotate Right in unsigned value (32 bit)

-

-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.

-

-    \param [in]    value  Value to rotate

-    \param [in]    value  Number of Bits to rotate

-    \return               Rotated value

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)

-{

-  return (op1 >> op2) | (op1 << (32 - op2)); 

-}

-

-

-/** \brief  Breakpoint

-

-    This function causes the processor to enter Debug state.

-    Debug tools can use this to investigate system state when the instruction at a particular address is reached.

-

-    \param [in]    value  is ignored by the processor.

-                   If required, a debugger can use it to store additional information about the breakpoint.

- */

-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)

-

-

-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)

-

-/** \brief  Reverse bit order of value

-

-    This function reverses the bit order of the given value.

-

-    \param [in]    value  Value to reverse

-    \return               Reversed value

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)

-{

-  uint32_t result;

-

-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );

-   return(result);

-}

-

-

-/** \brief  LDR Exclusive (8 bit)

-

-    This function executes a exclusive LDR instruction for 8 bit value.

-

-    \param [in]    ptr  Pointer to data

-    \return             value of type uint8_t at (*ptr)

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)

-{

-    uint32_t result;

-

-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

-   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );

-#else

-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not

-       accepted by assembler. So has to use following less efficient pattern.

-    */

-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );

-#endif

-   return ((uint8_t) result);    /* Add explicit type cast here */

-}

-

-

-/** \brief  LDR Exclusive (16 bit)

-

-    This function executes a exclusive LDR instruction for 16 bit values.

-

-    \param [in]    ptr  Pointer to data

-    \return        value of type uint16_t at (*ptr)

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)

-{

-    uint32_t result;

-

-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

-   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );

-#else

-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not

-       accepted by assembler. So has to use following less efficient pattern.

-    */

-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );

-#endif

-   return ((uint16_t) result);    /* Add explicit type cast here */

-}

-

-

-/** \brief  LDR Exclusive (32 bit)

-

-    This function executes a exclusive LDR instruction for 32 bit values.

-

-    \param [in]    ptr  Pointer to data

-    \return        value of type uint32_t at (*ptr)

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)

-{

-    uint32_t result;

-

-   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );

-   return(result);

-}

-

-

-/** \brief  STR Exclusive (8 bit)

-

-    This function executes a exclusive STR instruction for 8 bit values.

-

-    \param [in]  value  Value to store

-    \param [in]    ptr  Pointer to location

-    \return          0  Function succeeded

-    \return          1  Function failed

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)

-{

-   uint32_t result;

-

-   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );

-   return(result);

-}

-

-

-/** \brief  STR Exclusive (16 bit)

-

-    This function executes a exclusive STR instruction for 16 bit values.

-

-    \param [in]  value  Value to store

-    \param [in]    ptr  Pointer to location

-    \return          0  Function succeeded

-    \return          1  Function failed

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)

-{

-   uint32_t result;

-

-   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );

-   return(result);

-}

-

-

-/** \brief  STR Exclusive (32 bit)

-

-    This function executes a exclusive STR instruction for 32 bit values.

-

-    \param [in]  value  Value to store

-    \param [in]    ptr  Pointer to location

-    \return          0  Function succeeded

-    \return          1  Function failed

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)

-{

-   uint32_t result;

-

-   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );

-   return(result);

-}

-

-

-/** \brief  Remove the exclusive lock

-

-    This function removes the exclusive lock which is created by LDREX.

-

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)

-{

-  __ASM volatile ("clrex" ::: "memory");

-}

-

-

-/** \brief  Signed Saturate

-

-    This function saturates a signed value.

-

-    \param [in]  value  Value to be saturated

-    \param [in]    sat  Bit position to saturate to (1..32)

-    \return             Saturated value

- */

-#define __SSAT(ARG1,ARG2) \

-({                          \

-  uint32_t __RES, __ARG1 = (ARG1); \

-  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

-  __RES; \

- })

-

-

-/** \brief  Unsigned Saturate

-

-    This function saturates an unsigned value.

-

-    \param [in]  value  Value to be saturated

-    \param [in]    sat  Bit position to saturate to (0..31)

-    \return             Saturated value

- */

-#define __USAT(ARG1,ARG2) \

-({                          \

-  uint32_t __RES, __ARG1 = (ARG1); \

-  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

-  __RES; \

- })

-

-

-/** \brief  Count leading zeros

-

-    This function counts the number of leading zeros of a data value.

-

-    \param [in]  value  Value to count the leading zeros

-    \return             number of leading zeros in value

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)

-{

-  uint32_t result;

-

-  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );

-   return ((uint8_t) result);    /* Add explicit type cast here */

-}

-

-

-/** \brief  Rotate Right with Extend (32 bit)

-

-    This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.

-

-    \param [in]    value  Value to rotate

-    \return               Rotated value

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)

-{

-  uint32_t result;

-

-  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

-  return(result);

-}

-

-

-/** \brief  LDRT Unprivileged (8 bit)

-

-    This function executes a Unprivileged LDRT instruction for 8 bit value.

-

-    \param [in]    ptr  Pointer to data

-    \return             value of type uint8_t at (*ptr)

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)

-{

-    uint32_t result;

-

-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

-   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );

-#else

-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not

-       accepted by assembler. So has to use following less efficient pattern.

-    */

-   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );

-#endif

-   return ((uint8_t) result);    /* Add explicit type cast here */

-}

-

-

-/** \brief  LDRT Unprivileged (16 bit)

-

-    This function executes a Unprivileged LDRT instruction for 16 bit values.

-

-    \param [in]    ptr  Pointer to data

-    \return        value of type uint16_t at (*ptr)

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)

-{

-    uint32_t result;

-

-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

-   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );

-#else

-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not

-       accepted by assembler. So has to use following less efficient pattern.

-    */

-   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );

-#endif

-   return ((uint16_t) result);    /* Add explicit type cast here */

-}

-

-

-/** \brief  LDRT Unprivileged (32 bit)

-

-    This function executes a Unprivileged LDRT instruction for 32 bit values.

-

-    \param [in]    ptr  Pointer to data

-    \return        value of type uint32_t at (*ptr)

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)

-{

-    uint32_t result;

-

-   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );

-   return(result);

-}

-

-

-/** \brief  STRT Unprivileged (8 bit)

-

-    This function executes a Unprivileged STRT instruction for 8 bit values.

-

-    \param [in]  value  Value to store

-    \param [in]    ptr  Pointer to location

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)

-{

-   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );

-}

-

-

-/** \brief  STRT Unprivileged (16 bit)

-

-    This function executes a Unprivileged STRT instruction for 16 bit values.

-

-    \param [in]  value  Value to store

-    \param [in]    ptr  Pointer to location

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)

-{

-   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );

-}

-

-

-/** \brief  STRT Unprivileged (32 bit)

-

-    This function executes a Unprivileged STRT instruction for 32 bit values.

-

-    \param [in]  value  Value to store

-    \param [in]    ptr  Pointer to location

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)

-{

-   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );

-}

-

-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */

-

-

-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/

-/* IAR iccarm specific functions */

-#include <cmsis_iar.h>

-

-

-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/

-/* TI CCS specific functions */

-#include <cmsis_ccs.h>

-

-

-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/

-/* TASKING carm specific functions */

-/*

- * The CMSIS functions have been implemented as intrinsics in the compiler.

- * Please use "carm -?i" to get an up to date list of all intrinsics,

- * Including the CMSIS ones.

- */

-

-

-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/

-/* Cosmic specific functions */

-#include <cmsis_csm.h>

-

-#endif

-

-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */

-

-#endif /* __CORE_CMINSTR_H */

+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.00
+ * @date     28. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2)); 
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/firmware/inc/platform/stm32f4xx/cmsis/core_cmSimd.h b/firmware/os/cpu/cortexm4/inc/cpu/cmsis/core_cmSimd.h
index 04665617..ee58eee5 100644
--- a/firmware/inc/platform/stm32f4xx/cmsis/core_cmSimd.h
+++ b/firmware/os/cpu/cortexm4/inc/cpu/cmsis/core_cmSimd.h
@@ -1,697 +1,697 @@
-/**************************************************************************//**

- * @file     core_cmSimd.h

- * @brief    CMSIS Cortex-M SIMD Header File

- * @version  V4.00

- * @date     22. August 2014

- *

- * @note

- *

- ******************************************************************************/

-/* Copyright (c) 2009 - 2014 ARM LIMITED

-

-   All rights reserved.

-   Redistribution and use in source and binary forms, with or without

-   modification, are permitted provided that the following conditions are met:

-   - Redistributions of source code must retain the above copyright

-     notice, this list of conditions and the following disclaimer.

-   - Redistributions in binary form must reproduce the above copyright

-     notice, this list of conditions and the following disclaimer in the

-     documentation and/or other materials provided with the distribution.

-   - Neither the name of ARM nor the names of its contributors may be used

-     to endorse or promote products derived from this software without

-     specific prior written permission.

-   *

-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-   POSSIBILITY OF SUCH DAMAGE.

-   ---------------------------------------------------------------------------*/

-

-

-#if defined ( __ICCARM__ )

- #pragma system_include  /* treat file as system include file for MISRA check */

-#endif

-

-#ifndef __CORE_CMSIMD_H

-#define __CORE_CMSIMD_H

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-

-/*******************************************************************************

- *                Hardware Abstraction Layer

- ******************************************************************************/

-

-

-/* ###################  Compiler specific Intrinsics  ########################### */

-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics

-  Access to dedicated SIMD instructions

-  @{

-*/

-

-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/

-/* ARM armcc specific functions */

-#define __SADD8                           __sadd8

-#define __QADD8                           __qadd8

-#define __SHADD8                          __shadd8

-#define __UADD8                           __uadd8

-#define __UQADD8                          __uqadd8

-#define __UHADD8                          __uhadd8

-#define __SSUB8                           __ssub8

-#define __QSUB8                           __qsub8

-#define __SHSUB8                          __shsub8

-#define __USUB8                           __usub8

-#define __UQSUB8                          __uqsub8

-#define __UHSUB8                          __uhsub8

-#define __SADD16                          __sadd16

-#define __QADD16                          __qadd16

-#define __SHADD16                         __shadd16

-#define __UADD16                          __uadd16

-#define __UQADD16                         __uqadd16

-#define __UHADD16                         __uhadd16

-#define __SSUB16                          __ssub16

-#define __QSUB16                          __qsub16

-#define __SHSUB16                         __shsub16

-#define __USUB16                          __usub16

-#define __UQSUB16                         __uqsub16

-#define __UHSUB16                         __uhsub16

-#define __SASX                            __sasx

-#define __QASX                            __qasx

-#define __SHASX                           __shasx

-#define __UASX                            __uasx

-#define __UQASX                           __uqasx

-#define __UHASX                           __uhasx

-#define __SSAX                            __ssax

-#define __QSAX                            __qsax

-#define __SHSAX                           __shsax

-#define __USAX                            __usax

-#define __UQSAX                           __uqsax

-#define __UHSAX                           __uhsax

-#define __USAD8                           __usad8

-#define __USADA8                          __usada8

-#define __SSAT16                          __ssat16

-#define __USAT16                          __usat16

-#define __UXTB16                          __uxtb16

-#define __UXTAB16                         __uxtab16

-#define __SXTB16                          __sxtb16

-#define __SXTAB16                         __sxtab16

-#define __SMUAD                           __smuad

-#define __SMUADX                          __smuadx

-#define __SMLAD                           __smlad

-#define __SMLADX                          __smladx

-#define __SMLALD                          __smlald

-#define __SMLALDX                         __smlaldx

-#define __SMUSD                           __smusd

-#define __SMUSDX                          __smusdx

-#define __SMLSD                           __smlsd

-#define __SMLSDX                          __smlsdx

-#define __SMLSLD                          __smlsld

-#define __SMLSLDX                         __smlsldx

-#define __SEL                             __sel

-#define __QADD                            __qadd

-#define __QSUB                            __qsub

-

-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \

-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )

-

-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \

-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )

-

-#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \

-                                                      ((int64_t)(ARG3) << 32)      ) >> 32))

-

-

-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/

-/* GNU gcc specific functions */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)

-{

-  uint32_t result;

-

-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

-  return(result);

-}

-

-#define __SSAT16(ARG1,ARG2) \

-({                          \

-  uint32_t __RES, __ARG1 = (ARG1); \

-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

-  __RES; \

- })

-

-#define __USAT16(ARG1,ARG2) \

-({                          \

-  uint32_t __RES, __ARG1 = (ARG1); \

-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

-  __RES; \

- })

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)

-{

-  uint32_t result;

-

-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)

-{

-  uint32_t result;

-

-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)

-{

-  uint32_t result;

-

-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)

-{

-  uint32_t result;

-

-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)

-{

-  union llreg_u{

-    uint32_t w32[2];

-    uint64_t w64;

-  } llr;

-  llr.w64 = acc;

-

-#ifndef __ARMEB__   // Little endian

-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

-#else               // Big endian

-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

-#endif

-

-  return(llr.w64);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)

-{

-  union llreg_u{

-    uint32_t w32[2];

-    uint64_t w64;

-  } llr;

-  llr.w64 = acc;

-

-#ifndef __ARMEB__   // Little endian

-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

-#else               // Big endian

-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

-#endif

-

-  return(llr.w64);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)

-{

-  uint32_t result;

-

-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)

-{

-  uint32_t result;

-

-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)

-{

-  union llreg_u{

-    uint32_t w32[2];

-    uint64_t w64;

-  } llr;

-  llr.w64 = acc;

-

-#ifndef __ARMEB__   // Little endian

-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

-#else               // Big endian

-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

-#endif

-

-  return(llr.w64);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)

-{

-  union llreg_u{

-    uint32_t w32[2];

-    uint64_t w64;

-  } llr;

-  llr.w64 = acc;

-

-#ifndef __ARMEB__   // Little endian

-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

-#else               // Big endian

-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

-#endif

-

-  return(llr.w64);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-#define __PKHBT(ARG1,ARG2,ARG3) \

-({                          \

-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \

-  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \

-  __RES; \

- })

-

-#define __PKHTB(ARG1,ARG2,ARG3) \

-({                          \

-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \

-  if (ARG3 == 0) \

-    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \

-  else \

-    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \

-  __RES; \

- })

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)

-{

- int32_t result;

-

- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );

- return(result);

-}

-

-

-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/

-/* IAR iccarm specific functions */

-#include <cmsis_iar.h>

-

-

-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/

-/* TI CCS specific functions */

-#include <cmsis_ccs.h>

-

-

-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/

-/* TASKING carm specific functions */

-/* not yet supported */

-

-

-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/

-/* Cosmic specific functions */

-#include <cmsis_csm.h>

-

-#endif

-

-/*@} end of group CMSIS_SIMD_intrinsics */

-

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_CMSIMD_H */

+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/* not yet supported */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */
diff --git a/firmware/inc/platform/stm32f4xx/cmsis/core_sc000.h b/firmware/os/cpu/cortexm4/inc/cpu/cmsis/core_sc000.h
index 5a0635d2..5d0219c8 100644
--- a/firmware/inc/platform/stm32f4xx/cmsis/core_sc000.h
+++ b/firmware/os/cpu/cortexm4/inc/cpu/cmsis/core_sc000.h
@@ -1,842 +1,842 @@
-/**************************************************************************//**

- * @file     core_sc000.h

- * @brief    CMSIS SC000 Core Peripheral Access Layer Header File

- * @version  V4.00

- * @date     22. August 2014

- *

- * @note

- *

- ******************************************************************************/

-/* Copyright (c) 2009 - 2014 ARM LIMITED

-

-   All rights reserved.

-   Redistribution and use in source and binary forms, with or without

-   modification, are permitted provided that the following conditions are met:

-   - Redistributions of source code must retain the above copyright

-     notice, this list of conditions and the following disclaimer.

-   - Redistributions in binary form must reproduce the above copyright

-     notice, this list of conditions and the following disclaimer in the

-     documentation and/or other materials provided with the distribution.

-   - Neither the name of ARM nor the names of its contributors may be used

-     to endorse or promote products derived from this software without

-     specific prior written permission.

-   *

-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-   POSSIBILITY OF SUCH DAMAGE.

-   ---------------------------------------------------------------------------*/

-

-

-#if defined ( __ICCARM__ )

- #pragma system_include  /* treat file as system include file for MISRA check */

-#endif

-

-#ifndef __CORE_SC000_H_GENERIC

-#define __CORE_SC000_H_GENERIC

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions

-  CMSIS violates the following MISRA-C:2004 rules:

-

-   \li Required Rule 8.5, object/function definition in header file.<br>

-     Function definitions in header files are used to allow 'inlining'.

-

-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>

-     Unions are used for effective representation of core registers.

-

-   \li Advisory Rule 19.7, Function-like macro defined.<br>

-     Function-like macros are used to allow more efficient code.

- */

-

-

-/*******************************************************************************

- *                 CMSIS definitions

- ******************************************************************************/

-/** \ingroup SC000

-  @{

- */

-

-/*  CMSIS SC000 definitions */

-#define __SC000_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version */

-#define __SC000_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version  */

-#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16) | \

-                                      __SC000_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */

-

-#define __CORTEX_SC                 (000)                                       /*!< Cortex secure core             */

-

-

-#if   defined ( __CC_ARM )

-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */

-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */

-  #define __STATIC_INLINE  static __inline

-

-#elif defined ( __GNUC__ )

-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */

-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __ICCARM__ )

-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */

-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TMS470__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TASKING__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */

-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __CSMC__ )

-  #define __packed

-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */

-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */

-  #define __STATIC_INLINE  static inline

-

-#endif

-

-/** __FPU_USED indicates whether an FPU is used or not.

-    This core does not support an FPU at all

-*/

-#define __FPU_USED       0

-

-#if defined ( __CC_ARM )

-  #if defined __TARGET_FPU_VFP

-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __GNUC__ )

-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __ICCARM__ )

-  #if defined __ARMVFP__

-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __TMS470__ )

-  #if defined __TI__VFP_SUPPORT____

-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __TASKING__ )

-  #if defined __FPU_VFP__

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __CSMC__ )		/* Cosmic */

-  #if ( __CSMC__ & 0x400)		// FPU present for parser

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-#endif

-

-#include <stdint.h>                      /* standard types definitions                      */

-#include <core_cmInstr.h>                /* Core Instruction Access                         */

-#include <core_cmFunc.h>                 /* Core Function Access                            */

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_SC000_H_GENERIC */

-

-#ifndef __CMSIS_GENERIC

-

-#ifndef __CORE_SC000_H_DEPENDANT

-#define __CORE_SC000_H_DEPENDANT

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/* check device defines and use defaults */

-#if defined __CHECK_DEVICE_DEFINES

-  #ifndef __SC000_REV

-    #define __SC000_REV             0x0000

-    #warning "__SC000_REV not defined in device header file; using default!"

-  #endif

-

-  #ifndef __MPU_PRESENT

-    #define __MPU_PRESENT             0

-    #warning "__MPU_PRESENT not defined in device header file; using default!"

-  #endif

-

-  #ifndef __NVIC_PRIO_BITS

-    #define __NVIC_PRIO_BITS          2

-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"

-  #endif

-

-  #ifndef __Vendor_SysTickConfig

-    #define __Vendor_SysTickConfig    0

-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"

-  #endif

-#endif

-

-/* IO definitions (access restrictions to peripheral registers) */

-/**

-    \defgroup CMSIS_glob_defs CMSIS Global Defines

-

-    <strong>IO Type Qualifiers</strong> are used

-    \li to specify the access to peripheral variables.

-    \li for automatic generation of peripheral register debug information.

-*/

-#ifdef __cplusplus

-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */

-#else

-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */

-#endif

-#define     __O     volatile             /*!< Defines 'write only' permissions                */

-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */

-

-/*@} end of group SC000 */

-

-

-

-/*******************************************************************************

- *                 Register Abstraction

-  Core Register contain:

-  - Core Register

-  - Core NVIC Register

-  - Core SCB Register

-  - Core SysTick Register

-  - Core MPU Register

- ******************************************************************************/

-/** \defgroup CMSIS_core_register Defines and Type Definitions

-    \brief Type definitions and defines for Cortex-M processor based devices.

-*/

-

-/** \ingroup    CMSIS_core_register

-    \defgroup   CMSIS_CORE  Status and Control Registers

-    \brief  Core Register type definitions.

-  @{

- */

-

-/** \brief  Union type to access the Application Program Status Register (APSR).

- */

-typedef union

-{

-  struct

-  {

-#if (__CORTEX_M != 0x04)

-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */

-#else

-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */

-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */

-#endif

-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} APSR_Type;

-

-

-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} IPSR_Type;

-

-

-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

-#if (__CORTEX_M != 0x04)

-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */

-#else

-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */

-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */

-#endif

-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */

-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */

-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} xPSR_Type;

-

-

-/** \brief  Union type to access the Control Registers (CONTROL).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */

-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */

-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */

-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} CONTROL_Type;

-

-/*@} end of group CMSIS_CORE */

-

-

-/** \ingroup    CMSIS_core_register

-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)

-    \brief      Type definitions for the NVIC Registers

-  @{

- */

-

-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).

- */

-typedef struct

-{

-  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */

-       uint32_t RESERVED0[31];

-  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */

-       uint32_t RSERVED1[31];

-  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */

-       uint32_t RESERVED2[31];

-  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */

-       uint32_t RESERVED3[31];

-       uint32_t RESERVED4[64];

-  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */

-}  NVIC_Type;

-

-/*@} end of group CMSIS_NVIC */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_SCB     System Control Block (SCB)

-    \brief      Type definitions for the System Control Block Registers

-  @{

- */

-

-/** \brief  Structure type to access the System Control Block (SCB).

- */

-typedef struct

-{

-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */

-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */

-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */

-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */

-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */

-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */

-       uint32_t RESERVED0[1];

-  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */

-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */

-       uint32_t RESERVED1[154];

-  __IO uint32_t SFCR;                    /*!< Offset: 0x290 (R/W)  Security Features Register                            */

-} SCB_Type;

-

-/* SCB CPUID Register Definitions */

-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */

-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */

-

-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */

-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */

-

-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */

-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */

-

-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */

-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */

-

-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */

-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */

-

-/* SCB Interrupt Control State Register Definitions */

-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */

-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */

-

-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */

-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */

-

-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */

-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */

-

-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */

-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */

-

-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */

-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */

-

-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */

-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */

-

-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */

-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */

-

-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */

-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */

-

-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */

-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */

-

-/* SCB Interrupt Control State Register Definitions */

-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */

-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */

-

-/* SCB Application Interrupt and Reset Control Register Definitions */

-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */

-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */

-

-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */

-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */

-

-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */

-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */

-

-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */

-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */

-

-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */

-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */

-

-/* SCB System Control Register Definitions */

-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */

-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */

-

-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */

-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */

-

-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */

-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */

-

-/* SCB Configuration Control Register Definitions */

-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */

-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */

-

-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */

-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */

-

-/* SCB System Handler Control and State Register Definitions */

-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */

-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */

-

-/* SCB Security Features Register Definitions */

-#define SCB_SFCR_UNIBRTIMING_Pos            0                                             /*!< SCB SFCR: UNIBRTIMING Position */

-#define SCB_SFCR_UNIBRTIMING_Msk           (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SFCR: UNIBRTIMING Mask */

-

-#define SCB_SFCR_SECKEY_Pos                16                                             /*!< SCB SFCR: SECKEY Position */

-#define SCB_SFCR_SECKEY_Msk               (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos)        /*!< SCB SFCR: SECKEY Mask */

-

-/*@} end of group CMSIS_SCB */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)

-    \brief      Type definitions for the System Control and ID Register not in the SCB

-  @{

- */

-

-/** \brief  Structure type to access the System Control and ID Register not in the SCB.

- */

-typedef struct

-{

-       uint32_t RESERVED0[2];

-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */

-} SCnSCB_Type;

-

-/* Auxiliary Control Register Definitions */

-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */

-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */

-

-/*@} end of group CMSIS_SCnotSCB */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)

-    \brief      Type definitions for the System Timer Registers.

-  @{

- */

-

-/** \brief  Structure type to access the System Timer (SysTick).

- */

-typedef struct

-{

-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */

-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */

-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */

-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */

-} SysTick_Type;

-

-/* SysTick Control / Status Register Definitions */

-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */

-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */

-

-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */

-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */

-

-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */

-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */

-

-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */

-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */

-

-/* SysTick Reload Register Definitions */

-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */

-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */

-

-/* SysTick Current Register Definitions */

-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */

-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */

-

-/* SysTick Calibration Register Definitions */

-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */

-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */

-

-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */

-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */

-

-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */

-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */

-

-/*@} end of group CMSIS_SysTick */

-

-#if (__MPU_PRESENT == 1)

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)

-    \brief      Type definitions for the Memory Protection Unit (MPU)

-  @{

- */

-

-/** \brief  Structure type to access the Memory Protection Unit (MPU).

- */

-typedef struct

-{

-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */

-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */

-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */

-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */

-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */

-} MPU_Type;

-

-/* MPU Type Register */

-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */

-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */

-

-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */

-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */

-

-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */

-#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */

-

-/* MPU Control Register */

-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */

-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */

-

-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */

-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */

-

-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */

-#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */

-

-/* MPU Region Number Register */

-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */

-#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */

-

-/* MPU Region Base Address Register */

-#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */

-#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */

-

-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */

-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */

-

-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */

-#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */

-

-/* MPU Region Attribute and Size Register */

-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */

-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */

-

-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */

-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */

-

-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */

-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */

-

-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */

-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */

-

-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */

-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */

-

-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */

-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */

-

-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */

-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */

-

-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */

-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */

-

-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */

-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */

-

-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */

-#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */

-

-/*@} end of group CMSIS_MPU */

-#endif

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)

-    \brief      SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)

-                are only accessible over DAP and not via processor. Therefore

-                they are not covered by the Cortex-M0 header file.

-  @{

- */

-/*@} end of group CMSIS_CoreDebug */

-

-

-/** \ingroup    CMSIS_core_register

-    \defgroup   CMSIS_core_base     Core Definitions

-    \brief      Definitions for base addresses, unions, and structures.

-  @{

- */

-

-/* Memory mapping of SC000 Hardware */

-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */

-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */

-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */

-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */

-

-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */

-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */

-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */

-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */

-

-#if (__MPU_PRESENT == 1)

-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */

-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */

-#endif

-

-/*@} */

-

-

-

-/*******************************************************************************

- *                Hardware Abstraction Layer

-  Core Function Interface contains:

-  - Core NVIC Functions

-  - Core SysTick Functions

-  - Core Register Access Functions

- ******************************************************************************/

-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference

-*/

-

-

-

-/* ##########################   NVIC functions  #################################### */

-/** \ingroup  CMSIS_Core_FunctionInterface

-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions

-    \brief      Functions that manage interrupts and exceptions via the NVIC.

-    @{

- */

-

-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */

-/* The following MACROS handle generation of the register offset and byte masks */

-#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )

-#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )

-#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )

-

-

-/** \brief  Enable External Interrupt

-

-    The function enables a device-specific interrupt in the NVIC interrupt controller.

-

-    \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)

-{

-  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));

-}

-

-

-/** \brief  Disable External Interrupt

-

-    The function disables a device-specific interrupt in the NVIC interrupt controller.

-

-    \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));

-}

-

-

-/** \brief  Get Pending Interrupt

-

-    The function reads the pending register in the NVIC and returns the pending bit

-    for the specified interrupt.

-

-    \param [in]      IRQn  Interrupt number.

-

-    \return             0  Interrupt status is not pending.

-    \return             1  Interrupt status is pending.

- */

-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)

-{

-  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));

-}

-

-

-/** \brief  Set Pending Interrupt

-

-    The function sets the pending bit of an external interrupt.

-

-    \param [in]      IRQn  Interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));

-}

-

-

-/** \brief  Clear Pending Interrupt

-

-    The function clears the pending bit of an external interrupt.

-

-    \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */

-}

-

-

-/** \brief  Set Interrupt Priority

-

-    The function sets the priority of an interrupt.

-

-    \note The priority cannot be set for every core interrupt.

-

-    \param [in]      IRQn  Interrupt number.

-    \param [in]  priority  Priority to set.

- */

-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

-{

-  if(IRQn < 0) {

-    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |

-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }

-  else {

-    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |

-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }

-}

-

-

-/** \brief  Get Interrupt Priority

-

-    The function reads the priority of an interrupt. The interrupt

-    number can be positive to specify an external (device specific)

-    interrupt, or negative to specify an internal (core) interrupt.

-

-

-    \param [in]   IRQn  Interrupt number.

-    \return             Interrupt Priority. Value is aligned automatically to the implemented

-                        priority bits of the microcontroller.

- */

-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)

-{

-

-  if(IRQn < 0) {

-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */

-  else {

-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */

-}

-

-

-/** \brief  System Reset

-

-    The function initiates a system reset request to reset the MCU.

- */

-__STATIC_INLINE void NVIC_SystemReset(void)

-{

-  __DSB();                                                     /* Ensure all outstanding memory accesses included

-                                                                  buffered write are completed before reset */

-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |

-                 SCB_AIRCR_SYSRESETREQ_Msk);

-  __DSB();                                                     /* Ensure completion of memory access */

-  while(1);                                                    /* wait until reset */

-}

-

-/*@} end of CMSIS_Core_NVICFunctions */

-

-

-

-/* ##################################    SysTick function  ############################################ */

-/** \ingroup  CMSIS_Core_FunctionInterface

-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions

-    \brief      Functions that configure the System.

-  @{

- */

-

-#if (__Vendor_SysTickConfig == 0)

-

-/** \brief  System Tick Configuration

-

-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.

-    Counter is in free running mode to generate periodic interrupts.

-

-    \param [in]  ticks  Number of ticks between two interrupts.

-

-    \return          0  Function succeeded.

-    \return          1  Function failed.

-

-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the

-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>

-    must contain a vendor-specific implementation of this function.

-

- */

-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

-{

-  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */

-

-  SysTick->LOAD  = ticks - 1;                                  /* set reload register */

-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */

-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */

-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |

-                   SysTick_CTRL_TICKINT_Msk   |

-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */

-  return (0);                                                  /* Function successful */

-}

-

-#endif

-

-/*@} end of CMSIS_Core_SysTickFunctions */

-

-

-

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_SC000_H_DEPENDANT */

-

-#endif /* __CMSIS_GENERIC */

+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC000
+  @{
+ */
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC000_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
+
+#define __CORTEX_SC                 (000)                                       /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED0[1];
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+       uint32_t RESERVED1[154];
+  __IO uint32_t SFCR;                    /*!< Offset: 0x290 (R/W)  Security Features Register                            */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/* SCB Security Features Register Definitions */
+#define SCB_SFCR_UNIBRTIMING_Pos            0                                             /*!< SCB SFCR: UNIBRTIMING Position */
+#define SCB_SFCR_UNIBRTIMING_Msk           (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SFCR: UNIBRTIMING Mask */
+
+#define SCB_SFCR_SECKEY_Pos                16                                             /*!< SCB SFCR: SECKEY Position */
+#define SCB_SFCR_SECKEY_Msk               (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos)        /*!< SCB SFCR: SECKEY Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of SC000 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/firmware/inc/platform/stm32f4xx/cmsis/core_sc300.h b/firmware/os/cpu/cortexm4/inc/cpu/cmsis/core_sc300.h
index d82eab97..b6f6e8b5 100644
--- a/firmware/inc/platform/stm32f4xx/cmsis/core_sc300.h
+++ b/firmware/os/cpu/cortexm4/inc/cpu/cmsis/core_sc300.h
@@ -1,1630 +1,1630 @@
-/**************************************************************************//**

- * @file     core_sc300.h

- * @brief    CMSIS SC300 Core Peripheral Access Layer Header File

- * @version  V4.00

- * @date     22. August 2014

- *

- * @note

- *

- ******************************************************************************/

-/* Copyright (c) 2009 - 2014 ARM LIMITED

-

-   All rights reserved.

-   Redistribution and use in source and binary forms, with or without

-   modification, are permitted provided that the following conditions are met:

-   - Redistributions of source code must retain the above copyright

-     notice, this list of conditions and the following disclaimer.

-   - Redistributions in binary form must reproduce the above copyright

-     notice, this list of conditions and the following disclaimer in the

-     documentation and/or other materials provided with the distribution.

-   - Neither the name of ARM nor the names of its contributors may be used

-     to endorse or promote products derived from this software without

-     specific prior written permission.

-   *

-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-   POSSIBILITY OF SUCH DAMAGE.

-   ---------------------------------------------------------------------------*/

-

-

-#if defined ( __ICCARM__ )

- #pragma system_include  /* treat file as system include file for MISRA check */

-#endif

-

-#ifndef __CORE_SC300_H_GENERIC

-#define __CORE_SC300_H_GENERIC

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions

-  CMSIS violates the following MISRA-C:2004 rules:

-

-   \li Required Rule 8.5, object/function definition in header file.<br>

-     Function definitions in header files are used to allow 'inlining'.

-

-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>

-     Unions are used for effective representation of core registers.

-

-   \li Advisory Rule 19.7, Function-like macro defined.<br>

-     Function-like macros are used to allow more efficient code.

- */

-

-

-/*******************************************************************************

- *                 CMSIS definitions

- ******************************************************************************/

-/** \ingroup SC3000

-  @{

- */

-

-/*  CMSIS SC300 definitions */

-#define __SC300_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version */

-#define __SC300_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version  */

-#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16) | \

-                                      __SC300_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */

-

-#define __CORTEX_SC                 (300)                                     /*!< Cortex secure core             */

-

-

-#if   defined ( __CC_ARM )

-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */

-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */

-  #define __STATIC_INLINE  static __inline

-

-#elif defined ( __GNUC__ )

-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */

-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __ICCARM__ )

-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */

-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TMS470__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TASKING__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */

-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __CSMC__ )

-  #define __packed

-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */

-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */

-  #define __STATIC_INLINE  static inline

-

-#endif

-

-/** __FPU_USED indicates whether an FPU is used or not.

-    This core does not support an FPU at all

-*/

-#define __FPU_USED       0

-

-#if defined ( __CC_ARM )

-  #if defined __TARGET_FPU_VFP

-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __GNUC__ )

-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __ICCARM__ )

-  #if defined __ARMVFP__

-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __TMS470__ )

-  #if defined __TI__VFP_SUPPORT____

-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __TASKING__ )

-  #if defined __FPU_VFP__

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __CSMC__ )		/* Cosmic */

-  #if ( __CSMC__ & 0x400)		// FPU present for parser

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-#endif

-

-#include <stdint.h>                      /* standard types definitions                      */

-#include <core_cmInstr.h>                /* Core Instruction Access                         */

-#include <core_cmFunc.h>                 /* Core Function Access                            */

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_SC300_H_GENERIC */

-

-#ifndef __CMSIS_GENERIC

-

-#ifndef __CORE_SC300_H_DEPENDANT

-#define __CORE_SC300_H_DEPENDANT

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/* check device defines and use defaults */

-#if defined __CHECK_DEVICE_DEFINES

-  #ifndef __SC300_REV

-    #define __SC300_REV               0x0000

-    #warning "__SC300_REV not defined in device header file; using default!"

-  #endif

-

-  #ifndef __MPU_PRESENT

-    #define __MPU_PRESENT             0

-    #warning "__MPU_PRESENT not defined in device header file; using default!"

-  #endif

-

-  #ifndef __NVIC_PRIO_BITS

-    #define __NVIC_PRIO_BITS          4

-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"

-  #endif

-

-  #ifndef __Vendor_SysTickConfig

-    #define __Vendor_SysTickConfig    0

-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"

-  #endif

-#endif

-

-/* IO definitions (access restrictions to peripheral registers) */

-/**

-    \defgroup CMSIS_glob_defs CMSIS Global Defines

-

-    <strong>IO Type Qualifiers</strong> are used

-    \li to specify the access to peripheral variables.

-    \li for automatic generation of peripheral register debug information.

-*/

-#ifdef __cplusplus

-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */

-#else

-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */

-#endif

-#define     __O     volatile             /*!< Defines 'write only' permissions                */

-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */

-

-/*@} end of group SC300 */

-

-

-

-/*******************************************************************************

- *                 Register Abstraction

-  Core Register contain:

-  - Core Register

-  - Core NVIC Register

-  - Core SCB Register

-  - Core SysTick Register

-  - Core Debug Register

-  - Core MPU Register

- ******************************************************************************/

-/** \defgroup CMSIS_core_register Defines and Type Definitions

-    \brief Type definitions and defines for Cortex-M processor based devices.

-*/

-

-/** \ingroup    CMSIS_core_register

-    \defgroup   CMSIS_CORE  Status and Control Registers

-    \brief  Core Register type definitions.

-  @{

- */

-

-/** \brief  Union type to access the Application Program Status Register (APSR).

- */

-typedef union

-{

-  struct

-  {

-#if (__CORTEX_M != 0x04)

-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */

-#else

-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */

-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */

-#endif

-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} APSR_Type;

-

-

-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} IPSR_Type;

-

-

-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

-#if (__CORTEX_M != 0x04)

-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */

-#else

-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */

-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */

-#endif

-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */

-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */

-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} xPSR_Type;

-

-

-/** \brief  Union type to access the Control Registers (CONTROL).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */

-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */

-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */

-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */

-  } b;                                   /*!< Structure used for bit  access                  */

-  uint32_t w;                            /*!< Type      used for word access                  */

-} CONTROL_Type;

-

-/*@} end of group CMSIS_CORE */

-

-

-/** \ingroup    CMSIS_core_register

-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)

-    \brief      Type definitions for the NVIC Registers

-  @{

- */

-

-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).

- */

-typedef struct

-{

-  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */

-       uint32_t RESERVED0[24];

-  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */

-       uint32_t RSERVED1[24];

-  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */

-       uint32_t RESERVED2[24];

-  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */

-       uint32_t RESERVED3[24];

-  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */

-       uint32_t RESERVED4[56];

-  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */

-       uint32_t RESERVED5[644];

-  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */

-}  NVIC_Type;

-

-/* Software Triggered Interrupt Register Definitions */

-#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */

-#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */

-

-/*@} end of group CMSIS_NVIC */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_SCB     System Control Block (SCB)

-    \brief      Type definitions for the System Control Block Registers

-  @{

- */

-

-/** \brief  Structure type to access the System Control Block (SCB).

- */

-typedef struct

-{

-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */

-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */

-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */

-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */

-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */

-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */

-  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */

-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */

-  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */

-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */

-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */

-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */

-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */

-  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */

-  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */

-  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */

-  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */

-  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */

-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */

-       uint32_t RESERVED0[5];

-  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */

-} SCB_Type;

-

-/* SCB CPUID Register Definitions */

-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */

-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */

-

-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */

-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */

-

-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */

-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */

-

-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */

-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */

-

-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */

-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */

-

-/* SCB Interrupt Control State Register Definitions */

-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */

-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */

-

-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */

-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */

-

-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */

-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */

-

-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */

-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */

-

-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */

-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */

-

-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */

-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */

-

-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */

-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */

-

-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */

-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */

-

-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */

-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */

-

-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */

-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */

-

-/* SCB Vector Table Offset Register Definitions */

-#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */

-#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */

-

-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */

-#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */

-

-/* SCB Application Interrupt and Reset Control Register Definitions */

-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */

-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */

-

-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */

-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */

-

-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */

-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */

-

-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */

-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */

-

-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */

-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */

-

-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */

-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */

-

-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */

-#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */

-

-/* SCB System Control Register Definitions */

-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */

-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */

-

-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */

-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */

-

-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */

-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */

-

-/* SCB Configuration Control Register Definitions */

-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */

-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */

-

-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */

-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */

-

-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */

-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */

-

-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */

-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */

-

-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */

-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */

-

-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */

-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */

-

-/* SCB System Handler Control and State Register Definitions */

-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */

-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */

-

-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */

-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */

-

-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */

-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */

-

-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */

-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */

-

-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */

-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */

-

-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */

-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */

-

-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */

-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */

-

-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */

-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */

-

-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */

-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */

-

-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */

-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */

-

-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */

-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */

-

-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */

-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */

-

-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */

-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */

-

-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */

-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */

-

-/* SCB Configurable Fault Status Registers Definitions */

-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */

-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */

-

-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */

-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */

-

-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */

-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */

-

-/* SCB Hard Fault Status Registers Definitions */

-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */

-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */

-

-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */

-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */

-

-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */

-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */

-

-/* SCB Debug Fault Status Register Definitions */

-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */

-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */

-

-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */

-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */

-

-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */

-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */

-

-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */

-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */

-

-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */

-#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */

-

-/*@} end of group CMSIS_SCB */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)

-    \brief      Type definitions for the System Control and ID Register not in the SCB

-  @{

- */

-

-/** \brief  Structure type to access the System Control and ID Register not in the SCB.

- */

-typedef struct

-{

-       uint32_t RESERVED0[1];

-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */

-       uint32_t RESERVED1[1];

-} SCnSCB_Type;

-

-/* Interrupt Controller Type Register Definitions */

-#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */

-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */

-

-/*@} end of group CMSIS_SCnotSCB */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)

-    \brief      Type definitions for the System Timer Registers.

-  @{

- */

-

-/** \brief  Structure type to access the System Timer (SysTick).

- */

-typedef struct

-{

-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */

-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */

-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */

-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */

-} SysTick_Type;

-

-/* SysTick Control / Status Register Definitions */

-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */

-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */

-

-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */

-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */

-

-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */

-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */

-

-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */

-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */

-

-/* SysTick Reload Register Definitions */

-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */

-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */

-

-/* SysTick Current Register Definitions */

-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */

-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */

-

-/* SysTick Calibration Register Definitions */

-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */

-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */

-

-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */

-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */

-

-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */

-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */

-

-/*@} end of group CMSIS_SysTick */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)

-    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)

-  @{

- */

-

-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).

- */

-typedef struct

-{

-  __O  union

-  {

-    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */

-    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */

-    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */

-  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */

-       uint32_t RESERVED0[864];

-  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */

-       uint32_t RESERVED1[15];

-  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */

-       uint32_t RESERVED2[15];

-  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */

-       uint32_t RESERVED3[29];

-  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */

-  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */

-  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */

-       uint32_t RESERVED4[43];

-  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */

-  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */

-       uint32_t RESERVED5[6];

-  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */

-  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */

-  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */

-  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */

-  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */

-  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */

-  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */

-  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */

-  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */

-  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */

-  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */

-  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */

-} ITM_Type;

-

-/* ITM Trace Privilege Register Definitions */

-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */

-#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */

-

-/* ITM Trace Control Register Definitions */

-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */

-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */

-

-#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */

-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */

-

-#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */

-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */

-

-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */

-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */

-

-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */

-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */

-

-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */

-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */

-

-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */

-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */

-

-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */

-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */

-

-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */

-#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */

-

-/* ITM Integration Write Register Definitions */

-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */

-#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */

-

-/* ITM Integration Read Register Definitions */

-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */

-#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */

-

-/* ITM Integration Mode Control Register Definitions */

-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */

-#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */

-

-/* ITM Lock Status Register Definitions */

-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */

-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */

-

-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */

-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */

-

-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */

-#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */

-

-/*@}*/ /* end of group CMSIS_ITM */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)

-    \brief      Type definitions for the Data Watchpoint and Trace (DWT)

-  @{

- */

-

-/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).

- */

-typedef struct

-{

-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */

-  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */

-  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */

-  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */

-  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */

-  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */

-  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */

-  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */

-  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */

-  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */

-  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */

-       uint32_t RESERVED0[1];

-  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */

-  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */

-  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */

-       uint32_t RESERVED1[1];

-  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */

-  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */

-  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */

-       uint32_t RESERVED2[1];

-  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */

-  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */

-  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */

-} DWT_Type;

-

-/* DWT Control Register Definitions */

-#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */

-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */

-

-#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */

-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */

-

-#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */

-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */

-

-#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */

-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */

-

-#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */

-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */

-

-#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */

-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */

-

-#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */

-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */

-

-#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */

-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */

-

-#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */

-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */

-

-#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */

-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */

-

-#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */

-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */

-

-#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */

-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */

-

-#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */

-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */

-

-#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */

-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */

-

-#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */

-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */

-

-#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */

-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */

-

-#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */

-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */

-

-#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */

-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */

-

-/* DWT CPI Count Register Definitions */

-#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */

-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */

-

-/* DWT Exception Overhead Count Register Definitions */

-#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */

-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */

-

-/* DWT Sleep Count Register Definitions */

-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */

-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */

-

-/* DWT LSU Count Register Definitions */

-#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */

-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */

-

-/* DWT Folded-instruction Count Register Definitions */

-#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */

-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */

-

-/* DWT Comparator Mask Register Definitions */

-#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */

-#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */

-

-/* DWT Comparator Function Register Definitions */

-#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */

-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */

-

-#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */

-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */

-

-#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */

-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */

-

-#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */

-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */

-

-#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */

-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */

-

-#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */

-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */

-

-#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */

-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */

-

-#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */

-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */

-

-#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */

-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */

-

-/*@}*/ /* end of group CMSIS_DWT */

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_TPI     Trace Port Interface (TPI)

-    \brief      Type definitions for the Trace Port Interface (TPI)

-  @{

- */

-

-/** \brief  Structure type to access the Trace Port Interface Register (TPI).

- */

-typedef struct

-{

-  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */

-  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */

-       uint32_t RESERVED0[2];

-  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */

-       uint32_t RESERVED1[55];

-  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */

-       uint32_t RESERVED2[131];

-  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */

-  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */

-  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */

-       uint32_t RESERVED3[759];

-  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */

-  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */

-  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */

-       uint32_t RESERVED4[1];

-  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */

-  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */

-  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */

-       uint32_t RESERVED5[39];

-  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */

-  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */

-       uint32_t RESERVED7[8];

-  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */

-  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */

-} TPI_Type;

-

-/* TPI Asynchronous Clock Prescaler Register Definitions */

-#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */

-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */

-

-/* TPI Selected Pin Protocol Register Definitions */

-#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */

-#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */

-

-/* TPI Formatter and Flush Status Register Definitions */

-#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */

-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */

-

-#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */

-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */

-

-#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */

-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */

-

-#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */

-#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */

-

-/* TPI Formatter and Flush Control Register Definitions */

-#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */

-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */

-

-#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */

-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */

-

-/* TPI TRIGGER Register Definitions */

-#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */

-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */

-

-/* TPI Integration ETM Data Register Definitions (FIFO0) */

-#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */

-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */

-

-#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */

-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */

-

-#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */

-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */

-

-#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */

-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */

-

-#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */

-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */

-

-#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */

-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */

-

-#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */

-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */

-

-/* TPI ITATBCTR2 Register Definitions */

-#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */

-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */

-

-/* TPI Integration ITM Data Register Definitions (FIFO1) */

-#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */

-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */

-

-#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */

-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */

-

-#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */

-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */

-

-#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */

-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */

-

-#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */

-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */

-

-#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */

-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */

-

-#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */

-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */

-

-/* TPI ITATBCTR0 Register Definitions */

-#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */

-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */

-

-/* TPI Integration Mode Control Register Definitions */

-#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */

-#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */

-

-/* TPI DEVID Register Definitions */

-#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */

-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */

-

-#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */

-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */

-

-#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */

-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */

-

-#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */

-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */

-

-#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */

-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */

-

-#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */

-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */

-

-/* TPI DEVTYPE Register Definitions */

-#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */

-#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */

-

-#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */

-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */

-

-/*@}*/ /* end of group CMSIS_TPI */

-

-

-#if (__MPU_PRESENT == 1)

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)

-    \brief      Type definitions for the Memory Protection Unit (MPU)

-  @{

- */

-

-/** \brief  Structure type to access the Memory Protection Unit (MPU).

- */

-typedef struct

-{

-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */

-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */

-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */

-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */

-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */

-  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */

-  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */

-  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */

-  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */

-  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */

-  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */

-} MPU_Type;

-

-/* MPU Type Register */

-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */

-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */

-

-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */

-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */

-

-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */

-#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */

-

-/* MPU Control Register */

-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */

-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */

-

-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */

-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */

-

-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */

-#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */

-

-/* MPU Region Number Register */

-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */

-#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */

-

-/* MPU Region Base Address Register */

-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */

-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */

-

-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */

-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */

-

-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */

-#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */

-

-/* MPU Region Attribute and Size Register */

-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */

-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */

-

-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */

-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */

-

-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */

-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */

-

-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */

-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */

-

-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */

-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */

-

-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */

-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */

-

-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */

-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */

-

-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */

-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */

-

-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */

-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */

-

-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */

-#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */

-

-/*@} end of group CMSIS_MPU */

-#endif

-

-

-/** \ingroup  CMSIS_core_register

-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)

-    \brief      Type definitions for the Core Debug Registers

-  @{

- */

-

-/** \brief  Structure type to access the Core Debug Register (CoreDebug).

- */

-typedef struct

-{

-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */

-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */

-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */

-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */

-} CoreDebug_Type;

-

-/* Debug Halting Control and Status Register */

-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */

-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */

-

-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */

-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */

-

-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */

-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */

-

-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */

-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */

-

-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */

-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */

-

-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */

-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */

-

-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */

-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */

-

-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */

-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */

-

-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */

-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */

-

-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */

-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */

-

-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */

-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */

-

-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */

-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */

-

-/* Debug Core Register Selector Register */

-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */

-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */

-

-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */

-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */

-

-/* Debug Exception and Monitor Control Register */

-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */

-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */

-

-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */

-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */

-

-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */

-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */

-

-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */

-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */

-

-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */

-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */

-

-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */

-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */

-

-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */

-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */

-

-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */

-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */

-

-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */

-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */

-

-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */

-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */

-

-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */

-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */

-

-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */

-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */

-

-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */

-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */

-

-/*@} end of group CMSIS_CoreDebug */

-

-

-/** \ingroup    CMSIS_core_register

-    \defgroup   CMSIS_core_base     Core Definitions

-    \brief      Definitions for base addresses, unions, and structures.

-  @{

- */

-

-/* Memory mapping of Cortex-M3 Hardware */

-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */

-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */

-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */

-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */

-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */

-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */

-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */

-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */

-

-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */

-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */

-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */

-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */

-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */

-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */

-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */

-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */

-

-#if (__MPU_PRESENT == 1)

-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */

-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */

-#endif

-

-/*@} */

-

-

-

-/*******************************************************************************

- *                Hardware Abstraction Layer

-  Core Function Interface contains:

-  - Core NVIC Functions

-  - Core SysTick Functions

-  - Core Debug Functions

-  - Core Register Access Functions

- ******************************************************************************/

-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference

-*/

-

-

-

-/* ##########################   NVIC functions  #################################### */

-/** \ingroup  CMSIS_Core_FunctionInterface

-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions

-    \brief      Functions that manage interrupts and exceptions via the NVIC.

-    @{

- */

-

-/** \brief  Set Priority Grouping

-

-  The function sets the priority grouping field using the required unlock sequence.

-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.

-  Only values from 0..7 are used.

-  In case of a conflict between priority grouping and available

-  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

-

-    \param [in]      PriorityGroup  Priority grouping field.

- */

-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)

-{

-  uint32_t reg_value;

-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */

-

-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */

-  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */

-  reg_value  =  (reg_value                                 |

-                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |

-                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */

-  SCB->AIRCR =  reg_value;

-}

-

-

-/** \brief  Get Priority Grouping

-

-  The function reads the priority grouping field from the NVIC Interrupt Controller.

-

-    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).

- */

-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)

-{

-  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */

-}

-

-

-/** \brief  Enable External Interrupt

-

-    The function enables a device-specific interrupt in the NVIC interrupt controller.

-

-    \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)

-{

-  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */

-}

-

-

-/** \brief  Disable External Interrupt

-

-    The function disables a device-specific interrupt in the NVIC interrupt controller.

-

-    \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */

-}

-

-

-/** \brief  Get Pending Interrupt

-

-    The function reads the pending register in the NVIC and returns the pending bit

-    for the specified interrupt.

-

-    \param [in]      IRQn  Interrupt number.

-

-    \return             0  Interrupt status is not pending.

-    \return             1  Interrupt status is pending.

- */

-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)

-{

-  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */

-}

-

-

-/** \brief  Set Pending Interrupt

-

-    The function sets the pending bit of an external interrupt.

-

-    \param [in]      IRQn  Interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */

-}

-

-

-/** \brief  Clear Pending Interrupt

-

-    The function clears the pending bit of an external interrupt.

-

-    \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */

-}

-

-

-/** \brief  Get Active Interrupt

-

-    The function reads the active register in NVIC and returns the active bit.

-

-    \param [in]      IRQn  Interrupt number.

-

-    \return             0  Interrupt status is not active.

-    \return             1  Interrupt status is active.

- */

-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)

-{

-  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */

-}

-

-

-/** \brief  Set Interrupt Priority

-

-    The function sets the priority of an interrupt.

-

-    \note The priority cannot be set for every core interrupt.

-

-    \param [in]      IRQn  Interrupt number.

-    \param [in]  priority  Priority to set.

- */

-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

-{

-  if(IRQn < 0) {

-    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */

-  else {

-    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */

-}

-

-

-/** \brief  Get Interrupt Priority

-

-    The function reads the priority of an interrupt. The interrupt

-    number can be positive to specify an external (device specific)

-    interrupt, or negative to specify an internal (core) interrupt.

-

-

-    \param [in]   IRQn  Interrupt number.

-    \return             Interrupt Priority. Value is aligned automatically to the implemented

-                        priority bits of the microcontroller.

- */

-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)

-{

-

-  if(IRQn < 0) {

-    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */

-  else {

-    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */

-}

-

-

-/** \brief  Encode Priority

-

-    The function encodes the priority for an interrupt with the given priority group,

-    preemptive priority value, and subpriority value.

-    In case of a conflict between priority grouping and available

-    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

-

-    \param [in]     PriorityGroup  Used priority group.

-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).

-    \param [in]       SubPriority  Subpriority value (starting from 0).

-    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().

- */

-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)

-{

-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */

-  uint32_t PreemptPriorityBits;

-  uint32_t SubPriorityBits;

-

-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;

-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;

-

-  return (

-           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |

-           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))

-         );

-}

-

-

-/** \brief  Decode Priority

-

-    The function decodes an interrupt priority value with a given priority group to

-    preemptive priority value and subpriority value.

-    In case of a conflict between priority grouping and available

-    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.

-

-    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().

-    \param [in]     PriorityGroup  Used priority group.

-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).

-    \param [out]     pSubPriority  Subpriority value (starting from 0).

- */

-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)

-{

-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */

-  uint32_t PreemptPriorityBits;

-  uint32_t SubPriorityBits;

-

-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;

-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;

-

-  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);

-  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);

-}

-

-

-/** \brief  System Reset

-

-    The function initiates a system reset request to reset the MCU.

- */

-__STATIC_INLINE void NVIC_SystemReset(void)

-{

-  __DSB();                                                     /* Ensure all outstanding memory accesses included

-                                                                  buffered write are completed before reset */

-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |

-                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |

-                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */

-  __DSB();                                                     /* Ensure completion of memory access */

-  while(1);                                                    /* wait until reset */

-}

-

-/*@} end of CMSIS_Core_NVICFunctions */

-

-

-

-/* ##################################    SysTick function  ############################################ */

-/** \ingroup  CMSIS_Core_FunctionInterface

-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions

-    \brief      Functions that configure the System.

-  @{

- */

-

-#if (__Vendor_SysTickConfig == 0)

-

-/** \brief  System Tick Configuration

-

-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.

-    Counter is in free running mode to generate periodic interrupts.

-

-    \param [in]  ticks  Number of ticks between two interrupts.

-

-    \return          0  Function succeeded.

-    \return          1  Function failed.

-

-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the

-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>

-    must contain a vendor-specific implementation of this function.

-

- */

-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

-{

-  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */

-

-  SysTick->LOAD  = ticks - 1;                                  /* set reload register */

-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */

-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */

-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |

-                   SysTick_CTRL_TICKINT_Msk   |

-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */

-  return (0);                                                  /* Function successful */

-}

-

-#endif

-

-/*@} end of CMSIS_Core_SysTickFunctions */

-

-

-

-/* ##################################### Debug In/Output function ########################################### */

-/** \ingroup  CMSIS_Core_FunctionInterface

-    \defgroup CMSIS_core_DebugFunctions ITM Functions

-    \brief   Functions that access the ITM debug interface.

-  @{

- */

-

-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */

-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */

-

-

-/** \brief  ITM Send Character

-

-    The function transmits a character via the ITM channel 0, and

-    \li Just returns when no debugger is connected that has booked the output.

-    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.

-

-    \param [in]     ch  Character to transmit.

-

-    \returns            Character to transmit.

- */

-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)

-{

-  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */

-      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */

-  {

-    while (ITM->PORT[0].u32 == 0);

-    ITM->PORT[0].u8 = (uint8_t) ch;

-  }

-  return (ch);

-}

-

-

-/** \brief  ITM Receive Character

-

-    The function inputs a character via the external variable \ref ITM_RxBuffer.

-

-    \return             Received character.

-    \return         -1  No character pending.

- */

-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {

-  int32_t ch = -1;                           /* no character available */

-

-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {

-    ch = ITM_RxBuffer;

-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */

-  }

-

-  return (ch);

-}

-

-

-/** \brief  ITM Check Character

-

-    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.

-

-    \return          0  No character available.

-    \return          1  Character available.

- */

-__STATIC_INLINE int32_t ITM_CheckChar (void) {

-

-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {

-    return (0);                                 /* no character available */

-  } else {

-    return (1);                                 /*    character available */

-  }

-}

-

-/*@} end of CMSIS_core_DebugFunctions */

-

-

-

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_SC300_H_DEPENDANT */

-

-#endif /* __CMSIS_GENERIC */

+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC3000
+  @{
+ */
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC300_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
+
+#define __CORTEX_SC                 (300)                                     /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC300_REV
+    #define __SC300_REV               0x0000
+    #warning "__SC300_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+       uint32_t RESERVED1[1];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/firmware/inc/cpu/cortexm4f/cpuMath.h b/firmware/os/cpu/cortexm4/inc/cpu/cpuMath.h
index 70fb98a0..70fb98a0 100644
--- a/firmware/inc/cpu/cortexm4f/cpuMath.h
+++ b/firmware/os/cpu/cortexm4/inc/cpu/cpuMath.h
diff --git a/firmware/inc/cpu/cortexm4f/nanohub_math.h b/firmware/os/cpu/cortexm4/inc/cpu/nanohub_math.h
index 320154fb..f00ec91e 100644
--- a/firmware/inc/cpu/cortexm4f/nanohub_math.h
+++ b/firmware/os/cpu/cortexm4/inc/cpu/nanohub_math.h
@@ -17,6 +17,7 @@
 #ifndef _CPU_NANOHUB_MATH_H_
 #define _CPU_NANOHUB_MATH_H_
 
+#include <cpu/cmsis/arm_math.h>
 
 #define asinf  arm_asinf
 #define sinf   arm_sin_f32
diff --git a/firmware/inc/cpu/cortexm4f/pendsv.h b/firmware/os/cpu/cortexm4/inc/cpu/pendsv.h
index 4020a9fa..4020a9fa 100644
--- a/firmware/inc/cpu/cortexm4f/pendsv.h
+++ b/firmware/os/cpu/cortexm4/inc/cpu/pendsv.h
diff --git a/firmware/inc/cpu/cortexm4f/syscallDo.h b/firmware/os/cpu/cortexm4/inc/cpu/syscallDo.h
index 45cfdbab..45cfdbab 100644
--- a/firmware/inc/cpu/cortexm4f/syscallDo.h
+++ b/firmware/os/cpu/cortexm4/inc/cpu/syscallDo.h
diff --git a/firmware/src/cpu/cortexm4f/pendsv.c b/firmware/os/cpu/cortexm4/pendsv.c
index 1112de49..ef37c10a 100644
--- a/firmware/src/cpu/cortexm4f/pendsv.c
+++ b/firmware/os/cpu/cortexm4/pendsv.c
@@ -14,8 +14,8 @@
  * limitations under the License.
  */
 
-#include <plat/inc/cmsis.h>
-#include <cpu/inc/pendsv.h>
+#include <plat/cmsis.h>
+#include <cpu/pendsv.h>
 #include <stdio.h>
 
 
diff --git a/firmware/os/cpu/x86/Android.mk b/firmware/os/cpu/x86/Android.mk
new file mode 100644
index 00000000..6a9476b9
--- /dev/null
+++ b/firmware/os/cpu/x86/Android.mk
@@ -0,0 +1,33 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_PATH := $(call my-dir)
+
+########################################################
+# COMMON OS & BL defs
+########################################################
+
+include $(CLEAR_NANO_VARS)
+
+LOCAL_MODULE := libnanohub_os_x86
+LOCAL_AUX_CPU := x86
+
+LOCAL_SRC_FILES := \
+    atomic.c \
+    atomicBitset.c \
+    cpu.c \
+
+include $(BUILD_NANOHUB_OS_STATIC_LIBRARY)
diff --git a/firmware/src/cpu/x86/atomic.c b/firmware/os/cpu/x86/atomic.c
index 20cd2489..20cd2489 100644
--- a/firmware/src/cpu/x86/atomic.c
+++ b/firmware/os/cpu/x86/atomic.c
diff --git a/firmware/src/cpu/x86/atomicBitset.c b/firmware/os/cpu/x86/atomicBitset.c
index 98f25360..98f25360 100644
--- a/firmware/src/cpu/x86/atomicBitset.c
+++ b/firmware/os/cpu/x86/atomicBitset.c
diff --git a/firmware/src/cpu/x86/cpu.c b/firmware/os/cpu/x86/cpu.c
index af74873e..af74873e 100644
--- a/firmware/src/cpu/x86/cpu.c
+++ b/firmware/os/cpu/x86/cpu.c
diff --git a/firmware/inc/cpu/x86/atomicBitset.h b/firmware/os/cpu/x86/inc/cpu/atomicBitset.h
index d9d3d1d9..d9d3d1d9 100644
--- a/firmware/inc/cpu/x86/atomicBitset.h
+++ b/firmware/os/cpu/x86/inc/cpu/atomicBitset.h
diff --git a/firmware/inc/cpu/x86/barrier.h b/firmware/os/cpu/x86/inc/cpu/barrier.h
index 7411bf87..7411bf87 100644
--- a/firmware/inc/cpu/x86/barrier.h
+++ b/firmware/os/cpu/x86/inc/cpu/barrier.h
diff --git a/firmware/os/cpu/x86/inc/cpu/nanohub_math.h b/firmware/os/cpu/x86/inc/cpu/nanohub_math.h
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/firmware/os/cpu/x86/inc/cpu/nanohub_math.h
diff --git a/firmware/misc/cpu/x86/Makefile b/firmware/os/cpu/x86/x86.mk
index dcc9295c..352e91c3 100644
--- a/firmware/misc/cpu/x86/Makefile
+++ b/firmware/os/cpu/x86/x86.mk
@@ -20,9 +20,12 @@ OBJCOPY = objcopy
 FLAGS += -march=core2 -msse2 -DSYSCALL_VARARGS_PARAMS_PASSED_AS_PTRS
 
 #cpu runtime
-SRCS += src/cpu/$(CPU)/atomicBitset.c src/cpu/$(CPU)/cpu.c src/cpu/$(CPU)/atomic.c
+SRCS += \
+    os/cpu/$(CPU)/atomicBitset.c \
+    os/cpu/$(CPU)/cpu.c \
+    os/cpu/$(CPU)/atomic.c \
 
 #extra deps
-DEPS += $(wildcard inc/cpu/$(CPU)/*.h)
-
+DEPS += $(wildcard os/cpu/$(CPU)/inc/cpu/*.h)
 
+$(info Included x86 CPU)
diff --git a/firmware/src/drivers/ams_tmd2772/ams_tmd2772.c b/firmware/os/drivers/ams_tmd2772/ams_tmd2772.c
index ddd1270a..f075fd19 100644
--- a/firmware/src/drivers/ams_tmd2772/ams_tmd2772.c
+++ b/firmware/os/drivers/ams_tmd2772/ams_tmd2772.c
@@ -740,4 +740,4 @@ static void handle_event(uint32_t evtType, const void* evtData)
     }
 }
 
-INTERNAL_APP_INIT(APP_ID_MAKE(APP_ID_VENDOR_GOOGLE, 9), AMS_TMD2772_APP_VERSION, init_app, end_app, handle_event);
+INTERNAL_APP_INIT(APP_ID_MAKE(NANOHUB_VENDOR_GOOGLE, 9), AMS_TMD2772_APP_VERSION, init_app, end_app, handle_event);
diff --git a/firmware/src/drivers/ams_tmd4903/ams_tmd4903.c b/firmware/os/drivers/ams_tmd4903/ams_tmd4903.c
index a35ee985..133f2821 100644
--- a/firmware/src/drivers/ams_tmd4903/ams_tmd4903.c
+++ b/firmware/os/drivers/ams_tmd4903/ams_tmd4903.c
@@ -30,12 +30,12 @@
 #include <sensors.h>
 #include <seos.h>
 
-#include <plat/inc/exti.h>
-#include <plat/inc/gpio.h>
-#include <plat/inc/syscfg.h>
-#include <variant/inc/variant.h>
+#include <plat/exti.h>
+#include <plat/gpio.h>
+#include <plat/syscfg.h>
+#include <variant/variant.h>
 
-#define AMS_TMD4903_APP_ID      APP_ID_MAKE(APP_ID_VENDOR_GOOGLE, 12)
+#define AMS_TMD4903_APP_ID      APP_ID_MAKE(NANOHUB_VENDOR_GOOGLE, 12)
 #define AMS_TMD4903_APP_VERSION 14
 
 #ifndef PROX_INT_PIN
diff --git a/firmware/src/drivers/bosch_bmi160/akm_ak09915_slave.c b/firmware/os/drivers/bosch_bmi160/akm_ak09915_slave.c
index 371f997b..371f997b 100644
--- a/firmware/src/drivers/bosch_bmi160/akm_ak09915_slave.c
+++ b/firmware/os/drivers/bosch_bmi160/akm_ak09915_slave.c
diff --git a/firmware/src/drivers/bosch_bmi160/akm_ak09915_slave.h b/firmware/os/drivers/bosch_bmi160/akm_ak09915_slave.h
index d7bb12e9..d7bb12e9 100644
--- a/firmware/src/drivers/bosch_bmi160/akm_ak09915_slave.h
+++ b/firmware/os/drivers/bosch_bmi160/akm_ak09915_slave.h
diff --git a/firmware/src/drivers/bosch_bmi160/bosch_bmi160.c b/firmware/os/drivers/bosch_bmi160/bosch_bmi160.c
index 1d4dab1e..672ddb95 100644
--- a/firmware/src/drivers/bosch_bmi160/bosch_bmi160.c
+++ b/firmware/os/drivers/bosch_bmi160/bosch_bmi160.c
@@ -16,25 +16,25 @@
 
 #include <algos/time_sync.h>
 #include <atomic.h>
-#include <cpu/inc/cpuMath.h>
+#include <cpu/cpuMath.h>
 #include <gpio.h>
 #include <heap.h>
 #include <hostIntf.h>
 #include <isr.h>
 #include <nanohub_math.h>
 #include <nanohubPacket.h>
-#include <plat/inc/exti.h>
-#include <plat/inc/gpio.h>
-#include <plat/inc/syscfg.h>
-#include <plat/inc/rtc.h>
 #include <printf.h>
+#include <plat/exti.h>
+#include <plat/gpio.h>
+#include <plat/syscfg.h>
+#include <plat/rtc.h>
 #include <sensors.h>
 #include <seos.h>
 #include <slab.h>
 #include <spi.h>
 #include <timer.h>
-#include <variant/inc/sensType.h>
-#include <variant/inc/variant.h>
+#include <variant/sensType.h>
+#include <variant/variant.h>
 
 #ifdef MAG_SLAVE_PRESENT
 #include <algos/mag_cal.h>
@@ -90,7 +90,7 @@
 #include "akm_ak09915_slave.h"
 #endif
 
-#define BMI160_APP_ID APP_ID_MAKE(APP_ID_VENDOR_GOOGLE, 2)
+#define BMI160_APP_ID APP_ID_MAKE(NANOHUB_VENDOR_GOOGLE, 2)
 
 #define BMI160_SPI_WRITE          0x00
 #define BMI160_SPI_READ           0x80
diff --git a/firmware/src/drivers/bosch_bmi160/bosch_bmm150_slave.c b/firmware/os/drivers/bosch_bmi160/bosch_bmm150_slave.c
index 4a223fbd..4a223fbd 100644
--- a/firmware/src/drivers/bosch_bmi160/bosch_bmm150_slave.c
+++ b/firmware/os/drivers/bosch_bmi160/bosch_bmm150_slave.c
diff --git a/firmware/src/drivers/bosch_bmi160/bosch_bmm150_slave.h b/firmware/os/drivers/bosch_bmi160/bosch_bmm150_slave.h
index 59e53fba..59e53fba 100644
--- a/firmware/src/drivers/bosch_bmi160/bosch_bmm150_slave.h
+++ b/firmware/os/drivers/bosch_bmi160/bosch_bmm150_slave.h
diff --git a/firmware/src/drivers/bosch_bmp280/bosch_bmp280.c b/firmware/os/drivers/bosch_bmp280/bosch_bmp280.c
index 727c85e7..5982c0c0 100644
--- a/firmware/src/drivers/bosch_bmp280/bosch_bmp280.c
+++ b/firmware/os/drivers/bosch_bmp280/bosch_bmp280.c
@@ -25,12 +25,13 @@
 #include <nanohubPacket.h>
 #include <sensors.h>
 #include <seos.h>
+#include <slab.h>
 #include <timer.h>
 #include <util.h>
 
-#define BMP280_APP_ID APP_ID_MAKE(APP_ID_VENDOR_GOOGLE, 5)
+#define BMP280_APP_ID APP_ID_MAKE(NANOHUB_VENDOR_GOOGLE, 5)
 
-#define BMP280_APP_VERSION 2
+#define BMP280_APP_VERSION 3
 
 #define I2C_BUS_ID                      0
 #define I2C_SPEED                       400000
@@ -48,6 +49,10 @@
 #define BOSCH_BMP280_MAX_PENDING_I2C_REQUESTS   4
 #define BOSCH_BMP280_MAX_I2C_TRANSFER_SIZE      6
 
+// This defines how many baro events we could handle being backed up in the
+// queue. Use this to size our slab
+#define MAX_BARO_EVENTS  4
+
 // temp: 2x oversampling, baro: 16x oversampling, power: normal
 #define CTRL_ON    ((2 << 5) | (5 << 2) | 3)
 // temp: 2x oversampling, baro: 16x oversampling, power: sleep
@@ -97,6 +102,8 @@ static struct BMP280Task
 {
     struct BMP280CompParams comp;
 
+    struct SlabAllocator *evtSlab;
+
     uint32_t id;
     uint32_t baroHandle;
     uint32_t tempHandle;
@@ -192,6 +199,31 @@ static bool writeRegister(uint8_t reg, uint8_t value, uint8_t state)
     return (ret == 0);
 }
 
+static bool baroAllocateEvt(struct SingleAxisDataEvent **evPtr, float sample, uint64_t time)
+{
+    struct SingleAxisDataEvent *ev;
+
+    *evPtr = slabAllocatorAlloc(mTask.evtSlab);
+
+    ev = *evPtr;
+    if (!ev) {
+        osLog(LOG_ERROR, "[BMP280] slabAllocatorAlloc() failed\n");
+        return false;
+    }
+
+    memset(&ev->samples[0].firstSample, 0x00, sizeof(struct SensorFirstSample));
+    ev->referenceTime = time;
+    ev->samples[0].firstSample.numSamples = 1;
+    ev->samples[0].fdata = sample;
+
+    return true;
+}
+
+static void baroFreeEvt(void *ptr)
+{
+    slabAllocatorFree(mTask.evtSlab, ptr);
+}
+
 /* sensor callbacks from nanohub */
 
 static void i2cCallback(void *cookie, size_t tx, size_t rx, int err)
@@ -352,7 +384,7 @@ static const struct SensorInfo sensorInfoBaro =
     .sensorName = "Pressure",
     .supportedRates = baroSupportedRates,
     .sensorType = SENS_TYPE_BARO,
-    .numAxis = NUM_AXIS_EMBEDDED,
+    .numAxis = NUM_AXIS_ONE,
     .interrupt = NANOHUB_INT_NONWAKEUP,
     .minSamples = 300
 };
@@ -433,7 +465,9 @@ static void getTempAndBaro(const uint8_t *tmp, float *pressure_Pa, float *temp_c
 
 static void handleI2cEvent(struct I2cTransfer *xfer)
 {
-    union EmbeddedDataPoint sample;
+    union EmbeddedDataPoint embeddedSample;
+    struct SingleAxisDataEvent *baroSample;
+
     struct I2cTransfer *newXfer;
 
     switch (xfer->state) {
@@ -515,14 +549,17 @@ static void handleI2cEvent(struct I2cTransfer *xfer)
 
                     writeRegister(BOSCH_BMP280_REG_CTRL_MEAS, CTRL_SLEEP, STATE_IDLE);
                 } else {
-                    sample.fdata = pressure_Pa * 0.01f;
-                    osEnqueueEvt(sensorGetMyEventType(SENS_TYPE_BARO), sample.vptr, NULL);
+                    if (baroAllocateEvt(&baroSample, pressure_Pa * 0.01f, sensorGetTime())) {
+                        if (!osEnqueueEvtOrFree(EVENT_TYPE_BIT_DISCARDABLE | sensorGetMyEventType(SENS_TYPE_BARO), baroSample, baroFreeEvt)) {
+                            osLog(LOG_ERROR, "[BMP280] failed to enqueue baro sample\n");
+                        }
+                    }
                 }
             }
 
             if (mTask.tempOn && mTask.tempReading) {
-                sample.fdata = temp_centigrade;
-                osEnqueueEvt(sensorGetMyEventType(SENS_TYPE_TEMP), sample.vptr, NULL);
+                embeddedSample.fdata = temp_centigrade;
+                osEnqueueEvt(sensorGetMyEventType(SENS_TYPE_TEMP), embeddedSample.vptr, NULL);
             }
 
             mTask.baroReading = false;
@@ -600,6 +637,12 @@ static bool startTask(uint32_t taskId)
     mTask.baroHandle = sensorRegister(&sensorInfoBaro, &sensorOpsBaro, NULL, false);
     mTask.tempHandle = sensorRegister(&sensorInfoTemp, &sensorOpsTemp, NULL, false);
 
+    mTask.evtSlab = slabAllocatorNew(sizeof(struct SingleAxisDataEvent) + sizeof(struct SingleAxisDataPoint), 4, MAX_BARO_EVENTS);
+    if (!mTask.evtSlab) {
+        osLog(LOG_ERROR, "[BMP280] slabAllocatorNew() failed\n");
+        return false;
+    }
+
     osEventSubscribe(taskId, EVT_APP_START);
 
     return true;
@@ -607,7 +650,7 @@ static bool startTask(uint32_t taskId)
 
 static void endTask(void)
 {
-
+    slabAllocatorDestroy(mTask.evtSlab);
 }
 
 INTERNAL_APP_INIT(BMP280_APP_ID, BMP280_APP_VERSION, startTask, endTask, handleEvent);
diff --git a/firmware/src/drivers/hall/hall.c b/firmware/os/drivers/hall/hall.c
index 01e8c8a2..ef083e34 100644
--- a/firmware/src/drivers/hall/hall.c
+++ b/firmware/os/drivers/hall/hall.c
@@ -27,10 +27,10 @@
 #include <sensors.h>
 #include <seos.h>
 #include <timer.h>
-#include <plat/inc/gpio.h>
-#include <plat/inc/exti.h>
-#include <plat/inc/syscfg.h>
-#include <variant/inc/variant.h>
+#include <plat/gpio.h>
+#include <plat/exti.h>
+#include <plat/syscfg.h>
+#include <variant/variant.h>
 
 #define APP_VERSION 2
 
@@ -224,4 +224,4 @@ static void endTask(void)
     sensorUnregister(mTask.sensorHandle);
 }
 
-INTERNAL_APP_INIT(APP_ID_MAKE(APP_ID_VENDOR_GOOGLE, 6), APP_VERSION, startTask, endTask, handleEvent);
+INTERNAL_APP_INIT(APP_ID_MAKE(NANOHUB_VENDOR_GOOGLE, 6), APP_VERSION, startTask, endTask, handleEvent);
diff --git a/firmware/src/drivers/hall_twopole/hall_twopole.c b/firmware/os/drivers/hall_twopole/hall_twopole.c
index 11c77e53..b2c42c1b 100644
--- a/firmware/src/drivers/hall_twopole/hall_twopole.c
+++ b/firmware/os/drivers/hall_twopole/hall_twopole.c
@@ -27,12 +27,12 @@
 #include <sensors.h>
 #include <seos.h>
 #include <timer.h>
-#include <plat/inc/gpio.h>
-#include <plat/inc/exti.h>
-#include <plat/inc/syscfg.h>
-#include <variant/inc/variant.h>
+#include <plat/gpio.h>
+#include <plat/exti.h>
+#include <plat/syscfg.h>
+#include <variant/variant.h>
 
-#define APP_ID      APP_ID_MAKE(APP_ID_VENDOR_GOOGLE, 11)
+#define APP_ID      APP_ID_MAKE(NANOHUB_VENDOR_GOOGLE, 11)
 #define APP_VERSION 2
 
 #define HALL_REPORT_OPENED_VALUE  0
diff --git a/firmware/src/drivers/orientation/orientation.c b/firmware/os/drivers/orientation/orientation.c
index c9bd5e2e..9643e8e7 100644
--- a/firmware/src/drivers/orientation/orientation.c
+++ b/firmware/os/drivers/orientation/orientation.c
@@ -18,8 +18,8 @@
 #include <string.h>
 #include <timer.h>
 #include <heap.h>
-#include <plat/inc/rtc.h>
-#include <plat/inc/syscfg.h>
+#include <plat/rtc.h>
+#include <plat/syscfg.h>
 #include <hostIntf.h>
 #include <nanohubPacket.h>
 #include <floatRt.h>
@@ -29,7 +29,7 @@
 #include <nanohub_math.h>
 #include <algos/fusion.h>
 #include <sensors.h>
-#include <variant/inc/sensType.h>
+#include <variant/sensType.h>
 #include <limits.h>
 #include <slab.h>
 
@@ -837,7 +837,7 @@ static void fusionEnd()
 }
 
 INTERNAL_APP_INIT(
-        APP_ID_MAKE(APP_ID_VENDOR_GOOGLE, 4),
+        APP_ID_MAKE(NANOHUB_VENDOR_GOOGLE, 4),
         ORIENTATION_APP_VERSION,
         fusionStart,
         fusionEnd,
diff --git a/firmware/src/drivers/rohm_rpr0521/rohm_rpr0521.c b/firmware/os/drivers/rohm_rpr0521/rohm_rpr0521.c
index 4e8d9d70..55ca4a9f 100644
--- a/firmware/src/drivers/rohm_rpr0521/rohm_rpr0521.c
+++ b/firmware/os/drivers/rohm_rpr0521/rohm_rpr0521.c
@@ -30,10 +30,10 @@
 #include <sensors.h>
 #include <seos.h>
 
-#include <plat/inc/exti.h>
-#include <plat/inc/gpio.h>
-#include <plat/inc/syscfg.h>
-#include <variant/inc/variant.h>
+#include <plat/exti.h>
+#include <plat/gpio.h>
+#include <plat/syscfg.h>
+#include <variant/variant.h>
 
 #ifndef PROX_INT_PIN
 #error "PROX_INT_PIN is not defined; please define in variant.h"
@@ -779,4 +779,4 @@ static void handle_event(uint32_t evtType, const void* evtData)
     }
 }
 
-INTERNAL_APP_INIT(APP_ID_MAKE(APP_ID_VENDOR_GOOGLE, 10), RPR0521_APP_VERSION, init_app, end_app, handle_event);
+INTERNAL_APP_INIT(APP_ID_MAKE(NANOHUB_VENDOR_GOOGLE, 10), RPR0521_APP_VERSION, init_app, end_app, handle_event);
diff --git a/firmware/src/drivers/synaptics_s3708/synaptics_s3708.c b/firmware/os/drivers/synaptics_s3708/synaptics_s3708.c
index 1706a660..30054b2b 100644
--- a/firmware/src/drivers/synaptics_s3708/synaptics_s3708.c
+++ b/firmware/os/drivers/synaptics_s3708/synaptics_s3708.c
@@ -31,14 +31,14 @@
 #include <timer.h>
 #include <util.h>
 
-#include <cpu/inc/cpuMath.h>
+#include <cpu/cpuMath.h>
 
-#include <plat/inc/exti.h>
-#include <plat/inc/gpio.h>
-#include <plat/inc/syscfg.h>
+#include <plat/exti.h>
+#include <plat/gpio.h>
+#include <plat/syscfg.h>
 
-#define S3708_APP_ID                APP_ID_MAKE(APP_ID_VENDOR_GOOGLE, 13)
-#define S3708_APP_VERSION           2
+#define S3708_APP_ID                APP_ID_MAKE(NANOHUB_VENDOR_GOOGLE, 13)
+#define S3708_APP_VERSION           1
 
 #define I2C_BUS_ID                  0
 #define I2C_SPEED                   400000
diff --git a/firmware/src/drivers/tilt_detection/tilt_detection.c b/firmware/os/drivers/tilt_detection/tilt_detection.c
index c21d5b05..2e90bd9e 100644
--- a/firmware/src/drivers/tilt_detection/tilt_detection.c
+++ b/firmware/os/drivers/tilt_detection/tilt_detection.c
@@ -18,8 +18,8 @@
 #include <string.h>
 #include <timer.h>
 #include <heap.h>
-#include <plat/inc/rtc.h>
-#include <plat/inc/syscfg.h>
+#include <plat/rtc.h>
+#include <plat/syscfg.h>
 #include <hostIntf.h>
 #include <nanohubPacket.h>
 
@@ -289,7 +289,7 @@ static void tiltDetectionEnd()
 }
 
 INTERNAL_APP_INIT(
-        APP_ID_MAKE(APP_ID_VENDOR_GOOGLE, 8),
+        APP_ID_MAKE(NANOHUB_VENDOR_GOOGLE, 8),
         TILT_APP_VERSION,
         tiltDetectionStart,
         tiltDetectionEnd,
diff --git a/firmware/src/drivers/vsync/vsync.c b/firmware/os/drivers/vsync/vsync.c
index 2aba968b..1a250fc0 100644
--- a/firmware/src/drivers/vsync/vsync.c
+++ b/firmware/os/drivers/vsync/vsync.c
@@ -28,12 +28,12 @@
 #include <seos.h>
 #include <slab.h>
 #include <timer.h>
-#include <plat/inc/gpio.h>
-#include <plat/inc/exti.h>
-#include <plat/inc/syscfg.h>
-#include <variant/inc/variant.h>
+#include <plat/gpio.h>
+#include <plat/exti.h>
+#include <plat/syscfg.h>
+#include <variant/variant.h>
 
-#define VSYNC_APP_ID      APP_ID_MAKE(APP_ID_VENDOR_GOOGLE, 7)
+#define VSYNC_APP_ID      APP_ID_MAKE(NANOHUB_VENDOR_GOOGLE, 7)
 #define VSYNC_APP_VERSION 2
 
 // This defines how many vsync events we could handle being backed up in the
diff --git a/firmware/src/drivers/window_orientation/window_orientation.c b/firmware/os/drivers/window_orientation/window_orientation.c
index bed39504..8ed60148 100644
--- a/firmware/src/drivers/window_orientation/window_orientation.c
+++ b/firmware/os/drivers/window_orientation/window_orientation.c
@@ -18,8 +18,8 @@
 #include <string.h>
 #include <timer.h>
 #include <heap.h>
-#include <plat/inc/rtc.h>
-#include <plat/inc/syscfg.h>
+#include <plat/rtc.h>
+#include <plat/syscfg.h>
 #include <hostIntf.h>
 #include <nanohubPacket.h>
 #include <floatRt.h>
@@ -657,7 +657,7 @@ static void windowOrientationEnd()
 }
 
 INTERNAL_APP_INIT(
-        APP_ID_MAKE(APP_ID_VENDOR_GOOGLE, 3),
+        APP_ID_MAKE(NANOHUB_VENDOR_GOOGLE, 3),
         WINDOW_ORIENTATION_APP_VERSION,
         window_orientation_start,
         windowOrientationEnd,
diff --git a/firmware/inc/algos/accel_cal.h b/firmware/os/inc/algos/accel_cal.h
index e3204a95..e3204a95 100644
--- a/firmware/inc/algos/accel_cal.h
+++ b/firmware/os/inc/algos/accel_cal.h
diff --git a/firmware/inc/algos/ap_hub_sync.h b/firmware/os/inc/algos/ap_hub_sync.h
index ad5d4467..ad5d4467 100644
--- a/firmware/inc/algos/ap_hub_sync.h
+++ b/firmware/os/inc/algos/ap_hub_sync.h
diff --git a/firmware/inc/algos/fusion.h b/firmware/os/inc/algos/fusion.h
index 6bf4878c..6bf4878c 100644
--- a/firmware/inc/algos/fusion.h
+++ b/firmware/os/inc/algos/fusion.h
diff --git a/firmware/inc/algos/gyro_cal.h b/firmware/os/inc/algos/gyro_cal.h
index 59e9736d..59e9736d 100644
--- a/firmware/inc/algos/gyro_cal.h
+++ b/firmware/os/inc/algos/gyro_cal.h
diff --git a/firmware/inc/algos/gyro_stillness_detect.h b/firmware/os/inc/algos/gyro_stillness_detect.h
index 93516115..93516115 100644
--- a/firmware/inc/algos/gyro_stillness_detect.h
+++ b/firmware/os/inc/algos/gyro_stillness_detect.h
diff --git a/firmware/inc/algos/mag_cal.h b/firmware/os/inc/algos/mag_cal.h
index 425844d7..425844d7 100644
--- a/firmware/inc/algos/mag_cal.h
+++ b/firmware/os/inc/algos/mag_cal.h
diff --git a/firmware/inc/algos/mat.h b/firmware/os/inc/algos/mat.h
index c6f4705e..c6f4705e 100644
--- a/firmware/inc/algos/mat.h
+++ b/firmware/os/inc/algos/mat.h
diff --git a/firmware/inc/algos/quat.h b/firmware/os/inc/algos/quat.h
index b0f6fc55..b0f6fc55 100644
--- a/firmware/inc/algos/quat.h
+++ b/firmware/os/inc/algos/quat.h
diff --git a/firmware/inc/algos/time_sync.h b/firmware/os/inc/algos/time_sync.h
index ce497fc9..ce497fc9 100644
--- a/firmware/inc/algos/time_sync.h
+++ b/firmware/os/inc/algos/time_sync.h
diff --git a/firmware/inc/algos/vec.h b/firmware/os/inc/algos/vec.h
index ac7f139c..ac7f139c 100644
--- a/firmware/inc/algos/vec.h
+++ b/firmware/os/inc/algos/vec.h
diff --git a/firmware/inc/apInt.h b/firmware/os/inc/apInt.h
index 169e5938..169e5938 100644
--- a/firmware/inc/apInt.h
+++ b/firmware/os/inc/apInt.h
diff --git a/firmware/inc/appSec.h b/firmware/os/inc/appSec.h
index 8847a2a7..8847a2a7 100644
--- a/firmware/inc/appSec.h
+++ b/firmware/os/inc/appSec.h
diff --git a/firmware/inc/atomic.h b/firmware/os/inc/atomic.h
index 5a446243..129b8616 100644
--- a/firmware/inc/atomic.h
+++ b/firmware/os/inc/atomic.h
@@ -23,8 +23,6 @@ extern "C" {
 
 #include <stdint.h>
 #include <stdbool.h>
-#include <cpu/inc/atomic.h>
-#include <cpu/inc/barrier.h>
 
 /* almost all platforms support byte and 32-bit operations of this sort. please do not add other sizes here */
 uint32_t atomicXchgByte(volatile uint8_t *byte, uint32_t newVal);
@@ -36,6 +34,10 @@ bool atomicCmpXchg32bits(volatile uint32_t *word, uint32_t prevVal, uint32_t new
 uint32_t atomicAddByte(volatile uint8_t *byte, uint32_t addend);
 uint32_t atomicAdd32bits(volatile uint32_t *word, uint32_t addend);
 
+// pull in inline cpu-specific implementations, if any
+#include <cpu/atomic.h>
+#include <cpu/barrier.h>
+
 //writes with barriers
 static inline uint32_t atomicReadByte(volatile uint8_t *byte)
 {
diff --git a/firmware/inc/atomicBitset.h b/firmware/os/inc/atomicBitset.h
index 34374bfe..c7521769 100644
--- a/firmware/inc/atomicBitset.h
+++ b/firmware/os/inc/atomicBitset.h
@@ -19,7 +19,7 @@
 
 #include <stdint.h>
 #include <stdbool.h>
-#include <cpu/inc/atomicBitset.h>
+#include <cpu/atomicBitset.h>
 
 struct AtomicBitset;
 
diff --git a/firmware/inc/platform/stm32f4xx/bl.h b/firmware/os/inc/bl.h
index 34f08bd5..6a3d116a 100644
--- a/firmware/inc/platform/stm32f4xx/bl.h
+++ b/firmware/os/inc/bl.h
@@ -13,23 +13,14 @@
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
-
-#ifndef _BOOTLOADER_H_
-#define _BOOTLOADER_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
+#ifndef _BL_H_
+#define _BL_H_
 
 #include <stdbool.h>
 #include <stdarg.h>
 #include <stdint.h>
 
-struct Sha2state;
-struct RsaState;
-struct AesContext;
-struct AesSetupTempWorksSpace;
-struct AesCbcContext;
+#include <plat/bl.h>
 
 #define OS_UPDT_SUCCESS                0
 #define OS_UPDT_HDR_CHECK_FAILED       1
@@ -43,21 +34,15 @@ struct AesCbcContext;
 #define BL_VERSION_1        1
 #define BL_VERSION_CUR      BL_VERSION_1
 
-#define BL_FLASH_KEY1       0x45670123
-#define BL_FLASH_KEY2       0xCDEF89AB
+#define BL _BL.api
 
-struct BlVecTable {
-    /* cortex requirements */
-    uint32_t    blStackTop;
-    void        (*blEntry)(void);
-    void        (*blNmiHandler)(void);
-    void        (*blHardFaultHandler)(void);
-    void        (*blMmuFaultHandler)(void);
-    void        (*blBusFaultHandler)(void);
-    void        (*blUsageFaultHandler)(void);
-
-    /* bl api */
+struct Sha2state;
+struct RsaState;
+struct AesContext;
+struct AesSetupTempWorksSpace;
+struct AesCbcContext;
 
+struct BlApiTable {
     //ver 1 bl supports:
 
     //basics
@@ -92,21 +77,52 @@ struct BlVecTable {
     uint32_t        (*blVerifyOsUpdate)(void);
 };
 
-#ifndef BL_STACK_SIZE
-#define BL_STACK_SIZE 4096
-#endif
-
+struct BlTable {
+    struct BlVecTable vec;
+    struct BlApiTable api;
+};
 
 //for using outside of bootloader
-extern struct BlVecTable BL;
-
-
+extern struct BlTable _BL;
 
 //for code in bootloader to log things
 void blLog(const char *str, ...);
 
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+bool blEraseSectors(uint32_t sector_cnt, uint8_t *erase_mask, uint32_t key1, uint32_t key2);
+bool blPlatProgramFlash(uint8_t *dst, const uint8_t *src, uint32_t length, uint32_t key1, uint32_t key2);
+uint32_t blDisableInts(void);
+void blRestoreInts(uint32_t state);
+void blReboot(void);
+
+// return device serial number in array pointed to by snum
+// return value is actual copied data size in bytes
+uint32_t blGetSnum(uint32_t *snum, uint32_t length);
+// early platform init; after return from this call blHostActive() and blConfigIo() may be called immediately
+void blSetup();
+// platform cleanup before leaving bootloader; restore configuration altered by blSetup
+// on return from this call system state is similar enough to conditions seen after HW reset
+// it is safe to re-run all the bootloader code sequence again
+// it is also safe to start the custom code from flash
+void blCleanup();
+// returns true if host is requesting us to start bootloader
+bool blHostActive();
+// prepare data channel to exchange data with host
+void blConfigIo();
+// reads data stream from host until synccode is seen; returns true if received synccode, false otherwise
+// must be called after blConfigIo()
+bool blSyncWait(uint32_t syncCode);
+// reset IO channel HW;
+// makes controller ready for next data packet
+// current packet is abandoned
+void blResetRxData();
+
+// exchange 1 byte in both directions (SPI only)
+uint8_t blSpiTxRxByte(uint32_t val);
+
+// this must be called from reset vector handler
+// once data bss and stack are set properly
+// this method executes boot protocol, and returns when it is done
+// after calling method bootloader must jump to the OS boot address
+void blMain(uint32_t bootAddr);
+
+#endif /* _BL_H_ */
diff --git a/firmware/os/inc/chreApi.h b/firmware/os/inc/chreApi.h
new file mode 100644
index 00000000..ef43429d
--- /dev/null
+++ b/firmware/os/inc/chreApi.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _CHRE_API_H_
+#define _CHRE_API_H_
+
+#include <stdarg.h>
+#include <stdint.h>
+
+/* if va_list is passed by value it must fit in 32-bit register */
+#if !defined(SYSCALL_PARAMS_PASSED_AS_PTRS) || !defined(SYSCALL_VARARGS_PARAMS_PASSED_AS_PTRS)
+C_STATIC_ASSERT(va_list_size, sizeof(va_list) == sizeof(uint32_t));
+#endif
+
+/*
+ *  many syscalls rely on the property that uintptr_t can hold uint32_t without data loss
+ * This is enforced by static assertion below.
+ */
+C_STATIC_ASSERT(uintptr_size, sizeof(uintptr_t) >= sizeof(uint32_t));
+
+//EXTERNAL API
+#define SYSCALL_CHRE_MAIN                 0
+#define SYSCALL_CHRE_LAST                 1
+
+#define SYSCALL_CHRE_MAIN_API             0
+#define SYSCALL_CHRE_MAIN_LAST            1
+
+#define SYSCALL_CHRE_MAIN_API_GET_APP_ID             0 // (void) -> uint64_t
+#define SYSCALL_CHRE_MAIN_API_GET_INST_ID            1 // (void) -> uint32_t
+#define SYSCALL_CHRE_MAIN_API_LOG                    2 // (enum LogLevel, const char *, uintptr_t) -> void
+#define SYSCALL_CHRE_MAIN_API_GET_TIME               3 // (void) -> uint64_t
+#define SYSCALL_CHRE_MAIN_API_TIMER_SET              4 // (uint64_t, const void *, bool) -> uint32_t
+#define SYSCALL_CHRE_MAIN_API_TIMER_CANCEL           5 // (uint32_t) -> bool
+#define SYSCALL_CHRE_MAIN_API_ABORT                  6 // (uint32_t) -> void
+#define SYSCALL_CHRE_MAIN_API_HEAP_ALLOC             7 // (uint32_t) -> void *
+#define SYSCALL_CHRE_MAIN_API_HEAP_FREE              8 // (void *) -> void
+#define SYSCALL_CHRE_MAIN_API_SEND_EVENT             9 // (uint32_t, void *, chreEventCompleteFunction*, uint32_t) -> bool
+#define SYSCALL_CHRE_MAIN_API_SEND_MSG              10 // (void *, uint32_t, uint32_t, chreMessageFreeFunction *) -> bool
+#define SYSCALL_CHRE_MAIN_API_SENSOR_FIND_DEFAULT   11 //
+#define SYSCALL_CHRE_MAIN_API_SENSOR_GET_INFO       12 //
+#define SYSCALL_CHRE_MAIN_API_SENSOR_GET_STATUS     13 //
+#define SYSCALL_CHRE_MAIN_API_SENSOR_CONFIG         14 //
+#define SYSCALL_CHRE_MAIN_API_GET_OS_API_VERSION    15 //
+#define SYSCALL_CHRE_MAIN_API_GET_OS_VERSION        16 //
+#define SYSCALL_CHRE_MAIN_API_GET_PLATFORM_ID       17 //
+#define SYSCALL_CHRE_MAIN_API_LAST                  18 // always last. holes are allowed, but not immediately before this
+
+//called by os entry point to export the api
+void osChreApiExport(void);
+// release CHRE event and optionally call completion callback
+void osChreFreeEvent(uint32_t tid, void (*free_info)(uint16_t, void *), uint32_t evtType, void * evtData);
+
+#endif
diff --git a/firmware/inc/console.h b/firmware/os/inc/console.h
index c0c59582..c0c59582 100644
--- a/firmware/inc/console.h
+++ b/firmware/os/inc/console.h
diff --git a/firmware/inc/cpu.h b/firmware/os/inc/cpu.h
index 2cf44455..f8f1eb58 100644
--- a/firmware/inc/cpu.h
+++ b/firmware/os/inc/cpu.h
@@ -24,7 +24,7 @@ extern "C" {
 
 #include <seos.h>
 #include <stdint.h>
-#include <plat/inc/app.h>
+#include <plat/app.h>
 
 
 void cpuInit(void);
@@ -41,6 +41,8 @@ void cpuAppUnload(const struct AppHdr *appHdr, struct PlatAppInfo *platInfo);
 bool cpuAppInit(const struct AppHdr *appHdr, struct PlatAppInfo *platInfo, uint32_t tid);
 void cpuAppEnd(const struct AppHdr *appHdr, struct PlatAppInfo *platInfo);
 void cpuAppHandle(const struct AppHdr *appHdr, struct PlatAppInfo *platInfo, uint32_t evtType, const void* evtData);
+void cpuAppInvoke(const struct AppHdr *app, struct PlatAppInfo *platInfo,
+                  void (*method)(uintptr_t, uintptr_t), uintptr_t arg1, uintptr_t arg2);
 
 /* these default to false, there is CPU_NUM_PERSISTENT_RAM_BITS of them */
 bool cpuRamPersistentBitGet(uint32_t which);
diff --git a/firmware/os/inc/crc.h b/firmware/os/inc/crc.h
new file mode 100644
index 00000000..2c88d465
--- /dev/null
+++ b/firmware/os/inc/crc.h
@@ -0,0 +1,2 @@
+#include <nanohub/crc.h>
+#include <plat/crc.h>
diff --git a/firmware/inc/eeData.h b/firmware/os/inc/eeData.h
index 9b313eed..9b313eed 100644
--- a/firmware/inc/eeData.h
+++ b/firmware/os/inc/eeData.h
diff --git a/firmware/inc/eventQ.h b/firmware/os/inc/eventQ.h
index 2d4d417a..9e32210e 100644
--- a/firmware/inc/eventQ.h
+++ b/firmware/os/inc/eventQ.h
@@ -20,7 +20,7 @@
 
 #include <stdbool.h>
 #include <stdint.h>
-#include <plat/inc/taggedPtr.h>
+#include <plat/taggedPtr.h>
 
 
 #define EVENT_TYPE_BIT_DISCARDABLE_COMPAT    0x80000000 /* some external apps are using this one */
@@ -36,7 +36,6 @@ struct EvtQueue* evtQueueAlloc(uint32_t size, EvtQueueForciblyDiscardEvtCbkF for
 void evtQueueFree(struct EvtQueue* q);
 bool evtQueueEnqueue(struct EvtQueue* q, uint32_t evtType, void *evtData, TaggedPtr evtFreeData, bool atFront /* do not set this unless you know the repercussions. read: never set this in new code */);
 bool evtQueueDequeue(struct EvtQueue* q, uint32_t *evtTypeP, void **evtDataP, TaggedPtr *evtFreeDataP, bool sleepIfNone);
-
+void evtQueueRemoveAllMatching(struct EvtQueue* q,  bool (*match)(uint32_t evtType, const void *data, void *context), void *context);
 
 #endif
-
diff --git a/firmware/inc/eventnums.h b/firmware/os/inc/eventnums.h
index 88c2e5a5..e22fa043 100644
--- a/firmware/inc/eventnums.h
+++ b/firmware/os/inc/eventnums.h
@@ -53,6 +53,13 @@ struct HostHubRawPacket {
 SET_PACKED_STRUCT_MODE_OFF
 
 SET_PACKED_STRUCT_MODE_ON
+struct NanohubMsgChreHdr {
+    uint8_t size;
+    uint32_t appEvent;
+}ATTRIBUTE_PACKED;
+SET_PACKED_STRUCT_MODE_OFF
+
+SET_PACKED_STRUCT_MODE_ON
 struct MarshalledUserEventData {
     //for matching
     uint32_t origEvtType;
@@ -104,7 +111,8 @@ SET_PACKED_STRUCT_MODE_OFF
 // system ends the task unconditionally; no further checks performed (this is SIG_KILL)
 #define EVT_APP_END                      0x000000FD
 //for host comms
-#define EVT_APP_FROM_HOST                0x000000F8    //host data to an app. Type is struct HostHubRawPacket
+#define EVT_APP_FROM_HOST                0x000000F8    //host data to an app. Type is struct HostMsgHdr
+#define EVT_APP_FROM_HOST_CHRE           0x000000F9    //host data to an app. Type is struct HostMsgHdrChre
 
 //for apps that use I2C
 #define EVT_APP_I2C_CBK                  0x000000F0    //data pointer points to struct I2cEventData
diff --git a/firmware/inc/floatRt.h b/firmware/os/inc/floatRt.h
index 050cf54c..050cf54c 100644
--- a/firmware/inc/floatRt.h
+++ b/firmware/os/inc/floatRt.h
diff --git a/firmware/inc/gpio.h b/firmware/os/inc/gpio.h
index 7eb24b7f..7eb24b7f 100644
--- a/firmware/inc/gpio.h
+++ b/firmware/os/inc/gpio.h
diff --git a/firmware/inc/heap.h b/firmware/os/inc/heap.h
index c5bea591..c5bea591 100644
--- a/firmware/inc/heap.h
+++ b/firmware/os/inc/heap.h
diff --git a/firmware/inc/hostIntf.h b/firmware/os/inc/hostIntf.h
index 66ed7e4f..66ed7e4f 100644
--- a/firmware/inc/hostIntf.h
+++ b/firmware/os/inc/hostIntf.h
diff --git a/firmware/inc/hostIntf_priv.h b/firmware/os/inc/hostIntf_priv.h
index a5bfc689..a5bfc689 100644
--- a/firmware/inc/hostIntf_priv.h
+++ b/firmware/os/inc/hostIntf_priv.h
diff --git a/firmware/inc/i2c.h b/firmware/os/inc/i2c.h
index aae0d0c7..aae0d0c7 100644
--- a/firmware/inc/i2c.h
+++ b/firmware/os/inc/i2c.h
diff --git a/firmware/inc/isr.h b/firmware/os/inc/isr.h
index 73a8f033..73a8f033 100644
--- a/firmware/inc/isr.h
+++ b/firmware/os/inc/isr.h
diff --git a/firmware/inc/list.h b/firmware/os/inc/list.h
index c892e421..c892e421 100644
--- a/firmware/inc/list.h
+++ b/firmware/os/inc/list.h
diff --git a/firmware/inc/mpu.h b/firmware/os/inc/mpu.h
index 45bf7a9a..45bf7a9a 100644
--- a/firmware/inc/mpu.h
+++ b/firmware/os/inc/mpu.h
diff --git a/firmware/inc/nanohubCommand.h b/firmware/os/inc/nanohubCommand.h
index 0c4c5220..0c4c5220 100644
--- a/firmware/inc/nanohubCommand.h
+++ b/firmware/os/inc/nanohubCommand.h
diff --git a/firmware/inc/nanohubPacket.h b/firmware/os/inc/nanohubPacket.h
index ad962ea7..ad962ea7 100644
--- a/firmware/inc/nanohubPacket.h
+++ b/firmware/os/inc/nanohubPacket.h
diff --git a/firmware/inc/nanohub_math.h b/firmware/os/inc/nanohub_math.h
index 6257c764..27de6acd 100644
--- a/firmware/inc/nanohub_math.h
+++ b/firmware/os/inc/nanohub_math.h
@@ -14,5 +14,5 @@
  * limitations under the License.
  */
 
-#include <cpu/inc/nanohub_math.h>
+#include <cpu/nanohub_math.h>
 #include <math.h>
diff --git a/firmware/inc/osApi.h b/firmware/os/inc/osApi.h
index 20b2158b..287281c7 100644
--- a/firmware/inc/osApi.h
+++ b/firmware/os/inc/osApi.h
@@ -20,22 +20,7 @@
 #include <stdint.h>
 #include <slab.h>
 
-
-struct I2cEventData {
-    void *cookie;
-    uint32_t tx;
-    uint32_t rx;
-    int err;
-};
-
-union OsApiSlabItem { //main OS "things" slab must fit this
-    struct I2cEventData i2cAppCbkEvt;
-    struct {
-        uint32_t toTid;
-        void *cookie;
-    } i2cAppCbkInfo;
-};
-
+#include <seos_priv.h>
 
 //EXTERNAL API
 //level 1 indices in the OS table
diff --git a/firmware/inc/platform.h b/firmware/os/inc/platform.h
index aa706cad..aa706cad 100644
--- a/firmware/inc/platform.h
+++ b/firmware/os/inc/platform.h
diff --git a/firmware/inc/printf.h b/firmware/os/inc/printf.h
index f3c26cdc..f3c26cdc 100644
--- a/firmware/inc/printf.h
+++ b/firmware/os/inc/printf.h
diff --git a/firmware/inc/reset.h b/firmware/os/inc/reset.h
index 1e79d2ed..1e79d2ed 100644
--- a/firmware/inc/reset.h
+++ b/firmware/os/inc/reset.h
diff --git a/firmware/inc/sensType.h b/firmware/os/inc/sensType.h
index 25bdd8ec..25bdd8ec 100644
--- a/firmware/inc/sensType.h
+++ b/firmware/os/inc/sensType.h
diff --git a/firmware/inc/sensors.h b/firmware/os/inc/sensors.h
index 8ff9bf8d..dc1d5ad0 100644
--- a/firmware/inc/sensors.h
+++ b/firmware/os/inc/sensors.h
@@ -20,8 +20,8 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include <plat/inc/taggedPtr.h>
-#include <variant/inc/variant.h>
+#include <plat/taggedPtr.h>
+#include <variant/variant.h>
 #include <eventnums.h>
 #include <sensType.h>
 #include <stdbool.h>
diff --git a/firmware/os/inc/sensors_priv.h b/firmware/os/inc/sensors_priv.h
new file mode 100644
index 00000000..0e086dbe
--- /dev/null
+++ b/firmware/os/inc/sensors_priv.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SENSORS_PRIV_H__
+#define __SENSORS_PRIV_H__
+
+#include <inttypes.h>
+#include <seos.h>
+
+struct Sensor {
+    const struct SensorInfo *si;
+    uint32_t handle;         /* here 0 means invalid */
+    uint64_t currentLatency; /* here 0 means no batching */
+    uint32_t currentRate;    /* here 0 means off */
+    TaggedPtr callInfo;      /* pointer to ops struct or app tid */
+    void *callData;
+    uint32_t initComplete:1; /* sensor finished initializing */
+    uint32_t hasOnchange :1; /* sensor supports onchange and wants to be notified to send new clients current state */
+    uint32_t hasOndemand :1; /* sensor supports ondemand and wants to get triggers */
+};
+
+struct SensorsInternalEvent {
+    union {
+        struct {
+            uint32_t handle;
+            uint32_t value1;
+            uint64_t value2;
+        };
+        struct SensorPowerEvent externalPowerEvt;
+        struct SensorSetRateEvent externalSetRateEvt;
+        struct SensorCfgDataEvent externalCfgDataEvt;
+        struct SensorSendDirectEventEvent externalSendDirectEvt;
+        struct SensorMarshallUserEventEvent externalMarshallEvt;
+    };
+};
+
+struct SensorsClientRequest {
+    uint32_t handle;
+    uint32_t clientTid;
+    uint64_t latency;
+    uint32_t rate;
+};
+
+#define MAX_INTERNAL_EVENTS       32 //also used for external app sensors' setRate() calls
+#define MAX_CLI_SENS_MATRIX_SZ    64 /* MAX(numClients * numSensors) */
+
+#define SENSOR_RATE_OFF           UINT32_C(0x00000000) /* used in sensor state machine */
+#define SENSOR_RATE_POWERING_ON   UINT32_C(0xFFFFFFF0) /* used in sensor state machine */
+#define SENSOR_RATE_POWERING_OFF  UINT32_C(0xFFFFFFF1) /* used in sensor state machine */
+#define SENSOR_RATE_FW_UPLOADING  UINT32_C(0xFFFFFFF2) /* used in sensor state machine */
+#define SENSOR_RATE_IMPOSSIBLE    UINT32_C(0xFFFFFFF3) /* used in rate calc to indicate impossible combinations */
+#define SENSOR_LATENCY_INVALID    UINT64_C(0xFFFFFFFFFFFFFFFF)
+
+#define HANDLE_TO_TID(handle) (((handle) >> (32 - TASK_TID_BITS)) & TASK_TID_MASK)
+#define EXT_APP_TID(s) HANDLE_TO_TID(s->handle)
+#define LOCAL_APP_OPS(s) ((const struct SensorOps*)taggedPtrToPtr(s->callInfo))
+#define IS_LOCAL_APP(s) (taggedPtrIsPtr(s->callInfo))
+
+struct Sensor* sensorFindByHandle(uint32_t handle);
+
+#endif // __SENSORS_PRIV_H__
diff --git a/firmware/inc/seos.h b/firmware/os/inc/seos.h
index f417e576..6351de92 100644
--- a/firmware/inc/seos.h
+++ b/firmware/os/inc/seos.h
@@ -21,15 +21,15 @@
 extern "C" {
 #endif
 
-#include <plat/inc/taggedPtr.h>
+#include <plat/taggedPtr.h>
 #include <stdbool.h>
 #include <stdint.h>
 #include <stdarg.h>
 #include <stddef.h>
 #include <eventQ.h>
-#include <plat/inc/app.h>
+#include <plat/app.h>
 #include <eventnums.h>
-#include <variant/inc/variant.h>
+#include <variant/variant.h>
 #include "toolchain.h"
 
 #include <nanohub/nanohub.h>
@@ -85,19 +85,15 @@ struct AppFuncs { /* do not rearrange */
 #define FL_APP_HDR_APPLICATION     0x0002 // image has AppHdr; otherwise is has AppInfo header
 #define FL_APP_HDR_SECURE          0x0004 // secure content, needs to be zero-filled when discarded
 #define FL_APP_HDR_VOLATILE        0x0008 // volatile content, segment shall be deleted after operation is complete
+#define FL_APP_HDR_CHRE            0x0010 // app is CHRE API compatible
 #define FL_KEY_HDR_DELETE          0x8000 // key-specific flag: if set key id refers to existing key which has to be deleted
 
 /* app ids are split into vendor and app parts. vendor parts are assigned by google. App parts are free for each vendor to assign at will */
-#define APP_ID_FIRST_USABLE        0x0100000000000000ULL //all app ids lower than this are reserved for google's internal use
-#define APP_ID_GET_VENDOR(appid)   ((appid) >> 24)
-#define APP_ID_GET_SEQ_ID(appid)   ((appid) & 0xFFFFFF)
-#define APP_ID_MAKE(vendor, app)   ((((uint64_t)(vendor)) << 24) | ((app) & APP_SEQ_ID_ANY))
 #define KEY_ID_MAKE(vendor, key)   ((((uint64_t)(vendor)) << 24) | ((key) & KEY_SEQ_ID_ANY))
-#define APP_ID_VENDOR_GOOGLE       UINT64_C(0x476F6F676C) // "Googl"
-#define APP_VENDOR_ANY             UINT64_C(0xFFFFFFFFFF)
-#define APP_SEQ_ID_ANY             UINT64_C(0xFFFFFF)
+#define HW_ID_MAKE(vendor, ver)    ((((uint64_t)(vendor)) << 24) | (PLATFORM_ID(ver) & HW_ID_ANY))
 #define KEY_SEQ_ID_ANY             UINT64_C(0xFFFFFF)
-#define APP_ID_ANY                 UINT64_C(0xFFFFFFFFFFFFFFFF)
+#define HW_ID_ANY                  UINT64_C(0xFFFFFF)
+#define PLATFORM_ID(ver)           ((((PLATFORM_HW_TYPE) & 0xFFFF) << 8) | (ver & 0xFF))
 
 #define APP_INFO_CMD_ADD_KEY 1
 #define APP_INFO_CMD_REMOVE_KEY 2
@@ -159,17 +155,23 @@ void osMain(void);
 
 bool osEventSubscribe(uint32_t tid, uint32_t evtType); /* async */
 bool osEventUnsubscribe(uint32_t tid, uint32_t evtType);  /* async */
+// event free callback used to free event data which was previously allocated by heapAlloc()
+void osEventHeapFree(uint16_t event, void *data);
 
 bool osEnqueuePrivateEvt(uint32_t evtType, void *evtData, EventFreeF evtFreeF, uint32_t toTid);
 bool osEnqueuePrivateEvtAsApp(uint32_t evtType, void *evtData, uint32_t fromApp, uint32_t toTid);
+bool osEnqueuePrivateEvtNew(uint16_t evtType, void *evtData,
+                                   void (*evtFreeCallback)(uint16_t eventType, void *eventData),
+                                   uint32_t toTid);
 
 bool osEnqueueEvt(uint32_t evtType, void *evtData, EventFreeF evtFreeF);
 bool osEnqueueEvtOrFree(uint32_t evtType, void *evtData, EventFreeF evtFreeF);
 bool osEnqueueEvtAsApp(uint32_t evtType, void *evtData, uint32_t fromApp);
+void osRemovePendingEvents(bool (*match)(uint32_t evtType, const void *evtData, void *context), void *context);
 
 bool osDefer(OsDeferCbkF callback, void *cookie, bool urgent);
 
-bool osTidById(uint64_t appId, uint32_t *tid);
+bool osTidById(uint64_t *appId, uint32_t *tid);
 bool osAppInfoById(uint64_t appId, uint32_t *appIdx, uint32_t *appVer, uint32_t *appSize);
 bool osAppInfoByIndex(uint32_t appIdx, uint64_t *appId, uint32_t *appVer, uint32_t *appSize);
 uint32_t osGetCurrentTid();
@@ -264,6 +266,8 @@ uint32_t osExtAppStopApps(uint64_t appId);
 uint32_t osExtAppEraseApps(uint64_t appId);
 uint32_t osExtAppStartApps(uint64_t appId);
 
+bool osAppIsChre(uint16_t tid);
+
 /* Logging */
 enum LogLevel {
     LOG_ERROR = 'E',
@@ -272,7 +276,7 @@ enum LogLevel {
     LOG_DEBUG = 'D',
 };
 
-void osLogv(enum LogLevel level, const char *str, va_list vl);
+void osLogv(char clevel, const char *str, va_list vl);
 void osLog(enum LogLevel level, const char *str, ...) PRINTF_ATTRIBUTE(2, 3);
 
 #ifndef INTERNAL_APP_INIT
diff --git a/firmware/os/inc/seos_priv.h b/firmware/os/inc/seos_priv.h
new file mode 100644
index 00000000..b38cf4b7
--- /dev/null
+++ b/firmware/os/inc/seos_priv.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SEOS_PRIV_H__
+#define __SEOS_PRIV_H__
+
+#include <inttypes.h>
+#include <seos.h>
+
+#define NO_NODE (TaskIndex)(-1)
+#define for_each_task(listHead, task) for (task = osTaskByIdx((listHead)->next); task; task = osTaskByIdx(task->list.next))
+
+#define TID_TO_TASK_IDX(tid) (tid & TASK_TID_IDX_MASK)
+
+#define FL_TASK_STOPPED 1
+
+#define EVT_SUBSCRIBE_TO_EVT         0x00000000
+#define EVT_UNSUBSCRIBE_TO_EVT       0x00000001
+#define EVT_DEFERRED_CALLBACK        0x00000002
+#define EVT_PRIVATE_EVT              0x00000003
+
+#define EVT_PRIVATE_CLASS_CHRE       0x00000001
+
+#define EVENT_WITH_ORIGIN(evt, origin)       (((evt) & EVT_MASK) | ((origin) << (32 - TASK_TID_BITS)))
+#define EVENT_GET_ORIGIN(evt) ((evt) >> (32 - TASK_TID_BITS))
+#define EVENT_GET_EVENT(evt) ((evt) & (EVT_MASK & ~EVENT_TYPE_BIT_DISCARDABLE))
+
+
+SET_PACKED_STRUCT_MODE_ON
+struct TaskList {
+    TaskIndex prev;
+    TaskIndex next;
+} ATTRIBUTE_PACKED;
+SET_PACKED_STRUCT_MODE_OFF
+
+struct Task {
+    /* App entry points */
+    const struct AppHdr *app;
+
+    /* per-platform app info */
+    struct PlatAppInfo platInfo;
+
+    /* for some basic number of subbed events, the array is stored directly here. after that, a heap chunk is used */
+    uint32_t subbedEventsInt[MAX_EMBEDDED_EVT_SUBS];
+    uint32_t *subbedEvents; /* NULL for invalid tasks */
+
+    struct TaskList list;
+
+    /* task pointer will not change throughout task lifetime,
+     * however same task pointer may be reused for a new task; to eliminate the ambiguity,
+     * TID is maintained for each task such that new tasks will be guaranteed to receive different TID */
+    uint16_t tid;
+
+    uint8_t  subbedEvtCount;
+    uint8_t  subbedEvtListSz;
+    uint8_t  flags;
+    uint8_t  ioCount;
+
+};
+
+struct I2cEventData {
+    void *cookie;
+    uint32_t tx;
+    uint32_t rx;
+    int err;
+};
+
+union OsApiSlabItem {
+    struct I2cEventData i2cAppCbkEvt;
+    struct {
+        uint32_t toTid;
+        void *cookie;
+    } i2cAppCbkInfo;
+};
+
+/* this is a system salb allocator internal data type */
+union SeosInternalSlabData {
+    struct {
+        uint32_t tid;
+        uint32_t evt;
+    } evtSub;
+    struct {
+        OsDeferCbkF callback;
+        void *cookie;
+    } deferred;
+    struct {
+        uint32_t evtType;
+        void *evtData;
+        TaggedPtr evtFreeInfo;
+        uint16_t fromTid;
+        uint16_t toTid;
+    } privateEvt;
+    union OsApiSlabItem osApiItem;
+};
+
+uint8_t osTaskIndex(struct Task *task);
+struct Task *osGetCurrentTask();
+struct Task *osSetCurrentTask(struct Task *task);
+struct Task *osTaskFindByTid(uint32_t tid);
+void osTaskAbort(struct Task *task);
+void osTaskInvokeMessageFreeCallback(struct Task *task, void (*freeCallback)(void *, size_t), void *message, uint32_t messageSize);
+void osTaskInvokeEventFreeCallback(struct Task *task, void (*freeCallback)(uint16_t, void *), uint16_t event, void *data);
+void osChreTaskHandle(struct Task *task, uint32_t evtType, const void *evtData);
+
+static inline bool osTaskIsChre(const struct Task *task)
+{
+    return (task->app->hdr.fwFlags & FL_APP_HDR_CHRE) != 0;
+}
+
+static inline void osTaskMakeNewTid(struct Task *task)
+{
+    task->tid = ((task->tid + TASK_TID_INCREMENT) & TASK_TID_COUNTER_MASK) |
+                (osTaskIndex(task) & TASK_TID_IDX_MASK);
+}
+
+#endif // __SEOS_PRIV_H__
diff --git a/firmware/inc/simpleQ.h b/firmware/os/inc/simpleQ.h
index 62294d76..62294d76 100644
--- a/firmware/inc/simpleQ.h
+++ b/firmware/os/inc/simpleQ.h
diff --git a/firmware/inc/slab.h b/firmware/os/inc/slab.h
index a807ad62..a807ad62 100644
--- a/firmware/inc/slab.h
+++ b/firmware/os/inc/slab.h
diff --git a/firmware/inc/spi.h b/firmware/os/inc/spi.h
index 2647959d..2647959d 100644
--- a/firmware/inc/spi.h
+++ b/firmware/os/inc/spi.h
diff --git a/firmware/inc/spi_priv.h b/firmware/os/inc/spi_priv.h
index 97eb1cac..97eb1cac 100644
--- a/firmware/inc/spi_priv.h
+++ b/firmware/os/inc/spi_priv.h
diff --git a/firmware/inc/syscall.h b/firmware/os/inc/syscall.h
index 5970982a..de4038d6 100644
--- a/firmware/inc/syscall.h
+++ b/firmware/os/inc/syscall.h
@@ -53,7 +53,7 @@ extern "C" {
 //level 0 indices:
 #define SYSCALL_DOMAIN_OS         0
 #define SYSCALL_DOMAIN_DRIVERS    1 /* hardware drivers for custom hardware */
-
+#define SYSCALL_DOMAIN_CHRE       2 /* alternative API */
 
 typedef void (*SyscallFunc)(uintptr_t *retValP, va_list args); /* you better know what args you need */
 
diff --git a/firmware/inc/syscallDo.h b/firmware/os/inc/syscallDo.h
index 7dba269e..68bccee0 100644
--- a/firmware/inc/syscallDo.h
+++ b/firmware/os/inc/syscallDo.h
@@ -26,7 +26,7 @@ extern "C" {
     #error "Syscalls should not be called from OS code"
 #endif
 
-#include <cpu/inc/syscallDo.h>
+#include <cpu/syscallDo.h>
 #include <sensors.h>
 #include <syscall.h>
 #include <stdarg.h>
@@ -35,60 +35,7 @@ extern "C" {
 #include <seos.h>
 #include <util.h>
 
-
-/* it is always safe to use this, but using syscallDo0P .. syscallDo4P macros may produce faster code for free */
-static inline uintptr_t syscallDoGeneric(uint32_t syscallNo, ...)
-{
-    uintptr_t ret;
-    va_list vl;
-
-    va_start(vl, syscallNo);
-    #ifdef SYSCALL_PARAMS_PASSED_AS_PTRS
-        ret = cpuSyscallDo(syscallNo, &vl);
-    #else
-        ret = cpuSyscallDo(syscallNo, *(uint32_t*)&vl);
-    #endif
-    va_end(vl);
-
-    return ret;
-}
-
-#ifdef cpuSyscallDo0P
-    #define syscallDo0P(syscallNo) cpuSyscallDo0P(syscallNo)
-#else
-    #define syscallDo0P(syscallNo) syscallDoGeneric(syscallNo)
-#endif
-
-#ifdef cpuSyscallDo1P
-    #define syscallDo1P(syscallNo,p1) cpuSyscallDo1P(syscallNo,p1)
-#else
-    #define syscallDo1P(syscallNo,p1) syscallDoGeneric(syscallNo,p1)
-#endif
-
-#ifdef cpuSyscallDo2P
-    #define syscallDo2P(syscallNo,p1,p2) cpuSyscallDo2P(syscallNo,p1,p2)
-#else
-    #define syscallDo2P(syscallNo,p1,p2) syscallDoGeneric(syscallNo,p1,p2)
-#endif
-
-#ifdef cpuSyscallDo3P
-    #define syscallDo3P(syscallNo,p1,p2,p3) cpuSyscallDo3P(syscallNo,p1,p2,p3)
-#else
-    #define syscallDo3P(syscallNo,p1,p2,p3) syscallDoGeneric(syscallNo,p1,p2,p3)
-#endif
-
-#ifdef cpuSyscallDo4P
-    #define syscallDo4P(syscallNo,p1,p2,p3,p4) cpuSyscallDo4P(syscallNo,p1,p2,p3,p4)
-#else
-    #define syscallDo4P(syscallNo,p1,p2,p3,p4) syscallDoGeneric(syscallNo,p1,p2,p3,p4)
-#endif
-
-#ifdef cpuSyscallDo5P
-    #define syscallDo5P(syscallNo,p1,p2,p3,p4,p5) cpuSyscallDo5P(syscallNo,p1,p2,p3,p4,p5)
-#else
-    #define syscallDo5P(syscallNo,p1,p2,p3,p4,p5) syscallDoGeneric(syscallNo,p1,p2,p3,p4,p5)
-#endif
-
+#include <syscall_defs.h>
 
 
 //system syscalls live here
diff --git a/firmware/os/inc/syscall_defs.h b/firmware/os/inc/syscall_defs.h
new file mode 100644
index 00000000..0219d4a0
--- /dev/null
+++ b/firmware/os/inc/syscall_defs.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _INC_SYSCALL_DEFS_H_
+#define _INC_SYSCALL_DEFS_H_
+
+#include <cpu/syscallDo.h>
+
+/* it is always safe to use this, but using syscallDo0P .. syscallDo4P macros may produce faster code for free */
+static inline uintptr_t syscallDoGeneric(uint32_t syscallNo, ...)
+{
+    uintptr_t ret;
+    va_list vl;
+
+    va_start(vl, syscallNo);
+    #ifdef SYSCALL_PARAMS_PASSED_AS_PTRS
+        ret = cpuSyscallDo(syscallNo, &vl);
+    #else
+        ret = cpuSyscallDo(syscallNo, *(uint32_t*)&vl);
+    #endif
+    va_end(vl);
+
+    return ret;
+}
+
+#ifdef cpuSyscallDo0P
+    #define syscallDo0P(syscallNo) cpuSyscallDo0P(syscallNo)
+#else
+    #define syscallDo0P(syscallNo) syscallDoGeneric(syscallNo)
+#endif
+
+#ifdef cpuSyscallDo1P
+    #define syscallDo1P(syscallNo,p1) cpuSyscallDo1P(syscallNo,p1)
+#else
+    #define syscallDo1P(syscallNo,p1) syscallDoGeneric(syscallNo,p1)
+#endif
+
+#ifdef cpuSyscallDo2P
+    #define syscallDo2P(syscallNo,p1,p2) cpuSyscallDo2P(syscallNo,p1,p2)
+#else
+    #define syscallDo2P(syscallNo,p1,p2) syscallDoGeneric(syscallNo,p1,p2)
+#endif
+
+#ifdef cpuSyscallDo3P
+    #define syscallDo3P(syscallNo,p1,p2,p3) cpuSyscallDo3P(syscallNo,p1,p2,p3)
+#else
+    #define syscallDo3P(syscallNo,p1,p2,p3) syscallDoGeneric(syscallNo,p1,p2,p3)
+#endif
+
+#ifdef cpuSyscallDo4P
+    #define syscallDo4P(syscallNo,p1,p2,p3,p4) cpuSyscallDo4P(syscallNo,p1,p2,p3,p4)
+#else
+    #define syscallDo4P(syscallNo,p1,p2,p3,p4) syscallDoGeneric(syscallNo,p1,p2,p3,p4)
+#endif
+
+#ifdef cpuSyscallDo5P
+    #define syscallDo5P(syscallNo,p1,p2,p3,p4,p5) cpuSyscallDo5P(syscallNo,p1,p2,p3,p4,p5)
+#else
+    #define syscallDo5P(syscallNo,p1,p2,p3,p4,p5) syscallDoGeneric(syscallNo,p1,p2,p3,p4,p5)
+#endif
+
+#ifdef cpuSyscallDo6P
+    #define syscallDo6P(syscallNo,p1,p2,p3,p4,p5,p6) cpuSyscallDo5P(syscallNo,p1,p2,p3,p4,p5,p6)
+#else
+    #define syscallDo6P(syscallNo,p1,p2,p3,p4,p5,p6) syscallDoGeneric(syscallNo,p1,p2,p3,p4,p5,p6)
+#endif
+
+#endif /* _INC_SYSCALL_DEFS_H_ */
diff --git a/firmware/inc/timer.h b/firmware/os/inc/timer.h
index 18ea8153..abc5e19f 100644
--- a/firmware/inc/timer.h
+++ b/firmware/os/inc/timer.h
@@ -41,7 +41,9 @@ uint64_t timGetTime(void);   /* Time since some stable reference point in nanose
 
 uint32_t timTimerSet(uint64_t length, uint32_t jitterPpm, uint32_t driftPpm, TimTimerCbkF cbk, void* data, bool oneShot); /* return timer id or 0 if failed */
 uint32_t timTimerSetAsApp(uint64_t length, uint32_t jitterPpm, uint32_t driftPpm, uint32_t tid, void* data, bool oneShot); /* return timer id or 0 if failed */
+uint32_t timTimerSetNew(uint64_t length, const void* data, bool oneShot);
 bool timTimerCancel(uint32_t timerId);
+bool timTimerCancelEx(uint32_t timerId, bool cancelPending);
 int timTimerCancelAll(uint32_t tid);
 
 
diff --git a/firmware/inc/toolchain.h b/firmware/os/inc/toolchain.h
index d6829581..d6829581 100644
--- a/firmware/inc/toolchain.h
+++ b/firmware/os/inc/toolchain.h
diff --git a/firmware/inc/trylock.h b/firmware/os/inc/trylock.h
index 63a726db..e6eec911 100644
--- a/firmware/inc/trylock.h
+++ b/firmware/os/inc/trylock.h
@@ -21,7 +21,7 @@
 #include <stdbool.h>
 
 #ifdef PLATFORM_HAS_OWN_TRYLOCK
-#include <plat/inc/trylock.h>
+#include <plat/trylock.h>
 #else
 
 struct TryLock {
diff --git a/firmware/inc/usart.h b/firmware/os/inc/usart.h
index ab7a477d..ab7a477d 100644
--- a/firmware/inc/usart.h
+++ b/firmware/os/inc/usart.h
diff --git a/firmware/inc/util.h b/firmware/os/inc/util.h
index c29345d3..155322b9 100644
--- a/firmware/inc/util.h
+++ b/firmware/os/inc/util.h
@@ -16,7 +16,7 @@
 
 #ifndef __UTIL_H
 #define __UTIL_H
-#include <plat/inc/plat.h>
+#include <plat/plat.h>
 #include "toolchain.h"
 #include <limits.h>
 #include <stdbool.h>
@@ -29,6 +29,17 @@
 #ifndef alignof
 #define alignof(type) offsetof(struct { char x; type field; }, field)
 #endif
+/*
+ * this macro does not consume bytes from any segment; if condition is true it is a zero-sized array;
+ * if some compilers do try to allocate space for them we create a special section for those checks
+ * and discard this section at link time
+ */
+#define C_STATIC_ASSERT(name, condition) \
+    static const char __attribute__((used, section(".static_assert"))) \
+    static_assert_check_ ## name [(condition) ? 0 : -1]
+
+#define unlikely(x) (x)
+#define likely(x) (x)
 
 #define container_of(addr, struct_name, field_name) \
     ((struct_name *)((char *)(addr) - offsetof(struct_name, field_name)))
diff --git a/firmware/os/platform/native/Android.mk b/firmware/os/platform/native/Android.mk
new file mode 100644
index 00000000..54ed6f52
--- /dev/null
+++ b/firmware/os/platform/native/Android.mk
@@ -0,0 +1,37 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_PATH := $(call my-dir)
+
+NANOHUB_PALTFORM_PATH := $(LOCAL_PATH)
+
+########################################################
+# NANOHUB OS BINARY
+########################################################
+
+include $(CLEAR_NANO_VARS)
+
+LOCAL_MODULE := libnanohub_os_native
+LOCAL_AUX_ARCH := native
+
+LOCAL_SRC_FILES := \
+    hostIntf.c \
+    i2c.c \
+    platform.c \
+    rtc.c \
+    spi.c \
+
+include $(BUILD_NANOHUB_OS_STATIC_LIBRARY)
diff --git a/firmware/src/platform/linux/hostIntf.c b/firmware/os/platform/native/hostIntf.c
index 1320e8e2..1320e8e2 100644
--- a/firmware/src/platform/linux/hostIntf.c
+++ b/firmware/os/platform/native/hostIntf.c
diff --git a/firmware/src/platform/linux/i2c.c b/firmware/os/platform/native/i2c.c
index f58b454a..f58b454a 100644
--- a/firmware/src/platform/linux/i2c.c
+++ b/firmware/os/platform/native/i2c.c
diff --git a/firmware/inc/platform/linux/app.h b/firmware/os/platform/native/inc/plat/app.h
index 5617672c..5617672c 100644
--- a/firmware/inc/platform/linux/app.h
+++ b/firmware/os/platform/native/inc/plat/app.h
diff --git a/firmware/os/platform/native/inc/plat/crc.h b/firmware/os/platform/native/inc/plat/crc.h
new file mode 100644
index 00000000..2c846cbb
--- /dev/null
+++ b/firmware/os/platform/native/inc/plat/crc.h
@@ -0,0 +1,3 @@
+#include <nanohub/crc.h>
+
+#define crc32 soft_crc32
diff --git a/firmware/inc/platform/linux/plat.h b/firmware/os/platform/native/inc/plat/plat.h
index 5cda58f9..5cda58f9 100644
--- a/firmware/inc/platform/linux/plat.h
+++ b/firmware/os/platform/native/inc/plat/plat.h
diff --git a/firmware/inc/platform/linux/pwr.h b/firmware/os/platform/native/inc/plat/pwr.h
index 8ef4131e..8ef4131e 100644
--- a/firmware/inc/platform/linux/pwr.h
+++ b/firmware/os/platform/native/inc/plat/pwr.h
diff --git a/firmware/inc/platform/linux/rtc.h b/firmware/os/platform/native/inc/plat/rtc.h
index 38b698aa..38b698aa 100644
--- a/firmware/inc/platform/linux/rtc.h
+++ b/firmware/os/platform/native/inc/plat/rtc.h
diff --git a/firmware/inc/platform/linux/usart.h b/firmware/os/platform/native/inc/plat/usart.h
index 40516d46..40516d46 100644
--- a/firmware/inc/platform/linux/usart.h
+++ b/firmware/os/platform/native/inc/plat/usart.h
diff --git a/firmware/inc/platform/linux/wdt.h b/firmware/os/platform/native/inc/plat/wdt.h
index 430a385f..430a385f 100644
--- a/firmware/inc/platform/linux/wdt.h
+++ b/firmware/os/platform/native/inc/plat/wdt.h
diff --git a/firmware/os/platform/native/lkr/app.lkr b/firmware/os/platform/native/lkr/app.lkr
new file mode 100644
index 00000000..37766bde
--- /dev/null
+++ b/firmware/os/platform/native/lkr/app.lkr
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
diff --git a/firmware/misc/platform/linux/linux.extra.lkr b/firmware/os/platform/native/lkr/native.extra.lkr
index 94f3cd72..94f3cd72 100644
--- a/firmware/misc/platform/linux/linux.extra.lkr
+++ b/firmware/os/platform/native/lkr/native.extra.lkr
diff --git a/firmware/misc/platform/linux/Makefile b/firmware/os/platform/native/native.mk
index ad14dbfb..f113061d 100644
--- a/firmware/misc/platform/linux/Makefile
+++ b/firmware/os/platform/native/native.mk
@@ -15,21 +15,21 @@
 #
 
 DELIVERABLES = $(APP).bin
-LKR = misc/platform/$(PLATFORM)/linux.extra.lkr
+LKR = os/platform/$(PLATFORM)/lkr/native.extra.lkr
 
 FLAGS += -I. -fno-unwind-tables -fstack-reuse=all -ffunction-sections -fdata-sections -m32
 FLAGS += -Wl,-T $(LKR) -Wl,--gc-sections
 
 
 #platform drivers
-SRCS += src/platform/$(PLATFORM)/platform.c \
-	src/platform/$(PLATFORM)/i2c.c \
-	src/platform/$(PLATFORM)/spi.c \
-	src/platform/$(PLATFORM)/rtc.c \
-	src/platform/$(PLATFORM)/hostIntf.c
+SRCS += os/platform/$(PLATFORM)/platform.c \
+	os/platform/$(PLATFORM)/i2c.c \
+	os/platform/$(PLATFORM)/spi.c \
+	os/platform/$(PLATFORM)/rtc.c \
+	os/platform/$(PLATFORM)/hostIntf.c
 
 #extra deps
-DEPS += $(wildcard inc/platform/$(PLATFORM)/*.h)
+DEPS += $(wildcard os/platform/$(PLATFORM)/inc/plat/*.h)
 DEPS += $(LKR)
 
 #platform flags
@@ -40,5 +40,6 @@ FLAGS += -DPLAT_HAS_NO_U_TYPES_H
 #platform-specific rules
 
 %.bin : %.elf
-	mv $< $@
+	cp $< $@
 
+$(info Included NATIVE platfrom)
diff --git a/firmware/src/platform/linux/platform.c b/firmware/os/platform/native/platform.c
index 735f295b..ceac5a6d 100644
--- a/firmware/src/platform/linux/platform.c
+++ b/firmware/os/platform/native/platform.c
@@ -14,7 +14,7 @@
  * limitations under the License.
  */
 
-#include <plat/inc/rtc.h>
+#include <plat/rtc.h>
 #include <stdbool.h>
 #include <stdio.h>
 #include <string.h>
diff --git a/firmware/src/platform/linux/rtc.c b/firmware/os/platform/native/rtc.c
index e262f466..075f5e26 100644
--- a/firmware/src/platform/linux/rtc.c
+++ b/firmware/os/platform/native/rtc.c
@@ -14,8 +14,8 @@
  * limitations under the License.
  */
 
-#include <cpu/inc/barrier.h>
-#include <plat/inc/rtc.h>
+#include <cpu/barrier.h>
+#include <plat/rtc.h>
 #include <timer.h>
 #include <platform.h>
 
diff --git a/firmware/src/platform/linux/spi.c b/firmware/os/platform/native/spi.c
index efc41eaa..efc41eaa 100644
--- a/firmware/src/platform/linux/spi.c
+++ b/firmware/os/platform/native/spi.c
diff --git a/firmware/os/platform/stm32/Android.mk b/firmware/os/platform/stm32/Android.mk
new file mode 100644
index 00000000..b61dc3b7
--- /dev/null
+++ b/firmware/os/platform/stm32/Android.mk
@@ -0,0 +1,69 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_PATH := $(call my-dir)
+
+########################################################
+# COMMON OS & BL defs
+########################################################
+
+NANOHUB_PALTFORM_PATH := $(LOCAL_PATH)
+
+########################################################
+# BOOT LOADER BINARY
+########################################################
+
+include $(CLEAR_NANO_VARS)
+
+LOCAL_MODULE := libnanohub_bl_stm32
+LOCAL_AUX_ARCH := stm32
+
+LOCAL_SRC_FILES :=      \
+    bl.c                \
+    gpio.c              \
+    pwr.c               \
+
+include $(BUILD_NANOHUB_BL_STATIC_LIBRARY)
+
+########################################################
+# NANOHUB OS BINARY
+########################################################
+
+include $(CLEAR_NANO_VARS)
+
+LOCAL_MODULE := libnanohub_os_stm32
+LOCAL_AUX_ARCH := stm32
+
+LOCAL_SRC_FILES := \
+    apInt.c \
+    crc.c \
+    crt_stm32.c \
+    dma.c \
+    eeData.c \
+    exti.c \
+    gpio.c \
+    hostIntf.c \
+    i2c.c \
+    mpu.c \
+    platform.c \
+    pwr.c \
+    rtc.c \
+    spi.c \
+    syscfg.c \
+    usart.c \
+    wdt.c \
+
+include $(BUILD_NANOHUB_OS_STATIC_LIBRARY)
diff --git a/firmware/src/platform/stm32f4xx/apInt.c b/firmware/os/platform/stm32/apInt.c
index b8a1c016..d8521d13 100644
--- a/firmware/src/platform/stm32f4xx/apInt.c
+++ b/firmware/os/platform/stm32/apInt.c
@@ -16,11 +16,11 @@
 
 #include <apInt.h>
 #include <gpio.h>
-#include <variant/inc/variant.h>
-#include <plat/inc/gpio.h>
+#include <variant/variant.h>
+#include <plat/gpio.h>
 #include <seos.h>
 #include <platform.h>
-#include <plat/inc/plat.h>
+#include <plat/plat.h>
 
 static struct Gpio *apIntWkup;
 #ifdef AP_INT_NONWAKEUP
diff --git a/firmware/os/platform/stm32/bl.c b/firmware/os/platform/stm32/bl.c
new file mode 100644
index 00000000..e6412868
--- /dev/null
+++ b/firmware/os/platform/stm32/bl.c
@@ -0,0 +1,529 @@
+#include <alloca.h>
+#include <stdbool.h>
+#include <string.h>
+
+#include <variant/variant.h>
+
+#include <plat/pwr.h>
+#include <plat/gpio.h>
+#include <plat/cmsis.h>
+
+#include <bl.h>
+
+struct StmUdid
+{
+    volatile uint32_t U_ID[3];
+};
+
+struct StmSpi {
+    volatile uint32_t CR1;
+    volatile uint32_t CR2;
+    volatile uint32_t SR;
+    volatile uint32_t DR;
+    volatile uint32_t CRCPR;
+    volatile uint32_t RXCRCR;
+    volatile uint32_t TXCRCR;
+    volatile uint32_t I2SCFGR;
+    volatile uint32_t I2SPR;
+};
+
+struct StmGpio {
+    volatile uint32_t MODER;
+    volatile uint32_t OTYPER;
+    volatile uint32_t OSPEEDR;
+    volatile uint32_t PUPDR;
+    volatile uint32_t IDR;
+    volatile uint32_t ODR;
+    volatile uint32_t BSRR;
+    volatile uint32_t LCKR;
+    volatile uint32_t AFR[2];
+};
+
+struct StmFlash
+{
+    volatile uint32_t ACR;
+    volatile uint32_t KEYR;
+    volatile uint32_t OPTKEYR;
+    volatile uint32_t SR;
+    volatile uint32_t CR;
+    volatile uint32_t OPTCR;
+};
+
+struct StmCrc
+{
+    volatile uint32_t DR;
+    volatile uint32_t IDR;
+    volatile uint32_t CR;
+};
+
+struct StmRcc {
+    volatile uint32_t CR;
+    volatile uint32_t PLLCFGR;
+    volatile uint32_t CFGR;
+    volatile uint32_t CIR;
+    volatile uint32_t AHB1RSTR;
+    volatile uint32_t AHB2RSTR;
+    volatile uint32_t AHB3RSTR;
+    uint8_t unused0[4];
+    volatile uint32_t APB1RSTR;
+    volatile uint32_t APB2RSTR;
+    uint8_t unused1[8];
+    volatile uint32_t AHB1ENR;
+    volatile uint32_t AHB2ENR;
+    volatile uint32_t AHB3ENR;
+    uint8_t unused2[4];
+    volatile uint32_t APB1ENR;
+    volatile uint32_t APB2ENR;
+    uint8_t unused3[8];
+    volatile uint32_t AHB1LPENR;
+    volatile uint32_t AHB2LPENR;
+    volatile uint32_t AHB3LPENR;
+    uint8_t unused4[4];
+    volatile uint32_t APB1LPENR;
+    volatile uint32_t APB2LPENR;
+    uint8_t unused5[8];
+    volatile uint32_t BDCR;
+    volatile uint32_t CSR;
+    uint8_t unused6[8];
+    volatile uint32_t SSCGR;
+    volatile uint32_t PLLI2SCFGR;
+};
+
+typedef void (*FlashEraseF)(volatile uint32_t *, uint32_t, volatile uint32_t *);
+typedef void (*FlashWriteF)(volatile uint8_t *, uint8_t, volatile uint32_t *);
+
+static struct StmSpi *SPI;
+static struct StmGpio *GPIOA;
+static struct StmRcc *RCC;
+static uint32_t mOldApb2State;
+static uint32_t mOldAhb1State;
+
+#define INT_IN_PIN          (SH_INT_WAKEUP - GPIO_PA(0))
+
+#define FLASH_ACR_LAT(x)    ((x) & FLASH_ACR_LAT_MASK)
+#define FLASH_ACR_LAT_MASK  0x0F
+#define FLASH_ACR_PRFTEN    0x00000100
+#define FLASH_ACR_ICEN      0x00000200
+#define FLASH_ACR_DCEN      0x00000400
+#define FLASH_ACR_ICRST     0x00000800
+#define FLASH_ACR_DCRST     0x00001000
+
+#define FLASH_SR_EOP        0x00000001
+#define FLASH_SR_OPERR      0x00000002
+#define FLASH_SR_WRPERR     0x00000010
+#define FLASH_SR_PGAERR     0x00000020
+#define FLASH_SR_PGPERR     0x00000040
+#define FLASH_SR_PGSERR     0x00000080
+#define FLASH_SR_RDERR      0x00000100
+#define FLASH_SR_BSY        0x00010000
+
+#define FLASH_CR_PG         0x00000001
+#define FLASH_CR_SER        0x00000002
+#define FLASH_CR_MER        0x00000004
+#define FLASH_CR_SNB(x)     (((x) << FLASH_CR_SNB_SHIFT) & FLASH_CR_SNB_MASK)
+#define FLASH_CR_SNB_MASK   0x00000078
+#define FLASH_CR_SNB_SHIFT  3
+#define FLASH_CR_PSIZE(x)   (((x) << FLASH_CR_PSIZE_SHIFT) & FLASH_CR_PSIZE_MASK)
+#define FLASH_CR_PSIZE_MASK 0x00000300
+#define FLASH_CR_PSIZE_SHIFT 8
+#define FLASH_CR_PSIZE_8    0x0
+#define FLASH_CR_PSIZE_16   0x1
+#define FLASH_CR_PSIZE_32   0x2
+#define FLASH_CR_PSIZE_64   0x3
+#define FLASH_CR_STRT       0x00010000
+#define FLASH_CR_EOPIE      0x01000000
+#define FLASH_CR_ERRIE      0x02000000
+#define FLASH_CR_LOCK       0x80000000
+
+//stm defines
+#define BL_MAX_FLASH_CODE   1024
+
+/*
+ * Return the address of the erase code and the length of the code
+ *
+ * This code needs to run out of ram and not flash since accessing flash
+ * while erasing is undefined (best case the processor stalls, worst case
+ * it starts executing garbage)
+ *
+ * This function is used to get a pointer to the actual code that does the
+ * erase and polls for completion (so we can copy it to ram) as well as the
+ * length of the code (so we know how much space to allocate for it)
+ *
+ * void FlashEraseF(volatile uint32_t *addr, uint32_t value, volatile uint32_t *status)
+ * {
+ *     *addr = value;
+ *     while (*status & FLASH_SR_BSY) ;
+ * }
+ */
+static void __attribute__((naked)) blGetFlashEraseCode(uint16_t **addr, uint32_t *size)
+{
+    asm volatile (
+        "  push {lr}          \n"
+        "  bl   9f            \n"
+        "  str  r1, [r0, #0]  \n" // *addr = value
+        "1:                   \n"
+        "  ldr  r3, [r2, #0]  \n" // r3 = *status
+        "  lsls r3, #15       \n" // r3 <<= 15
+        "  bmi  1b            \n" // if (r3 < 0) goto 1
+        "  bx   lr            \n" // return
+        "9:                   \n"
+        "  bic  lr, #0x1      \n"
+        "  adr  r3, 9b        \n"
+        "  sub  r3, lr        \n"
+        "  str  lr, [r0]      \n"
+        "  str  r3, [r1]      \n"
+        "  pop {pc}           \n"
+    );
+}
+
+static void _blEraseSectors(uint32_t sector_cnt, uint8_t *erase_mask)
+{
+    struct StmFlash *flash = (struct StmFlash *)FLASH_BASE;
+    uint16_t *code_src, *code;
+    uint32_t i, code_length;
+    FlashEraseF func;
+
+    blGetFlashEraseCode(&code_src, &code_length);
+
+    if (code_length < BL_MAX_FLASH_CODE) {
+        code = (uint16_t *)(((uint32_t)alloca(code_length + 1) + 1) & ~0x1);
+        func = (FlashEraseF)((uint8_t *)code+1);
+
+        for (i = 0; i < code_length / sizeof(uint16_t); i++)
+            code[i] = code_src[i];
+
+        for (i = 0; i < sector_cnt; i++) {
+            if (erase_mask[i]) {
+                flash->CR = (flash->CR & ~(FLASH_CR_SNB_MASK)) |
+                    FLASH_CR_SNB(i) | FLASH_CR_SER;
+                func(&flash->CR, flash->CR | FLASH_CR_STRT, &flash->SR);
+                flash->CR &= ~(FLASH_CR_SNB_MASK | FLASH_CR_SER);
+            }
+        }
+    }
+}
+
+bool blEraseSectors(uint32_t sector_cnt, uint8_t *erase_mask, uint32_t key1, uint32_t key2)
+{
+    struct StmFlash *flash = (struct StmFlash *)FLASH_BASE;
+    uint32_t acr_cache, cr_cache;
+    // disable interrupts
+    // otherwise an interrupt during flash write/erase will stall the processor
+    // until the write/erase completes
+    uint32_t int_state = blDisableInts();
+
+    // wait for flash to not be busy (should never be set at this point)
+    while (flash->SR & FLASH_SR_BSY);
+
+    cr_cache = flash->CR;
+
+    if (flash->CR & FLASH_CR_LOCK) {
+        // unlock flash
+        flash->KEYR = key1;
+        flash->KEYR = key2;
+    }
+
+    if (!(flash->CR & FLASH_CR_LOCK)) {
+        flash->CR = FLASH_CR_PSIZE(FLASH_CR_PSIZE_8);
+        acr_cache = flash->ACR;
+
+        // disable and flush data and instruction caches
+        flash->ACR &= ~(FLASH_ACR_DCEN | FLASH_ACR_ICEN);
+        flash->ACR |= (FLASH_ACR_DCRST | FLASH_ACR_ICRST);
+
+        _blEraseSectors(sector_cnt, erase_mask);
+
+        flash->ACR = acr_cache;
+        flash->CR = cr_cache;
+
+        // restore interrupts
+        blRestoreInts(int_state);
+        return true;
+    }
+    return false;
+}
+
+/*
+ * Return the address of the write code and the length of the code
+ *
+ * This code needs to run out of ram and not flash since accessing flash
+ * while writing to flash is undefined (best case the processor stalls, worst
+ * case it starts executing garbage)
+ *
+ * This function is used to get a pointer to the actual code that does the
+ * write and polls for completion (so we can copy it to ram) as well as the
+ * length of the code (so we know how much space to allocate for it)
+ *
+ * void FlashWriteF(volatile uint8_t *addr, uint8_t value, volatile uint32_t *status)
+ * {
+ *     *addr = value;
+ *     while (*status & FLASH_SR_BSY) ;
+ * }
+ */
+static void __attribute__((naked)) blGetFlashWriteCode(uint16_t **addr, uint32_t *size)
+{
+    asm volatile (
+        "  push {lr}          \n"
+        "  bl   9f            \n"
+        "  strb r1, [r0, #0]  \n" // *addr = value
+        "1:                   \n"
+        "  ldr  r3, [r2, #0]  \n" // r3 = *status
+        "  lsls r3, #15       \n" // r3 <<= 15
+        "  bmi  1b            \n" // if (r3 < 0) goto 1
+        "  bx   lr            \n" // return
+        "9:                   \n"
+        "  bic  lr, #0x1      \n"
+        "  adr  r3, 9b        \n"
+        "  sub  r3, lr        \n"
+        "  str  lr, [r0]      \n"
+        "  str  r3, [r1]      \n"
+        "  pop {pc}           \n"
+    );
+}
+
+static void blWriteBytes(uint8_t *dst, const uint8_t *src, uint32_t length)
+{
+    struct StmFlash *flash = (struct StmFlash *)FLASH_BASE;
+    uint16_t *code_src, *code;
+    uint32_t i, code_length;
+    FlashWriteF func;
+
+    blGetFlashWriteCode(&code_src, &code_length);
+
+    if (code_length < BL_MAX_FLASH_CODE) {
+        code = (uint16_t *)(((uint32_t)alloca(code_length+1) + 1) & ~0x1);
+        func = (FlashWriteF)((uint8_t *)code+1);
+
+        for (i = 0; i < code_length / sizeof(uint16_t); i++)
+            code[i] = code_src[i];
+
+        flash->CR |= FLASH_CR_PG;
+
+        for (i = 0; i < length; i++) {
+            if (dst[i] != src[i])
+                func(&dst[i], src[i], &flash->SR);
+        }
+
+        flash->CR &= ~FLASH_CR_PG;
+    }
+}
+
+bool blPlatProgramFlash(uint8_t *dst, const uint8_t *src, uint32_t length, uint32_t key1, uint32_t key2)
+{
+    struct StmFlash *flash = (struct StmFlash *)FLASH_BASE;
+    uint32_t acr_cache, cr_cache;
+    // disable interrupts
+    // otherwise an interrupt during flash write will stall the processor
+    // until the write completes
+    uint32_t int_state = blDisableInts();
+
+    // wait for flash to not be busy (should never be set at this point)
+    while (flash->SR & FLASH_SR_BSY);
+
+    cr_cache = flash->CR;
+
+    if (flash->CR & FLASH_CR_LOCK) {
+        // unlock flash
+        flash->KEYR = key1;
+        flash->KEYR = key2;
+    }
+
+    if (flash->CR & FLASH_CR_LOCK) {
+        // unlock failed, restore interrupts
+        blRestoreInts(int_state);
+
+        return false;
+    }
+
+    flash->CR = FLASH_CR_PSIZE(FLASH_CR_PSIZE_8);
+
+    acr_cache = flash->ACR;
+
+    // disable and flush data and instruction caches
+    flash->ACR &= ~(FLASH_ACR_DCEN | FLASH_ACR_ICEN);
+    flash->ACR |= (FLASH_ACR_DCRST | FLASH_ACR_ICRST);
+
+    blWriteBytes(dst, src, length);
+
+    flash->ACR = acr_cache;
+    flash->CR = cr_cache;
+
+    blRestoreInts(int_state);
+    return true;
+}
+
+uint32_t blDisableInts(void)
+{
+    uint32_t state;
+
+    asm volatile (
+        "mrs %0, PRIMASK    \n"
+        "cpsid i            \n"
+        :"=r"(state)
+    );
+
+    return state;
+}
+
+void blRestoreInts(uint32_t state)
+{
+    asm volatile(
+        "msr PRIMASK, %0   \n"
+        ::"r"((uint32_t)state)
+    );
+}
+
+void blReboot(void)
+{
+    SCB->AIRCR = 0x05FA0004;
+    //we never get here
+    while(1);
+}
+
+void blResetRxData()
+{
+    (void)SPI->DR;
+    while (!(SPI->SR & 1));
+    (void)SPI->DR;
+}
+
+uint8_t blSpiTxRxByte(uint32_t val)
+{
+    while (!(SPI->SR & 2));
+    SPI->DR = val;
+    while (!(SPI->SR & 1));
+    return SPI->DR;
+}
+
+uint32_t blGetSnum(uint32_t *snum, uint32_t length)
+{
+    struct StmUdid *reg = (struct StmUdid *)UDID_BASE;
+    uint32_t i;
+
+    if (length > 3)
+        length = 3;
+
+    for (i = 0; i < length; i++)
+        snum[i] = reg->U_ID[i];
+
+    return (length << 2);
+}
+
+void blSetup()
+{
+    SPI = (struct StmSpi*)SPI1_BASE;
+    GPIOA = (struct StmGpio*)GPIOA_BASE;
+    RCC = (struct StmRcc*)RCC_BASE;
+
+    if (SH_INT_WAKEUP < GPIO_PA(0) || SH_INT_WAKEUP > GPIO_PA(15)) {
+
+        //link time assert :)
+        extern void ThisIsAnError_BlIntPinNotInGpioA(void);
+        ThisIsAnError_BlIntPinNotInGpioA();
+    }
+
+    //SPI & GPIOA on
+    mOldApb2State = RCC->APB2ENR;
+    mOldAhb1State = RCC->AHB1ENR;
+    RCC->APB2ENR |= PERIPH_APB2_SPI1;
+    RCC->AHB1ENR |= PERIPH_AHB1_GPIOA;
+
+    //reset units
+    RCC->APB2RSTR |= PERIPH_APB2_SPI1;
+    RCC->AHB1RSTR |= PERIPH_AHB1_GPIOA;
+    RCC->APB2RSTR &=~ PERIPH_APB2_SPI1;
+    RCC->AHB1RSTR &=~ PERIPH_AHB1_GPIOA;
+
+    //configure GPIOA for SPI A4..A7 for SPI use (function 5), int pin as not func, high speed, no pullups, not open drain, proper directions
+    GPIOA->AFR[0] = (GPIOA->AFR[0] & 0x0000ffff & ~(0x0f << (INT_IN_PIN * 4))) | 0x55550000;
+    GPIOA->OSPEEDR |= 0x0000ff00 | (3 << (INT_IN_PIN * 2));
+    GPIOA->PUPDR &=~ (0x0000ff00 | (3 << (INT_IN_PIN * 2)));
+    GPIOA->OTYPER &=~ (0x00f0 | (1 << INT_IN_PIN));
+    GPIOA->MODER = (GPIOA->MODER & 0xffff00ff & ~(0x03 << (INT_IN_PIN * 2))) | 0x0000aa00;
+}
+
+void blCleanup()
+{
+    //reset units & return APB2 & AHB1 to initial state
+    RCC->APB2RSTR |= PERIPH_APB2_SPI1;
+    RCC->AHB1RSTR |= PERIPH_AHB1_GPIOA;
+    RCC->APB2RSTR &=~ PERIPH_APB2_SPI1;
+    RCC->AHB1RSTR &=~ PERIPH_AHB1_GPIOA;
+    RCC->APB2ENR = mOldApb2State;
+    RCC->AHB1ENR = mOldAhb1State;
+}
+
+bool blHostActive()
+{
+    return !(GPIOA->IDR & (1 << INT_IN_PIN));
+}
+
+void blConfigIo()
+{
+    //config SPI
+    SPI->CR1 = 0x00000040; //spi is on, configured same as bootloader would
+    SPI->CR2 = 0x00000000; //spi is on, configured same as bootloader would
+}
+
+bool blSyncWait(uint32_t syncCode)
+{
+    uint32_t nRetries;
+    //wait for sync
+    for (nRetries = 10000; nRetries; nRetries--) {
+        if (SPI->SR & 1) {
+            if (SPI->DR == syncCode)
+                break;
+            (void)SPI->SR; //re-read to clear overlfow condition (if any)
+        }
+    }
+    return nRetries > 0;
+}
+
+static void __blEntry(void)
+{
+    extern char __code_start[], __bss_end[], __bss_start[], __data_end[], __data_start[], __data_data[];
+    uint32_t appBase = ((uint32_t)&__code_start) & ~1;
+
+    //make sure we're the vector table and no ints happen (BL does not use them)
+    blDisableInts();
+    SCB->VTOR = (uint32_t)&BL;
+
+    //init things a little for the higher levels
+    memset(__bss_start, 0, __bss_end - __bss_start);
+    memcpy(__data_start, __data_data, __data_end - __data_start);
+
+    blMain(appBase);
+
+    //call OS with ints off
+    blDisableInts();
+    SCB->VTOR = appBase;
+    asm volatile(
+        "LDR SP, [%0, #0]    \n"
+        "LDR PC, [%0, #4]    \n"
+        :
+        :"r"(appBase)
+        :"memory", "cc"
+    );
+
+    //we should never return here
+    while(1);
+}
+
+static void blSpuriousIntHandler(void)
+{
+    //BAD!
+    blReboot();
+}
+
+extern uint8_t __stack_top[];
+uint64_t __attribute__ ((section (".stack"))) _STACK[BL_STACK_SIZE / sizeof(uint64_t)];
+
+const struct BlVecTable __attribute__((section(".blvec"))) __BL_VEC =
+{
+    .blStackTop             = (uint32_t)&__stack_top,
+    .blEntry                = &__blEntry,
+    .blNmiHandler           = &blSpuriousIntHandler,
+    .blMmuFaultHandler      = &blSpuriousIntHandler,
+    .blBusFaultHandler      = &blSpuriousIntHandler,
+    .blUsageFaultHandler    = &blSpuriousIntHandler,
+};
diff --git a/firmware/src/platform/stm32f4xx/crc.c b/firmware/os/platform/stm32/crc.c
index 771703d2..ece90e73 100644
--- a/firmware/src/platform/stm32f4xx/crc.c
+++ b/firmware/os/platform/stm32/crc.c
@@ -19,7 +19,7 @@
 #include <nanohub/crc.h>
 #include <seos.h>
 
-#include <plat/inc/pwr.h>
+#include <plat/pwr.h>
 
 struct StmCrcRegs {
     volatile uint32_t DR;
diff --git a/firmware/src/platform/stm32f4xx/crt_stm32f4xx.c b/firmware/os/platform/stm32/crt_stm32.c
index 52e3f7c5..52e3f7c5 100644
--- a/firmware/src/platform/stm32f4xx/crt_stm32f4xx.c
+++ b/firmware/os/platform/stm32/crt_stm32.c
diff --git a/firmware/src/platform/stm32f4xx/dma.c b/firmware/os/platform/stm32/dma.c
index 226bb989..6813b256 100644
--- a/firmware/src/platform/stm32f4xx/dma.c
+++ b/firmware/os/platform/stm32/dma.c
@@ -20,9 +20,9 @@
 #include <seos.h>
 #include <util.h>
 
-#include <plat/inc/cmsis.h>
-#include <plat/inc/dma.h>
-#include <plat/inc/pwr.h>
+#include <plat/cmsis.h>
+#include <plat/dma.h>
+#include <plat/pwr.h>
 
 #define DMA_VERBOSE_DEBUG 0
 
diff --git a/firmware/src/platform/stm32f4xx/eeData.c b/firmware/os/platform/stm32/eeData.c
index 906b9f38..20e859ef 100644
--- a/firmware/src/platform/stm32f4xx/eeData.c
+++ b/firmware/os/platform/stm32/eeData.c
@@ -14,10 +14,11 @@
  * limitations under the License.
  */
 
-#include <plat/inc/bl.h>
 #include <stdbool.h>
-#include <string.h>
 #include <stdint.h>
+#include <string.h>
+
+#include <bl.h>
 #include <eeData.h>
 
 extern uint32_t __eedata_start[], __eedata_end[];
diff --git a/firmware/src/platform/stm32f4xx/exti.c b/firmware/os/platform/stm32/exti.c
index 5d5cb4b8..7c0d7852 100644
--- a/firmware/src/platform/stm32f4xx/exti.c
+++ b/firmware/os/platform/stm32/exti.c
@@ -18,9 +18,9 @@
 #include <isr.h>
 #include <platform.h>
 
-#include <plat/inc/cmsis.h>
-#include <plat/inc/exti.h>
-#include <plat/inc/pwr.h>
+#include <plat/cmsis.h>
+#include <plat/exti.h>
+#include <plat/pwr.h>
 
 struct StmExti
 {
diff --git a/firmware/misc/platform/stm32f4xx/flash_script/Makefile b/firmware/os/platform/stm32/flash_script/Makefile
index ca5d0ef4..ca5d0ef4 100644
--- a/firmware/misc/platform/stm32f4xx/flash_script/Makefile
+++ b/firmware/os/platform/stm32/flash_script/Makefile
diff --git a/firmware/misc/platform/stm32f4xx/flash_script/tool.c b/firmware/os/platform/stm32/flash_script/tool.c
index 2b607d09..2b607d09 100644
--- a/firmware/misc/platform/stm32f4xx/flash_script/tool.c
+++ b/firmware/os/platform/stm32/flash_script/tool.c
diff --git a/firmware/src/platform/stm32f4xx/gpio.c b/firmware/os/platform/stm32/gpio.c
index ff17c79c..648ca098 100644
--- a/firmware/src/platform/stm32f4xx/gpio.c
+++ b/firmware/os/platform/stm32/gpio.c
@@ -14,8 +14,8 @@
  * limitations under the License.
  */
 
-#include <plat/inc/gpio.h>
-#include <plat/inc/pwr.h>
+#include <plat/gpio.h>
+#include <plat/pwr.h>
 #include <gpio.h>
 #include <cpu.h>
 
diff --git a/firmware/src/platform/stm32f4xx/hostIntf.c b/firmware/os/platform/stm32/hostIntf.c
index c561d9a0..2a96032d 100644
--- a/firmware/src/platform/stm32f4xx/hostIntf.c
+++ b/firmware/os/platform/stm32/hostIntf.c
@@ -14,12 +14,14 @@
  * limitations under the License.
  */
 
+#include <bl.h>
 #include <hostIntf.h>
 #include <hostIntf_priv.h>
-#include <variant/inc/variant.h>
-#include <plat/inc/bl.h>
-#include <plat/inc/cmsis.h>
-#include <plat/inc/spi.h>
+
+#include <variant/variant.h>
+
+#include <plat/cmsis.h>
+#include <plat/spi.h>
 
 
 const struct HostIntfComm *platHostIntfInit()
diff --git a/firmware/src/platform/stm32f4xx/i2c.c b/firmware/os/platform/stm32/i2c.c
index 17d87dde..9abedc6a 100644
--- a/firmware/src/platform/stm32f4xx/i2c.c
+++ b/firmware/os/platform/stm32/i2c.c
@@ -27,14 +27,14 @@
 #include <atomic.h>
 #include <platform.h>
 
-#include <plat/inc/cmsis.h>
-#include <plat/inc/dma.h>
-#include <plat/inc/gpio.h>
-#include <plat/inc/i2c.h>
-#include <plat/inc/pwr.h>
-#include <plat/inc/plat.h>
-
-#include <cpu/inc/barrier.h>
+#include <plat/cmsis.h>
+#include <plat/dma.h>
+#include <plat/gpio.h>
+#include <plat/i2c.h>
+#include <plat/pwr.h>
+#include <plat/plat.h>
+
+#include <cpu/barrier.h>
 
 #define I2C_VERBOSE_DEBUG       0
 #define I2C_MAX_QUEUE_DEPTH     5
diff --git a/firmware/inc/platform/stm32f4xx/app.h b/firmware/os/platform/stm32/inc/plat/app.h
index 98c61bd7..98c61bd7 100644
--- a/firmware/inc/platform/stm32f4xx/app.h
+++ b/firmware/os/platform/stm32/inc/plat/app.h
diff --git a/firmware/os/platform/stm32/inc/plat/bl.h b/firmware/os/platform/stm32/inc/plat/bl.h
new file mode 100644
index 00000000..990a48a9
--- /dev/null
+++ b/firmware/os/platform/stm32/inc/plat/bl.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _PLAT_BL_H_
+#define _PLAT_BL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BL_FLASH_KEY1       0x45670123
+#define BL_FLASH_KEY2       0xCDEF89AB
+
+struct BlVecTable {
+    /* cortex requirements */
+    uint32_t    blStackTop;
+    void        (*blEntry)(void);
+    void        (*blNmiHandler)(void);
+    void        (*blHardFaultHandler)(void);
+    void        (*blMmuFaultHandler)(void);
+    void        (*blBusFaultHandler)(void);
+    void        (*blUsageFaultHandler)(void);
+};
+
+#ifndef BL_STACK_SIZE
+#define BL_STACK_SIZE 4096
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _PLAT_BL_H_
diff --git a/firmware/inc/platform/stm32f4xx/cmsis.h b/firmware/os/platform/stm32/inc/plat/cmsis.h
index efac7cd4..8b79368d 100644
--- a/firmware/inc/platform/stm32f4xx/cmsis.h
+++ b/firmware/os/platform/stm32/inc/plat/cmsis.h
@@ -14,124 +14,124 @@
  * limitations under the License.
  */
 
-#ifndef _CMSIS_H_

-#define _CMSIS_H_

-

-

-#ifdef __cplusplus

-extern "C" {

-#endif

-

-#define __NVIC_PRIO_BITS 4

-#define __FPU_PRESENT 1

-

-

-

-typedef enum IRQn

-{

-/* -------------------  Cortex    Processor Exceptions Numbers  ------------------ */

-    NonMaskableInt_IRQn          = -14,      /*!<  2 Non Maskable Interrupt          */

-    HardFault_IRQn               = -13,      /*!<  3 HardFault Interrupt             */

-    MemoryManagement_IRQn        = -12,      /*!<  4 Memory Management Interrupt     */

-    BusFault_IRQn                = -11,      /*!<  5 Bus Fault Interrupt             */

-    UsageFault_IRQn              = -10,      /*!<  6 Usage Fault Interrupt           */

-    SVCall_IRQn                  =  -5,      /*!< 11 SV Call Interrupt               */

-    DebugMonitor_IRQn            =  -4,      /*!< 12 Debug Monitor Interrupt         */

-    PendSV_IRQn                  =  -2,      /*!< 14 Pend SV Interrupt               */

-    SysTick_IRQn                 =  -1,      /*!< 15 System Tick Interrupt           */

-    

-/* ----------------------  STM32F411 Specific Interrupt Numbers  ----------------- */

-    WWDG_IRQn                    = 0,

-    PVD_IRQn                     = 1,

-    TAMP_STAMP_IRQn              = 2,

-    RTC_WKUP_IRQn                = 3,

-    FLASH_IRQn                   = 4,

-    RCC_IRQn                     = 5,

-    EXTI0_IRQn                   = 6,

-    EXTI1_IRQn                   = 7,

-    EXTI2_IRQn                   = 8,

-    EXTI3_IRQn                   = 9,

-    EXTI4_IRQn                   = 10,

-    DMA1_Stream0_IRQn            = 11,

-    DMA1_Stream1_IRQn            = 12,

-    DMA1_Stream2_IRQn            = 13,

-    DMA1_Stream3_IRQn            = 14,

-    DMA1_Stream4_IRQn            = 15,

-    DMA1_Stream5_IRQn            = 16,

-    DMA1_Stream6_IRQn            = 17,

-    ADC_IRQn                     = 18,

-    CAN1_TX_IRQn                 = 19,

-    CAN1_RX0_IRQn                = 20,

-    CAN1_RX1_IRQn                = 21,

-    CAN1_SCE_IRQn                = 22,

-    EXTI9_5_IRQn                 = 23,

-    TIM1_BRK_TIM9_IRQn           = 24,

-    TIM1_UP_TIM10_IRQn           = 25,

-    TIM1_TRG_COM_TIM11_IRQn      = 26,

-    TIM1_CC_IRQn                 = 27,

-    TIM2_IRQn                    = 28,

-    TIM3_IRQn                    = 29,

-    TIM4_IRQn                    = 30,

-    I2C1_EV_IRQn                 = 31,

-    I2C1_ER_IRQn                 = 32,

-    I2C2_EV_IRQn                 = 33,

-    I2C2_ER_IRQn                 = 34,

-    SPI1_IRQn                    = 35,

-    SPI2_IRQn                    = 36,

-    USART1_IRQn                  = 37,

-    USART2_IRQn                  = 38,

-    USART3_IRQn                  = 39,

-    EXTI15_10_IRQn               = 40,

-    RTC_Alarm_IRQn               = 41,

-    OTG_FS_WKUP_IRQn             = 42,

-    TIM8_BRK_TIM12_IRQn          = 43,

-    TIM8_UP_TIM13_IRQn           = 44,

-    TIM8_TRG_COM_TIM14_IRQn      = 45,

-    TIM8_CC_IRQn                 = 46,

-    DMA1_Stream7_IRQn            = 47,

-    FSMC_IRQn                    = 48,

-    SDIO_IRQn                    = 49,

-    TIM5_IRQn                    = 50,

-    SPI3_IRQn                    = 51,

-    UART4_IRQn                   = 52,

-    UART5_IRQn                   = 53,

-    TIM6_DAC_IRQn                = 54,

-    TIM7_IRQn                    = 55,

-    DMA2_Stream0_IRQn            = 56,

-    DMA2_Stream1_IRQn            = 57,

-    DMA2_Stream2_IRQn            = 58,

-    DMA2_Stream3_IRQn            = 59,

-    DMA2_Stream4_IRQn            = 60,

-    ETH_IRQn                     = 61,

-    ETH_WKUP_IRQn                = 62,

-    CAN2_TX_IRQn                 = 63,

-    CAN2_RX0_IRQn                = 64,

-    CAN2_RX1_IRQn                = 65,

-    CAN2_SCE_IRQn                = 66,

-    OTG_FS_IRQn                  = 67,

-    DMA2_Stream5_IRQn            = 68,

-    DMA2_Stream6_IRQn            = 69,

-    DMA2_Stream7_IRQn            = 70,

-    USART6_IRQn                  = 71,

-    I2C3_EV_IRQn                 = 72,

-    I2C3_ER_IRQn                 = 73,

-    OTG_HS_EP1_OUT_IRQn          = 74,

-    OTG_HS_EP1_IN_IRQn           = 75,

-    OTG_HS_WKUP_IRQn             = 76,

-    OTG_HS_IRQn                  = 77,

-    DCMI_IRQn                    = 78,

-    CRYP_IRQn                    = 79,

-    HASH_RNG_IRQn                = 80,

-    FPU_IRQn                     = 81,

-    NUM_INTERRUPTS

-} IRQn_Type;

-

-#include "core_cm4.h"

-

-#ifdef __cplusplus

-}

-#endif

-

-

-#endif

-

+#ifndef _CMSIS_H_
+#define _CMSIS_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define __NVIC_PRIO_BITS 4
+#define __FPU_PRESENT 1
+
+
+
+typedef enum IRQn
+{
+/* -------------------  Cortex    Processor Exceptions Numbers  ------------------ */
+    NonMaskableInt_IRQn          = -14,      /*!<  2 Non Maskable Interrupt          */
+    HardFault_IRQn               = -13,      /*!<  3 HardFault Interrupt             */
+    MemoryManagement_IRQn        = -12,      /*!<  4 Memory Management Interrupt     */
+    BusFault_IRQn                = -11,      /*!<  5 Bus Fault Interrupt             */
+    UsageFault_IRQn              = -10,      /*!<  6 Usage Fault Interrupt           */
+    SVCall_IRQn                  =  -5,      /*!< 11 SV Call Interrupt               */
+    DebugMonitor_IRQn            =  -4,      /*!< 12 Debug Monitor Interrupt         */
+    PendSV_IRQn                  =  -2,      /*!< 14 Pend SV Interrupt               */
+    SysTick_IRQn                 =  -1,      /*!< 15 System Tick Interrupt           */
+    
+/* ----------------------  STM32F411 Specific Interrupt Numbers  ----------------- */
+    WWDG_IRQn                    = 0,
+    PVD_IRQn                     = 1,
+    TAMP_STAMP_IRQn              = 2,
+    RTC_WKUP_IRQn                = 3,
+    FLASH_IRQn                   = 4,
+    RCC_IRQn                     = 5,
+    EXTI0_IRQn                   = 6,
+    EXTI1_IRQn                   = 7,
+    EXTI2_IRQn                   = 8,
+    EXTI3_IRQn                   = 9,
+    EXTI4_IRQn                   = 10,
+    DMA1_Stream0_IRQn            = 11,
+    DMA1_Stream1_IRQn            = 12,
+    DMA1_Stream2_IRQn            = 13,
+    DMA1_Stream3_IRQn            = 14,
+    DMA1_Stream4_IRQn            = 15,
+    DMA1_Stream5_IRQn            = 16,
+    DMA1_Stream6_IRQn            = 17,
+    ADC_IRQn                     = 18,
+    CAN1_TX_IRQn                 = 19,
+    CAN1_RX0_IRQn                = 20,
+    CAN1_RX1_IRQn                = 21,
+    CAN1_SCE_IRQn                = 22,
+    EXTI9_5_IRQn                 = 23,
+    TIM1_BRK_TIM9_IRQn           = 24,
+    TIM1_UP_TIM10_IRQn           = 25,
+    TIM1_TRG_COM_TIM11_IRQn      = 26,
+    TIM1_CC_IRQn                 = 27,
+    TIM2_IRQn                    = 28,
+    TIM3_IRQn                    = 29,
+    TIM4_IRQn                    = 30,
+    I2C1_EV_IRQn                 = 31,
+    I2C1_ER_IRQn                 = 32,
+    I2C2_EV_IRQn                 = 33,
+    I2C2_ER_IRQn                 = 34,
+    SPI1_IRQn                    = 35,
+    SPI2_IRQn                    = 36,
+    USART1_IRQn                  = 37,
+    USART2_IRQn                  = 38,
+    USART3_IRQn                  = 39,
+    EXTI15_10_IRQn               = 40,
+    RTC_Alarm_IRQn               = 41,
+    OTG_FS_WKUP_IRQn             = 42,
+    TIM8_BRK_TIM12_IRQn          = 43,
+    TIM8_UP_TIM13_IRQn           = 44,
+    TIM8_TRG_COM_TIM14_IRQn      = 45,
+    TIM8_CC_IRQn                 = 46,
+    DMA1_Stream7_IRQn            = 47,
+    FSMC_IRQn                    = 48,
+    SDIO_IRQn                    = 49,
+    TIM5_IRQn                    = 50,
+    SPI3_IRQn                    = 51,
+    UART4_IRQn                   = 52,
+    UART5_IRQn                   = 53,
+    TIM6_DAC_IRQn                = 54,
+    TIM7_IRQn                    = 55,
+    DMA2_Stream0_IRQn            = 56,
+    DMA2_Stream1_IRQn            = 57,
+    DMA2_Stream2_IRQn            = 58,
+    DMA2_Stream3_IRQn            = 59,
+    DMA2_Stream4_IRQn            = 60,
+    ETH_IRQn                     = 61,
+    ETH_WKUP_IRQn                = 62,
+    CAN2_TX_IRQn                 = 63,
+    CAN2_RX0_IRQn                = 64,
+    CAN2_RX1_IRQn                = 65,
+    CAN2_SCE_IRQn                = 66,
+    OTG_FS_IRQn                  = 67,
+    DMA2_Stream5_IRQn            = 68,
+    DMA2_Stream6_IRQn            = 69,
+    DMA2_Stream7_IRQn            = 70,
+    USART6_IRQn                  = 71,
+    I2C3_EV_IRQn                 = 72,
+    I2C3_ER_IRQn                 = 73,
+    OTG_HS_EP1_OUT_IRQn          = 74,
+    OTG_HS_EP1_IN_IRQn           = 75,
+    OTG_HS_WKUP_IRQn             = 76,
+    OTG_HS_IRQn                  = 77,
+    DCMI_IRQn                    = 78,
+    CRYP_IRQn                    = 79,
+    HASH_RNG_IRQn                = 80,
+    FPU_IRQn                     = 81,
+    NUM_INTERRUPTS
+} IRQn_Type;
+
+#include <cpu/cmsis.h>
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
+
diff --git a/firmware/os/platform/stm32/inc/plat/crc.h b/firmware/os/platform/stm32/inc/plat/crc.h
new file mode 100644
index 00000000..40a8c178
--- /dev/null
+++ b/firmware/os/platform/stm32/inc/plat/crc.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/firmware/inc/platform/stm32f4xx/dma.h b/firmware/os/platform/stm32/inc/plat/dma.h
index a4ef66a2..a4ef66a2 100644
--- a/firmware/inc/platform/stm32f4xx/dma.h
+++ b/firmware/os/platform/stm32/inc/plat/dma.h
diff --git a/firmware/inc/platform/stm32f4xx/eeData.h b/firmware/os/platform/stm32/inc/plat/eeData.h
index 6cba1503..6cba1503 100644
--- a/firmware/inc/platform/stm32f4xx/eeData.h
+++ b/firmware/os/platform/stm32/inc/plat/eeData.h
diff --git a/firmware/inc/platform/stm32f4xx/exti.h b/firmware/os/platform/stm32/inc/plat/exti.h
index 59d9db69..2f21f867 100644
--- a/firmware/inc/platform/stm32f4xx/exti.h
+++ b/firmware/os/platform/stm32/inc/plat/exti.h
@@ -19,8 +19,8 @@
 
 #include <isr.h>
 #include <stdbool.h>
-#include <plat/inc/cmsis.h>
-#include <plat/inc/gpio.h>
+#include <plat/cmsis.h>
+#include <plat/gpio.h>
 #include <gpio.h>
 
 #ifdef __cplusplus
diff --git a/firmware/inc/platform/stm32f4xx/gpio.h b/firmware/os/platform/stm32/inc/plat/gpio.h
index a45110f6..a45110f6 100644
--- a/firmware/inc/platform/stm32f4xx/gpio.h
+++ b/firmware/os/platform/stm32/inc/plat/gpio.h
diff --git a/firmware/inc/platform/stm32f4xx/i2c.h b/firmware/os/platform/stm32/inc/plat/i2c.h
index f1f021fd..bf46f452 100644
--- a/firmware/inc/platform/stm32f4xx/i2c.h
+++ b/firmware/os/platform/stm32/inc/plat/i2c.h
@@ -19,9 +19,9 @@
 
 #include <gpio.h>
 #include <platform.h>
-#include <plat/inc/cmsis.h>
-#include <plat/inc/gpio.h>
-#include <plat/inc/plat.h>
+#include <plat/cmsis.h>
+#include <plat/gpio.h>
+#include <plat/plat.h>
 
 struct StmI2cDmaCfg {
     uint8_t channel;
diff --git a/firmware/inc/platform/stm32f4xx/plat.h b/firmware/os/platform/stm32/inc/plat/plat.h
index c07ae564..c07ae564 100644
--- a/firmware/inc/platform/stm32f4xx/plat.h
+++ b/firmware/os/platform/stm32/inc/plat/plat.h
diff --git a/firmware/inc/platform/stm32f4xx/pwr.h b/firmware/os/platform/stm32/inc/plat/pwr.h
index fde926fc..e142c513 100644
--- a/firmware/inc/platform/stm32f4xx/pwr.h
+++ b/firmware/os/platform/stm32/inc/plat/pwr.h
@@ -23,7 +23,7 @@ extern "C" {
 
 #include <stdint.h>
 #include <stdbool.h>
-#include <plat/inc/rtc.h>
+#include <plat/rtc.h>
 
 /* busses */
 #define PERIPH_BUS_AHB1               0
diff --git a/firmware/inc/platform/stm32f4xx/rtc.h b/firmware/os/platform/stm32/inc/plat/rtc.h
index e807a1d1..5615356b 100644
--- a/firmware/inc/platform/stm32f4xx/rtc.h
+++ b/firmware/os/platform/stm32/inc/plat/rtc.h
@@ -22,7 +22,7 @@ extern "C" {
 #endif
 
 #include <stdint.h>
-#include <inc/seos.h>
+#include <seos.h>
 
 enum RtcClock
 {
diff --git a/firmware/inc/platform/stm32f4xx/spi.h b/firmware/os/platform/stm32/inc/plat/spi.h
index 79bc3c41..22c80708 100644
--- a/firmware/inc/platform/stm32f4xx/spi.h
+++ b/firmware/os/platform/stm32/inc/plat/spi.h
@@ -19,9 +19,9 @@
 
 #include <gpio.h>
 #include <platform.h>
-#include <plat/inc/cmsis.h>
-#include <plat/inc/gpio.h>
-#include <plat/inc/plat.h>
+#include <plat/cmsis.h>
+#include <plat/gpio.h>
+#include <plat/plat.h>
 
 struct StmSpiDmaCfg {
     uint8_t channel;
diff --git a/firmware/inc/platform/stm32f4xx/syscfg.h b/firmware/os/platform/stm32/inc/plat/syscfg.h
index de8bab19..464895e2 100644
--- a/firmware/inc/platform/stm32f4xx/syscfg.h
+++ b/firmware/os/platform/stm32/inc/plat/syscfg.h
@@ -17,7 +17,7 @@
 #ifndef _STM32F4XX_SYSCFG_H_
 #define _STM32F4XX_SYSCFG_H_
 
-#include <plat/inc/gpio.h>
+#include <plat/gpio.h>
 #include <gpio.h>
 
 #ifdef __cplusplus
diff --git a/firmware/inc/platform/stm32f4xx/taggedPtr.h b/firmware/os/platform/stm32/inc/plat/taggedPtr.h
index b4839775..b4839775 100644
--- a/firmware/inc/platform/stm32f4xx/taggedPtr.h
+++ b/firmware/os/platform/stm32/inc/plat/taggedPtr.h
diff --git a/firmware/inc/platform/stm32f4xx/usart.h b/firmware/os/platform/stm32/inc/plat/usart.h
index 62f249fc..62f249fc 100644
--- a/firmware/inc/platform/stm32f4xx/usart.h
+++ b/firmware/os/platform/stm32/inc/plat/usart.h
diff --git a/firmware/inc/platform/stm32f4xx/wdt.h b/firmware/os/platform/stm32/inc/plat/wdt.h
index afc8de2e..afc8de2e 100644
--- a/firmware/inc/platform/stm32f4xx/wdt.h
+++ b/firmware/os/platform/stm32/inc/plat/wdt.h
diff --git a/firmware/misc/cpu/cortexm4f/app.lkr b/firmware/os/platform/stm32/lkr/app.lkr
index 6766e291..ae934bd5 100644
--- a/firmware/misc/cpu/cortexm4f/app.lkr
+++ b/firmware/os/platform/stm32/lkr/app.lkr
@@ -81,12 +81,26 @@ SECTIONS
     .data : {
         . = ALIGN(4);
         __data_start = ABSOLUTE(.);
+        __dso_handle = ABSOLUTE(__data_start);
         *(.data);
         *(.data.*);
         . = ALIGN(4);
         __data_end = ABSOLUTE(.);
 
         . = ALIGN(4);
+        __init_array_start = ABSOLUTE(.);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        __init_array_end = ABSOLUTE(.);
+
+        . = ALIGN(4);
+        __fini_array_start = ABSOLUTE(.);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        __fini_array_end = ABSOLUTE(.);
+        LONG(0) /* size in 32-bit words, to add to bss section for dynamic destructor registration */
+
+        . = ALIGN(4);
         __got_start = ABSOLUTE(.);
         *(.got) *(.got.*) ;
         __got_end = ABSOLUTE(.);
diff --git a/firmware/misc/variant/common/stm32f401.bl.lkr b/firmware/os/platform/stm32/lkr/stm32f401.bl.lkr
index bb187ea6..c903e152 100644
--- a/firmware/misc/variant/common/stm32f401.bl.lkr
+++ b/firmware/os/platform/stm32/lkr/stm32f401.bl.lkr
@@ -15,6 +15,6 @@
  */
 
 
-INCLUDE misc/variant/common/stm32f401.map.lkr
-INCLUDE misc/variant/common/stm32f4xx.bl.lkr
-INCLUDE misc/variant/common/stm32f4xx.common.lkr
+INCLUDE os/platform/stm32/lkr/stm32f401.map.lkr
+INCLUDE os/platform/stm32/lkr/stm32f4xx.bl.lkr
+INCLUDE os/platform/stm32/lkr/stm32f4xx.common.lkr
diff --git a/firmware/misc/variant/common/stm32f401.map.lkr b/firmware/os/platform/stm32/lkr/stm32f401.map.lkr
index f03ef569..b726f14e 100644
--- a/firmware/misc/variant/common/stm32f401.map.lkr
+++ b/firmware/os/platform/stm32/lkr/stm32f401.map.lkr
@@ -14,8 +14,6 @@
  * limitations under the License.
  */
 
-
-
 MEMORY
 {
 	bl	: ORIGIN = 0x08000000,	LENGTH = 16K	/* one block */
@@ -24,4 +22,3 @@ MEMORY
 	shared	: ORIGIN = 0x08020000,	LENGTH = 384K	/* 3x 128K blocks */
 	ram	: ORIGIN = 0x20000000,	LENGTH = 96K
 }
-
diff --git a/firmware/misc/variant/common/stm32f401.os.lkr b/firmware/os/platform/stm32/lkr/stm32f401.os.lkr
index b842ce97..aef5c61e 100644
--- a/firmware/misc/variant/common/stm32f401.os.lkr
+++ b/firmware/os/platform/stm32/lkr/stm32f401.os.lkr
@@ -15,6 +15,6 @@
  */
 
 
-INCLUDE misc/variant/common/stm32f401.map.lkr
-INCLUDE misc/variant/common/stm32f4xx.os.lkr
-INCLUDE misc/variant/common/stm32f4xx.common.lkr
+INCLUDE os/platform/stm32/lkr/stm32f401.map.lkr
+INCLUDE os/platform/stm32/lkr/stm32f4xx.os.lkr
+INCLUDE os/platform/stm32/lkr/stm32f4xx.common.lkr
diff --git a/firmware/misc/variant/common/stm32f411.bl.lkr b/firmware/os/platform/stm32/lkr/stm32f411.bl.lkr
index 0bb4e40f..09a21364 100644
--- a/firmware/misc/variant/common/stm32f411.bl.lkr
+++ b/firmware/os/platform/stm32/lkr/stm32f411.bl.lkr
@@ -15,6 +15,6 @@
  */
 
 
-INCLUDE misc/variant/common/stm32f411.map.lkr
-INCLUDE misc/variant/common/stm32f4xx.bl.lkr
-INCLUDE misc/variant/common/stm32f4xx.common.lkr
+INCLUDE os/platform/stm32/lkr/stm32f411.map.lkr
+INCLUDE os/platform/stm32/lkr/stm32f4xx.bl.lkr
+INCLUDE os/platform/stm32/lkr/stm32f4xx.common.lkr
diff --git a/firmware/misc/variant/common/stm32f411.map.lkr b/firmware/os/platform/stm32/lkr/stm32f411.map.lkr
index 4aa0be01..4aa0be01 100644
--- a/firmware/misc/variant/common/stm32f411.map.lkr
+++ b/firmware/os/platform/stm32/lkr/stm32f411.map.lkr
diff --git a/firmware/misc/variant/common/stm32f411.os.lkr b/firmware/os/platform/stm32/lkr/stm32f411.os.lkr
index 25534599..db0a6c82 100644
--- a/firmware/misc/variant/common/stm32f411.os.lkr
+++ b/firmware/os/platform/stm32/lkr/stm32f411.os.lkr
@@ -15,6 +15,6 @@
  */
 
 
-INCLUDE misc/variant/common/stm32f411.map.lkr
-INCLUDE misc/variant/common/stm32f4xx.os.lkr
-INCLUDE misc/variant/common/stm32f4xx.common.lkr
+INCLUDE os/platform/stm32/lkr/stm32f411.map.lkr
+INCLUDE os/platform/stm32/lkr/stm32f4xx.os.lkr
+INCLUDE os/platform/stm32/lkr/stm32f4xx.common.lkr
diff --git a/firmware/os/platform/stm32/lkr/stm32f412.bl.lkr b/firmware/os/platform/stm32/lkr/stm32f412.bl.lkr
new file mode 100644
index 00000000..1ae513d8
--- /dev/null
+++ b/firmware/os/platform/stm32/lkr/stm32f412.bl.lkr
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+INCLUDE os/platform/stm32/lkr/stm32f412.map.lkr
+INCLUDE os/platform/stm32/lkr/stm32f4xx.bl.lkr
+INCLUDE os/platform/stm32/lkr/stm32f4xx.common.lkr
diff --git a/firmware/os/platform/stm32/lkr/stm32f412.map.lkr b/firmware/os/platform/stm32/lkr/stm32f412.map.lkr
new file mode 100644
index 00000000..5e5f82a4
--- /dev/null
+++ b/firmware/os/platform/stm32/lkr/stm32f412.map.lkr
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+MEMORY
+{
+	bl	: ORIGIN = 0x08000000,	LENGTH = 16K	/* one block */
+	eedata	: ORIGIN = 0x08004000,	LENGTH = 32K	/* two 16K blocks */
+	code	: ORIGIN = 0x0800C000,	LENGTH = 208K	/* 16K block + 64K block + 128K block */
+	shared	: ORIGIN = 0x08040000,	LENGTH = 768K	/* 6x 128K blocks */
+	ram	: ORIGIN = 0x20000000,	LENGTH = 256K
+}
diff --git a/firmware/os/platform/stm32/lkr/stm32f412.os.lkr b/firmware/os/platform/stm32/lkr/stm32f412.os.lkr
new file mode 100644
index 00000000..0662cba8
--- /dev/null
+++ b/firmware/os/platform/stm32/lkr/stm32f412.os.lkr
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+INCLUDE os/platform/stm32/lkr/stm32f412.map.lkr
+INCLUDE os/platform/stm32/lkr/stm32f4xx.os.lkr
+INCLUDE os/platform/stm32/lkr/stm32f4xx.common.lkr
diff --git a/firmware/misc/variant/common/stm32f4xx.bl.lkr b/firmware/os/platform/stm32/lkr/stm32f4xx.bl.lkr
index d83b5291..890fac70 100644
--- a/firmware/misc/variant/common/stm32f4xx.bl.lkr
+++ b/firmware/os/platform/stm32/lkr/stm32f4xx.bl.lkr
@@ -14,13 +14,13 @@
  * limitations under the License.
  */
 
-
 SECTIONS
 {
 	/* bootloader */
 	.bl : {
-		BL = ABSOLUTE(.);
+		_BL = ABSOLUTE(.);
 		KEEP (*(.blvec) ) ;
+		KEEP (*(.blapi) ) ;
 		*(.text) *(.text.*) ;
 		*(.rodata) *(.rodata.*) ;
 		. = ALIGN(4);
@@ -74,6 +74,4 @@ SECTIONS
 	} > ram
 }
 
-
-ENTRY(__BL_VECTORS)
-
+ENTRY(_BL)
diff --git a/firmware/misc/variant/common/stm32f4xx.common.lkr b/firmware/os/platform/stm32/lkr/stm32f4xx.common.lkr
index 30b2d7e5..8df1d051 100644
--- a/firmware/misc/variant/common/stm32f4xx.common.lkr
+++ b/firmware/os/platform/stm32/lkr/stm32f4xx.common.lkr
@@ -1,4 +1,3 @@
-
 __ram_start = ORIGIN(ram);
 __ram_end = ORIGIN(ram) + LENGTH(ram);
 __eedata_start = ORIGIN(eedata);
@@ -8,5 +7,3 @@ __code_end = ORIGIN(code) + LENGTH(code);
 __shared_start = ORIGIN(shared);
 __shared_end = ORIGIN(shared) + LENGTH(shared);
 __data_data = LOADADDR(.data);
-
-
diff --git a/firmware/misc/variant/common/stm32f4xx.os.lkr b/firmware/os/platform/stm32/lkr/stm32f4xx.os.lkr
index 153faeda..0c3ecf5e 100644
--- a/firmware/misc/variant/common/stm32f4xx.os.lkr
+++ b/firmware/os/platform/stm32/lkr/stm32f4xx.os.lkr
@@ -14,7 +14,6 @@
  * limitations under the License.
  */
 
-
 SECTIONS
 {
 	/* things that live in the main app image */
@@ -64,9 +63,7 @@ SECTIONS
 	} > ram
 }
 
-BL = ORIGIN(bl);
+_BL = ORIGIN(bl);
 __app_start = __data_data + __data_end - __data_start;
 __heap_end = ORIGIN(ram) + LENGTH(ram);
 ENTRY(__VECTORS)
-
-
diff --git a/firmware/misc/debug.privkey b/firmware/os/platform/stm32/misc/debug.privkey
index 9a634276..9a634276 100644
--- a/firmware/misc/debug.privkey
+++ b/firmware/os/platform/stm32/misc/debug.privkey
diff --git a/firmware/misc/debug.pubkey b/firmware/os/platform/stm32/misc/debug.pubkey
index b4d49531..b4d49531 100644
--- a/firmware/misc/debug.pubkey
+++ b/firmware/os/platform/stm32/misc/debug.pubkey
diff --git a/firmware/misc/platform/stm32f4xx/m3debug.script b/firmware/os/platform/stm32/misc/m3debug.script
index 3ad5912e..3ad5912e 100644
--- a/firmware/misc/platform/stm32f4xx/m3debug.script
+++ b/firmware/os/platform/stm32/misc/m3debug.script
diff --git a/firmware/misc/platform/stm32f4xx/showsizes.sh b/firmware/os/platform/stm32/misc/showsizes.sh
index e7401114..e7401114 100755
--- a/firmware/misc/platform/stm32f4xx/showsizes.sh
+++ b/firmware/os/platform/stm32/misc/showsizes.sh
diff --git a/firmware/src/platform/stm32f4xx/mpu.c b/firmware/os/platform/stm32/mpu.c
index 175657a7..f45a1531 100644
--- a/firmware/src/platform/stm32f4xx/mpu.c
+++ b/firmware/os/platform/stm32/mpu.c
@@ -14,12 +14,13 @@
  * limitations under the License.
  */
 
-#include <plat/inc/bl.h>
-#include <platform.h>
 #include <stdbool.h>
 #include <stdint.h>
-#include <mpu.h>
+
+#include <bl.h>
 #include <cpu.h>
+#include <mpu.h>
+#include <platform.h>
 
 struct CortexMpu {
     volatile uint32_t CTRL;
diff --git a/firmware/src/platform/stm32f4xx/platform.c b/firmware/os/platform/stm32/platform.c
index f4fc6c61..ca39cad7 100644
--- a/firmware/src/platform/stm32f4xx/platform.c
+++ b/firmware/os/platform/stm32/platform.c
@@ -14,17 +14,17 @@
  * limitations under the License.
  */
 
-#include <cpu/inc/cpuMath.h>
-#include <plat/inc/gpio.h>
-#include <plat/inc/usart.h>
-#include <plat/inc/cmsis.h>
-#include <plat/inc/pwr.h>
-#include <plat/inc/rtc.h>
-#include <plat/inc/plat.h>
-#include <plat/inc/exti.h>
-#include <plat/inc/syscfg.h>
-#include <plat/inc/wdt.h>
-#include <plat/inc/dma.h>
+#include <cpu/cpuMath.h>
+#include <plat/gpio.h>
+#include <plat/usart.h>
+#include <plat/cmsis.h>
+#include <plat/pwr.h>
+#include <plat/rtc.h>
+#include <plat/plat.h>
+#include <plat/exti.h>
+#include <plat/syscfg.h>
+#include <plat/wdt.h>
+#include <plat/dma.h>
 #include <stdbool.h>
 #include <stdio.h>
 #include <string.h>
@@ -43,7 +43,7 @@
 #include <hostIntf.h>
 #include <nanohubPacket.h>
 #include <sensType.h>
-#include <variant/inc/variant.h>
+#include <variant/variant.h>
 
 
 struct StmDbg {
diff --git a/firmware/src/platform/stm32f4xx/pwr.c b/firmware/os/platform/stm32/pwr.c
index e0e07cbd..39510a50 100644
--- a/firmware/src/platform/stm32f4xx/pwr.c
+++ b/firmware/os/platform/stm32/pwr.c
@@ -14,10 +14,10 @@
  * limitations under the License.
  */
 
-#include <cpu/inc/barrier.h>
-#include <plat/inc/cmsis.h>
-#include <plat/inc/pwr.h>
-#include <plat/inc/rtc.h>
+#include <cpu/barrier.h>
+#include <plat/cmsis.h>
+#include <plat/pwr.h>
+#include <plat/rtc.h>
 #include <reset.h>
 #include <stddef.h>
 
diff --git a/firmware/src/platform/stm32f4xx/rtc.c b/firmware/os/platform/stm32/rtc.c
index 86a2ed66..4918d429 100644
--- a/firmware/src/platform/stm32f4xx/rtc.c
+++ b/firmware/os/platform/stm32/rtc.c
@@ -14,15 +14,15 @@
  * limitations under the License.
  */
 
-#include <cpu/inc/barrier.h>
-#include <cpu/inc/cpuMath.h>
-#include <plat/inc/rtc.h>
-#include <plat/inc/pwr.h>
-#include <inc/timer.h>
-#include <inc/platform.h>
-#include <plat/inc/exti.h>
-#include <plat/inc/cmsis.h>
-#include <variant/inc/variant.h>
+#include <cpu/barrier.h>
+#include <cpu/cpuMath.h>
+#include <plat/rtc.h>
+#include <plat/pwr.h>
+#include <timer.h>
+#include <platform.h>
+#include <plat/exti.h>
+#include <plat/cmsis.h>
+#include <variant/variant.h>
 
 #ifndef NS_PER_S
 #define NS_PER_S                    UINT64_C(1000000000)
diff --git a/firmware/src/platform/stm32f4xx/spi.c b/firmware/os/platform/stm32/spi.c
index dc305a5a..5f1915b7 100644
--- a/firmware/src/platform/stm32f4xx/spi.c
+++ b/firmware/os/platform/stm32/spi.c
@@ -25,14 +25,14 @@
 #include <atomic.h>
 #include <platform.h>
 
-#include <plat/inc/cmsis.h>
-#include <plat/inc/dma.h>
-#include <plat/inc/gpio.h>
-#include <plat/inc/pwr.h>
-#include <plat/inc/exti.h>
-#include <plat/inc/syscfg.h>
-#include <plat/inc/spi.h>
-#include <plat/inc/plat.h>
+#include <plat/cmsis.h>
+#include <plat/dma.h>
+#include <plat/gpio.h>
+#include <plat/pwr.h>
+#include <plat/exti.h>
+#include <plat/syscfg.h>
+#include <plat/spi.h>
+#include <plat/plat.h>
 
 #define SPI_CR1_CPHA                (1 << 0)
 #define SPI_CR1_CPOL                (1 << 1)
diff --git a/firmware/os/platform/stm32/stm32.mk b/firmware/os/platform/stm32/stm32.mk
new file mode 100644
index 00000000..103ca3df
--- /dev/null
+++ b/firmware/os/platform/stm32/stm32.mk
@@ -0,0 +1,86 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+M3DEBUG ?= m3debug
+
+ifneq ($(CPU),cortexm4)
+        $(error "stm32 cplatform only supports Cortex-M4 CPUs")
+endif
+
+BL_FILE = $(OUT)/bl.unchecked.bin
+OS_FILE = $(OUT)/os.checked.bin
+
+DELIVERABLES += showsizes
+FLAGS += -I. -fno-unwind-tables -fstack-reuse=all -ffunction-sections -fdata-sections
+FLAGS += -Wl,--gc-sections -nostartfiles
+FLAGS_os += -nostdlib
+
+#platform bootloader
+SRCS_bl += os/platform/$(PLATFORM)/bl.c
+
+#platform runtime
+SRCS_os +=  os/platform/$(PLATFORM)/crt_$(PLATFORM).c
+
+#platform drivers
+SRCS_os += os/platform/$(PLATFORM)/platform.c \
+	os/platform/$(PLATFORM)/usart.c \
+	os/platform/$(PLATFORM)/gpio.c \
+	os/platform/$(PLATFORM)/pwr.c \
+	os/platform/$(PLATFORM)/wdt.c \
+	os/platform/$(PLATFORM)/i2c.c \
+	os/platform/$(PLATFORM)/exti.c \
+	os/platform/$(PLATFORM)/syscfg.c \
+	os/platform/$(PLATFORM)/spi.c \
+	os/platform/$(PLATFORM)/rtc.c \
+	os/platform/$(PLATFORM)/mpu.c \
+	os/platform/$(PLATFORM)/dma.c \
+	os/platform/$(PLATFORM)/crc.c \
+	os/platform/$(PLATFORM)/hostIntf.c \
+	os/platform/$(PLATFORM)/apInt.c \
+	os/platform/$(PLATFORM)/eeData.c
+
+
+#platform drivers for bootloader
+SRCS_bl += os/platform/$(PLATFORM)/pwr.c os/platform/$(PLATFORM)/gpio.c
+
+#extra deps
+DEPS += $(wildcard os/platform/$(PLATFORM)/inc/plat/*.h)
+DEPS += $(wildcard os/platform/$(PLATFORM)/inc/plat/cmsis/*.h)
+
+#linker script
+LKR_os = os/platform/$(PLATFORM)/lkr/$(CHIP).os.lkr
+LKR_bl = os/platform/$(PLATFORM)/lkr/$(CHIP).bl.lkr
+OSFLAGS_os += -Wl,-T $(LKR_os)
+OSFLAGS_bl += -Wl,-T $(LKR_bl)
+DEPS += $(LKR_os) $(LKR_bl)
+
+#platform flags
+PLATFORM_HAS_HARDWARE_CRC = true
+FLAGS += -DPLATFORM_HW_VER=0
+
+#platform-specific rules
+OBJCOPY_PARAMS = -I elf32-littlearm -O binary
+
+$(OUT)/bl.%.bin : $(OUT)/bl.%.elf
+	$(OBJCOPY) -j .bl -j .blrodata -j .eedata $(OBJCOPY_PARAMS) $< $@
+
+$(OUT)/os.%.bin : $(OUT)/os.%.elf
+	$(OBJCOPY) -j .data -j .text $(OBJCOPY_PARAMS) $< $@
+
+showsizes: $(OUT)/os.unchecked.elf
+	os/platform/$(PLATFORM)/misc/showsizes.sh $<
+
+$(info Included STM32 platfrom)
diff --git a/firmware/src/platform/stm32f4xx/syscfg.c b/firmware/os/platform/stm32/syscfg.c
index 27aa132d..845bf0d6 100644
--- a/firmware/src/platform/stm32f4xx/syscfg.c
+++ b/firmware/os/platform/stm32/syscfg.c
@@ -14,8 +14,8 @@
  * limitations under the License.
  */
 
-#include <plat/inc/pwr.h>
-#include <plat/inc/syscfg.h>
+#include <plat/pwr.h>
+#include <plat/syscfg.h>
 
 #define SYSCFG_REG_SHIFT 2
 
diff --git a/firmware/src/platform/stm32f4xx/usart.c b/firmware/os/platform/stm32/usart.c
index ae20f9c9..302cb852 100644
--- a/firmware/src/platform/stm32f4xx/usart.c
+++ b/firmware/os/platform/stm32/usart.c
@@ -14,9 +14,9 @@
  * limitations under the License.
  */
 
-#include <plat/inc/gpio.h>
-#include <plat/inc/usart.h>
-#include <plat/inc/pwr.h>
+#include <plat/gpio.h>
+#include <plat/usart.h>
+#include <plat/pwr.h>
 #include <usart.h>
 #include <gpio.h>
 
diff --git a/firmware/src/platform/stm32f4xx/wdt.c b/firmware/os/platform/stm32/wdt.c
index d29fcf11..b3c785f0 100644
--- a/firmware/src/platform/stm32f4xx/wdt.c
+++ b/firmware/os/platform/stm32/wdt.c
@@ -14,9 +14,9 @@
  * limitations under the License.
  */
 
-#include <plat/inc/pwr.h>
-#include <plat/inc/wdt.h>
-#include <plat/inc/cmsis.h>
+#include <plat/pwr.h>
+#include <plat/wdt.h>
+#include <plat/cmsis.h>
 
 struct StmWwdg {
     volatile uint16_t CR;
diff --git a/firmware/src/eventQ.c b/firmware/src/eventQ.c
deleted file mode 100644
index 6c77b09f..00000000
--- a/firmware/src/eventQ.c
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * Copyright (C) 2016 The Android Open Source Project
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include <platform.h>
-#include <eventQ.h>
-#include <stddef.h>
-#include <timer.h>
-#include <stdio.h>
-#include <heap.h>
-#include <slab.h>
-#include <cpu.h>
-#include <util.h>
-#include <plat/inc/plat.h>
-#include <plat/inc/taggedPtr.h>
-
-
-struct EvtRecord {
-    struct EvtRecord *next;
-    struct EvtRecord *prev;
-    uint32_t evtType;
-    void* evtData;
-    TaggedPtr evtFreeData;
-};
-
-struct EvtQueue {
-    struct EvtRecord *head;
-    struct EvtRecord *tail;
-    struct SlabAllocator *evtsSlab;
-    EvtQueueForciblyDiscardEvtCbkF forceDiscardCbk;
-};
-
-
-
-struct EvtQueue* evtQueueAlloc(uint32_t size, EvtQueueForciblyDiscardEvtCbkF forceDiscardCbk)
-{
-    struct EvtQueue *q = heapAlloc(sizeof(struct EvtQueue));
-    struct SlabAllocator *slab = slabAllocatorNew(sizeof(struct EvtRecord), alignof(struct EvtRecord), size);
-
-    if (q && slab) {
-        q->forceDiscardCbk = forceDiscardCbk;
-        q->evtsSlab = slab;
-        q->head = NULL;
-        q->tail = NULL;
-        return q;
-    }
-
-    if (q)
-        heapFree(q);
-    if (slab)
-        slabAllocatorDestroy(slab);
-
-    return NULL;
-}
-
-void evtQueueFree(struct EvtQueue* q)
-{
-    struct EvtRecord *t;
-
-    while (q->head) {
-        t = q->head;
-        q->head = q->head->next;
-        q->forceDiscardCbk(t->evtType, t->evtData, t->evtFreeData);
-        slabAllocatorFree(q->evtsSlab, t);
-    }
-
-    slabAllocatorDestroy(q->evtsSlab);
-    heapFree(q);
-}
-
-bool evtQueueEnqueue(struct EvtQueue* q, uint32_t evtType, void *evtData, TaggedPtr evtFreeData, bool atFront)
-{
-    struct EvtRecord *rec;
-    uint64_t intSta;
-
-    if (!q)
-        return false;
-
-    rec = slabAllocatorAlloc(q->evtsSlab);
-    if (!rec) {
-        intSta = cpuIntsOff();
-
-        //find a victim for discarding
-        rec = q->head;
-        while (rec && !(rec->evtType & EVENT_TYPE_BIT_DISCARDABLE))
-            rec = rec->next;
-
-        if (rec) {
-            q->forceDiscardCbk(rec->evtType, rec->evtData, rec->evtFreeData);
-            if (rec->prev)
-                rec->prev->next = rec->next;
-            else
-                q->head = rec->next;
-            if (rec->next)
-                rec->next->prev = rec->prev;
-            else
-                q->tail = rec->prev;
-        }
-
-        cpuIntsRestore (intSta);
-        if (!rec)
-           return false;
-    }
-
-    rec->next = NULL;
-    rec->evtType = evtType;
-    rec->evtData = evtData;
-    rec->evtFreeData = evtFreeData;
-
-    intSta = cpuIntsOff();
-
-    if (atFront) { /* this is almost always not the case */
-        rec->prev = NULL;
-        rec->next = q->head;
-        q->head = rec;
-        if (q->tail)
-            rec->next->prev = rec;
-        else
-            q->tail = rec;
-    }
-    else { /* the common case */
-        rec->prev = q->tail;
-        q->tail = rec;
-        if (q->head)
-            rec->prev->next = rec;
-        else
-            q->head = rec;
-    }
-
-    cpuIntsRestore(intSta);
-    platWake();
-    return true;
-}
-
-bool evtQueueDequeue(struct EvtQueue* q, uint32_t *evtTypeP, void **evtDataP, TaggedPtr *evtFreeDataP, bool sleepIfNone)
-{
-    struct EvtRecord *rec = NULL;
-    uint64_t intSta;
-
-    while(1) {
-        intSta = cpuIntsOff();
-
-        rec = q->head;
-        if (rec) {
-            q->head = rec->next;
-            if (q->head)
-                q->head->prev = NULL;
-            else
-                q->tail = NULL;
-            break;
-        }
-        else if (!sleepIfNone)
-            break;
-        else if (!timIntHandler()) { // check for timers. if any fire, do not sleep (since by the time callbacks run, moremight be due)
-            platSleep();     //sleep
-            timIntHandler(); //first thing when awake: check timers
-        }
-        cpuIntsRestore(intSta);
-    }
-
-    cpuIntsRestore(intSta);
-
-    if (!rec)
-        return false;
-
-    *evtTypeP = rec->evtType;
-    *evtDataP = rec->evtData;
-    *evtFreeDataP = rec->evtFreeData;
-    slabAllocatorFree(q->evtsSlab, rec);
-
-    return true;
-}
-
diff --git a/firmware/toolchain-setup.sh b/firmware/toolchain-setup.sh
new file mode 100644
index 00000000..e3a001a3
--- /dev/null
+++ b/firmware/toolchain-setup.sh
@@ -0,0 +1,16 @@
+#!/bin/bash
+
+[[ $_ != $0 ]] && echo "configuring external toolchain for nanohub" || (echo "Script has to be sourced" && exit 1)
+
+if [ ! -e $HOME/toolchains/gcc-arm-none-eabi-5_3-2016q1/bin ] ; then
+    echo Toolchain is not found, downloading
+    (mkdir -p $HOME/toolchains && cd $HOME/toolchains &&
+     wget https://launchpad.net/gcc-arm-embedded/5.0/5-2016-q1-update/+download/gcc-arm-none-eabi-5_3-2016q1-20160330-linux.tar.bz2 &&
+     tar xjf gcc-arm-none-eabi-5_3-2016q1-20160330-linux.tar.bz2 &&
+     echo Toolchain download done
+    ) || (echo Toolchain download failed)
+fi
+
+export ARM_NONE_GCC_PATH=$HOME/toolchains/gcc-arm-none-eabi-5_3-2016q1
+export CROSS_COMPILE=$ARM_NONE_GCC_PATH/bin/arm-none-eabi-
+export NANOHUB_TOOLCHAIN=$CROSS_COMPILE
diff --git a/firmware/variant/Android.mk b/firmware/variant/Android.mk
new file mode 100644
index 00000000..558a505b
--- /dev/null
+++ b/firmware/variant/Android.mk
@@ -0,0 +1,18 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+subdirs := nucleo lunchbox linux
+include $(call all-named-subdir-makefiles,$(subdirs))
diff --git a/firmware/variant/README b/firmware/variant/README
new file mode 100644
index 00000000..3cece9db
--- /dev/null
+++ b/firmware/variant/README
@@ -0,0 +1,2 @@
+for ease of source browsing this directory may contain soft links to variant directories located elsewhere;
+build scripts fully support such layout, however this is not necessary in order to build such variants.
diff --git a/firmware/variant/linux/Android.mk b/firmware/variant/linux/Android.mk
new file mode 100644
index 00000000..669b221a
--- /dev/null
+++ b/firmware/variant/linux/Android.mk
@@ -0,0 +1,33 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_PATH := $(call my-dir)
+
+include $(CLEAR_NANO_VARS)
+
+LOCAL_MODULE := libnanohub_os_linux
+LOCAL_MODULE_TAGS := optional
+LOCAL_AUX_OS_VARIANT := linux
+
+LOCAL_SRC_FILES :=      \
+
+LOCAL_C_INCLUDES := \
+    $(LOCAL_PATH)/inc \
+
+LOCAL_EXPORT_C_INCLUDE_DIRS := \
+    $(LOCAL_C_INCLUDES)
+
+include $(BUILD_NANOHUB_OS_STATIC_LIBRARY)
diff --git a/firmware/variant/linux/Makefile b/firmware/variant/linux/Makefile
new file mode 100644
index 00000000..4ba26a3f
--- /dev/null
+++ b/firmware/variant/linux/Makefile
@@ -0,0 +1,5 @@
+include linux_conf.mk
+
+SRC_PATH=../..
+
+include $(SRC_PATH)/variant/variant.mk
diff --git a/firmware/inc/variant/linux/variant.h b/firmware/variant/linux/inc/variant/variant.h
index 092ce1cb..1d02d431 100644
--- a/firmware/inc/variant/linux/variant.h
+++ b/firmware/variant/linux/inc/variant/variant.h
@@ -21,6 +21,10 @@
 extern "C" {
 #endif
 
+#define PLATFORM_HW_TYPE  0x8086
+
+#define PLAT_HAS_NO_U_TYPES_H
+
 //we have no LSE in linux
 #define HAVE_LSE    false
 
diff --git a/firmware/misc/variant/linux/Makefile b/firmware/variant/linux/linux.mk
index 9149d8cb..9149d8cb 100644
--- a/firmware/misc/variant/linux/Makefile
+++ b/firmware/variant/linux/linux.mk
diff --git a/firmware/variant/linux/linux_conf.mk b/firmware/variant/linux/linux_conf.mk
new file mode 100644
index 00000000..fac0d664
--- /dev/null
+++ b/firmware/variant/linux/linux_conf.mk
@@ -0,0 +1,26 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+# settings that apps and OS both want to know about variant
+
+VENDOR := google
+VARIANT := linux
+CPU := x86
+CHIP := x86
+PLATFORM := native
+
+# VARIANT_PATH is relative to ANDROID TOP
+VARIANT_PATH := device/google/contexthub/firmware/variant/$(VARIANT)
diff --git a/firmware/variant/lunchbox/Android.mk b/firmware/variant/lunchbox/Android.mk
new file mode 100644
index 00000000..d743a54b
--- /dev/null
+++ b/firmware/variant/lunchbox/Android.mk
@@ -0,0 +1,35 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_PATH := $(call my-dir)
+
+include $(CLEAR_NANO_VARS)
+
+LOCAL_MODULE := libnanohub_os_lunchbox
+LOCAL_MODULE_TAGS := optional
+LOCAL_AUX_OS_VARIANT := lunchbox
+
+LOCAL_SRC_FILES :=      \
+    src/os/i2c.c        \
+    src/os/spi.c        \
+
+LOCAL_C_INCLUDES := \
+    $(LOCAL_PATH)/inc \
+
+LOCAL_EXPORT_C_INCLUDE_DIRS := \
+    $(LOCAL_C_INCLUDES)
+
+include $(BUILD_NANOHUB_OS_STATIC_LIBRARY)
diff --git a/firmware/variant/lunchbox/Makefile b/firmware/variant/lunchbox/Makefile
new file mode 100644
index 00000000..a632fcea
--- /dev/null
+++ b/firmware/variant/lunchbox/Makefile
@@ -0,0 +1,6 @@
+include lunchbox_conf.mk
+
+SRC_PATH := ../..
+OUT := out/nanohub/$(VARIANT)
+
+include $(SRC_PATH)/variant/variant.mk
diff --git a/firmware/inc/variant/lunchbox/sensType.h b/firmware/variant/lunchbox/inc/variant/sensType.h
index 23cd0ef4..23cd0ef4 100644
--- a/firmware/inc/variant/lunchbox/sensType.h
+++ b/firmware/variant/lunchbox/inc/variant/sensType.h
diff --git a/firmware/inc/variant/lunchbox/variant.h b/firmware/variant/lunchbox/inc/variant/variant.h
index dafe9f23..ae499f2e 100644
--- a/firmware/inc/variant/lunchbox/variant.h
+++ b/firmware/variant/lunchbox/inc/variant/variant.h
@@ -21,6 +21,9 @@
 extern "C" {
 #endif
 
+#define PLATFORM_HW_TYPE  0x4C75   // 'Lu' -> lunchbox
+//#define DEBUG_UART_PIN    16       // GPIOB0 is debug uart at 2MBps
+
 #define VARIANT_VER                 0x00000000
 
 //we have LSE in lunchbox
diff --git a/firmware/misc/variant/lunchbox/Makefile b/firmware/variant/lunchbox/lunchbox.mk
index db18758c..59c8010e 100644
--- a/firmware/misc/variant/lunchbox/Makefile
+++ b/firmware/variant/lunchbox/lunchbox.mk
@@ -16,57 +16,50 @@
 
 #variant makefile for lunchbox
 
-ifneq ($(PLATFORM),stm32f4xx)
-        $(error "LUNCHBOX variant cannot be build on a platform that is not stm32f411")
+ifneq ($(PLATFORM),stm32)
+        $(error "LUNCHBOX variant cannot be build on a platform that is not stm32")
 endif
 
 FLAGS += -DPLATFORM_HW_TYPE=0x4C75   #'Lu' -> lunchbox
 FLAGS += -DDEBUG_UART_PIN=16         #GPIOB0 is debug uart at 2MBps
 
+FLAGS += -I$(VARIANT_PATH)/inc
 
 #board configuration shims
-SRCS_os += links/variant/src/i2c.c
-SRCS_os += links/variant/src/spi.c
-
+SRCS_os += $(VARIANT_PATH)/src/os/i2c.c
+SRCS_os += $(VARIANT_PATH)/src/os/spi.c
 #keys
 
 #drivers
 # ROHM ALS/prox
-SRCS_os += src/drivers/rohm_rpr0521/rohm_rpr0521.c
+SRCS_os += os/drivers/rohm_rpr0521/rohm_rpr0521.c
 
 # Fusion algorithms
-SRCS_os += src/algos/fusion.c src/algos/mat.c src/algos/quat.c src/algos/vec.c
+SRCS_os += os/algos/fusion.c os/algos/mat.c os/algos/quat.c os/algos/vec.c
 
 # BMI160 accel and gyro, BMM150 mag drivers
 FLAGS += -DUSE_BMM150 -DMAG_SLAVE_PRESENT
-SRCS_os += src/drivers/bosch_bmi160/bosch_bmi160.c \
-	src/drivers/bosch_bmi160/bosch_bmm150_slave.c \
-	src/algos/mag_cal.c \
-	src/algos/time_sync.c
+SRCS_os += os/drivers/bosch_bmi160/bosch_bmi160.c \
+	os/drivers/bosch_bmi160/bosch_bmm150_slave.c \
+	os/algos/mag_cal.c \
+	os/algos/time_sync.c
 
 # Orientation sensor driver
-SRCS_os += src/drivers/orientation/orientation.c
+SRCS_os += os/drivers/orientation/orientation.c
 
 # Window orientation sensor driver
-SRCS_os += src/drivers/window_orientation/window_orientation.c
+SRCS_os += os/drivers/window_orientation/window_orientation.c
 
 # Bosch BMP280 Barometer/Temperature
-SRCS_os += src/drivers/bosch_bmp280/bosch_bmp280.c
+SRCS_os += os/drivers/bosch_bmp280/bosch_bmp280.c
 
 # Hall effect sensor driver
-SRCS_os += src/drivers/hall/hall.c
+SRCS_os += os/drivers/hall/hall.c
 
 # Camera Vsync driver
-SRCS_os += src/drivers/vsync/vsync.c
+SRCS_os += os/drivers/vsync/vsync.c
 
 # Tilt detection
-SRCS_os += src/drivers/tilt_detection/tilt_detection.c
-
-DEPS += $(wildcard links/variant/inc/*.h)
+SRCS_os += os/drivers/tilt_detection/tilt_detection.c
 
-#linker script
-LKR_os = misc/variant/common/stm32f411.os.lkr
-LKR_bl = misc/variant/common/stm32f411.bl.lkr
-OSFLAGS_os += -Wl,-T $(LKR_os)
-OSFLAGS_bl += -Wl,-T $(LKR_bl)
-DEPS += $(LKR_os) $(LKR_bl)
+$(info included LUNCHBOX variant)
diff --git a/firmware/variant/lunchbox/lunchbox_conf.mk b/firmware/variant/lunchbox/lunchbox_conf.mk
new file mode 100644
index 00000000..248d6736
--- /dev/null
+++ b/firmware/variant/lunchbox/lunchbox_conf.mk
@@ -0,0 +1,26 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+# settings that apps and OS both want to know about variant
+
+VENDOR := google
+VARIANT := lunchbox
+CPU := cortexm4
+CHIP := stm32f411
+PLATFORM := stm32
+
+# VARIANT_PATH is relative to ANDROID TOP
+VARIANT_PATH := device/google/contexthub/firmware/variant/$(VARIANT)
diff --git a/firmware/src/variant/nucleo/i2c.c b/firmware/variant/lunchbox/src/os/i2c.c
index 87278a4e..ec4c899f 100644
--- a/firmware/src/variant/nucleo/i2c.c
+++ b/firmware/variant/lunchbox/src/os/i2c.c
@@ -14,7 +14,7 @@
  * limitations under the License.
  */
 
-#include <plat/inc/i2c.h>
+#include <plat/i2c.h>
 #include <util.h>
 
 static const struct StmI2cBoardCfg mStmI2cBoardCfgs[] = {
diff --git a/firmware/src/variant/lunchbox/spi.c b/firmware/variant/lunchbox/src/os/spi.c
index bbe986d8..40457bd1 100644
--- a/firmware/src/variant/lunchbox/spi.c
+++ b/firmware/variant/lunchbox/src/os/spi.c
@@ -14,7 +14,7 @@
  * limitations under the License.
  */
 
-#include <plat/inc/spi.h>
+#include <plat/spi.h>
 #include <util.h>
 
 static const struct StmSpiBoardCfg mStmSpiBoardCfgs[] = {
diff --git a/firmware/variant/nucleo/Android.mk b/firmware/variant/nucleo/Android.mk
new file mode 100644
index 00000000..1e00b258
--- /dev/null
+++ b/firmware/variant/nucleo/Android.mk
@@ -0,0 +1,35 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_PATH := $(call my-dir)
+
+include $(CLEAR_NANO_VARS)
+
+LOCAL_MODULE := libnanohub_os_nucleo
+LOCAL_MODULE_TAGS := optional
+LOCAL_AUX_OS_VARIANT := nucleo
+
+LOCAL_SRC_FILES :=      \
+    src/os/i2c.c        \
+    src/os/spi.c        \
+
+LOCAL_C_INCLUDES := \
+    $(LOCAL_PATH)/inc \
+
+LOCAL_EXPORT_C_INCLUDE_DIRS := \
+    $(LOCAL_C_INCLUDES)
+
+include $(BUILD_NANOHUB_OS_STATIC_LIBRARY)
diff --git a/firmware/variant/nucleo/Makefile b/firmware/variant/nucleo/Makefile
new file mode 100644
index 00000000..916c7f8f
--- /dev/null
+++ b/firmware/variant/nucleo/Makefile
@@ -0,0 +1,6 @@
+include nucleo_conf.mk
+
+SRC_PATH := ../..
+OUT := out/nanohub/$(VARIANT)
+
+include $(SRC_PATH)/variant/variant.mk
diff --git a/firmware/inc/variant/nucleo/sensType.h b/firmware/variant/nucleo/inc/variant/sensType.h
index 1a21b3cb..1a21b3cb 100644
--- a/firmware/inc/variant/nucleo/sensType.h
+++ b/firmware/variant/nucleo/inc/variant/sensType.h
diff --git a/firmware/inc/variant/nucleo/variant.h b/firmware/variant/nucleo/inc/variant/variant.h
index 4cefbeeb..4cefbeeb 100644
--- a/firmware/inc/variant/nucleo/variant.h
+++ b/firmware/variant/nucleo/inc/variant/variant.h
diff --git a/firmware/misc/variant/nucleo/Makefile b/firmware/variant/nucleo/nucleo.mk
index 12ba238c..af070ed7 100644
--- a/firmware/misc/variant/nucleo/Makefile
+++ b/firmware/variant/nucleo/nucleo.mk
@@ -17,58 +17,54 @@
 #variant makefile for nucleo
 
 
-ifneq ($(PLATFORM),stm32f4xx)
-        $(error "NUCLEO variant cannot be build on a platform that is not stm32f411")
+ifneq ($(PLATFORM),stm32)
+        $(error "NUCLEO variant cannot be build on a platform that is not stm32")
 endif
 
 FLAGS += -DPLATFORM_HW_TYPE=0x4E75   #'Nu' ->nucleo
 FLAGS += -DDEBUG_SWD
 
+FLAGS += -I$(VARIANT_PATH)/inc
+
 #board configuration shims
-SRCS_os += src/variant/$(VARIANT)/i2c.c
-SRCS_os += src/variant/$(VARIANT)/spi.c
+SRCS_os += $(VARIANT_PATH)/src/os/i2c.c
+SRCS_os += $(VARIANT_PATH)/src/os/spi.c
 
 #keys
 
 #drivers
 # AMS ALS/prox
-SRCS_os += src/drivers/ams_tmd2772/ams_tmd2772.c
+SRCS_os += os/drivers/ams_tmd2772/ams_tmd2772.c
 
 # ROHM ALS/prox
-SRCS_os += src/drivers/rohm_rpr0521/rohm_rpr0521.c
+SRCS_os += os/drivers/rohm_rpr0521/rohm_rpr0521.c
 
 # Fusion algorithm
-SRCS_os += src/algos/fusion.c src/algos/mat.c src/algos/quat.c src/algos/vec.c
+SRCS_os += os/algos/fusion.c os/algos/mat.c os/algos/quat.c os/algos/vec.c
 
 # BMI160 accel and gyro, BMM150 mag drivers
-FLAGS += -DUSE_BMM150
-SRCS_os += src/drivers/bosch_bmi160/bosch_bmi160.c \
-	src/drivers/bosch_bmi160/bosch_bmm150_slave.c \
-	src/algos/mag_cal.c \
-	src/algos/time_sync.c
+FLAGS += -DUSE_BMM150 -DMAG_SLAVE_PRESENT
+SRCS_os += os/drivers/bosch_bmi160/bosch_bmi160.c \
+	os/drivers/bosch_bmi160/bosch_bmm150_slave.c \
+	os/algos/mag_cal.c \
+	os/algos/time_sync.c
 
 # Orientation sensor driver
-SRCS_os += src/drivers/orientation/orientation.c
+SRCS_os += os/drivers/orientation/orientation.c
 
 # Window orientation sensor driver
-SRCS_os += src/drivers/window_orientation/window_orientation.c
+SRCS_os += os/drivers/window_orientation/window_orientation.c
 
 # Bosch BMP280 Barometer/Temperature
-SRCS_os += src/drivers/bosch_bmp280/bosch_bmp280.c
+SRCS_os += os/drivers/bosch_bmp280/bosch_bmp280.c
 
 # Hall effect sensor driver
-SRCS_os += src/drivers/hall/hall.c
+SRCS_os += os/drivers/hall/hall.c
 
 # Camera Vsync driver
-SRCS_os += src/drivers/vsync/vsync.c
+SRCS_os += os/drivers/vsync/vsync.c
 
 # Tilt detection
-SRCS_os += src/drivers/tilt_detection/tilt_detection.c
-
-#linker script
-LKR_os = misc/variant/common/stm32f411.os.lkr
-LKR_bl = misc/variant/common/stm32f411.bl.lkr
-OSFLAGS_os += -Wl,-T $(LKR_os)
-OSFLAGS_bl += -Wl,-T $(LKR_bl)
-DEPS += $(LKR_os) $(LKR_bl)
-DEPS += $(LKR)
+SRCS_os += os/drivers/tilt_detection/tilt_detection.c
+
+$(info included NUCLEO variant)
diff --git a/firmware/variant/nucleo/nucleo_conf.mk b/firmware/variant/nucleo/nucleo_conf.mk
new file mode 100644
index 00000000..e58aaff6
--- /dev/null
+++ b/firmware/variant/nucleo/nucleo_conf.mk
@@ -0,0 +1,26 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+# settings that apps and OS both want to know about variant
+
+VENDOR := google
+VARIANT := nucleo
+CPU := cortexm4
+CHIP := stm32f411
+PLATFORM := stm32
+
+# VARIANT_PATH is relative to ANDROID TOP
+VARIANT_PATH := device/google/contexthub/firmware/variant/$(VARIANT)
diff --git a/firmware/src/variant/lunchbox/i2c.c b/firmware/variant/nucleo/src/os/i2c.c
index 87278a4e..ec4c899f 100644
--- a/firmware/src/variant/lunchbox/i2c.c
+++ b/firmware/variant/nucleo/src/os/i2c.c
@@ -14,7 +14,7 @@
  * limitations under the License.
  */
 
-#include <plat/inc/i2c.h>
+#include <plat/i2c.h>
 #include <util.h>
 
 static const struct StmI2cBoardCfg mStmI2cBoardCfgs[] = {
diff --git a/firmware/src/variant/nucleo/spi.c b/firmware/variant/nucleo/src/os/spi.c
index 6a694522..d75824c5 100644
--- a/firmware/src/variant/nucleo/spi.c
+++ b/firmware/variant/nucleo/src/os/spi.c
@@ -14,7 +14,7 @@
  * limitations under the License.
  */
 
-#include <plat/inc/spi.h>
+#include <plat/spi.h>
 #include <util.h>
 
 static const struct StmSpiBoardCfg mStmSpiBoardCfgs[] = {
diff --git a/firmware/variant/variant.mk b/firmware/variant/variant.mk
new file mode 100644
index 00000000..fad20c3f
--- /dev/null
+++ b/firmware/variant/variant.mk
@@ -0,0 +1,77 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+PLATFORM?=stm32
+CPU?=cortexm4
+CHIP?=stm32f411
+
+# SRC_PATH points to "firmware"; TOP_PATH is the abs path to top of andrlid tree
+TOP_RELPATH := ../../../..
+TOP_ABSPATH := $(realpath $(SRC_PATH)/$(TOP_RELPATH))
+VARIANT_ABSPATH := $(TOP_ABSPATH)/$(VARIANT_PATH)
+VARIANT_PATH := $(TOP_RELPATH)/$(VARIANT_PATH)
+
+ifndef OUT
+OUT:=out/nanohub/$(VARIANT)
+MAKE_OUT=$(VARIANT_PATH)/$(OUT)
+else
+ifneq ($(filter $(TOP_ABSPATH)/out/target/product/%,$(OUT)),)
+# this looks like Android OUT env var; update it
+OUT:=$(OUT)/nanohub/$(VARIANT)
+IMAGE_TARGET_OUT:=vendor/firmware/nanohub.full.bin
+endif
+MAKE_OUT:=$(OUT)
+endif
+
+ifdef IMAGE_TARGET_OUT
+IMAGE_TARGET_OUT_ELF := $(patsubst %.bin,%.elf,$(IMAGE_TARGET_OUT))
+endif
+
+ifdef IMAGE_OUT
+IMAGE_OUT_ELF := $(patsubst %.bin,%.elf,$(IMAGE_OUT))
+endif
+
+.PHONY: all clean sync
+
+all:
+	make -C $(SRC_PATH) -f firmware.mk VARIANT=$(VARIANT) VARIANT_PATH=$(VARIANT_PATH) OUT=$(MAKE_OUT) PLATFORM=$(PLATFORM) CPU=$(CPU) CHIP=$(CHIP) $(EXTRA_ARGS)
+ifdef IMAGE_OUT
+	cd $(VARIANT_ABSPATH) && \
+	cp $(OUT)/full.bin $(IMAGE_OUT) && \
+	cp $(OUT)/os.unchecked.elf $(IMAGE_OUT_ELF) && \
+	chmod -x $(IMAGE_OUT_ELF)
+endif
+ifdef IMAGE_TARGET_OUT
+	cd $(VARIANT_ABSPATH) && \
+	mkdir -p $(dir $(TOP_ABSPATH)/$(IMAGE_TARGET_OUT)) && \
+	cp $(OUT)/full.bin $(TOP_ABSPATH)/$(IMAGE_TARGET_OUT) && \
+	cp $(OUT)/os.unchecked.elf $(TOP_ABSPATH)/$(IMAGE_TARGET_OUT_ELF)
+	chmod -x $(TOP_ABSPATH)/$(IMAGE_TARGET_OUT_ELF)
+endif
+
+clean:
+	rm -rf $(OUT)
+ifdef IMAGE_OUT
+	rm $(VARIANT_ABSPATH)/$(IMAGE_OUT)
+	rm $(VARIANT_ABSPATH)/$(IMAGE_OUT_ELF)
+endif
+ifdef IMAGE_TARGET_OUT
+	rm $(TOP_ABSPATH)/$(IMAGE_TARGET_OUT)
+	rm $(TOP_ABSPATH)/$(IMAGE_TARGET_OUT_ELF)
+endif
+
+sync:
+	adb push $(OUT)/full.bin /vendor/firmware/nanohub.full.bin
diff --git a/inc/chre.h b/inc/chre.h
index 3cad8930..55fed265 100644
--- a/inc/chre.h
+++ b/inc/chre.h
@@ -30,11 +30,11 @@
  * for overall platform information.
  */
 
-#include "chre_event.h"
-#include "chre_nanoapp.h"
-#include "chre_re.h"
-#include "chre_sensor.h"
-#include "chre_version.h"
+#include <chre/event.h>
+#include <chre/nanoapp.h>
+#include <chre/re.h>
+#include <chre/sensor.h>
+#include <chre/version.h>
 
 
 /**
diff --git a/inc/chre_event.h b/inc/chre/event.h
index 465c40ac..465c40ac 100644
--- a/inc/chre_event.h
+++ b/inc/chre/event.h
diff --git a/inc/chre_nanoapp.h b/inc/chre/nanoapp.h
index 78a8accd..78a8accd 100644
--- a/inc/chre_nanoapp.h
+++ b/inc/chre/nanoapp.h
diff --git a/inc/chre_re.h b/inc/chre/re.h
index 31b0ed7c..31b0ed7c 100644
--- a/inc/chre_re.h
+++ b/inc/chre/re.h
diff --git a/inc/chre_sensor.h b/inc/chre/sensor.h
index eafedd96..1b350c52 100644
--- a/inc/chre_sensor.h
+++ b/inc/chre/sensor.h
@@ -29,7 +29,7 @@
 #include <stdint.h>
 
 // For CHRE_EVENT_SENSOR_FIRST_EVENT and CHRE_EVENT_SENSOR_LAST_EVENT
-#include "chre_event.h"
+#include <chre/event.h>
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/inc/chre_version.h b/inc/chre/version.h
index ae6b14ca..ae6b14ca 100644
--- a/inc/chre_version.h
+++ b/inc/chre/version.h
diff --git a/lib/Android.mk b/lib/Android.mk
new file mode 100644
index 00000000..e88b9757
--- /dev/null
+++ b/lib/Android.mk
@@ -0,0 +1,78 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+LOCAL_PATH := $(call my-dir)
+
+src_files := \
+    nanohub/aes.c \
+    nanohub/rsa.c \
+    nanohub/sha2.c \
+    nanohub/softcrc.c \
+
+src_includes := \
+    $(LOCAL_PATH)/include \
+
+include $(CLEAR_NANO_VARS)
+
+LOCAL_MODULE := libnanohub_common_bl
+LOCAL_MODULE_TAGS := optional
+
+LOCAL_SRC_FILES := $(src_files)
+LOCAL_C_INCLUDES := $(src_includes)
+LOCAL_EXPORT_C_INCLUDE_DIRS := $(src_includes)
+
+include $(BUILD_NANOHUB_BL_STATIC_LIBRARY)
+
+include $(CLEAR_VARS)
+
+LOCAL_MODULE := libnanohub_common
+LOCAL_MODULE_TAGS := optional
+LOCAL_SRC_FILES := \
+    $(src_files) \
+    nanohub/nanoapp.c \
+
+LOCAL_CFLAGS := \
+    -DHOST_BUILD \
+    -DRSA_SUPPORT_PRIV_OP_BIGRAM \
+
+LOCAL_C_INCLUDES := \
+    $(src_includes)
+
+LOCAL_EXPORT_C_INCLUDE_DIRS := \
+    $(src_includes)
+
+LOCAL_MULTILIB := both
+
+include $(BUILD_HOST_STATIC_LIBRARY)
+
+include $(CLEAR_VARS)
+
+# now-empty static library to export include files for other projects
+LOCAL_MODULE := libnanohub_common
+LOCAL_MODULE_TAGS := optional
+
+LOCAL_C_INCLUDES := \
+    $(src_includes)
+
+LOCAL_EXPORT_C_INCLUDE_DIRS := \
+    $(src_includes)
+
+include $(BUILD_STATIC_LIBRARY)
+
+include $(call first-makefiles-under, $(LOCAL_PATH))
+
+src_files :=
+src_includes :=
diff --git a/lib/include/nanohub/crc.h b/lib/include/nanohub/crc.h
index 96b7e4c4..35d716e4 100644
--- a/lib/include/nanohub/crc.h
+++ b/lib/include/nanohub/crc.h
@@ -38,4 +38,8 @@
  */
 uint32_t crc32(const void *buf, size_t size, uint32_t crc);
 
+/* concrete public implementation of crc32() w/o HW acceleration */
+uint32_t soft_crc32(const void *buf, size_t size, uint32_t crc);
+
+
 #endif /* _NANOHUB_CRC_H_ */
diff --git a/lib/include/nanohub/nanoapp.h b/lib/include/nanohub/nanoapp.h
index da6f341f..06aa6000 100644
--- a/lib/include/nanohub/nanoapp.h
+++ b/lib/include/nanohub/nanoapp.h
@@ -20,6 +20,10 @@
 #include <stdint.h>
 #include <stdbool.h>
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 void *reallocOrDie(void *buf, size_t bufSz);
 void assertMem(size_t used, size_t total);
 bool readFile(void *dst, uint32_t len, const char *fileName);
@@ -27,4 +31,8 @@ void *loadFile(const char *fileName, uint32_t *size);
 void printHash(FILE *out, const char *pfx, const uint32_t *hash, size_t size);
 void printHashRev(FILE *out, const char *pfx, const uint32_t *hash, size_t size);
 
+#ifdef __cplusplus
+}; /* extern "C" */
+#endif
+
 #endif /* _NANOHUB_NANOAPP_H_ */
diff --git a/lib/include/nanohub/nanohub.h b/lib/include/nanohub/nanohub.h
index 53c51895..451df9dd 100644
--- a/lib/include/nanohub/nanohub.h
+++ b/lib/include/nanohub/nanohub.h
@@ -26,6 +26,11 @@
  * generate/parse compatible images
  */
 
+#define NANOHUB_OS_PATCH_LEVEL  0x0000
+
+#define NANOHUB_VENDOR_GOOGLE      UINT64_C(0x476F6F676C) // "Googl"
+#define NANOHUB_VENDOR_STMICRO     UINT64_C(0x53544d6963) // "STMic"
+
 #define NANOAPP_SIGNED_FLAG    0x1  // contents is signed with one or more signature block(s)
 #define NANOAPP_ENCRYPTED_FLAG 0x2  // contents is encrypted with exactly one encryption key
 
@@ -33,7 +38,16 @@
 #define NANOAPP_FW_MAGIC (((uint32_t)'N' <<  0) | ((uint32_t)'B' <<  8) | ((uint32_t)'I' << 16) | ((uint32_t)'N' << 24))
 #define GOOGLE_LAYOUT_MAGIC (((uint32_t)'G' <<  0) | ((uint32_t)'o' <<  8) | ((uint32_t)'o' << 16) | ((uint32_t)'g' << 24))
 
-// The binary format below is in little endian format
+#define APP_ID_ANY                 UINT64_C(0xFFFFFFFFFFFFFFFF)
+#define APP_VENDOR_ANY             UINT64_C(0xFFFFFFFFFF)
+#define APP_VENDOR_SHF             (24)
+#define APP_SEQ_ID_ANY             UINT32_C(0xFFFFFF)
+#define APP_ID_GET_VENDOR(appid)   ((appid) >> APP_VENDOR_SHF)
+#define APP_ID_GET_SEQ_ID(appid)   ((appid) & APP_SEQ_ID_ANY)
+#define APP_ID_MAKE(vendor, app)   ((((uint64_t)(vendor)) << APP_VENDOR_SHF) | ((app) & APP_SEQ_ID_ANY))
+
+#ifndef CONTEXT_HUB_H
+// The binary format below is in little endian format; borrowed from CONTEXT_HUB_H
 struct nano_app_binary_t {
     uint32_t header_version;       // 0x1 for this version
     uint32_t magic;                // "NANO"
@@ -45,6 +59,21 @@ struct nano_app_binary_t {
     uint8_t  custom_binary[0];     // start of custom binary data
 };
 
+#endif
+
+struct HostMsgHdr {
+    uint32_t eventId;
+    uint64_t appId;
+    uint8_t len;
+} __attribute__((packed));
+
+struct HostMsgHdrChre {
+    uint32_t eventId;
+    uint64_t appId;
+    uint8_t len;
+    uint32_t appEventId;
+} __attribute__((packed));
+
 // we translate AOSP header into FW header: this header is in LE format
 // please maintain natural alignment for every field (matters to Intel; otherwise is has to be declared as packed)
 struct FwCommonHdr {
diff --git a/lib/nanohub/softcrc.c b/lib/nanohub/softcrc.c
index fb2b7119..286e36b4 100644
--- a/lib/nanohub/softcrc.c
+++ b/lib/nanohub/softcrc.c
@@ -29,7 +29,7 @@ static const uint32_t crctab[] =
 
 static uint32_t crcOneWord(uint32_t crc, uint32_t data, int cnt)
 {
-        uint32_t i;
+        int i;
 
         crc = crc ^ data;
         for (i = 0; i < cnt; i++)
@@ -38,11 +38,12 @@ static uint32_t crcOneWord(uint32_t crc, uint32_t data, int cnt)
         return crc;
 }
 
-uint32_t crc32(const void *buf, size_t size, uint32_t crc)
+uint32_t soft_crc32(const void *buf, size_t size, uint32_t crc)
 {
         const uint32_t *data32 = (const uint32_t *)buf;
         const uint8_t *data8;
-        uint32_t word, i;
+        uint32_t word;
+        size_t i;
 
         // word by word crc32
         for (i = 0; i < size / 4; i++)
diff --git a/sensorhal/Android.mk b/sensorhal/Android.mk
index 2a680076..cdda9d99 100644
--- a/sensorhal/Android.mk
+++ b/sensorhal/Android.mk
@@ -56,7 +56,7 @@ LOCAL_MODULE_OWNER := google
 LOCAL_CFLAGS += $(COMMON_CFLAGS)
 
 LOCAL_C_INCLUDES += \
-	device/google/contexthub/firmware/inc \
+	device/google/contexthub/firmware/os/inc \
 	device/google/contexthub/util/common
 
 LOCAL_SRC_FILES := \
@@ -84,7 +84,7 @@ LOCAL_MODULE_OWNER := google
 LOCAL_CFLAGS += $(COMMON_CFLAGS)
 
 LOCAL_C_INCLUDES += \
-	device/google/contexthub/firmware/inc \
+	device/google/contexthub/firmware/os/inc \
 	device/google/contexthub/util/common
 
 LOCAL_SRC_FILES := \
@@ -122,7 +122,7 @@ LOCAL_CFLAGS += -DDOUBLE_TOUCH_ENABLED
 endif
 
 LOCAL_C_INCLUDES += \
-	device/google/contexthub/firmware/inc \
+	device/google/contexthub/firmware/os/inc \
 	device/google/contexthub/util/common
 
 LOCAL_SRC_FILES := \
@@ -135,6 +135,7 @@ LOCAL_SHARED_LIBRARIES := \
 	libcutils \
 	liblog \
 	libstagefright_foundation \
+	libhardware_legacy \
 	libutils
 
 include $(BUILD_SHARED_LIBRARY)
diff --git a/sensorhal/hubconnection.cpp b/sensorhal/hubconnection.cpp
index b43f7ab9..909d7b1e 100644
--- a/sensorhal/hubconnection.cpp
+++ b/sensorhal/hubconnection.cpp
@@ -29,13 +29,15 @@
 #include <unistd.h>
 #include <math.h>
 #include <inttypes.h>
+#include <sched.h>
+#include <sys/inotify.h>
 
-#include <cutils/properties.h>
 #include <linux/input.h>
 #include <linux/uinput.h>
+
+#include <cutils/properties.h>
+#include <hardware_legacy/power.h>
 #include <media/stagefright/foundation/ADebug.h>
-#include <sched.h>
-#include <sys/inotify.h>
 
 #define APP_ID_GET_VENDOR(appid)       ((appid) >> 24)
 #define APP_ID_MAKE(vendor, app)       ((((uint64_t)(vendor)) << 24) | ((app) & 0x00FFFFFF))
@@ -116,6 +118,9 @@ HubConnection::HubConnection()
     mPollFds[0].revents = 0;
     mNumPollFds = 1;
 
+    mWakelockHeld = false;
+    mWakeEventCount = 0;
+
     initNanohubLock();
 
 #ifdef USB_MAG_BIAS_REPORTING_ENABLED
@@ -407,6 +412,49 @@ sensors_event_t *HubConnection::initEv(sensors_event_t *ev, uint64_t timestamp,
     return ev;
 }
 
+ssize_t HubConnection::getWakeEventCount()
+{
+    return mWakeEventCount;
+}
+
+ssize_t HubConnection::decrementWakeEventCount()
+{
+    return --mWakeEventCount;
+}
+
+bool HubConnection::isWakeEvent(int32_t sensor)
+{
+    switch (sensor) {
+    case COMMS_SENSOR_PROXIMITY:
+    case COMMS_SENSOR_SIGNIFICANT_MOTION:
+    case COMMS_SENSOR_TILT:
+    case COMMS_SENSOR_DOUBLE_TWIST:
+    case COMMS_SENSOR_GESTURE:
+        return true;
+    default:
+        return false;
+    }
+}
+
+void HubConnection::protectIfWakeEvent(int32_t sensor)
+{
+    if (isWakeEvent(sensor)) {
+        if (mWakelockHeld == false) {
+            acquire_wake_lock(PARTIAL_WAKE_LOCK, WAKELOCK_NAME);
+            mWakelockHeld = true;
+        }
+        mWakeEventCount++;
+    }
+}
+
+void HubConnection::releaseWakeLockIfAppropriate()
+{
+    if (mWakelockHeld && (mWakeEventCount == 0)) {
+        mWakelockHeld = false;
+        release_wake_lock(WAKELOCK_NAME);
+    }
+}
+
 void HubConnection::processSample(uint64_t timestamp, uint32_t type, uint32_t sensor, struct OneAxisSample *sample, __attribute__((unused)) bool highAccuracy)
 {
     sensors_event_t nev[1];
@@ -472,8 +520,11 @@ void HubConnection::processSample(uint64_t timestamp, uint32_t type, uint32_t se
         break;
     }
 
-    if (cnt > 0)
+    if (cnt > 0) {
+        // If event is a wake event, protect it with a wakelock
+        protectIfWakeEvent(sensor);
         mRing.write(nev, cnt);
+    }
 }
 
 void HubConnection::magAccuracyUpdate(float x, float y, float z)
@@ -509,8 +560,11 @@ void HubConnection::processSample(uint64_t timestamp, uint32_t type, uint32_t se
         break;
     }
 
-    if (cnt > 0)
+    if (cnt > 0) {
+        // If event is a wake event, protect it with a wakelock
+        protectIfWakeEvent(sensor);
         mRing.write(nev, cnt);
+    }
 }
 
 void HubConnection::processSample(uint64_t timestamp, uint32_t type, uint32_t sensor, struct ThreeAxisSample *sample, bool highAccuracy)
@@ -640,8 +694,11 @@ void HubConnection::processSample(uint64_t timestamp, uint32_t type, uint32_t se
         break;
     }
 
-    if (cnt > 0)
+    if (cnt > 0) {
+        // If event is a wake event, protect it with a wakelock
+        protectIfWakeEvent(sensor);
         mRing.write(nev, cnt);
+    }
 }
 
 void HubConnection::discardInotifyEvent() {
diff --git a/sensorhal/hubconnection.h b/sensorhal/hubconnection.h
index 20d3c326..77b5fe1d 100644
--- a/sensorhal/hubconnection.h
+++ b/sensorhal/hubconnection.h
@@ -32,6 +32,8 @@
 #include "hubdefs.h"
 #include "ring.h"
 
+#define WAKELOCK_NAME "sensorHal"
+
 namespace android {
 
 struct HubConnection : public Thread {
@@ -57,6 +59,11 @@ struct HubConnection : public Thread {
     void queueFlush(int handle);
     void queueData(int handle, void *data, size_t length);
 
+    bool isWakeEvent(int32_t sensor);
+    void releaseWakeLockIfAppropriate();
+    ssize_t getWakeEventCount();
+    ssize_t decrementWakeEventCount();
+
     ssize_t read(sensors_event_t *ev, size_t size);
 
     void setActivityCallback(ActivityEventHandler *eventHandler);
@@ -72,6 +79,11 @@ protected:
 private:
     typedef uint32_t rate_q10_t;  // q10 means lower 10 bits are for fractions
 
+    bool mWakelockHeld;
+    int32_t mWakeEventCount;
+
+    void protectIfWakeEvent(int32_t sensor);
+
     static inline uint64_t period_ns_to_frequency_q10(nsecs_t period_ns) {
         return 1024000000000ULL / period_ns;
     }
diff --git a/sensorhal/sensors.cpp b/sensorhal/sensors.cpp
index bf8b668c..77ab3ba8 100644
--- a/sensorhal/sensors.cpp
+++ b/sensorhal/sensors.cpp
@@ -95,12 +95,30 @@ int SensorContext::setDelay(int handle, int64_t delayNs) {
 int SensorContext::poll(sensors_event_t *data, int count) {
     ALOGV("poll");
 
+    // Release wakelock if held and no more events in ring buffer
+    mHubConnection->releaseWakeLockIfAppropriate();
+
     ssize_t n = mHubConnection->read(data, count);
 
     if (n < 0) {
         return -1;
     }
 
+    // If we have wake events in the queue, determine how many we're sending
+    // up this round and decrement that count now so that when we get called back,
+    // we'll have an accurate count of how many wake events are STILL in the HAL queue
+    // to be able to determine whether we can release our wakelock if held.
+    if (mHubConnection->getWakeEventCount() != 0) {
+        for (ssize_t i = 0; i < n; i++) {
+            if (mHubConnection->isWakeEvent(data[i].sensor)) {
+                ssize_t count = mHubConnection->decrementWakeEventCount();
+                if (count == 0) {
+                    break;
+                }
+            }
+        }
+    }
+
     return n;
 }
 
diff --git a/util/nanoapp_cmd/Android.mk b/util/nanoapp_cmd/Android.mk
index b9eb4934..80af7540 100644
--- a/util/nanoapp_cmd/Android.mk
+++ b/util/nanoapp_cmd/Android.mk
@@ -19,7 +19,7 @@ include $(CLEAR_VARS)
 
 LOCAL_SRC_FILES:= nanoapp_cmd.c
 
-LOCAL_C_INCLUDES := $(LOCAL_PATH)/../../firmware/inc
+LOCAL_C_INCLUDES := $(LOCAL_PATH)/../../firmware/os/inc
 LOCAL_CFLAGS := -Wall -Werror -Wextra
 
 LOCAL_MODULE:= nanoapp_cmd
@@ -27,8 +27,7 @@ LOCAL_MODULE:= nanoapp_cmd
 LOCAL_MODULE_TAGS:= optional
 LOCAL_MODULE_OWNER := google
 
-LOCAL_LDLIBS := \
-	-L$(SYSROOT)/usr/lib -llog
+LOCAL_LDLIBS := -llog
 
 LOCAL_SHARED_LIBRARIES := \
 	libutils \
diff --git a/util/nanoapp_encr/Android.mk b/util/nanoapp_encr/Android.mk
index 4d64acc6..84444e12 100644
--- a/util/nanoapp_encr/Android.mk
+++ b/util/nanoapp_encr/Android.mk
@@ -20,9 +20,6 @@ include $(CLEAR_VARS)
 
 
 LOCAL_SRC_FILES := \
-    ../../lib/nanohub/aes.c \
-    ../../lib/nanohub/sha2.c \
-    ../../lib/nanohub/nanoapp.c \
     nanoapp_encr.c \
 
 
@@ -34,9 +31,7 @@ LOCAL_CFLAGS := \
         -DBOOTLOADER= \
         -DBOOTLOADER_RO= \
 
-
-LOCAL_C_INCLUDES := \
-        device/google/contexthub/lib/include \
+LOCAL_STATIC_LIBRARIES := libnanohub_common
 
 LOCAL_MODULE := nanoapp_encr
 
diff --git a/util/nanoapp_postprocess/Android.mk b/util/nanoapp_postprocess/Android.mk
index 89a62a3b..9b4539be 100644
--- a/util/nanoapp_postprocess/Android.mk
+++ b/util/nanoapp_postprocess/Android.mk
@@ -23,18 +23,16 @@ LOCAL_PATH := $(call my-dir)
 include $(CLEAR_VARS)
 
 LOCAL_SRC_FILES := \
-    postprocess.c \
-    ../../lib/nanohub/nanoapp.c \
+    postprocess_elf.c \
 
 LOCAL_CFLAGS := -Wall -Werror -Wextra
 
-LOCAL_C_INCLUDES += \
-    device/google/contexthub/lib/include \
+LOCAL_STATIC_LIBRARIES := libnanohub_common
 
 LOCAL_MODULE := nanoapp_postprocess
 
 # libelf needed for ELF parsing support, libz required by libelf
-LOCAL_STATIC_LIBRARIES := libelf libz
+LOCAL_STATIC_LIBRARIES += libelf libz
 
 # Statically linking libc++ so this binary can be copied out of the tree and
 # still work (needed by dependencies)
diff --git a/util/nanoapp_postprocess/Makefile b/util/nanoapp_postprocess/Makefile
index 9b059162..772fe5de 100644
--- a/util/nanoapp_postprocess/Makefile
+++ b/util/nanoapp_postprocess/Makefile
@@ -15,7 +15,7 @@
 #
 
 APP = nanoapp_postprocess
-SRC = postprocess.c ../../lib/nanohub/nanoapp.c
+SRC = postprocess_elf.c ../../lib/nanohub/nanoapp.c
 CC ?= gcc
 CC_FLAGS = -Wall -Wextra -Werror -I../../lib/include --std=c99
 
diff --git a/util/nanoapp_postprocess/postprocess.c b/util/nanoapp_postprocess/postprocess.c
index 739454ce..18602e99 100644
--- a/util/nanoapp_postprocess/postprocess.c
+++ b/util/nanoapp_postprocess/postprocess.c
@@ -16,8 +16,6 @@
 
 #include <assert.h>
 #include <fcntl.h>
-#include <gelf.h>
-#include <libelf.h>
 #include <sys/types.h>
 #include <stdbool.h>
 #include <unistd.h>
@@ -34,11 +32,11 @@
 
 //This code assumes it is run on a LE CPU with unaligned access abilities. Sorry.
 
-#define FLASH_BASE  0x10000000
-#define RAM_BASE    0x80000000
+#define FLASH_BASE  0x10000000u
+#define RAM_BASE    0x80000000u
 
-#define FLASH_SIZE  0x10000000  //256MB ought to be enough for everyone
-#define RAM_SIZE    0x10000000  //256MB ought to be enough for everyone
+#define FLASH_SIZE  0x10000000u  //256MB ought to be enough for everyone
+#define RAM_SIZE    0x10000000u  //256MB ought to be enough for everyone
 
 //caution: double evaluation
 #define IS_IN_RANGE_E(_val, _rstart, _rend) (((_val) >= (_rstart)) && ((_val) < (_rend)))
@@ -72,115 +70,128 @@ struct NanoRelocEntry {
     uint8_t type;
 };
 
+struct NanoAppInfo {
+    union {
+        struct BinHdr *bin;
+        uint8_t *data;
+    };
+    size_t dataSizeUsed;
+    size_t dataSizeAllocated;
+    size_t codeAndDataSize;   // not including symbols, relocs and BinHdr
+    size_t codeAndRoDataSize; // also not including GOT & RW data in flash
+    struct SymtabEntry *symtab;
+    size_t symtabSize; // number of symbols
+    struct RelocEntry *reloc;
+    size_t relocSize; // number of reloc entries
+    struct NanoRelocEntry *nanoReloc;
+    size_t nanoRelocSize; // number of nanoReloc entries <= relocSize
+    uint8_t *packedNanoReloc;
+    size_t packedNanoRelocSize;
+
+    bool debug;
+};
+
 #ifndef ARRAY_SIZE
 #define ARRAY_SIZE(ary) (sizeof(ary) / sizeof((ary)[0]))
 #endif
 
-#define DBG(fmt, ...) printf(fmt "\n", ##__VA_ARGS__)
-#define ERR(fmt, ...) fprintf(stderr, fmt "\n", ##__VA_ARGS__)
-
-// Prints the given message followed by the most recent libelf error
-#define ELF_ERR(fmt, ...) ERR(fmt ": %s\n", ##__VA_ARGS__, elf_errmsg(-1))
-
-struct ElfAppSection {
-    void  *data;
-    size_t size;
-};
-
-struct ElfNanoApp {
-    struct ElfAppSection flash;
-    struct ElfAppSection data;
-    struct ElfAppSection relocs;
-    struct ElfAppSection symtab;
+static FILE *stdlog = NULL;
 
-    // Not parsed from file, but constructed via genElfNanoRelocs
-    struct ElfAppSection packedNanoRelocs;
-};
+#define DBG(fmt, ...) fprintf(stdlog, fmt "\n", ##__VA_ARGS__)
+#define ERR(fmt, ...) fprintf(stderr, fmt "\n", ##__VA_ARGS__)
 
 static void fatalUsage(const char *name, const char *msg, const char *arg)
 {
     if (msg && arg)
-        fprintf(stderr, "Error: %s: %s\n\n", msg, arg);
+        ERR("Error: %s: %s\n", msg, arg);
     else if (msg)
-        fprintf(stderr, "Error: %s\n\n", msg);
-
-    fprintf(stderr, "USAGE: %s [-v] [-k <key id>] [-a <app id>] [-r] [-n <layout name>] [-i <layout id>] <input file> [<output file>]\n"
-                    "       -v               : be verbose\n"
-                    "       -n <layout name> : app, os, key\n"
-                    "       -i <layout id>   : 1 (app), 2 (key), 3 (os)\n"
-                    "       -f <layout flags>: 16-bit hex value, stored as layout-specific flags\n"
-                    "       -a <app ID>      : 64-bit hex number != 0\n"
-                    "       -k <key ID>      : 64-bit hex number != 0\n"
-                    "       -r               : bare (no AOSP header); used only for inner OS image generation\n"
-                    "       -s               : treat input as statically linked ELF (app layout only)\n"
-                    "       layout ID and layout name control the same parameter, so only one of them needs to be used\n"
-                    , name);
+        ERR("Error: %s\n", msg);
+
+    ERR("USAGE: %s [-v] [-k <key id>] [-a <app id>] [-r] [-n <layout name>] [-i <layout id>] <input file> [<output file>]\n"
+        "       -v               : be verbose\n"
+        "       -n <layout name> : app, os, key\n"
+        "       -i <layout id>   : 1 (app), 2 (key), 3 (os)\n"
+        "       -f <layout flags>: 16-bit hex value, stored as layout-specific flags\n"
+        "       -a <app ID>      : 64-bit hex number != 0\n"
+        "       -k <key ID>      : 64-bit hex number != 0\n"
+        "       -r               : bare (no AOSP header); used only for inner OS image generation\n"
+        "       layout ID and layout name control the same parameter, so only one of them needs to be used\n"
+        , name);
     exit(1);
 }
 
-static uint8_t *packNanoRelocs(struct NanoRelocEntry *nanoRelocs, uint32_t outNumRelocs, uint32_t *finalPackedNanoRelocSz, bool verbose)
+bool packNanoRelocs(struct NanoAppInfo *app)
 {
-    uint32_t i, j, k;
+    size_t i, j, k;
     uint8_t *packedNanoRelocs;
     uint32_t packedNanoRelocSz;
     uint32_t lastOutType = 0, origin = 0;
+    bool verbose = app->debug;
 
     //sort by type and then offset
-    for (i = 0; i < outNumRelocs; i++) {
+    for (i = 0; i < app->nanoRelocSize; i++) {
         struct NanoRelocEntry t;
 
-        for (k = i, j = k + 1; j < outNumRelocs; j++) {
-            if (nanoRelocs[j].type > nanoRelocs[k].type)
+        for (k = i, j = k + 1; j < app->nanoRelocSize; j++) {
+            if (app->nanoReloc[j].type > app->nanoReloc[k].type)
                 continue;
-            if ((nanoRelocs[j].type < nanoRelocs[k].type) || (nanoRelocs[j].ofstInRam < nanoRelocs[k].ofstInRam))
+            if ((app->nanoReloc[j].type < app->nanoReloc[k].type) || (app->nanoReloc[j].ofstInRam < app->nanoReloc[k].ofstInRam))
                 k = j;
         }
-        memcpy(&t, nanoRelocs + i, sizeof(struct NanoRelocEntry));
-        memcpy(nanoRelocs + i, nanoRelocs + k, sizeof(struct NanoRelocEntry));
-        memcpy(nanoRelocs + k, &t, sizeof(struct NanoRelocEntry));
+        memcpy(&t, app->nanoReloc + i, sizeof(struct NanoRelocEntry));
+        memcpy(app->nanoReloc + i, app->nanoReloc + k, sizeof(struct NanoRelocEntry));
+        memcpy(app->nanoReloc + k, &t, sizeof(struct NanoRelocEntry));
 
-        if (verbose)
-            fprintf(stderr, "SortedReloc[%3" PRIu32 "] = {0x%08" PRIX32 ",0x%02" PRIX8 "}\n", i, nanoRelocs[i].ofstInRam, nanoRelocs[i].type);
+        if (app->debug)
+            DBG("SortedReloc[%3zu] = {0x%08" PRIX32 ",0x%02" PRIX8 "}", i, app->nanoReloc[i].ofstInRam, app->nanoReloc[i].type);
     }
 
     //produce output nanorelocs in packed format
-    packedNanoRelocs = malloc(outNumRelocs * 6); //definitely big enough
+    packedNanoRelocs = malloc(app->nanoRelocSize * 6); //definitely big enough
     packedNanoRelocSz = 0;
-    for (i = 0; i < outNumRelocs; i++) {
+
+    if (!packedNanoRelocs) {
+        ERR("Failed to allocate memory for packed relocs");
+        return false;
+    }
+
+    for (i = 0; i < app->nanoRelocSize; i++) {
         uint32_t displacement;
 
-        if (lastOutType != nanoRelocs[i].type) {  //output type if ti changed
-            if (nanoRelocs[i].type - lastOutType == 1) {
+        if (lastOutType != app->nanoReloc[i].type) {  //output type if ti changed
+            if (app->nanoReloc[i].type - lastOutType == 1) {
                 packedNanoRelocs[packedNanoRelocSz++] = TOKEN_RELOC_TYPE_NEXT;
                 if (verbose)
-                    fprintf(stderr, "Out: RelocTC (1) // to 0x%02" PRIX8 "\n", nanoRelocs[i].type);
-            }
-            else {
+                    DBG("Out: RelocTC [size 1] // to 0x%02" PRIX8, app->nanoReloc[i].type);
+            } else {
                 packedNanoRelocs[packedNanoRelocSz++] = TOKEN_RELOC_TYPE_CHG;
-                packedNanoRelocs[packedNanoRelocSz++] = nanoRelocs[i].type - lastOutType - 1;
+                packedNanoRelocs[packedNanoRelocSz++] = app->nanoReloc[i].type - lastOutType - 1;
                 if (verbose)
-                    fprintf(stderr, "Out: RelocTC (0x%02" PRIX8 ")  // to 0x%02" PRIX8 "\n", (uint8_t)(nanoRelocs[i].type - lastOutType - 1), nanoRelocs[i].type);
+                    DBG("Out: RelocTC [size 2] (0x%02" PRIX8 ")  // to 0x%02" PRIX8,
+                        (uint8_t)(app->nanoReloc[i].type - lastOutType - 1), app->nanoReloc[i].type);
             }
-            lastOutType = nanoRelocs[i].type;
+            lastOutType = app->nanoReloc[i].type;
             origin = 0;
         }
-        displacement = nanoRelocs[i].ofstInRam - origin;
-        origin = nanoRelocs[i].ofstInRam + 4;
+        displacement = app->nanoReloc[i].ofstInRam - origin;
+        origin = app->nanoReloc[i].ofstInRam + 4;
         if (displacement & 3) {
-            fprintf(stderr, "Unaligned relocs are not possible!\n");
-            exit(-5);
+            ERR("Unaligned relocs are not possible!");
+            return false;
         }
         displacement /= 4;
 
         //might be start of a run. look into that
         if (!displacement) {
-            for (j = 1; j + i < outNumRelocs && j < MAX_RUN_LEN && nanoRelocs[j + i].type == lastOutType && nanoRelocs[j + i].ofstInRam - nanoRelocs[j + i - 1].ofstInRam == 4; j++);
+            for (j = 1; (j + i) < app->nanoRelocSize && j < MAX_RUN_LEN &&
+                        app->nanoReloc[j + i].type == lastOutType &&
+                        (app->nanoReloc[j + i].ofstInRam - app->nanoReloc[j + i - 1].ofstInRam) == 4; j++);
             if (j >= MIN_RUN_LEN) {
                 if (verbose)
-                    fprintf(stderr, "Out: Reloc0  x%" PRIX32 "\n", j);
+                    DBG("Out: Reloc0 [size 2]; repeat=%zu", j);
                 packedNanoRelocs[packedNanoRelocSz++] = TOKEN_CONSECUTIVE;
                 packedNanoRelocs[packedNanoRelocSz++] = j - MIN_RUN_LEN;
-                origin = nanoRelocs[j + i - 1].ofstInRam + 4;  //reset origin to last one
+                origin = app->nanoReloc[j + i - 1].ofstInRam + 4;  //reset origin to last one
                 i += j - 1;  //loop will increment anyways, hence +1
                 continue;
             }
@@ -189,29 +200,26 @@ static uint8_t *packNanoRelocs(struct NanoRelocEntry *nanoRelocs, uint32_t outNu
         //produce output
         if (displacement <= MAX_8_BIT_NUM) {
             if (verbose)
-                fprintf(stderr, "Out: Reloc8  0x%02" PRIX32 "\n", displacement);
+                DBG("Out: Reloc8 [size 1] 0x%02" PRIX32, displacement);
             packedNanoRelocs[packedNanoRelocSz++] = displacement;
-        }
-        else if (displacement <= MAX_16_BIT_NUM) {
+        } else if (displacement <= MAX_16_BIT_NUM) {
             if (verbose)
-                fprintf(stderr, "Out: Reloc16 0x%06" PRIX32 "\n", displacement);
+                DBG("Out: Reloc16 [size 3] 0x%06" PRIX32, displacement);
                         displacement -= MAX_8_BIT_NUM;
             packedNanoRelocs[packedNanoRelocSz++] = TOKEN_16BIT_OFST;
             packedNanoRelocs[packedNanoRelocSz++] = displacement;
             packedNanoRelocs[packedNanoRelocSz++] = displacement >> 8;
-        }
-        else if (displacement <= MAX_24_BIT_NUM) {
+        } else if (displacement <= MAX_24_BIT_NUM) {
             if (verbose)
-                fprintf(stderr, "Out: Reloc24 0x%08" PRIX32 "\n", displacement);
+                DBG("Out: Reloc24 [size 4] 0x%08" PRIX32, displacement);
                         displacement -= MAX_16_BIT_NUM;
             packedNanoRelocs[packedNanoRelocSz++] = TOKEN_24BIT_OFST;
             packedNanoRelocs[packedNanoRelocSz++] = displacement;
             packedNanoRelocs[packedNanoRelocSz++] = displacement >> 8;
             packedNanoRelocs[packedNanoRelocSz++] = displacement >> 16;
-        }
-        else  {
+        } else {
             if (verbose)
-                fprintf(stderr, "Out: Reloc32 0x%08" PRIX32 "\n", displacement);
+                DBG("Out: Reloc32 [size 5] 0x%08" PRIX32, displacement);
             packedNanoRelocs[packedNanoRelocSz++] = TOKEN_32BIT_OFST;
             packedNanoRelocs[packedNanoRelocSz++] = displacement;
             packedNanoRelocs[packedNanoRelocSz++] = displacement >> 8;
@@ -220,16 +228,18 @@ static uint8_t *packNanoRelocs(struct NanoRelocEntry *nanoRelocs, uint32_t outNu
         }
     }
 
-    *finalPackedNanoRelocSz = packedNanoRelocSz;
-    return packedNanoRelocs;
+    app->packedNanoReloc = packedNanoRelocs;
+    app->packedNanoRelocSize = packedNanoRelocSz;
+
+    return true;
 }
 
-static int finalizeAndWrite(uint8_t *buf, uint32_t bufUsed, uint32_t bufSz, FILE *out, uint32_t layoutFlags, uint64_t appId)
+static int finalizeAndWrite(struct NanoAppInfo *inf, FILE *out, uint32_t layoutFlags, uint64_t appId)
 {
-    int ret;
+    bool good = true;
     struct AppInfo app;
     struct SectInfo *sect;
-    struct BinHdr *bin = (struct BinHdr *) buf;
+    struct BinHdr *bin = inf->bin;
     struct ImageHeader outHeader = {
         .aosp = (struct nano_app_binary_t) {
             .header_version = 1,
@@ -245,58 +255,159 @@ static int finalizeAndWrite(uint8_t *buf, uint32_t bufUsed, uint32_t bufSz, FILE
             .flags = layoutFlags,
         },
     };
-    uint32_t dataOffset = sizeof(outHeader) + sizeof(app);
-    uint32_t hdrDiff = dataOffset - sizeof(*bin);
+
     app.sect = bin->sect;
     app.vec  = bin->vec;
-
-    assertMem(bufUsed + hdrDiff, bufSz);
-
-    memmove(buf + dataOffset, buf + sizeof(*bin), bufUsed - sizeof(*bin));
-    bufUsed += hdrDiff;
-    memcpy(buf, &outHeader, sizeof(outHeader));
-    memcpy(buf + sizeof(outHeader), &app, sizeof(app));
     sect = &app.sect;
 
     //if we have any bytes to output, show stats
-    if (bufUsed) {
-        uint32_t codeAndRoDataSz = sect->data_data;
-        uint32_t relocsSz = sect->rel_end - sect->rel_start;
-        uint32_t gotSz = sect->got_end - sect->data_start;
-        uint32_t bssSz = sect->bss_end - sect->bss_start;
-
-        fprintf(stderr,"Final binary size %" PRIu32 " bytes\n", bufUsed);
-        fprintf(stderr, "\n");
-        fprintf(stderr, "       FW header size (flash):      %6zu bytes\n", FLASH_RELOC_OFFSET);
-        fprintf(stderr, "       Code + RO data (flash):      %6" PRIu32 " bytes\n", codeAndRoDataSz);
-        fprintf(stderr, "       Relocs (flash):              %6" PRIu32 " bytes\n", relocsSz);
-        fprintf(stderr, "       GOT + RW data (flash & RAM): %6" PRIu32 " bytes\n", gotSz);
-        fprintf(stderr, "       BSS (RAM):                   %6" PRIu32 " bytes\n", bssSz);
-        fprintf(stderr, "\n");
-        fprintf(stderr,"Runtime flash use: %" PRIu32 " bytes\n", (uint32_t)(codeAndRoDataSz + relocsSz + gotSz + FLASH_RELOC_OFFSET));
-        fprintf(stderr,"Runtime RAM use: %" PRIu32 " bytes\n", gotSz + bssSz);
+    if (inf->codeAndRoDataSize) {
+        size_t binarySize = 0;
+        size_t gotSz = sect->got_end - sect->data_start;
+        size_t bssSz = sect->bss_end - sect->bss_start;
+
+        good = fwrite(&outHeader, sizeof(outHeader), 1, out) == 1 && good;
+        binarySize += sizeof(outHeader);
+
+        good = fwrite(&app, sizeof(app), 1, out) == 1 && good;
+        binarySize += sizeof(app);
+
+        good = fwrite(&bin[1], inf->codeAndDataSize, 1, out) == 1 && good;
+        binarySize += inf->codeAndDataSize;
+
+        if (inf->packedNanoReloc && inf->packedNanoRelocSize) {
+            good = fwrite(inf->packedNanoReloc, inf->packedNanoRelocSize, 1, out) == 1 && good;
+            binarySize += inf->packedNanoRelocSize;
+        }
+
+        if (!good) {
+            ERR("Failed to write output file: %s\n", strerror(errno));
+        } else {
+            DBG("Final binary size %zu bytes", binarySize);
+            DBG("");
+            DBG("       FW header size (flash):      %6zu bytes", FLASH_RELOC_OFFSET);
+            DBG("       Code + RO data (flash):      %6zu bytes", inf->codeAndRoDataSize);
+            DBG("       Relocs (flash):              %6zu bytes", inf->packedNanoRelocSize);
+            DBG("       GOT + RW data (flash & RAM): %6zu bytes", gotSz);
+            DBG("       BSS (RAM):                   %6zu bytes", bssSz);
+            DBG("");
+            DBG("Runtime flash use: %zu bytes",
+                (size_t)(inf->codeAndRoDataSize + inf->packedNanoRelocSize + gotSz + FLASH_RELOC_OFFSET));
+            DBG("Runtime RAM use: %zu bytes", gotSz + bssSz);
+        }
     }
 
-    ret = fwrite(buf, bufUsed, 1, out) == 1 ? 0 : 2;
-    if (ret)
-        fprintf(stderr, "Failed to write output file: %s\n", strerror(errno));
+    return good ? 0 : 2;
+}
 
-    return ret;
+// Subtracts the fixed memory region offset from an absolute address and returns
+// the associated NANO_RELOC_* value, or NANO_RELOC_LAST if the address is not
+// in the expected range.
+static uint8_t fixupAddress(uint32_t *addr, struct SymtabEntry *sym, bool debug)
+{
+    uint8_t type;
+    uint32_t old = *addr;
+
+    (*addr) += sym->addr;
+    // TODO: this assumes that the host running this tool has the same
+    // endianness as the image file/target processor
+    if (IS_IN_RAM(*addr)) {
+        *addr -= RAM_BASE;
+        type = NANO_RELOC_TYPE_RAM;
+        if (debug)
+            DBG("Fixup addr 0x%08" PRIX32 " (RAM) --> 0x%08" PRIX32, old, *addr);
+    } else if (IS_IN_FLASH(*addr)) {
+        *addr -= FLASH_BASE + BINARY_RELOC_OFFSET;
+        type = NANO_RELOC_TYPE_FLASH;
+        if (debug)
+            DBG("Fixup addr 0x%08" PRIX32 " (FLASH) --> 0x%08" PRIX32, old, *addr);
+    } else {
+        ERR("Error: invalid address 0x%08" PRIX32, *addr);
+        type = NANO_RELOC_LAST;
+    }
+
+    return type;
+}
+
+static void relocDiag(const struct NanoAppInfo *app, const struct RelocEntry *reloc, const char *msg)
+{
+    size_t symIdx = reloc->info >> 8;
+    uint8_t symType = reloc->info;
+
+    ERR("Reloc %zu %s", reloc - app->reloc, msg);
+    ERR("INFO:");
+    ERR("        Where: 0x%08" PRIX32, reloc->where);
+    ERR("        type: %" PRIu8, symType);
+    ERR("        sym: %zu", symIdx);
+    if (symIdx < app->symtabSize) {
+        struct SymtabEntry *sym = &app->symtab[symIdx];
+        ERR("        addr: %" PRIu32, sym->addr);
+    } else {
+        ERR("        addr: <invalid>");
+    }
+}
+
+static uint8_t fixupReloc(struct NanoAppInfo *app, struct RelocEntry *reloc,
+                          struct SymtabEntry *sym, struct NanoRelocEntry *nanoReloc)
+{
+    uint8_t type;
+    uint32_t *addr;
+    uint32_t relocOffset = reloc->where;
+    uint32_t flashDataOffset = 0;
+
+    if (IS_IN_FLASH(relocOffset)) {
+        relocOffset -= FLASH_BASE;
+        flashDataOffset = 0;
+    } else if (IS_IN_RAM(reloc->where)) {
+        relocOffset = reloc->where - RAM_BASE;
+        flashDataOffset = app->bin->sect.data_data - FLASH_BASE;
+    } else {
+        relocDiag(app, reloc, "is neither in RAM nor in FLASH");
+        return NANO_RELOC_LAST;
+    }
+
+    addr = (uint32_t*)(app->data + flashDataOffset + relocOffset);
+
+    if (flashDataOffset + relocOffset >= app->dataSizeUsed - sizeof(*addr)) {
+        relocDiag(app, reloc, "points outside valid data area");
+        return NANO_RELOC_LAST;
+    }
+
+    switch (reloc->info & 0xFF) {
+    case RELOC_TYPE_ABS_S:
+    case RELOC_TYPE_ABS_D:
+        type = fixupAddress(addr, sym, app->debug);
+        break;
+
+    case RELOC_TYPE_SECT:
+        if (sym->addr) {
+            relocDiag(app, reloc, "has section relocation with non-zero symbol address");
+            return NANO_RELOC_LAST;
+        }
+        type = fixupAddress(addr, sym, app->debug);
+        break;
+    default:
+        relocDiag(app, reloc, "has unknown type");
+        type = NANO_RELOC_LAST;
+    }
+
+    if (nanoReloc && type != NANO_RELOC_LAST) {
+        nanoReloc->ofstInRam = relocOffset;
+        nanoReloc->type = type;
+    }
+
+    return type;
 }
 
 static int handleApp(uint8_t **pbuf, uint32_t bufUsed, FILE *out, uint32_t layoutFlags, uint64_t appId, bool verbose)
 {
-    uint32_t i, numRelocs, numSyms, outNumRelocs = 0, packedNanoRelocSz;
-    struct NanoRelocEntry *nanoRelocs = NULL;
-    struct RelocEntry *relocs;
-    struct SymtabEntry *syms;
-    uint8_t *packedNanoRelocs;
-    uint32_t t;
+    uint32_t i;
     struct BinHdr *bin;
     int ret = -1;
     struct SectInfo *sect;
     uint8_t *buf = *pbuf;
     uint32_t bufSz = bufUsed * 3 /2;
+    struct NanoAppInfo app;
 
     //make buffer 50% bigger than bufUsed in case relocs grow out of hand
     buf = reallocOrDie(buf, bufSz);
@@ -305,212 +416,139 @@ static int handleApp(uint8_t **pbuf, uint32_t bufUsed, FILE *out, uint32_t layou
     //sanity checks
     bin = (struct BinHdr*)buf;
     if (bufUsed < sizeof(*bin)) {
-        fprintf(stderr, "File size too small\n");
+        ERR("File size too small: %" PRIu32, bufUsed);
         goto out;
     }
 
     if (bin->hdr.magic != NANOAPP_FW_MAGIC) {
-        fprintf(stderr, "Magic value is wrong: found %08" PRIX32
-                        "; expected %08" PRIX32 "\n",
-                        bin->hdr.magic, NANOAPP_FW_MAGIC);
+        ERR("Magic value is wrong: found %08" PRIX32"; expected %08" PRIX32, bin->hdr.magic, NANOAPP_FW_MAGIC);
         goto out;
     }
 
     sect = &bin->sect;
 
+    if (!IS_IN_FLASH(sect->rel_start) || !IS_IN_FLASH(sect->rel_end) || !IS_IN_FLASH(sect->data_data)) {
+        ERR("relocation data or initialized data is not in FLASH");
+        goto out;
+    }
+    if (!IS_IN_RAM(sect->data_start) || !IS_IN_RAM(sect->data_end) || !IS_IN_RAM(sect->bss_start) ||
+        !IS_IN_RAM(sect->bss_end) || !IS_IN_RAM(sect->got_start) || !IS_IN_RAM(sect->got_end)) {
+        ERR("data, bss, or got not in ram\n");
+        goto out;
+    }
+
     //do some math
-    relocs = (struct RelocEntry*)(buf + sect->rel_start - FLASH_BASE);
-    syms = (struct SymtabEntry*)(buf + sect->rel_end - FLASH_BASE);
-    numRelocs = (sect->rel_end - sect->rel_start) / sizeof(struct RelocEntry);
-    numSyms = (bufUsed + FLASH_BASE - sect->rel_end) / sizeof(struct SymtabEntry);
+    app.reloc = (struct RelocEntry*)(buf + sect->rel_start - FLASH_BASE);
+    app.symtab = (struct SymtabEntry*)(buf + sect->rel_end - FLASH_BASE);
+    app.relocSize = (sect->rel_end - sect->rel_start) / sizeof(struct RelocEntry);
+    app.nanoRelocSize = 0;
+    app.symtabSize = (struct SymtabEntry*)(buf + bufUsed) - app.symtab;
+    app.data = buf;
+    app.dataSizeAllocated = bufSz;
+    app.dataSizeUsed = bufUsed;
+    app.codeAndRoDataSize = sect->data_data - FLASH_BASE - sizeof(*bin);
+    app.codeAndDataSize = sect->rel_start - FLASH_BASE - sizeof(*bin);
+    app.debug = verbose;
+    app.nanoReloc = NULL;
+    app.packedNanoReloc = NULL;
 
     //sanity
-    if (numRelocs * sizeof(struct RelocEntry) + sect->rel_start != sect->rel_end) {
-        fprintf(stderr, "Relocs of nonstandard size\n");
+    if (app.relocSize * sizeof(struct RelocEntry) + sect->rel_start != sect->rel_end) {
+        ERR("Relocs of nonstandard size");
         goto out;
     }
-    if (numSyms * sizeof(struct SymtabEntry) + sect->rel_end != bufUsed + FLASH_BASE) {
-        fprintf(stderr, "Syms of nonstandard size\n");
+    if (app.symtabSize * sizeof(struct SymtabEntry) + sect->rel_end != bufUsed + FLASH_BASE) {
+        ERR("Syms of nonstandard size");
         goto out;
     }
 
     //show some info
-    fprintf(stderr, "\nRead %" PRIu32 " bytes of binary.\n", bufUsed);
 
     if (verbose)
-        fprintf(stderr, "Found %" PRIu32 " relocs and a %" PRIu32 "-entry symbol table\n", numRelocs, numSyms);
+        DBG("Found %zu relocs and a %zu-entry symbol table", app.relocSize, app.symtabSize);
 
     //handle relocs
-    nanoRelocs = malloc(sizeof(struct NanoRelocEntry[numRelocs]));
-    if (!nanoRelocs) {
-        fprintf(stderr, "Failed to allocate a nano-reloc table\n");
+    app.nanoReloc = malloc(sizeof(struct NanoRelocEntry[app.relocSize]));
+    if (!app.nanoReloc) {
+        ERR("Failed to allocate a nano-reloc table\n");
         goto out;
     }
 
-    for (i = 0; i < numRelocs; i++) {
-        uint32_t relocType = relocs[i].info & 0xff;
-        uint32_t whichSym = relocs[i].info >> 8;
-        uint32_t *valThereP;
-
-        if (whichSym >= numSyms) {
-            fprintf(stderr, "Reloc %" PRIu32 " references a nonexistent symbol!\n"
-                            "INFO:\n"
-                            "        Where: 0x%08" PRIX32 "\n"
-                            "        type: %" PRIu32 "\n"
-                            "        sym: %" PRIu32 "\n",
-                i, relocs[i].where, relocs[i].info & 0xff, whichSym);
+    for (i = 0; i < app.relocSize; i++) {
+        struct RelocEntry *reloc = &app.reloc[i];
+        struct NanoRelocEntry *nanoReloc = &app.nanoReloc[app.nanoRelocSize];
+        uint32_t relocType = reloc->info & 0xff;
+        uint32_t whichSym = reloc->info >> 8;
+        struct SymtabEntry *sym = &app.symtab[whichSym];
+
+        if (whichSym >= app.symtabSize) {
+            relocDiag(&app, reloc, "references a nonexistent symbol");
             goto out;
         }
 
         if (verbose) {
             const char *seg;
 
-            fprintf(stderr, "Reloc[%3" PRIu32 "]:\n {@0x%08" PRIX32 ", type %3" PRIu32 ", -> sym[%3" PRIu32 "]: {@0x%08" PRIX32 "}, ",
-                i, relocs[i].where, relocs[i].info & 0xff, whichSym, syms[whichSym].addr);
-
-            if (IS_IN_RANGE_E(relocs[i].where, sect->bss_start, sect->bss_end))
+            if (IS_IN_RANGE_E(reloc->where, sect->bss_start, sect->bss_end))
                 seg = ".bss";
-            else if (IS_IN_RANGE_E(relocs[i].where, sect->data_start, sect->data_end))
+            else if (IS_IN_RANGE_E(reloc->where, sect->data_start, sect->data_end))
                 seg = ".data";
-            else if (IS_IN_RANGE_E(relocs[i].where, sect->got_start, sect->got_end))
+            else if (IS_IN_RANGE_E(reloc->where, sect->got_start, sect->got_end))
                 seg = ".got";
-            else if (IS_IN_RANGE_E(relocs[i].where, FLASH_BASE, FLASH_BASE + sizeof(struct BinHdr)))
+            else if (IS_IN_RANGE_E(reloc->where, FLASH_BASE, FLASH_BASE + sizeof(struct BinHdr)))
                 seg = "APPHDR";
             else
                 seg = "???";
 
-            fprintf(stderr, "in   %s}\n", seg);
+            DBG("Reloc[%3" PRIu32 "]:\n {@0x%08" PRIX32 ", type %3" PRIu32 ", -> sym[%3" PRIu32 "]: {@0x%08" PRIX32 "}, in   %s}",
+                i, reloc->where, reloc->info & 0xff, whichSym, sym->addr, seg);
         }
         /* handle relocs inside the header */
-        if (IS_IN_FLASH(relocs[i].where) && relocs[i].where - FLASH_BASE < sizeof(struct BinHdr) && relocType == RELOC_TYPE_SECT) {
+        if (IS_IN_FLASH(reloc->where) && reloc->where - FLASH_BASE < sizeof(struct BinHdr) && relocType == RELOC_TYPE_SECT) {
             /* relocs in header are special - runtime corrects for them */
-            if (syms[whichSym].addr) {
-                fprintf(stderr, "Weird in-header sect reloc %" PRIu32 " to symbol %" PRIu32 " with nonzero addr 0x%08" PRIX32 "\n",
-                        i, whichSym, syms[whichSym].addr);
-                goto out;
-            }
-
-            valThereP = (uint32_t*)(buf + relocs[i].where - FLASH_BASE);
-            if (!IS_IN_FLASH(*valThereP)) {
-                fprintf(stderr, "In-header reloc %" PRIu32 " of location 0x%08" PRIX32 " is outside of FLASH!\n"
-                                "INFO:\n"
-                                "        type: %" PRIu32 "\n"
-                                "        sym: %" PRIu32 "\n"
-                                "        Sym Addr: 0x%08" PRIX32 "\n",
-                                i, relocs[i].where, relocType, whichSym, syms[whichSym].addr);
-                goto out;
-            }
-
-            // binary header generated by objcopy, .napp header and final FW header in flash are of different size.
+            // binary header generated by objcopy, .napp header and final FW header in flash are of different layout and size.
             // we subtract binary header offset here, so all the entry points are relative to beginning of "sect".
             // FW will use &sect as a base to call these vectors; no more problems with different header sizes;
             // Assumption: offsets between sect & vec, vec & code are the same in all images (or, in a simpler words, { sect, vec, code }
             // must go together). this is enforced by linker script, and maintained by all tools and FW download code in the OS.
-            *valThereP -= FLASH_BASE + BINARY_RELOC_OFFSET;
+
+            switch (fixupReloc(&app, reloc, sym, NULL)) {
+            case NANO_RELOC_TYPE_RAM:
+                relocDiag(&app, reloc, "is in APPHDR but relocated to RAM");
+                goto out;
+            case NANO_RELOC_TYPE_FLASH:
+                break;
+            default:
+                // other error happened; it is already reported
+                goto out;
+            }
 
             if (verbose)
-                fprintf(stderr, "  -> Nano reloc skipped for in-header reloc\n");
+                DBG("  -> Nano reloc skipped for in-header reloc");
 
             continue; /* do not produce an output reloc */
         }
 
-        if (!IS_IN_RAM(relocs[i].where)) {
-            fprintf(stderr, "In-header reloc %" PRIu32 " of location 0x%08" PRIX32 " is outside of RAM!\n"
-                            "INFO:\n"
-                            "        type: %" PRIu32 "\n"
-                            "        sym: %" PRIu32 "\n"
-                            "        Sym Addr: 0x%08" PRIX32 "\n",
-                            i, relocs[i].where, relocType, whichSym, syms[whichSym].addr);
+        // any other relocs may only happen in RAM
+        if (!IS_IN_RAM(reloc->where)) {
+            relocDiag(&app, reloc, "is not in RAM");
             goto out;
         }
 
-        valThereP = (uint32_t*)(buf + relocs[i].where + sect->data_data - RAM_BASE - FLASH_BASE);
-
-        nanoRelocs[outNumRelocs].ofstInRam = relocs[i].where - RAM_BASE;
-
-        switch (relocType) {
-            case RELOC_TYPE_ABS_S:
-            case RELOC_TYPE_ABS_D:
-                t = *valThereP;
-
-                (*valThereP) += syms[whichSym].addr;
-
-                if (IS_IN_FLASH(syms[whichSym].addr)) {
-                    (*valThereP) -= FLASH_BASE + BINARY_RELOC_OFFSET;
-                    nanoRelocs[outNumRelocs].type = NANO_RELOC_TYPE_FLASH;
-                }
-                else if (IS_IN_RAM(syms[whichSym].addr)) {
-                    (*valThereP) -= RAM_BASE;
-                    nanoRelocs[outNumRelocs].type = NANO_RELOC_TYPE_RAM;
-                }
-                else {
-                    fprintf(stderr, "Weird reloc %" PRIu32 " to symbol %" PRIu32 " in unknown memory space (addr 0x%08" PRIX32 ")\n",
-                            i, whichSym, syms[whichSym].addr);
-                    goto out;
-                }
-                if (verbose)
-                    fprintf(stderr, "  -> Abs reference fixed up 0x%08" PRIX32 " -> 0x%08" PRIX32 "\n", t, *valThereP);
-                break;
-
-            case RELOC_TYPE_SECT:
-                if (syms[whichSym].addr) {
-                    fprintf(stderr, "Weird sect reloc %" PRIu32 " to symbol %" PRIu32 " with nonzero addr 0x%08" PRIX32 "\n",
-                            i, whichSym, syms[whichSym].addr);
-                    goto out;
-                }
-
-                t = *valThereP;
-
-                if (IS_IN_FLASH(*valThereP)) {
-                    nanoRelocs[outNumRelocs].type = NANO_RELOC_TYPE_FLASH;
-                    *valThereP -= FLASH_BASE + BINARY_RELOC_OFFSET;
-                }
-                else if (IS_IN_RAM(*valThereP)) {
-                    nanoRelocs[outNumRelocs].type = NANO_RELOC_TYPE_RAM;
-                    *valThereP -= RAM_BASE;
-                }
-                else {
-                    fprintf(stderr, "Weird sec reloc %" PRIu32 " to symbol %" PRIu32
-                                    " in unknown memory space (addr 0x%08" PRIX32 ")\n",
-                                    i, whichSym, *valThereP);
-                    goto out;
-                }
-                if (verbose)
-                    fprintf(stderr, "  -> Sect reference fixed up 0x%08" PRIX32 " -> 0x%08" PRIX32 "\n", t, *valThereP);
-                break;
-
-            default:
-                fprintf(stderr, "Weird reloc %" PRIX32 " type %" PRIX32 " to symbol %" PRIX32 "\n", i, relocType, whichSym);
-                goto out;
+        if (fixupReloc(&app, reloc, sym, nanoReloc) != NANO_RELOC_LAST) {
+            app.nanoRelocSize++;
+            if (verbose)
+                DBG("  -> Nano reloc calculated as 0x%08" PRIX32 ",0x%02" PRIX8 "\n", nanoReloc->ofstInRam, nanoReloc->type);
         }
-
-        if (verbose)
-            fprintf(stderr, "  -> Nano reloc calculated as 0x%08" PRIX32 ",0x%02" PRIX8 "\n", nanoRelocs[i].ofstInRam, nanoRelocs[i].type);
-        outNumRelocs++;
     }
 
-    packedNanoRelocs = packNanoRelocs(nanoRelocs, outNumRelocs, &packedNanoRelocSz, verbose);
-
-    //overwrite original relocs and symtab with nanorelocs and adjust sizes
-    memcpy(relocs, packedNanoRelocs, packedNanoRelocSz);
-    bufUsed -= sizeof(struct RelocEntry[numRelocs]);
-    bufUsed -= sizeof(struct SymtabEntry[numSyms]);
-    bufUsed += packedNanoRelocSz;
-    assertMem(bufUsed, bufSz);
-    sect->rel_end = sect->rel_start + packedNanoRelocSz;
-
-    //sanity
-    if (sect->rel_end - FLASH_BASE != bufUsed) {
-        fprintf(stderr, "Relocs end and file end not coincident\n");
+    if (!packNanoRelocs(&app))
         goto out;
-    }
+
+    // we're going to write packed relocs; set correct size
+    sect->rel_end = sect->rel_start + app.packedNanoRelocSize;
 
     //adjust headers for easy access (RAM)
-    if (!IS_IN_RAM(sect->data_start) || !IS_IN_RAM(sect->data_end) || !IS_IN_RAM(sect->bss_start) ||
-        !IS_IN_RAM(sect->bss_end) || !IS_IN_RAM(sect->got_start) || !IS_IN_RAM(sect->got_end)) {
-        fprintf(stderr, "data, bss, or got not in ram\n");
-        goto out;
-    }
     sect->data_start -= RAM_BASE;
     sect->data_end -= RAM_BASE;
     sect->bss_start -= RAM_BASE;
@@ -519,312 +557,17 @@ static int handleApp(uint8_t **pbuf, uint32_t bufUsed, FILE *out, uint32_t layou
     sect->got_end -= RAM_BASE;
 
     //adjust headers for easy access (FLASH)
-    if (!IS_IN_FLASH(sect->data_data) || !IS_IN_FLASH(sect->rel_start) || !IS_IN_FLASH(sect->rel_end)) {
-        fprintf(stderr, "data.data, or rel not in flash\n");
-        goto out;
-    }
     sect->data_data -= FLASH_BASE + BINARY_RELOC_OFFSET;
     sect->rel_start -= FLASH_BASE + BINARY_RELOC_OFFSET;
     sect->rel_end -= FLASH_BASE + BINARY_RELOC_OFFSET;
 
-    ret = finalizeAndWrite(buf, bufUsed, bufSz, out, layoutFlags, appId);
+    ret = finalizeAndWrite(&app, out, layoutFlags, appId);
 out:
-    free(nanoRelocs);
+    free(app.nanoReloc);
+    free(app.packedNanoReloc);
     return ret;
 }
 
-static void elfExtractSectionPointer(const Elf_Data *data, const char *name, struct ElfNanoApp *app)
-{
-    // Maps section names to their byte offset in struct ElfNanoApp. Note that
-    // this assumes that the linker script puts text/code in the .flash section,
-    // RW data in .data, that relocs for .data are included in .rel.data, and
-    // the symbol table is emitted in .symtab
-    const struct SectionMap {
-        const char *name;
-        size_t offset;
-    } sectionMap[] = {
-        {
-            .name = ".flash",
-            .offset = offsetof(struct ElfNanoApp, flash),
-        },
-        {
-            .name = ".data",
-            .offset = offsetof(struct ElfNanoApp, data),
-        },
-        {
-            .name = ".rel.data",
-            .offset = offsetof(struct ElfNanoApp, relocs),
-        },
-        {
-            .name = ".symtab",
-            .offset = offsetof(struct ElfNanoApp, symtab),
-        },
-    };
-    struct ElfAppSection *appSection;
-    uint8_t *appBytes = (uint8_t *) app;
-
-    for (size_t i = 0; i < ARRAY_SIZE(sectionMap); i++) {
-        if (strcmp(name, sectionMap[i].name) != 0) {
-            continue;
-        }
-        appSection = (struct ElfAppSection *) &appBytes[sectionMap[i].offset];
-
-        appSection->data = data->d_buf;
-        appSection->size = data->d_size;
-
-        DBG("Found section %s with size %zu", name, appSection->size);
-        break;
-    }
-}
-
-// Populates a struct ElfNanoApp with data parsed from the ELF
-static bool elfParse(Elf *elf, struct ElfNanoApp *app)
-{
-    size_t shdrstrndx;
-    Elf_Scn *scn = NULL;
-    GElf_Shdr shdr;
-    char *sectionName;
-    Elf_Data *elf_data;
-
-    memset(app, 0, sizeof(*app));
-    if (elf_getshdrstrndx(elf, &shdrstrndx) != 0) {
-        ELF_ERR("Couldn't get section name string table index");
-        return false;
-    }
-
-    while ((scn = elf_nextscn(elf, scn)) != NULL) {
-        if (gelf_getshdr(scn, &shdr) != &shdr) {
-            ELF_ERR("Error getting section header");
-            return false;
-        }
-        sectionName = elf_strptr(elf, shdrstrndx, shdr.sh_name);
-
-        elf_data = elf_getdata(scn, NULL);
-        if (!elf_data) {
-            ELF_ERR("Error getting data for section %s", sectionName);
-            return false;
-        }
-
-        elfExtractSectionPointer(elf_data, sectionName, app);
-    }
-
-    return true;
-}
-
-static bool loadNanoappElfFile(const char *fileName, struct ElfNanoApp *app)
-{
-    int fd;
-    Elf *elf;
-
-    if (elf_version(EV_CURRENT) == EV_NONE) {
-        ELF_ERR("Failed to initialize ELF library");
-        return false;
-    }
-
-    fd = open(fileName, O_RDONLY, 0);
-    if (fd < 0) {
-        ERR("Failed to open file %s for reading: %s", fileName, strerror(errno));
-        return false;
-    }
-
-    elf = elf_begin(fd, ELF_C_READ, NULL);
-    if (elf == NULL) {
-        ELF_ERR("Failed to open ELF");
-        return false;
-    }
-
-    if (!elfParse(elf, app)) {
-        ERR("Failed to parse ELF file");
-        return false;
-    }
-
-    return true;
-}
-
-// Subtracts the fixed memory region offset from an absolute address and returns
-// the associated NANO_RELOC_* value, or NANO_RELOC_LAST if the address is not
-// in the expected range.
-// Not strictly tied to ELF usage, but handled slightly differently.
-static uint8_t fixupAddrElf(uint32_t *addr)
-{
-    uint8_t type;
-
-    // TODO: this assumes that the host running this tool has the same
-    // endianness as the image file/target processor
-    if (IS_IN_FLASH(*addr)) {
-        DBG("Fixup addr 0x%08" PRIX32 " (flash) --> 0x%08" PRIX32, *addr,
-            (uint32_t) (*addr - (FLASH_BASE + BINARY_RELOC_OFFSET)));
-        *addr -= FLASH_BASE + BINARY_RELOC_OFFSET;
-        type = NANO_RELOC_TYPE_FLASH;
-    } else if (IS_IN_RAM(*addr)) {
-        DBG("Fixup addr 0x%08" PRIX32 " (ram)   --> 0x%08" PRIX32, *addr,
-            *addr - RAM_BASE);
-        *addr -= RAM_BASE;
-        type = NANO_RELOC_TYPE_RAM;
-    } else {
-        DBG("Error: invalid address 0x%08" PRIX32, *addr);
-        type = NANO_RELOC_LAST;
-    }
-
-    return type;
-}
-
-// Fixup addresses in the header to be relative. Not strictly tied to the ELF
-// format, but used only in that program flow in the current implementation.
-static bool fixupHeaderElf(const struct ElfNanoApp *app)
-{
-    struct BinHdr *hdr = (struct BinHdr *) app->flash.data;
-
-    DBG("Appyling fixups to header");
-    if (fixupAddrElf(&hdr->sect.data_start) != NANO_RELOC_TYPE_RAM ||
-        fixupAddrElf(&hdr->sect.data_end)   != NANO_RELOC_TYPE_RAM ||
-        fixupAddrElf(&hdr->sect.bss_start)  != NANO_RELOC_TYPE_RAM ||
-        fixupAddrElf(&hdr->sect.bss_end)    != NANO_RELOC_TYPE_RAM ||
-        fixupAddrElf(&hdr->sect.got_start)  != NANO_RELOC_TYPE_RAM ||
-        fixupAddrElf(&hdr->sect.got_end)    != NANO_RELOC_TYPE_RAM) {
-        ERR(".data, .bss, or .got not in RAM address space!");
-        return false;
-    }
-
-    if (fixupAddrElf(&hdr->sect.rel_start) != NANO_RELOC_TYPE_FLASH ||
-        fixupAddrElf(&hdr->sect.rel_end)   != NANO_RELOC_TYPE_FLASH ||
-        fixupAddrElf(&hdr->sect.data_data) != NANO_RELOC_TYPE_FLASH) {
-        ERR(".data loadaddr, or .relocs not in flash address space!");
-        return false;
-    }
-
-    if (fixupAddrElf(&hdr->vec.init)   != NANO_RELOC_TYPE_FLASH ||
-        fixupAddrElf(&hdr->vec.end)    != NANO_RELOC_TYPE_FLASH ||
-        fixupAddrElf(&hdr->vec.handle) != NANO_RELOC_TYPE_FLASH) {
-        ERR("Entry point(s) not in flash address space!");
-        return false;
-    }
-
-    return true;
-}
-
-// Fixup addresses in .data, .init_array/.fini_array, and .got, and generates
-// packed array of nano reloc entries. The app header must have already been
-// fixed up.
-static bool genElfNanoRelocs(struct ElfNanoApp *app, bool verbose)
-{
-    const struct BinHdr *hdr = (const struct BinHdr *) app->flash.data;
-    const struct SectInfo *sect = &hdr->sect;
-    bool success = false;
-
-    size_t numDataRelocs = app->relocs.size / sizeof(Elf32_Rel);
-    size_t gotCount = (sect->got_end - sect->got_start) / sizeof(uint32_t);
-    size_t numInitFuncs  = (sect->bss_start - sect->data_end) / sizeof(uint32_t);
-
-    size_t totalRelocCount = (numDataRelocs + numInitFuncs + gotCount);
-    struct NanoRelocEntry *nanoRelocs = malloc(
-        totalRelocCount * sizeof(struct NanoRelocEntry));
-    if (!nanoRelocs) {
-        ERR("Couldn't allocate memory for nano relocs! Needed %zu bytes",
-            totalRelocCount * sizeof(struct NanoRelocEntry));
-        return false;
-    }
-
-    uint8_t *data = app->data.data;
-    const Elf32_Rel *relocs = (const Elf32_Rel *) app->relocs.data;
-    const Elf32_Sym *syms   = (const Elf32_Sym *) app->symtab.data;
-    size_t numRelocs = 0;
-
-    DBG("Parsing relocs for .data (%zu):", numDataRelocs);
-    for (size_t i = 0; i < numDataRelocs; i++) {
-        uint32_t type = ELF32_R_TYPE(relocs[i].r_info);
-        uint32_t sym = ELF32_R_SYM(relocs[i].r_info);
-
-        DBG(" [%3zu] 0x%08" PRIx32 " type %2" PRIu32 " symIdx %3" PRIu32
-            " --> 0x%08" PRIx32, i, relocs[i].r_offset, type, sym,
-            syms[sym].st_value);
-        // Note that R_ARM_TARGET1 is used for .init_array/.fini_array support,
-        // and can be interpreted either as ABS32 or REL32, depending on the
-        // runtime; we expect it to be ABS32.
-        if (type == R_ARM_ABS32 || type == R_ARM_TARGET1) {
-            if (!IS_IN_RAM(relocs[i].r_offset)) {
-                ERR("Reloc for .data not in RAM address range!");
-                goto out;
-            }
-            uint32_t offset = relocs[i].r_offset - RAM_BASE;
-            uint32_t *addr = (uint32_t *) &data[offset];
-
-            nanoRelocs[numRelocs].type = fixupAddrElf(addr);
-            nanoRelocs[numRelocs].ofstInRam = offset;
-            numRelocs++;
-        } else {
-            // TODO: Assuming that the ELF only contains absolute addresses in
-            // the .data section; may need to handle other relocation types in
-            // the future
-            ERR("Error: Unexpected reloc type %" PRIu32 " at index %zu",
-                type, i);
-            goto out;
-        }
-    }
-
-    DBG("Updating GOT entries (%zu):", gotCount);
-    for (uint32_t offset = sect->got_start; offset < sect->got_end;
-            offset += sizeof(uint32_t)) {
-        uint32_t *addr = (uint32_t *) &data[offset];
-        // Skip values that are set to 0, these seem to be padding (?)
-        if (*addr) {
-            nanoRelocs[numRelocs].type = fixupAddrElf(addr);
-            nanoRelocs[numRelocs].ofstInRam = offset;
-            numRelocs++;
-        }
-    }
-
-    uint32_t packedNanoRelocSz = 0;
-    app->packedNanoRelocs.data = packNanoRelocs(
-        nanoRelocs, numRelocs, &packedNanoRelocSz, verbose);
-    app->packedNanoRelocs.size = packedNanoRelocSz;
-    success = true;
-out:
-    free(nanoRelocs);
-    return success;
-}
-
-static int handleAppStatic(const char *fileName, FILE *out, uint32_t layoutFlags, uint64_t appId, bool verbose)
-{
-    struct ElfNanoApp app;
-
-    if (!loadNanoappElfFile(fileName, &app)
-            || !fixupHeaderElf(&app)
-            || !genElfNanoRelocs(&app, verbose)) {
-        exit(2);
-    }
-
-    // Construct a single contiguous buffer, with extra room to fit the
-    // ImageHeader that will be prepended by finalizeAndWrite(). Note that this
-    // will allocate a bit more space than is needed, because some of the data
-    // from BinHdr will get discarded.
-    // TODO: this should be refactored to just write the binary components in
-    // order rather than allocating a big buffer, and moving data around
-    size_t bufSize = app.flash.size + app.data.size + app.packedNanoRelocs.size
-        + sizeof(struct ImageHeader);
-    uint8_t *buf = malloc(bufSize);
-    if (!buf) {
-        ERR("Failed to allocate %zu bytes for final app", bufSize);
-        exit(2);
-    }
-
-    size_t offset = 0;
-    memcpy(buf, app.flash.data, app.flash.size);
-    offset += app.flash.size;
-    memcpy(&buf[offset], app.data.data, app.data.size);
-    offset += app.data.size;
-    memcpy(&buf[offset], app.packedNanoRelocs.data, app.packedNanoRelocs.size);
-    offset += app.packedNanoRelocs.size;
-
-    // Update rel_end in the header to reflect the packed reloc size
-    struct BinHdr *hdr = (struct BinHdr *) buf;
-    hdr->sect.rel_end = hdr->sect.rel_start + app.packedNanoRelocs.size;
-
-    return finalizeAndWrite(buf, offset, bufSize, out, layoutFlags, appId);
-    // TODO: should free all memory we allocated... just letting the OS handle
-    // it for now
-}
-
 static int handleKey(uint8_t **pbuf, uint32_t bufUsed, FILE *out, uint32_t layoutFlags, uint64_t appId, uint64_t keyId)
 {
     uint8_t *buf = *pbuf;
@@ -905,7 +648,6 @@ int main(int argc, char **argv)
     const char *layoutName = "app";
     const char *prev = NULL;
     bool bareData = false;
-    bool staticElf = false;
 
     for (int i = 1; i < argc; i++) {
         char *end = NULL;
@@ -915,8 +657,6 @@ int main(int argc, char **argv)
                 verbose = true;
             else if (!strcmp(argv[i], "-r"))
                 bareData = true;
-            else if (!strcmp(argv[i], "-s"))
-                staticElf = true;
             else if (!strcmp(argv[i], "-a"))
                 u64Arg = &appId;
             else if (!strcmp(argv[i], "-k"))
@@ -969,9 +709,6 @@ int main(int argc, char **argv)
             fatalUsage(appName, "Invalid layout name", layoutName);
     }
 
-    if (staticElf && layoutId != LAYOUT_APP)
-        fatalUsage(appName, "Only app layout is supported for static option", NULL);
-
     if (layoutId == LAYOUT_APP && !appId)
         fatalUsage(appName, "App layout requires app ID", NULL);
     if (layoutId == LAYOUT_KEY && !keyId)
@@ -979,25 +716,22 @@ int main(int argc, char **argv)
     if (layoutId == LAYOUT_OS && (keyId || appId))
         fatalUsage(appName, "OS layout does not need any ID", NULL);
 
-    if (!staticElf) {
-        buf = loadFile(posArg[0], &bufUsed);
-        fprintf(stderr, "Read %" PRIu32 " bytes\n", bufUsed);
-    }
-
-    if (!posArg[1])
+    if (!posArg[1]) {
         out = stdout;
-    else
+        stdlog = stderr;
+    } else {
         out = fopen(posArg[1], "w");
+        stdlog = stdout;
+    }
     if (!out)
         fatalUsage(appName, "failed to create/open output file", posArg[1]);
 
+    buf = loadFile(posArg[0], &bufUsed);
+    DBG("Read %" PRIu32 " bytes from %s", bufUsed, posArg[0]);
+
     switch(layoutId) {
     case LAYOUT_APP:
-        if (staticElf) {
-            ret = handleAppStatic(posArg[0], out, layoutFlags, appId, verbose);
-        } else {
-            ret = handleApp(&buf, bufUsed, out, layoutFlags, appId, verbose);
-        }
+        ret = handleApp(&buf, bufUsed, out, layoutFlags, appId, verbose);
         break;
     case LAYOUT_KEY:
         ret = handleKey(&buf, bufUsed, out, layoutFlags, appId, keyId);
diff --git a/util/nanoapp_postprocess/postprocess_elf.c b/util/nanoapp_postprocess/postprocess_elf.c
new file mode 100644
index 00000000..739454ce
--- /dev/null
+++ b/util/nanoapp_postprocess/postprocess_elf.c
@@ -0,0 +1,1013 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <assert.h>
+#include <fcntl.h>
+#include <gelf.h>
+#include <libelf.h>
+#include <sys/types.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include <nanohub/nanohub.h>
+#include <nanohub/nanoapp.h>
+#include <nanohub/appRelocFormat.h>
+
+//This code assumes it is run on a LE CPU with unaligned access abilities. Sorry.
+
+#define FLASH_BASE  0x10000000
+#define RAM_BASE    0x80000000
+
+#define FLASH_SIZE  0x10000000  //256MB ought to be enough for everyone
+#define RAM_SIZE    0x10000000  //256MB ought to be enough for everyone
+
+//caution: double evaluation
+#define IS_IN_RANGE_E(_val, _rstart, _rend) (((_val) >= (_rstart)) && ((_val) < (_rend)))
+#define IS_IN_RANGE(_val, _rstart, _rsz)    IS_IN_RANGE_E((_val), (_rstart), ((_rstart) + (_rsz)))
+#define IS_IN_RAM(_val)              IS_IN_RANGE(_val, RAM_BASE, RAM_SIZE)
+#define IS_IN_FLASH(_val)            IS_IN_RANGE(_val, FLASH_BASE, FLASH_SIZE)
+
+
+#define NANO_RELOC_TYPE_RAM    0
+#define NANO_RELOC_TYPE_FLASH  1
+#define NANO_RELOC_LAST        2 //must be <= (RELOC_TYPE_MASK >> RELOC_TYPE_SHIFT)
+
+struct RelocEntry {
+    uint32_t where;
+    uint32_t info;  //bottom 8 bits is type, top 24 is sym idx
+};
+
+#define RELOC_TYPE_ABS_S    2
+#define RELOC_TYPE_ABS_D    21
+#define RELOC_TYPE_SECT     23
+
+
+struct SymtabEntry {
+    uint32_t a;
+    uint32_t addr;
+    uint32_t b, c;
+};
+
+struct NanoRelocEntry {
+    uint32_t ofstInRam;
+    uint8_t type;
+};
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(ary) (sizeof(ary) / sizeof((ary)[0]))
+#endif
+
+#define DBG(fmt, ...) printf(fmt "\n", ##__VA_ARGS__)
+#define ERR(fmt, ...) fprintf(stderr, fmt "\n", ##__VA_ARGS__)
+
+// Prints the given message followed by the most recent libelf error
+#define ELF_ERR(fmt, ...) ERR(fmt ": %s\n", ##__VA_ARGS__, elf_errmsg(-1))
+
+struct ElfAppSection {
+    void  *data;
+    size_t size;
+};
+
+struct ElfNanoApp {
+    struct ElfAppSection flash;
+    struct ElfAppSection data;
+    struct ElfAppSection relocs;
+    struct ElfAppSection symtab;
+
+    // Not parsed from file, but constructed via genElfNanoRelocs
+    struct ElfAppSection packedNanoRelocs;
+};
+
+static void fatalUsage(const char *name, const char *msg, const char *arg)
+{
+    if (msg && arg)
+        fprintf(stderr, "Error: %s: %s\n\n", msg, arg);
+    else if (msg)
+        fprintf(stderr, "Error: %s\n\n", msg);
+
+    fprintf(stderr, "USAGE: %s [-v] [-k <key id>] [-a <app id>] [-r] [-n <layout name>] [-i <layout id>] <input file> [<output file>]\n"
+                    "       -v               : be verbose\n"
+                    "       -n <layout name> : app, os, key\n"
+                    "       -i <layout id>   : 1 (app), 2 (key), 3 (os)\n"
+                    "       -f <layout flags>: 16-bit hex value, stored as layout-specific flags\n"
+                    "       -a <app ID>      : 64-bit hex number != 0\n"
+                    "       -k <key ID>      : 64-bit hex number != 0\n"
+                    "       -r               : bare (no AOSP header); used only for inner OS image generation\n"
+                    "       -s               : treat input as statically linked ELF (app layout only)\n"
+                    "       layout ID and layout name control the same parameter, so only one of them needs to be used\n"
+                    , name);
+    exit(1);
+}
+
+static uint8_t *packNanoRelocs(struct NanoRelocEntry *nanoRelocs, uint32_t outNumRelocs, uint32_t *finalPackedNanoRelocSz, bool verbose)
+{
+    uint32_t i, j, k;
+    uint8_t *packedNanoRelocs;
+    uint32_t packedNanoRelocSz;
+    uint32_t lastOutType = 0, origin = 0;
+
+    //sort by type and then offset
+    for (i = 0; i < outNumRelocs; i++) {
+        struct NanoRelocEntry t;
+
+        for (k = i, j = k + 1; j < outNumRelocs; j++) {
+            if (nanoRelocs[j].type > nanoRelocs[k].type)
+                continue;
+            if ((nanoRelocs[j].type < nanoRelocs[k].type) || (nanoRelocs[j].ofstInRam < nanoRelocs[k].ofstInRam))
+                k = j;
+        }
+        memcpy(&t, nanoRelocs + i, sizeof(struct NanoRelocEntry));
+        memcpy(nanoRelocs + i, nanoRelocs + k, sizeof(struct NanoRelocEntry));
+        memcpy(nanoRelocs + k, &t, sizeof(struct NanoRelocEntry));
+
+        if (verbose)
+            fprintf(stderr, "SortedReloc[%3" PRIu32 "] = {0x%08" PRIX32 ",0x%02" PRIX8 "}\n", i, nanoRelocs[i].ofstInRam, nanoRelocs[i].type);
+    }
+
+    //produce output nanorelocs in packed format
+    packedNanoRelocs = malloc(outNumRelocs * 6); //definitely big enough
+    packedNanoRelocSz = 0;
+    for (i = 0; i < outNumRelocs; i++) {
+        uint32_t displacement;
+
+        if (lastOutType != nanoRelocs[i].type) {  //output type if ti changed
+            if (nanoRelocs[i].type - lastOutType == 1) {
+                packedNanoRelocs[packedNanoRelocSz++] = TOKEN_RELOC_TYPE_NEXT;
+                if (verbose)
+                    fprintf(stderr, "Out: RelocTC (1) // to 0x%02" PRIX8 "\n", nanoRelocs[i].type);
+            }
+            else {
+                packedNanoRelocs[packedNanoRelocSz++] = TOKEN_RELOC_TYPE_CHG;
+                packedNanoRelocs[packedNanoRelocSz++] = nanoRelocs[i].type - lastOutType - 1;
+                if (verbose)
+                    fprintf(stderr, "Out: RelocTC (0x%02" PRIX8 ")  // to 0x%02" PRIX8 "\n", (uint8_t)(nanoRelocs[i].type - lastOutType - 1), nanoRelocs[i].type);
+            }
+            lastOutType = nanoRelocs[i].type;
+            origin = 0;
+        }
+        displacement = nanoRelocs[i].ofstInRam - origin;
+        origin = nanoRelocs[i].ofstInRam + 4;
+        if (displacement & 3) {
+            fprintf(stderr, "Unaligned relocs are not possible!\n");
+            exit(-5);
+        }
+        displacement /= 4;
+
+        //might be start of a run. look into that
+        if (!displacement) {
+            for (j = 1; j + i < outNumRelocs && j < MAX_RUN_LEN && nanoRelocs[j + i].type == lastOutType && nanoRelocs[j + i].ofstInRam - nanoRelocs[j + i - 1].ofstInRam == 4; j++);
+            if (j >= MIN_RUN_LEN) {
+                if (verbose)
+                    fprintf(stderr, "Out: Reloc0  x%" PRIX32 "\n", j);
+                packedNanoRelocs[packedNanoRelocSz++] = TOKEN_CONSECUTIVE;
+                packedNanoRelocs[packedNanoRelocSz++] = j - MIN_RUN_LEN;
+                origin = nanoRelocs[j + i - 1].ofstInRam + 4;  //reset origin to last one
+                i += j - 1;  //loop will increment anyways, hence +1
+                continue;
+            }
+        }
+
+        //produce output
+        if (displacement <= MAX_8_BIT_NUM) {
+            if (verbose)
+                fprintf(stderr, "Out: Reloc8  0x%02" PRIX32 "\n", displacement);
+            packedNanoRelocs[packedNanoRelocSz++] = displacement;
+        }
+        else if (displacement <= MAX_16_BIT_NUM) {
+            if (verbose)
+                fprintf(stderr, "Out: Reloc16 0x%06" PRIX32 "\n", displacement);
+                        displacement -= MAX_8_BIT_NUM;
+            packedNanoRelocs[packedNanoRelocSz++] = TOKEN_16BIT_OFST;
+            packedNanoRelocs[packedNanoRelocSz++] = displacement;
+            packedNanoRelocs[packedNanoRelocSz++] = displacement >> 8;
+        }
+        else if (displacement <= MAX_24_BIT_NUM) {
+            if (verbose)
+                fprintf(stderr, "Out: Reloc24 0x%08" PRIX32 "\n", displacement);
+                        displacement -= MAX_16_BIT_NUM;
+            packedNanoRelocs[packedNanoRelocSz++] = TOKEN_24BIT_OFST;
+            packedNanoRelocs[packedNanoRelocSz++] = displacement;
+            packedNanoRelocs[packedNanoRelocSz++] = displacement >> 8;
+            packedNanoRelocs[packedNanoRelocSz++] = displacement >> 16;
+        }
+        else  {
+            if (verbose)
+                fprintf(stderr, "Out: Reloc32 0x%08" PRIX32 "\n", displacement);
+            packedNanoRelocs[packedNanoRelocSz++] = TOKEN_32BIT_OFST;
+            packedNanoRelocs[packedNanoRelocSz++] = displacement;
+            packedNanoRelocs[packedNanoRelocSz++] = displacement >> 8;
+            packedNanoRelocs[packedNanoRelocSz++] = displacement >> 16;
+            packedNanoRelocs[packedNanoRelocSz++] = displacement >> 24;
+        }
+    }
+
+    *finalPackedNanoRelocSz = packedNanoRelocSz;
+    return packedNanoRelocs;
+}
+
+static int finalizeAndWrite(uint8_t *buf, uint32_t bufUsed, uint32_t bufSz, FILE *out, uint32_t layoutFlags, uint64_t appId)
+{
+    int ret;
+    struct AppInfo app;
+    struct SectInfo *sect;
+    struct BinHdr *bin = (struct BinHdr *) buf;
+    struct ImageHeader outHeader = {
+        .aosp = (struct nano_app_binary_t) {
+            .header_version = 1,
+            .magic = NANOAPP_AOSP_MAGIC,
+            .app_id = appId,
+            .app_version = bin->hdr.appVer,
+            .flags       = 0, // encrypted (1), signed (2) (will be set by other tools)
+        },
+        .layout = (struct ImageLayout) {
+            .magic = GOOGLE_LAYOUT_MAGIC,
+            .version = 1,
+            .payload = LAYOUT_APP,
+            .flags = layoutFlags,
+        },
+    };
+    uint32_t dataOffset = sizeof(outHeader) + sizeof(app);
+    uint32_t hdrDiff = dataOffset - sizeof(*bin);
+    app.sect = bin->sect;
+    app.vec  = bin->vec;
+
+    assertMem(bufUsed + hdrDiff, bufSz);
+
+    memmove(buf + dataOffset, buf + sizeof(*bin), bufUsed - sizeof(*bin));
+    bufUsed += hdrDiff;
+    memcpy(buf, &outHeader, sizeof(outHeader));
+    memcpy(buf + sizeof(outHeader), &app, sizeof(app));
+    sect = &app.sect;
+
+    //if we have any bytes to output, show stats
+    if (bufUsed) {
+        uint32_t codeAndRoDataSz = sect->data_data;
+        uint32_t relocsSz = sect->rel_end - sect->rel_start;
+        uint32_t gotSz = sect->got_end - sect->data_start;
+        uint32_t bssSz = sect->bss_end - sect->bss_start;
+
+        fprintf(stderr,"Final binary size %" PRIu32 " bytes\n", bufUsed);
+        fprintf(stderr, "\n");
+        fprintf(stderr, "       FW header size (flash):      %6zu bytes\n", FLASH_RELOC_OFFSET);
+        fprintf(stderr, "       Code + RO data (flash):      %6" PRIu32 " bytes\n", codeAndRoDataSz);
+        fprintf(stderr, "       Relocs (flash):              %6" PRIu32 " bytes\n", relocsSz);
+        fprintf(stderr, "       GOT + RW data (flash & RAM): %6" PRIu32 " bytes\n", gotSz);
+        fprintf(stderr, "       BSS (RAM):                   %6" PRIu32 " bytes\n", bssSz);
+        fprintf(stderr, "\n");
+        fprintf(stderr,"Runtime flash use: %" PRIu32 " bytes\n", (uint32_t)(codeAndRoDataSz + relocsSz + gotSz + FLASH_RELOC_OFFSET));
+        fprintf(stderr,"Runtime RAM use: %" PRIu32 " bytes\n", gotSz + bssSz);
+    }
+
+    ret = fwrite(buf, bufUsed, 1, out) == 1 ? 0 : 2;
+    if (ret)
+        fprintf(stderr, "Failed to write output file: %s\n", strerror(errno));
+
+    return ret;
+}
+
+static int handleApp(uint8_t **pbuf, uint32_t bufUsed, FILE *out, uint32_t layoutFlags, uint64_t appId, bool verbose)
+{
+    uint32_t i, numRelocs, numSyms, outNumRelocs = 0, packedNanoRelocSz;
+    struct NanoRelocEntry *nanoRelocs = NULL;
+    struct RelocEntry *relocs;
+    struct SymtabEntry *syms;
+    uint8_t *packedNanoRelocs;
+    uint32_t t;
+    struct BinHdr *bin;
+    int ret = -1;
+    struct SectInfo *sect;
+    uint8_t *buf = *pbuf;
+    uint32_t bufSz = bufUsed * 3 /2;
+
+    //make buffer 50% bigger than bufUsed in case relocs grow out of hand
+    buf = reallocOrDie(buf, bufSz);
+    *pbuf = buf;
+
+    //sanity checks
+    bin = (struct BinHdr*)buf;
+    if (bufUsed < sizeof(*bin)) {
+        fprintf(stderr, "File size too small\n");
+        goto out;
+    }
+
+    if (bin->hdr.magic != NANOAPP_FW_MAGIC) {
+        fprintf(stderr, "Magic value is wrong: found %08" PRIX32
+                        "; expected %08" PRIX32 "\n",
+                        bin->hdr.magic, NANOAPP_FW_MAGIC);
+        goto out;
+    }
+
+    sect = &bin->sect;
+
+    //do some math
+    relocs = (struct RelocEntry*)(buf + sect->rel_start - FLASH_BASE);
+    syms = (struct SymtabEntry*)(buf + sect->rel_end - FLASH_BASE);
+    numRelocs = (sect->rel_end - sect->rel_start) / sizeof(struct RelocEntry);
+    numSyms = (bufUsed + FLASH_BASE - sect->rel_end) / sizeof(struct SymtabEntry);
+
+    //sanity
+    if (numRelocs * sizeof(struct RelocEntry) + sect->rel_start != sect->rel_end) {
+        fprintf(stderr, "Relocs of nonstandard size\n");
+        goto out;
+    }
+    if (numSyms * sizeof(struct SymtabEntry) + sect->rel_end != bufUsed + FLASH_BASE) {
+        fprintf(stderr, "Syms of nonstandard size\n");
+        goto out;
+    }
+
+    //show some info
+    fprintf(stderr, "\nRead %" PRIu32 " bytes of binary.\n", bufUsed);
+
+    if (verbose)
+        fprintf(stderr, "Found %" PRIu32 " relocs and a %" PRIu32 "-entry symbol table\n", numRelocs, numSyms);
+
+    //handle relocs
+    nanoRelocs = malloc(sizeof(struct NanoRelocEntry[numRelocs]));
+    if (!nanoRelocs) {
+        fprintf(stderr, "Failed to allocate a nano-reloc table\n");
+        goto out;
+    }
+
+    for (i = 0; i < numRelocs; i++) {
+        uint32_t relocType = relocs[i].info & 0xff;
+        uint32_t whichSym = relocs[i].info >> 8;
+        uint32_t *valThereP;
+
+        if (whichSym >= numSyms) {
+            fprintf(stderr, "Reloc %" PRIu32 " references a nonexistent symbol!\n"
+                            "INFO:\n"
+                            "        Where: 0x%08" PRIX32 "\n"
+                            "        type: %" PRIu32 "\n"
+                            "        sym: %" PRIu32 "\n",
+                i, relocs[i].where, relocs[i].info & 0xff, whichSym);
+            goto out;
+        }
+
+        if (verbose) {
+            const char *seg;
+
+            fprintf(stderr, "Reloc[%3" PRIu32 "]:\n {@0x%08" PRIX32 ", type %3" PRIu32 ", -> sym[%3" PRIu32 "]: {@0x%08" PRIX32 "}, ",
+                i, relocs[i].where, relocs[i].info & 0xff, whichSym, syms[whichSym].addr);
+
+            if (IS_IN_RANGE_E(relocs[i].where, sect->bss_start, sect->bss_end))
+                seg = ".bss";
+            else if (IS_IN_RANGE_E(relocs[i].where, sect->data_start, sect->data_end))
+                seg = ".data";
+            else if (IS_IN_RANGE_E(relocs[i].where, sect->got_start, sect->got_end))
+                seg = ".got";
+            else if (IS_IN_RANGE_E(relocs[i].where, FLASH_BASE, FLASH_BASE + sizeof(struct BinHdr)))
+                seg = "APPHDR";
+            else
+                seg = "???";
+
+            fprintf(stderr, "in   %s}\n", seg);
+        }
+        /* handle relocs inside the header */
+        if (IS_IN_FLASH(relocs[i].where) && relocs[i].where - FLASH_BASE < sizeof(struct BinHdr) && relocType == RELOC_TYPE_SECT) {
+            /* relocs in header are special - runtime corrects for them */
+            if (syms[whichSym].addr) {
+                fprintf(stderr, "Weird in-header sect reloc %" PRIu32 " to symbol %" PRIu32 " with nonzero addr 0x%08" PRIX32 "\n",
+                        i, whichSym, syms[whichSym].addr);
+                goto out;
+            }
+
+            valThereP = (uint32_t*)(buf + relocs[i].where - FLASH_BASE);
+            if (!IS_IN_FLASH(*valThereP)) {
+                fprintf(stderr, "In-header reloc %" PRIu32 " of location 0x%08" PRIX32 " is outside of FLASH!\n"
+                                "INFO:\n"
+                                "        type: %" PRIu32 "\n"
+                                "        sym: %" PRIu32 "\n"
+                                "        Sym Addr: 0x%08" PRIX32 "\n",
+                                i, relocs[i].where, relocType, whichSym, syms[whichSym].addr);
+                goto out;
+            }
+
+            // binary header generated by objcopy, .napp header and final FW header in flash are of different size.
+            // we subtract binary header offset here, so all the entry points are relative to beginning of "sect".
+            // FW will use &sect as a base to call these vectors; no more problems with different header sizes;
+            // Assumption: offsets between sect & vec, vec & code are the same in all images (or, in a simpler words, { sect, vec, code }
+            // must go together). this is enforced by linker script, and maintained by all tools and FW download code in the OS.
+            *valThereP -= FLASH_BASE + BINARY_RELOC_OFFSET;
+
+            if (verbose)
+                fprintf(stderr, "  -> Nano reloc skipped for in-header reloc\n");
+
+            continue; /* do not produce an output reloc */
+        }
+
+        if (!IS_IN_RAM(relocs[i].where)) {
+            fprintf(stderr, "In-header reloc %" PRIu32 " of location 0x%08" PRIX32 " is outside of RAM!\n"
+                            "INFO:\n"
+                            "        type: %" PRIu32 "\n"
+                            "        sym: %" PRIu32 "\n"
+                            "        Sym Addr: 0x%08" PRIX32 "\n",
+                            i, relocs[i].where, relocType, whichSym, syms[whichSym].addr);
+            goto out;
+        }
+
+        valThereP = (uint32_t*)(buf + relocs[i].where + sect->data_data - RAM_BASE - FLASH_BASE);
+
+        nanoRelocs[outNumRelocs].ofstInRam = relocs[i].where - RAM_BASE;
+
+        switch (relocType) {
+            case RELOC_TYPE_ABS_S:
+            case RELOC_TYPE_ABS_D:
+                t = *valThereP;
+
+                (*valThereP) += syms[whichSym].addr;
+
+                if (IS_IN_FLASH(syms[whichSym].addr)) {
+                    (*valThereP) -= FLASH_BASE + BINARY_RELOC_OFFSET;
+                    nanoRelocs[outNumRelocs].type = NANO_RELOC_TYPE_FLASH;
+                }
+                else if (IS_IN_RAM(syms[whichSym].addr)) {
+                    (*valThereP) -= RAM_BASE;
+                    nanoRelocs[outNumRelocs].type = NANO_RELOC_TYPE_RAM;
+                }
+                else {
+                    fprintf(stderr, "Weird reloc %" PRIu32 " to symbol %" PRIu32 " in unknown memory space (addr 0x%08" PRIX32 ")\n",
+                            i, whichSym, syms[whichSym].addr);
+                    goto out;
+                }
+                if (verbose)
+                    fprintf(stderr, "  -> Abs reference fixed up 0x%08" PRIX32 " -> 0x%08" PRIX32 "\n", t, *valThereP);
+                break;
+
+            case RELOC_TYPE_SECT:
+                if (syms[whichSym].addr) {
+                    fprintf(stderr, "Weird sect reloc %" PRIu32 " to symbol %" PRIu32 " with nonzero addr 0x%08" PRIX32 "\n",
+                            i, whichSym, syms[whichSym].addr);
+                    goto out;
+                }
+
+                t = *valThereP;
+
+                if (IS_IN_FLASH(*valThereP)) {
+                    nanoRelocs[outNumRelocs].type = NANO_RELOC_TYPE_FLASH;
+                    *valThereP -= FLASH_BASE + BINARY_RELOC_OFFSET;
+                }
+                else if (IS_IN_RAM(*valThereP)) {
+                    nanoRelocs[outNumRelocs].type = NANO_RELOC_TYPE_RAM;
+                    *valThereP -= RAM_BASE;
+                }
+                else {
+                    fprintf(stderr, "Weird sec reloc %" PRIu32 " to symbol %" PRIu32
+                                    " in unknown memory space (addr 0x%08" PRIX32 ")\n",
+                                    i, whichSym, *valThereP);
+                    goto out;
+                }
+                if (verbose)
+                    fprintf(stderr, "  -> Sect reference fixed up 0x%08" PRIX32 " -> 0x%08" PRIX32 "\n", t, *valThereP);
+                break;
+
+            default:
+                fprintf(stderr, "Weird reloc %" PRIX32 " type %" PRIX32 " to symbol %" PRIX32 "\n", i, relocType, whichSym);
+                goto out;
+        }
+
+        if (verbose)
+            fprintf(stderr, "  -> Nano reloc calculated as 0x%08" PRIX32 ",0x%02" PRIX8 "\n", nanoRelocs[i].ofstInRam, nanoRelocs[i].type);
+        outNumRelocs++;
+    }
+
+    packedNanoRelocs = packNanoRelocs(nanoRelocs, outNumRelocs, &packedNanoRelocSz, verbose);
+
+    //overwrite original relocs and symtab with nanorelocs and adjust sizes
+    memcpy(relocs, packedNanoRelocs, packedNanoRelocSz);
+    bufUsed -= sizeof(struct RelocEntry[numRelocs]);
+    bufUsed -= sizeof(struct SymtabEntry[numSyms]);
+    bufUsed += packedNanoRelocSz;
+    assertMem(bufUsed, bufSz);
+    sect->rel_end = sect->rel_start + packedNanoRelocSz;
+
+    //sanity
+    if (sect->rel_end - FLASH_BASE != bufUsed) {
+        fprintf(stderr, "Relocs end and file end not coincident\n");
+        goto out;
+    }
+
+    //adjust headers for easy access (RAM)
+    if (!IS_IN_RAM(sect->data_start) || !IS_IN_RAM(sect->data_end) || !IS_IN_RAM(sect->bss_start) ||
+        !IS_IN_RAM(sect->bss_end) || !IS_IN_RAM(sect->got_start) || !IS_IN_RAM(sect->got_end)) {
+        fprintf(stderr, "data, bss, or got not in ram\n");
+        goto out;
+    }
+    sect->data_start -= RAM_BASE;
+    sect->data_end -= RAM_BASE;
+    sect->bss_start -= RAM_BASE;
+    sect->bss_end -= RAM_BASE;
+    sect->got_start -= RAM_BASE;
+    sect->got_end -= RAM_BASE;
+
+    //adjust headers for easy access (FLASH)
+    if (!IS_IN_FLASH(sect->data_data) || !IS_IN_FLASH(sect->rel_start) || !IS_IN_FLASH(sect->rel_end)) {
+        fprintf(stderr, "data.data, or rel not in flash\n");
+        goto out;
+    }
+    sect->data_data -= FLASH_BASE + BINARY_RELOC_OFFSET;
+    sect->rel_start -= FLASH_BASE + BINARY_RELOC_OFFSET;
+    sect->rel_end -= FLASH_BASE + BINARY_RELOC_OFFSET;
+
+    ret = finalizeAndWrite(buf, bufUsed, bufSz, out, layoutFlags, appId);
+out:
+    free(nanoRelocs);
+    return ret;
+}
+
+static void elfExtractSectionPointer(const Elf_Data *data, const char *name, struct ElfNanoApp *app)
+{
+    // Maps section names to their byte offset in struct ElfNanoApp. Note that
+    // this assumes that the linker script puts text/code in the .flash section,
+    // RW data in .data, that relocs for .data are included in .rel.data, and
+    // the symbol table is emitted in .symtab
+    const struct SectionMap {
+        const char *name;
+        size_t offset;
+    } sectionMap[] = {
+        {
+            .name = ".flash",
+            .offset = offsetof(struct ElfNanoApp, flash),
+        },
+        {
+            .name = ".data",
+            .offset = offsetof(struct ElfNanoApp, data),
+        },
+        {
+            .name = ".rel.data",
+            .offset = offsetof(struct ElfNanoApp, relocs),
+        },
+        {
+            .name = ".symtab",
+            .offset = offsetof(struct ElfNanoApp, symtab),
+        },
+    };
+    struct ElfAppSection *appSection;
+    uint8_t *appBytes = (uint8_t *) app;
+
+    for (size_t i = 0; i < ARRAY_SIZE(sectionMap); i++) {
+        if (strcmp(name, sectionMap[i].name) != 0) {
+            continue;
+        }
+        appSection = (struct ElfAppSection *) &appBytes[sectionMap[i].offset];
+
+        appSection->data = data->d_buf;
+        appSection->size = data->d_size;
+
+        DBG("Found section %s with size %zu", name, appSection->size);
+        break;
+    }
+}
+
+// Populates a struct ElfNanoApp with data parsed from the ELF
+static bool elfParse(Elf *elf, struct ElfNanoApp *app)
+{
+    size_t shdrstrndx;
+    Elf_Scn *scn = NULL;
+    GElf_Shdr shdr;
+    char *sectionName;
+    Elf_Data *elf_data;
+
+    memset(app, 0, sizeof(*app));
+    if (elf_getshdrstrndx(elf, &shdrstrndx) != 0) {
+        ELF_ERR("Couldn't get section name string table index");
+        return false;
+    }
+
+    while ((scn = elf_nextscn(elf, scn)) != NULL) {
+        if (gelf_getshdr(scn, &shdr) != &shdr) {
+            ELF_ERR("Error getting section header");
+            return false;
+        }
+        sectionName = elf_strptr(elf, shdrstrndx, shdr.sh_name);
+
+        elf_data = elf_getdata(scn, NULL);
+        if (!elf_data) {
+            ELF_ERR("Error getting data for section %s", sectionName);
+            return false;
+        }
+
+        elfExtractSectionPointer(elf_data, sectionName, app);
+    }
+
+    return true;
+}
+
+static bool loadNanoappElfFile(const char *fileName, struct ElfNanoApp *app)
+{
+    int fd;
+    Elf *elf;
+
+    if (elf_version(EV_CURRENT) == EV_NONE) {
+        ELF_ERR("Failed to initialize ELF library");
+        return false;
+    }
+
+    fd = open(fileName, O_RDONLY, 0);
+    if (fd < 0) {
+        ERR("Failed to open file %s for reading: %s", fileName, strerror(errno));
+        return false;
+    }
+
+    elf = elf_begin(fd, ELF_C_READ, NULL);
+    if (elf == NULL) {
+        ELF_ERR("Failed to open ELF");
+        return false;
+    }
+
+    if (!elfParse(elf, app)) {
+        ERR("Failed to parse ELF file");
+        return false;
+    }
+
+    return true;
+}
+
+// Subtracts the fixed memory region offset from an absolute address and returns
+// the associated NANO_RELOC_* value, or NANO_RELOC_LAST if the address is not
+// in the expected range.
+// Not strictly tied to ELF usage, but handled slightly differently.
+static uint8_t fixupAddrElf(uint32_t *addr)
+{
+    uint8_t type;
+
+    // TODO: this assumes that the host running this tool has the same
+    // endianness as the image file/target processor
+    if (IS_IN_FLASH(*addr)) {
+        DBG("Fixup addr 0x%08" PRIX32 " (flash) --> 0x%08" PRIX32, *addr,
+            (uint32_t) (*addr - (FLASH_BASE + BINARY_RELOC_OFFSET)));
+        *addr -= FLASH_BASE + BINARY_RELOC_OFFSET;
+        type = NANO_RELOC_TYPE_FLASH;
+    } else if (IS_IN_RAM(*addr)) {
+        DBG("Fixup addr 0x%08" PRIX32 " (ram)   --> 0x%08" PRIX32, *addr,
+            *addr - RAM_BASE);
+        *addr -= RAM_BASE;
+        type = NANO_RELOC_TYPE_RAM;
+    } else {
+        DBG("Error: invalid address 0x%08" PRIX32, *addr);
+        type = NANO_RELOC_LAST;
+    }
+
+    return type;
+}
+
+// Fixup addresses in the header to be relative. Not strictly tied to the ELF
+// format, but used only in that program flow in the current implementation.
+static bool fixupHeaderElf(const struct ElfNanoApp *app)
+{
+    struct BinHdr *hdr = (struct BinHdr *) app->flash.data;
+
+    DBG("Appyling fixups to header");
+    if (fixupAddrElf(&hdr->sect.data_start) != NANO_RELOC_TYPE_RAM ||
+        fixupAddrElf(&hdr->sect.data_end)   != NANO_RELOC_TYPE_RAM ||
+        fixupAddrElf(&hdr->sect.bss_start)  != NANO_RELOC_TYPE_RAM ||
+        fixupAddrElf(&hdr->sect.bss_end)    != NANO_RELOC_TYPE_RAM ||
+        fixupAddrElf(&hdr->sect.got_start)  != NANO_RELOC_TYPE_RAM ||
+        fixupAddrElf(&hdr->sect.got_end)    != NANO_RELOC_TYPE_RAM) {
+        ERR(".data, .bss, or .got not in RAM address space!");
+        return false;
+    }
+
+    if (fixupAddrElf(&hdr->sect.rel_start) != NANO_RELOC_TYPE_FLASH ||
+        fixupAddrElf(&hdr->sect.rel_end)   != NANO_RELOC_TYPE_FLASH ||
+        fixupAddrElf(&hdr->sect.data_data) != NANO_RELOC_TYPE_FLASH) {
+        ERR(".data loadaddr, or .relocs not in flash address space!");
+        return false;
+    }
+
+    if (fixupAddrElf(&hdr->vec.init)   != NANO_RELOC_TYPE_FLASH ||
+        fixupAddrElf(&hdr->vec.end)    != NANO_RELOC_TYPE_FLASH ||
+        fixupAddrElf(&hdr->vec.handle) != NANO_RELOC_TYPE_FLASH) {
+        ERR("Entry point(s) not in flash address space!");
+        return false;
+    }
+
+    return true;
+}
+
+// Fixup addresses in .data, .init_array/.fini_array, and .got, and generates
+// packed array of nano reloc entries. The app header must have already been
+// fixed up.
+static bool genElfNanoRelocs(struct ElfNanoApp *app, bool verbose)
+{
+    const struct BinHdr *hdr = (const struct BinHdr *) app->flash.data;
+    const struct SectInfo *sect = &hdr->sect;
+    bool success = false;
+
+    size_t numDataRelocs = app->relocs.size / sizeof(Elf32_Rel);
+    size_t gotCount = (sect->got_end - sect->got_start) / sizeof(uint32_t);
+    size_t numInitFuncs  = (sect->bss_start - sect->data_end) / sizeof(uint32_t);
+
+    size_t totalRelocCount = (numDataRelocs + numInitFuncs + gotCount);
+    struct NanoRelocEntry *nanoRelocs = malloc(
+        totalRelocCount * sizeof(struct NanoRelocEntry));
+    if (!nanoRelocs) {
+        ERR("Couldn't allocate memory for nano relocs! Needed %zu bytes",
+            totalRelocCount * sizeof(struct NanoRelocEntry));
+        return false;
+    }
+
+    uint8_t *data = app->data.data;
+    const Elf32_Rel *relocs = (const Elf32_Rel *) app->relocs.data;
+    const Elf32_Sym *syms   = (const Elf32_Sym *) app->symtab.data;
+    size_t numRelocs = 0;
+
+    DBG("Parsing relocs for .data (%zu):", numDataRelocs);
+    for (size_t i = 0; i < numDataRelocs; i++) {
+        uint32_t type = ELF32_R_TYPE(relocs[i].r_info);
+        uint32_t sym = ELF32_R_SYM(relocs[i].r_info);
+
+        DBG(" [%3zu] 0x%08" PRIx32 " type %2" PRIu32 " symIdx %3" PRIu32
+            " --> 0x%08" PRIx32, i, relocs[i].r_offset, type, sym,
+            syms[sym].st_value);
+        // Note that R_ARM_TARGET1 is used for .init_array/.fini_array support,
+        // and can be interpreted either as ABS32 or REL32, depending on the
+        // runtime; we expect it to be ABS32.
+        if (type == R_ARM_ABS32 || type == R_ARM_TARGET1) {
+            if (!IS_IN_RAM(relocs[i].r_offset)) {
+                ERR("Reloc for .data not in RAM address range!");
+                goto out;
+            }
+            uint32_t offset = relocs[i].r_offset - RAM_BASE;
+            uint32_t *addr = (uint32_t *) &data[offset];
+
+            nanoRelocs[numRelocs].type = fixupAddrElf(addr);
+            nanoRelocs[numRelocs].ofstInRam = offset;
+            numRelocs++;
+        } else {
+            // TODO: Assuming that the ELF only contains absolute addresses in
+            // the .data section; may need to handle other relocation types in
+            // the future
+            ERR("Error: Unexpected reloc type %" PRIu32 " at index %zu",
+                type, i);
+            goto out;
+        }
+    }
+
+    DBG("Updating GOT entries (%zu):", gotCount);
+    for (uint32_t offset = sect->got_start; offset < sect->got_end;
+            offset += sizeof(uint32_t)) {
+        uint32_t *addr = (uint32_t *) &data[offset];
+        // Skip values that are set to 0, these seem to be padding (?)
+        if (*addr) {
+            nanoRelocs[numRelocs].type = fixupAddrElf(addr);
+            nanoRelocs[numRelocs].ofstInRam = offset;
+            numRelocs++;
+        }
+    }
+
+    uint32_t packedNanoRelocSz = 0;
+    app->packedNanoRelocs.data = packNanoRelocs(
+        nanoRelocs, numRelocs, &packedNanoRelocSz, verbose);
+    app->packedNanoRelocs.size = packedNanoRelocSz;
+    success = true;
+out:
+    free(nanoRelocs);
+    return success;
+}
+
+static int handleAppStatic(const char *fileName, FILE *out, uint32_t layoutFlags, uint64_t appId, bool verbose)
+{
+    struct ElfNanoApp app;
+
+    if (!loadNanoappElfFile(fileName, &app)
+            || !fixupHeaderElf(&app)
+            || !genElfNanoRelocs(&app, verbose)) {
+        exit(2);
+    }
+
+    // Construct a single contiguous buffer, with extra room to fit the
+    // ImageHeader that will be prepended by finalizeAndWrite(). Note that this
+    // will allocate a bit more space than is needed, because some of the data
+    // from BinHdr will get discarded.
+    // TODO: this should be refactored to just write the binary components in
+    // order rather than allocating a big buffer, and moving data around
+    size_t bufSize = app.flash.size + app.data.size + app.packedNanoRelocs.size
+        + sizeof(struct ImageHeader);
+    uint8_t *buf = malloc(bufSize);
+    if (!buf) {
+        ERR("Failed to allocate %zu bytes for final app", bufSize);
+        exit(2);
+    }
+
+    size_t offset = 0;
+    memcpy(buf, app.flash.data, app.flash.size);
+    offset += app.flash.size;
+    memcpy(&buf[offset], app.data.data, app.data.size);
+    offset += app.data.size;
+    memcpy(&buf[offset], app.packedNanoRelocs.data, app.packedNanoRelocs.size);
+    offset += app.packedNanoRelocs.size;
+
+    // Update rel_end in the header to reflect the packed reloc size
+    struct BinHdr *hdr = (struct BinHdr *) buf;
+    hdr->sect.rel_end = hdr->sect.rel_start + app.packedNanoRelocs.size;
+
+    return finalizeAndWrite(buf, offset, bufSize, out, layoutFlags, appId);
+    // TODO: should free all memory we allocated... just letting the OS handle
+    // it for now
+}
+
+static int handleKey(uint8_t **pbuf, uint32_t bufUsed, FILE *out, uint32_t layoutFlags, uint64_t appId, uint64_t keyId)
+{
+    uint8_t *buf = *pbuf;
+    struct KeyInfo ki = { .data = keyId };
+    bool good = true;
+
+    struct ImageHeader outHeader = {
+        .aosp = (struct nano_app_binary_t) {
+            .header_version = 1,
+            .magic = NANOAPP_AOSP_MAGIC,
+            .app_id = appId,
+        },
+        .layout = (struct ImageLayout) {
+            .magic = GOOGLE_LAYOUT_MAGIC,
+            .version = 1,
+            .payload = LAYOUT_KEY,
+            .flags = layoutFlags,
+        },
+    };
+
+    good = good && fwrite(&outHeader, sizeof(outHeader), 1, out) == 1;
+    good = good && fwrite(&ki, sizeof(ki), 1, out) ==  1;
+    good = good && fwrite(buf, bufUsed, 1, out) == 1;
+
+    return good ? 0 : 2;
+}
+
+static int handleOs(uint8_t **pbuf, uint32_t bufUsed, FILE *out, uint32_t layoutFlags, bool bare)
+{
+    uint8_t *buf = *pbuf;
+    bool good;
+
+    struct OsUpdateHdr os = {
+        .magic = OS_UPDT_MAGIC,
+        .marker = OS_UPDT_MARKER_INPROGRESS,
+        .size = bufUsed
+    };
+
+    struct ImageHeader outHeader = {
+        .aosp = (struct nano_app_binary_t) {
+            .header_version = 1,
+            .magic = NANOAPP_AOSP_MAGIC,
+        },
+        .layout = (struct ImageLayout) {
+            .magic = GOOGLE_LAYOUT_MAGIC,
+            .version = 1,
+            .payload = LAYOUT_OS,
+            .flags = layoutFlags,
+        },
+    };
+
+    if (!bare)
+        good = fwrite(&outHeader, sizeof(outHeader), 1, out) == 1;
+    else
+        good = fwrite(&os, sizeof(os), 1, out) == 1;
+    good = good && fwrite(buf, bufUsed, 1, out) == 1;
+
+    return good ? 0 : 2;
+}
+
+int main(int argc, char **argv)
+{
+    uint32_t bufUsed = 0;
+    bool verbose = false;
+    uint8_t *buf = NULL;
+    uint64_t appId = 0;
+    uint64_t keyId = 0;
+    uint32_t layoutId = 0;
+    uint32_t layoutFlags = 0;
+    int ret = -1;
+    uint32_t *u32Arg = NULL;
+    uint64_t *u64Arg = NULL;
+    const char **strArg = NULL;
+    const char *appName = argv[0];
+    int posArgCnt = 0;
+    const char *posArg[2] = { NULL };
+    FILE *out = NULL;
+    const char *layoutName = "app";
+    const char *prev = NULL;
+    bool bareData = false;
+    bool staticElf = false;
+
+    for (int i = 1; i < argc; i++) {
+        char *end = NULL;
+        if (argv[i][0] == '-') {
+            prev = argv[i];
+            if (!strcmp(argv[i], "-v"))
+                verbose = true;
+            else if (!strcmp(argv[i], "-r"))
+                bareData = true;
+            else if (!strcmp(argv[i], "-s"))
+                staticElf = true;
+            else if (!strcmp(argv[i], "-a"))
+                u64Arg = &appId;
+            else if (!strcmp(argv[i], "-k"))
+                u64Arg = &keyId;
+            else if (!strcmp(argv[i], "-n"))
+                strArg = &layoutName;
+            else if (!strcmp(argv[i], "-i"))
+                u32Arg = &layoutId;
+            else if (!strcmp(argv[i], "-f"))
+                u32Arg = &layoutFlags;
+            else
+                fatalUsage(appName, "unknown argument", argv[i]);
+        } else {
+            if (u64Arg) {
+                uint64_t tmp = strtoull(argv[i], &end, 16);
+                if (*end == '\0')
+                    *u64Arg = tmp;
+                u64Arg = NULL;
+            } else if (u32Arg) {
+                uint32_t tmp = strtoul(argv[i], &end, 16);
+                if (*end == '\0')
+                    *u32Arg = tmp;
+                u32Arg = NULL;
+            } else if (strArg) {
+                    *strArg = argv[i];
+                strArg = NULL;
+            } else {
+                if (posArgCnt < 2)
+                    posArg[posArgCnt++] = argv[i];
+                else
+                    fatalUsage(appName, "too many positional arguments", argv[i]);
+            }
+            prev = NULL;
+        }
+    }
+    if (prev)
+        fatalUsage(appName, "missing argument after", prev);
+
+    if (!posArgCnt)
+        fatalUsage(appName, "missing input file name", NULL);
+
+    if (!layoutId) {
+        if (strcmp(layoutName, "app") == 0)
+            layoutId = LAYOUT_APP;
+        else if (strcmp(layoutName, "os") == 0)
+            layoutId = LAYOUT_OS;
+        else if (strcmp(layoutName, "key") == 0)
+            layoutId = LAYOUT_KEY;
+        else
+            fatalUsage(appName, "Invalid layout name", layoutName);
+    }
+
+    if (staticElf && layoutId != LAYOUT_APP)
+        fatalUsage(appName, "Only app layout is supported for static option", NULL);
+
+    if (layoutId == LAYOUT_APP && !appId)
+        fatalUsage(appName, "App layout requires app ID", NULL);
+    if (layoutId == LAYOUT_KEY && !keyId)
+        fatalUsage(appName, "Key layout requires key ID", NULL);
+    if (layoutId == LAYOUT_OS && (keyId || appId))
+        fatalUsage(appName, "OS layout does not need any ID", NULL);
+
+    if (!staticElf) {
+        buf = loadFile(posArg[0], &bufUsed);
+        fprintf(stderr, "Read %" PRIu32 " bytes\n", bufUsed);
+    }
+
+    if (!posArg[1])
+        out = stdout;
+    else
+        out = fopen(posArg[1], "w");
+    if (!out)
+        fatalUsage(appName, "failed to create/open output file", posArg[1]);
+
+    switch(layoutId) {
+    case LAYOUT_APP:
+        if (staticElf) {
+            ret = handleAppStatic(posArg[0], out, layoutFlags, appId, verbose);
+        } else {
+            ret = handleApp(&buf, bufUsed, out, layoutFlags, appId, verbose);
+        }
+        break;
+    case LAYOUT_KEY:
+        ret = handleKey(&buf, bufUsed, out, layoutFlags, appId, keyId);
+        break;
+    case LAYOUT_OS:
+        ret = handleOs(&buf, bufUsed, out, layoutFlags, bareData);
+        break;
+    }
+
+    free(buf);
+    fclose(out);
+    return ret;
+}
diff --git a/util/nanoapp_sign/Android.mk b/util/nanoapp_sign/Android.mk
index 81e204a7..7be51975 100644
--- a/util/nanoapp_sign/Android.mk
+++ b/util/nanoapp_sign/Android.mk
@@ -19,12 +19,8 @@ LOCAL_PATH := $(call my-dir)
 include $(CLEAR_VARS)
 
 LOCAL_SRC_FILES := \
-    ../../lib/nanohub/rsa.c \
-    ../../lib/nanohub/sha2.c \
-    ../../lib/nanohub/nanoapp.c \
     nanoapp_sign.c \
 
-
 LOCAL_CFLAGS := \
     -Wall \
     -Werror \
@@ -35,13 +31,12 @@ LOCAL_CFLAGS := \
     -DBOOTLOADER_RO= \
 
 
-LOCAL_C_INCLUDES := \
-    device/google/contexthub/lib/include \
-
 ifneq ($(filter userdebug eng,$(TARGET_BUILD_VARIANT)),)
 LOCAL_CFLAGS += -DDEBUG_KEYS
 endif
 
+LOCAL_STATIC_LIBRARIES := libnanohub_common
+
 LOCAL_MODULE := nanoapp_sign
 
 LOCAL_MODULE_TAGS := optional
diff --git a/util/stm32_flash/flash.c b/util/stm32_flash/flash.c
index e7881983..3f3ab24c 100644
--- a/util/stm32_flash/flash.c
+++ b/util/stm32_flash/flash.c
@@ -207,6 +207,8 @@ int main(int argc, char *argv[])
 
         if (fread(&buffer[sizeof(uint32_t)], 1, length, file) < (size_t)length) {
             perror("Error reading input file");
+            free(buffer);
+            fclose(file);
             return -1;
         }