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author | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2016-11-18 12:58:28 +0000 |
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committer | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2016-12-15 15:41:40 +0000 |
commit | 5dd9dbb5bfe64b1eb2e78648f3a2e900678ef433 (patch) | |
tree | 14340eb6c21aafc10aac402cf0ca6f7d2efc28c2 /docs | |
parent | a4af0c2e8409696667695f3781a22cba2eafbd2c (diff) | |
download | arm-trusted-firmware-5dd9dbb5bfe64b1eb2e78648f3a2e900678ef433.tar.gz |
Add provision to extend CPU operations at more levels
Various CPU drivers in ARM Trusted Firmware register functions to handle
power-down operations. At present, separate functions are registered to
power down individual cores and clusters.
This scheme operates on the basis of core and cluster, and doesn't cater
for extending the hierarchy for power-down operations. For example,
future CPUs might support multiple threads which might need powering
down individually.
This patch therefore reworks the CPU operations framework to allow for
registering power down handlers on specific level basis. Henceforth:
- Generic code invokes CPU power down operations by the level
required.
- CPU drivers explicitly mention CPU_NO_RESET_FUNC when the CPU has no
reset function.
- CPU drivers register power down handlers as a list: a mandatory
handler for level 0, and optional handlers for higher levels.
All existing CPU drivers are adapted to the new CPU operations framework
without needing any functional changes within.
Also update firmware design guide.
Change-Id: I1826842d37a9e60a9e85fdcee7b4b8f6bc1ad043
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Diffstat (limited to 'docs')
-rw-r--r-- | docs/firmware-design.md | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/docs/firmware-design.md b/docs/firmware-design.md index c37f9c5f..0acb1fa8 100644 --- a/docs/firmware-design.md +++ b/docs/firmware-design.md @@ -1127,7 +1127,8 @@ can be found in the [cpu-specific-build-macros.md][CPUBM] file. The CPU specific operations framework depends on the `cpu_ops` structure which needs to be exported for each type of CPU in the platform. It is defined in `include/lib/cpus/aarch64/cpu_macros.S` and has the following fields : `midr`, -`reset_func()`, `core_pwr_dwn()`, `cluster_pwr_dwn()` and `cpu_reg_dump()`. +`reset_func()`, `cpu_pwr_down_ops` (array of power down functions) and +`cpu_reg_dump()`. The CPU specific files in `lib/cpus` export a `cpu_ops` data structure with suitable handlers for that CPU. For example, `lib/cpus/aarch64/cortex_a53.S` @@ -1161,15 +1162,15 @@ During the BL31 initialization sequence, the pointer to the matching `cpu_ops` entry is stored in per-CPU data by `init_cpu_ops()` so that it can be quickly retrieved during power down sequences. -The PSCI service, upon receiving a power down request, determines the highest -power level at which to execute power down sequence for a particular CPU and -invokes the corresponding 'prepare' power down handler in the CPU specific -operations framework. For example, when a CPU executes a power down for power -level 0, the `prepare_core_pwr_dwn()` retrieves the `cpu_ops` pointer from the -per-CPU data and the corresponding `core_pwr_dwn()` is invoked. Similarly when -a CPU executes power down at power level 1, the `prepare_cluster_pwr_dwn()` -retrieves the `cpu_ops` pointer and the corresponding `cluster_pwr_dwn()` is -invoked. +Various CPU drivers register handlers to perform power down at certain power +levels for that specific CPU. The PSCI service, upon receiving a power down +request, determines the highest power level at which to execute power down +sequence for a particular CPU. It uses the `prepare_cpu_pwr_dwn()` function to +pick the right power down handler for the requested level. The function +retrieves `cpu_ops` pointer member of per-CPU data, and from that, further +retrieves `cpu_pwr_down_ops` array, and indexes into the required level. If the +requested power level is higher than what a CPU driver supports, the handler +registered for highest level is invoked. At runtime the platform hooks for power down are invoked by the PSCI service to perform platform specific operations during a power down sequence, for example |