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| author | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2016-04-21 11:30:41 +0100 |
|---|---|---|
| committer | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2016-04-21 13:00:28 +0100 |
| commit | 86d8948c781404ec7091538588c1403664603649 (patch) | |
| tree | 43b90cecce19ef4373a1a346cb8396285dbe1684 /docs | |
| parent | adeecf9219fd542379e704ce190701f6a78eb42a (diff) | |
| download | arm-trusted-firmware-86d8948c781404ec7091538588c1403664603649.tar.gz | |
Doc: Add links to the A53/A57 Errata Notice documents
This patch adds links to the Cortex-A53 and Cortex-A57 MPCores
Software Developers Errata Notice documents in the ARM CPU Specific
Build Macros document.
Change-Id: I0aa26d7f373026097ed012a02bc61ee2c5b9d6fc
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/cpu-specific-build-macros.md | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/docs/cpu-specific-build-macros.md b/docs/cpu-specific-build-macros.md index 202cea70..df2fbd86 100644 --- a/docs/cpu-specific-build-macros.md +++ b/docs/cpu-specific-build-macros.md @@ -22,14 +22,19 @@ for a specific CPU on a platform. ARM Trusted Firmware exports a series of build flags which control the errata workarounds that are applied to each CPU by the reset handler. The errata details can be found in the CPU specific errata documents published -by ARM. The errata workarounds are implemented for a particular revision -or a set of processor revisions. This is checked by reset handler at runtime. -Each errata workaround is identified by its `ID` as specified in the processor's +by ARM: + +* [Cortex-A53 MPCore Software Developers Errata Notice][A53 Errata Notice] +* [Cortex-A57 MPCore Software Developers Errata Notice][A57 Errata Notice] + +The errata workarounds are implemented for a particular revision or a set of +processor revisions. This is checked by the reset handler at runtime. Each +errata workaround is identified by its `ID` as specified in the processor's errata notice document. The format of the define used to enable/disable the errata workaround is `ERRATA_<Processor name>_<ID>`, where the `Processor name` is for example `A57` for the `Cortex_A57` CPU. -All workarounds are disabled by default. The platform is reponsible for +All workarounds are disabled by default. The platform is responsible for enabling these workarounds according to its requirement by defining the errata workaround build flags in the platform specific makefile. In case these workarounds are enabled for the wrong CPU revision then the errata @@ -109,3 +114,5 @@ architecture that can be enabled by the platform as desired. _Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved._ [A57 SW Optimization Guide]: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf +[A53 Errata Notice]: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html +[A57 Errata Notice]: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/cortex_a57_mpcore_software_developers_errata_notice.pdf |