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| author | Soby Mathew <soby.mathew@arm.com> | 2016-05-17 14:01:32 +0100 |
|---|---|---|
| committer | Soby Mathew <soby.mathew@arm.com> | 2016-06-03 10:50:52 +0100 |
| commit | 8cd16e6b5b4a83a2cf704362b9acb1c2eea1417e (patch) | |
| tree | b514a455aa4ab76bb08f0313c170b6c160448ac0 /docs | |
| parent | e141aa0357fd4977ba874f4f86874e2cadc73498 (diff) | |
| download | arm-trusted-firmware-8cd16e6b5b4a83a2cf704362b9acb1c2eea1417e.tar.gz | |
Build option to include AArch32 registers in cpu context
The system registers that are saved and restored in CPU context include
AArch32 systems registers like SPSR_ABT, SPSR_UND, SPSR_IRQ, SPSR_FIQ,
DACR32_EL2, IFSR32_EL2 and FPEXC32_EL2. Accessing these registers on an
AArch64-only (i.e. on hardware that does not implement AArch32, or at
least not at EL1 and higher ELs) platform leads to an exception. This patch
introduces the build option `CTX_INCLUDE_AARCH32_REGS` to specify whether to
include these AArch32 systems registers in the cpu context or not. By default
this build option is set to 1 to ensure compatibility. AArch64-only platforms
must set it to 0. A runtime check is added in BL1 and BL31 cold boot path to
verify this.
Fixes ARM-software/tf-issues#386
Change-Id: I720cdbd7ed7f7d8516635a2ec80d025f478b95ee
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/user-guide.md | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/docs/user-guide.md b/docs/user-guide.md index cd9c8c33..0911eb8b 100644 --- a/docs/user-guide.md +++ b/docs/user-guide.md @@ -380,6 +380,12 @@ performed. any register that is not part of the SBSA generic UART specification. Default value is 0 (a full PL011 compliant UART is present). +* `CTX_INCLUDE_AARCH32_REGS` : Boolean option that, when set to 1, will cause + the AArch32 system registers to be included when saving and restoring the + CPU context. The option must be set to 0 for AArch64-only platforms (that + is on hardware that does not implement AArch32, or at least not at EL1 and + higher ELs). Default value is 1. + * `CTX_INCLUDE_FPREGS`: Boolean option that, when set to 1, will cause the FP registers to be included when saving and restoring the CPU context. Default is 0. |