Always enable CCI coherency in BL3-1

On ARM standard platforms, snoop and DVM requests used to be enabled
for the primary CPU's cluster only in the first EL3 bootloader.
In other words, if the platform reset into BL1 then CCI coherency
would be enabled by BL1 only, and not by BL3-1 again.

However, this doesn't cater for platforms that use BL3-1 along with
a non-TF ROM bootloader that doesn't enable snoop and DVM requests.
In this case, CCI coherency is never enabled.

This patch modifies the function bl31_early_platform_setup() on
ARM standard platforms so that it always enables snoop and DVM
requests regardless of whether earlier bootloader stages have
already done it. There is no harm in executing this code twice.

ARM Trusted Firmware Design document updated accordingly.

Change-Id: Idf1bdeb24d2e1947adfbb76a509f10beef224e1c

1 files changed, 5 insertions, 5 deletions

diff --git a/plat/arm/board/fvp/fvp_bl31_setup.c b/plat/arm/board/fvp/fvp_bl31_setup.c
index b50ae55c..f29af647 100644
--- a/plat/arm/board/fvp/fvp_bl31_setup.c
+++ b/plat/arm/board/fvp/fvp_bl31_setup.c
@@ -45,13 +45,13 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
 	 * No need for locks as no other CPU is active.
 	 */
 	fvp_cci_init();
-#if RESET_TO_BL31
+
 	/*
-	 * Enable CCI coherency for the primary CPU's cluster
-	 * (if earlier BL has not already done so).
+	 * Enable CCI coherency for the primary CPU's cluster.
+	 * Earlier bootloader stages might already do this (e.g. Trusted
+	 * Firmware's BL1 does it) but we can't assume so. There is no harm in
+	 * executing this code twice anyway.
 	 * FVP PSCI code will enable coherency for other clusters.
 	 */
 	fvp_cci_enable();
-
-#endif /* RESET_TO_BL31 */
 }