diff options
author | John Stultz <john.stultz@linaro.org> | 2017-10-30 12:19:50 -0700 |
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committer | John Stultz <john.stultz@linaro.org> | 2017-10-30 12:19:50 -0700 |
commit | 21de417bf7501457bbe383f551a5e012c11381ce (patch) | |
tree | eeec888aa7b85c109be64d7393a8a983711bd4bc /plat/arm/soc/common/soc_css_security.c | |
parent | 8fa3096942d2faed55122efd47348dacca991141 (diff) | |
parent | fd3bba4bd523ee622c448e64e946d2d3b1875d02 (diff) | |
download | arm-trusted-firmware-21de417bf7501457bbe383f551a5e012c11381ce.tar.gz |
Merge branch 'armtf/master/update' into bootloader-update
Big transition to upstream ARMTF code.
This merges the aosp/mater code with fd3bba4bd523 but merges
such that the tree should be identical with the fd3bba4bd523
side of the merge.
Change-Id: Ib416a13ce19c6c26fb62c38ccc6fdfbbdf9c4304
Signed-off-by: John Stultz <john.stultz@linaro.org>
Diffstat (limited to 'plat/arm/soc/common/soc_css_security.c')
-rw-r--r-- | plat/arm/soc/common/soc_css_security.c | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/plat/arm/soc/common/soc_css_security.c b/plat/arm/soc/common/soc_css_security.c new file mode 100644 index 00000000..a8747f18 --- /dev/null +++ b/plat/arm/soc/common/soc_css_security.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <board_css_def.h> +#include <mmio.h> +#include <nic_400.h> +#include <platform_def.h> +#include <soc_css_def.h> + +void soc_css_init_nic400(void) +{ + /* + * NIC-400 Access Control Initialization + * + * Define access privileges by setting each corresponding bit to: + * 0 = Secure access only + * 1 = Non-secure access allowed + */ + + /* + * Allow non-secure access to some SOC regions, excluding UART1, which + * remains secure. + * Note: This is the NIC-400 device on the SOC + */ + mmio_write_32(SOC_CSS_NIC400_BASE + + NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_USB_EHCI), ~0); + mmio_write_32(SOC_CSS_NIC400_BASE + + NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_TLX_MASTER), ~0); + mmio_write_32(SOC_CSS_NIC400_BASE + + NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_USB_OHCI), ~0); + mmio_write_32(SOC_CSS_NIC400_BASE + + NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_PL354_SMC), ~0); + mmio_write_32(SOC_CSS_NIC400_BASE + + NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_APB4_BRIDGE), ~0); + mmio_write_32(SOC_CSS_NIC400_BASE + + NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_BOOTSEC_BRIDGE), + ~SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1); + +} + + +#define PCIE_SECURE_REG 0x3000 +/* Mask uses REG and MEM access bits */ +#define PCIE_SEC_ACCESS_MASK ((1 << 0) | (1 << 1)) + +void soc_css_init_pcie(void) +{ +#if !PLAT_juno + /* + * Do not initialize PCIe in emulator environment. + * Platform ID register not supported on Juno + */ + if (BOARD_CSS_GET_PLAT_TYPE(BOARD_CSS_PLAT_ID_REG_ADDR) == + BOARD_CSS_PLAT_TYPE_EMULATOR) + return; +#endif /* PLAT_juno */ + + /* + * PCIE Root Complex Security settings to enable non-secure + * access to config registers. + */ + mmio_write_32(SOC_CSS_PCIE_CONTROL_BASE + PCIE_SECURE_REG, + PCIE_SEC_ACCESS_MASK); +} |