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| author | Lin Huang <hl@rock-chips.com> | 2016-12-16 13:59:07 +0800 |
|---|---|---|
| committer | Xing Zheng <zhengxing@rock-chips.com> | 2017-02-24 20:07:44 +0800 |
| commit | 46b9dbce2f4ee16e91d10f5abe825e45b2009a9b (patch) | |
| tree | e338b83e63338b0901fc3ca58bca237424d7eb82 /plat/rockchip | |
| parent | c6e15d1437a50a17b17ff852ec6850e21f73d677 (diff) | |
| download | arm-trusted-firmware-46b9dbce2f4ee16e91d10f5abe825e45b2009a9b.tar.gz | |
rockchip: rk3399: enable CA training when do ddr dfs
For ddr dfs stable, We need to enable ddr CA training
when do ddr dfs.
Signed-off-by: Lin Huang <hl@rock-chips.com>
Diffstat (limited to 'plat/rockchip')
| -rw-r--r-- | plat/rockchip/rk3399/drivers/dram/dfs.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/plat/rockchip/rk3399/drivers/dram/dfs.c b/plat/rockchip/rk3399/drivers/dram/dfs.c index c2353141..b4aa3f9f 100644 --- a/plat/rockchip/rk3399/drivers/dram/dfs.c +++ b/plat/rockchip/rk3399/drivers/dram/dfs.c @@ -1017,6 +1017,7 @@ static void gen_rk3399_enable_training(uint32_t ch_cnt, uint32_t nmhz) for (i = 0; i < ch_cnt; i++) { mmio_clrsetbits_32(CTL_REG(i, 305), 1 << 16, tmp << 16); mmio_clrsetbits_32(CTL_REG(i, 71), 1, tmp); + mmio_clrsetbits_32(CTL_REG(i, 70), 1 << 8, 1 << 8); } } |