diff options
| author | Derek Basehore <dbasehore@chromium.org> | 2017-02-09 22:02:42 -0800 |
|---|---|---|
| committer | Xing Zheng <zhengxing@rock-chips.com> | 2017-02-24 20:07:45 +0800 |
| commit | 5a5dc61713fd563a3bb8a89bd26729f4348bb5d6 (patch) | |
| tree | 9b65ed64df3530d3d33aca4274df3da604fb2d81 /plat/rockchip | |
| parent | 43f52e92e45823c6967b20fb9e90dd6e3dc7275f (diff) | |
| download | arm-trusted-firmware-5a5dc61713fd563a3bb8a89bd26729f4348bb5d6.tar.gz | |
rockchip: rk3399: Fix CAS latency setting
The F1 CAS latency setting was not bit shifted, which resulted in
setting the DRAM additive latency value instead.
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Diffstat (limited to 'plat/rockchip')
| -rw-r--r-- | plat/rockchip/rk3399/drivers/dram/dfs.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/plat/rockchip/rk3399/drivers/dram/dfs.c b/plat/rockchip/rk3399/drivers/dram/dfs.c index 37f666a5..98ecd51d 100644 --- a/plat/rockchip/rk3399/drivers/dram/dfs.c +++ b/plat/rockchip/rk3399/drivers/dram/dfs.c @@ -1254,7 +1254,7 @@ static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config, mmio_clrsetbits_32(PI_REG(i, 44), 0x3f, PI_ADD_LATENCY); /* PI_44 PI_CASLAT_LIN_F1:RW:8:7:=0x18 */ mmio_clrsetbits_32(PI_REG(i, 44), 0x7f << 8, - pdram_timing->cl * 2); + (pdram_timing->cl * 2) << 8); /* PI_47 PI_TREF_F1:RW:16:16 */ mmio_clrsetbits_32(PI_REG(i, 47), 0xffff << 16, pdram_timing->trefi << 16); |