Merge remote-tracking branch 'aosp/upstream-hikey-temp' into armtf am: 4120b1ce3c am: d2baddd32b am: b285e553e7

am: 1943d93354

Change-Id: I90f0a956b124501fb8b2daf10d01c5eb77929637

5 files changed, 50 insertions, 6 deletions

diff --git a/plat/hikey/bl1_plat_setup.c b/plat/hikey/bl1_plat_setup.c
index 984c0eea..cb3b252b 100644
--- a/plat/hikey/bl1_plat_setup.c
+++ b/plat/hikey/bl1_plat_setup.c
@@ -384,6 +384,12 @@ static void hikey_hi6553_init(void)
 	hi6553_write_8(LDO15_REG_ADJ, data);
 	hi6553_write_8(ENABLE3_LDO9_16, 1 << 6);
 	mdelay(5);
+	/* enable LDO21 */
+	data = hi6553_read_8(LDO21_REG_ADJ);
+	data = (data & 0xf8) | 0x3;
+	hi6553_write_8(LDO21_REG_ADJ, data);
+	hi6553_write_8(ENABLE4_LDO17_22, 1 << 4);
+	mdelay(5);
 	/* enable LDO22 */
 	data = hi6553_read_8(LDO22_REG_ADJ);
 	data = (data & 0xf8) | 0x7;
@@ -393,6 +399,11 @@ static void hikey_hi6553_init(void)
 
 	/* select 32.764KHz */
 	hi6553_write_8(CLK19M2_600_586_EN, 0x01);
+
+	/* Disable PMIC internal interrupt */
+	data = hi6553_read_8(IRQ2_MASK);
+	data = data | 0x3;
+	hi6553_write_8(IRQ2_MASK, data);
 }
 
 static void hikey_gpio_init(void)
@@ -425,6 +436,10 @@ static void hikey_gpio_init(void)
 	gpio_direction_output(34);
 	gpio_direction_output(35);
 
+	/* Clear GPIO5 and GPIO6 interrutps */
+	mmio_write_32(GPIO5_BASE + 0x41C, 0xFF);
+	mmio_write_32(GPIO6_BASE + 0x41C, 0xFF);
+
 	/* Initialize PWR_HOLD GPIO */
 	gpio_set_value(0, 1);
 	gpio_direction_output(0);
diff --git a/plat/hikey/drivers/hisi_ipc.c b/plat/hikey/drivers/hisi_ipc.c
index c3b34d31..393982c1 100644
--- a/plat/hikey/drivers/hisi_ipc.c
+++ b/plat/hikey/drivers/hisi_ipc.c
@@ -37,6 +37,8 @@
 #include <stdarg.h>
 #include <string.h>
 
+#include <hi6220_regs_acpu.h>
+
 #define BIT(x)	(0x1 << (x))
 
 static int  _ipc_init = 0;
@@ -138,7 +140,21 @@ void hisi_ipc_cpu_on_off(unsigned int cpu, unsigned int cluster,
 
 void hisi_ipc_cpu_on(unsigned int cpu, unsigned int cluster)
 {
+	unsigned int data, expected;
+
 	hisi_ipc_cpu_on_off(cpu, cluster, HISI_IPC_PM_ON);
+
+	/* Enable debug module */
+	data = mmio_read_32(ACPU_SC_PDBGUP_MBIST);
+	if (cluster)
+		expected = 1 << (cpu + PDBGUP_CLUSTER1_SHIFT);
+	else
+		expected = 1 << cpu;
+	mmio_write_32(ACPU_SC_PDBGUP_MBIST, data | expected);
+	do {
+		/* RAW barrier */
+		data = mmio_read_32(ACPU_SC_PDBGUP_MBIST);
+	} while (!(data & expected));
 }
 
 void hisi_ipc_cpu_off(unsigned int cpu, unsigned int cluster)
diff --git a/plat/hikey/hikey_def.h b/plat/hikey/hikey_def.h
index 20076337..d81b6d7a 100644
--- a/plat/hikey/hikey_def.h
+++ b/plat/hikey/hikey_def.h
@@ -46,13 +46,19 @@
 #define PLAT_TRUSTED_DRAM_ID	1
 
 /*
- * DRAM at 0x0000_0000 is divided in two regions:
- *   - Secure DRAM (default is the top 16MB)
+ * DRAM (1 GB) at 0x0000_0000 is divided in several regions:
+ *   - Secure DRAM (default is the top 16MB) used by OP-TEE
+ *   - Non-secure DRAM used by OP-TEE (shared memory and padding) (4MB)
+ *   - Secure DRAM (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature
  *   - Non-Secure DRAM (remaining DRAM starting at DRAM_BASE)
  */
 #define DRAM_SEC_SIZE			0x01000000
 #define DRAM_SEC_BASE			(DRAM_BASE + DRAM_SIZE - DRAM_SEC_SIZE)
 
+#define DRAM_SDP_SIZE			0x00400000
+#define DRAM_SDP_BASE			(DRAM_SEC_BASE - 0x400000 /* align */ - \
+					 DRAM_SDP_SIZE)
+
 #define DRAM_NS_BASE			DRAM_BASE
 #define DRAM_NS_SIZE			(DRAM_SIZE - DRAM_SEC_SIZE)
 
diff --git a/plat/hikey/include/hi6553.h b/plat/hikey/include/hi6553.h
index 9efc5808..7e642c02 100644
--- a/plat/hikey/include/hi6553.h
+++ b/plat/hikey/include/hi6553.h
@@ -41,6 +41,7 @@
 #define DISABLE6_XO_CLK_RF2			(1 << 4)
 
 #define VERSION_REG				0x000
+#define IRQ2_MASK				0x008
 #define ENABLE2_LDO1_8				0x029
 #define DISABLE2_LDO1_8				0x02a
 #define ONOFF_STATUS2_LDO1_8			0x02b
@@ -70,6 +71,7 @@
 #define LDO15_REG_ADJ				0x080
 #define LDO19_REG_ADJ				0x084
 #define LDO20_REG_ADJ				0x085
+#define LDO21_REG_ADJ				0x086
 #define LDO22_REG_ADJ				0x087
 #define DR_LED_CTRL				0x098
 #define DR_OUT_CTRL				0x099
diff --git a/plat/hikey/plat_security.c b/plat/hikey/plat_security.c
index b2cd6024..dc439c7b 100644
--- a/plat/hikey/plat_security.c
+++ b/plat/hikey/plat_security.c
@@ -90,13 +90,17 @@ static int is_power_of_two(uint32_t x)
  * region_size must be a power of 2 and at least 64KB
  * region_base must be region_size aligned
  */
-static void sec_protect(uint32_t region_base, uint32_t region_size)
+static void sec_protect(uint32_t region_base, uint32_t region_size,
+			int region)
 {
 	volatile struct int_en_reg *int_en_reg ;
 	volatile struct rgn_map_reg *rgn_map_reg;
 	volatile struct rgn_attr_reg *rgn_attr_reg;
 	uint32_t i = 0;
 
+	if (region < 1 || region > 15) {
+		ERROR("Secure region number is invalid\n");
+	}
 	if (!is_power_of_two(region_size) || region_size < 0x10000) {
 		ERROR("Secure region size is not a power of 2 >= 64KB\n");
 		return;
@@ -113,8 +117,8 @@ static void sec_protect(uint32_t region_base, uint32_t region_size)
 	int_en_reg->in_en = 0x1;
 
 	for (i = 0; i < PORTNUM_MAX; i++) {
-		rgn_map_reg = get_rgn_map_reg(MDDRC_SECURITY_BASE, 1, i);
-		rgn_attr_reg = get_rgn_attr_reg(MDDRC_SECURITY_BASE, 1, i);
+		rgn_map_reg = get_rgn_map_reg(MDDRC_SECURITY_BASE, region, i);
+		rgn_attr_reg = get_rgn_attr_reg(MDDRC_SECURITY_BASE, region, i);
 		rgn_map_reg->rgn_base_addr = region_base >> 16;
 		rgn_attr_reg->subrgn_disable = 0x0;
 		rgn_attr_reg->sp = (i == 3) ? 0xC : 0x0;
@@ -128,5 +132,6 @@ static void sec_protect(uint32_t region_base, uint32_t region_size)
  ******************************************************************************/
 void plat_security_setup(void)
 {
-	sec_protect(DRAM_SEC_BASE, DRAM_SEC_SIZE);
+	sec_protect(DRAM_SEC_BASE, DRAM_SEC_SIZE, 1);
+	sec_protect(DRAM_SDP_BASE, DRAM_SDP_SIZE, 2);
 }