diff options
| -rw-r--r-- | docs/plat/nvidia-tegra.md | 13 | ||||
| -rw-r--r-- | plat/nvidia/tegra/common/tegra_bl31_setup.c | 13 | ||||
| -rw-r--r-- | plat/nvidia/tegra/common/tegra_pm.c | 2 | ||||
| -rw-r--r-- | plat/nvidia/tegra/include/tegra_private.h | 3 |
4 files changed, 24 insertions, 7 deletions
diff --git a/docs/plat/nvidia-tegra.md b/docs/plat/nvidia-tegra.md index b29532c9..e6ec4622 100644 --- a/docs/plat/nvidia-tegra.md +++ b/docs/plat/nvidia-tegra.md @@ -62,6 +62,19 @@ TARGET_SOC=<target-soc e.g. t210|t132> SPD=<dispatcher e.g. tlkd> bl31' Platforms wanting to use different TZDRAM_BASE, can add 'TZDRAM_BASE=<value>' to the build command line. +The Tegra platform code expects a pointer to the following platform specific +structure via 'x1' register from the BL2 layer which is used by the +bl31_early_platform_setup() handler to extract the TZDRAM carveout base and +size for loading the Trusted OS. The Tegra memory controller driver programs +this base/size in order to restrict NS accesses. + +typedef struct plat_params_from_bl2 { + /* TZ memory size */ + uint64_t tzdram_size; + /* TZ memory base */ + uint64_t tzdram_base; +} plat_params_from_bl2_t; + Power Management ================ The PSCI implementation expects each platform to expose the 'power state' diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c index 1635bfb0..f762d6a0 100644 --- a/plat/nvidia/tegra/common/tegra_bl31_setup.c +++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c @@ -130,17 +130,18 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, * Copy BL3-3, BL3-2 entry point information. * They are stored in Secure RAM, in BL2's address space. */ - if (from_bl2->bl33_ep_info) - bl33_image_ep_info = *from_bl2->bl33_ep_info; + assert(from_bl2->bl33_ep_info); + bl33_image_ep_info = *from_bl2->bl33_ep_info; if (from_bl2->bl32_ep_info) bl32_image_ep_info = *from_bl2->bl32_ep_info; /* - * Parse platform specific parameters - TZDRAM aperture size + * Parse platform specific parameters - TZDRAM aperture base and size */ - if (plat_params) - plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; + assert(plat_params); + plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; + plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; } /******************************************************************************* @@ -168,7 +169,7 @@ void bl31_platform_setup(void) /* * Do initial security configuration to allow DRAM/device access. */ - tegra_memctrl_tzdram_setup(tegra_bl31_phys_base, + tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base, plat_bl31_params_from_bl2.tzdram_size); /* Set the next EL to be AArch64 */ diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c index 6fb3e9c6..8b7a0590 100644 --- a/plat/nvidia/tegra/common/tegra_pm.c +++ b/plat/nvidia/tegra/common/tegra_pm.c @@ -174,7 +174,7 @@ void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state) * Security configuration to allow DRAM/device access. */ plat_params = bl31_get_plat_params(); - tegra_memctrl_tzdram_setup(tegra_bl31_phys_base, + tegra_memctrl_tzdram_setup(plat_params->tzdram_base, plat_params->tzdram_size); } diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h index cf75d9f5..9e660233 100644 --- a/plat/nvidia/tegra/include/tegra_private.h +++ b/plat/nvidia/tegra/include/tegra_private.h @@ -43,7 +43,10 @@ #define TEGRA_DRAM_END 0x27FFFFFFF typedef struct plat_params_from_bl2 { + /* TZ memory size */ uint64_t tzdram_size; + /* TZ memory base */ + uint64_t tzdram_base; } plat_params_from_bl2_t; /* Declarations for plat_psci_handlers.c */ |