blob: 02e001b5599daf82fb0f916ea3dd3e7bd3657cec (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
|
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __ROCKCHIP_RK3399_INCLUDE_SHARED_MISC_REGS_H__
#define __ROCKCHIP_RK3399_INCLUDE_SHARED_MISC_REGS_H__
/* CRU */
#define CRU_DPLL_CON0 0x40
#define CRU_DPLL_CON1 0x44
#define CRU_DPLL_CON2 0x48
#define CRU_DPLL_CON3 0x4c
#define CRU_DPLL_CON4 0x50
#define CRU_DPLL_CON5 0x54
/* CRU_PLL_CON3 */
#define PLL_SLOW_MODE 0
#define PLL_NORMAL_MODE 1
#define PLL_MODE(n) ((0x3 << (8 + 16)) | ((n) << 8))
#define PLL_POWER_DOWN(n) ((0x1 << (0 + 16)) | ((n) << 0))
/* PMU CRU */
#define PMU_CRU_GATEDIS_CON0 0x130
#endif /* __ROCKCHIP_RK3399_INCLUDE_SHARED_MISC_REGS_H__ */
|
