/*******************************************************************************
* Copyright (C) 2018 Cadence Design Systems, Inc.
* 
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to use this Software with Cadence processor cores only and 
* not with any other processors and platforms, subject to
* the following conditions:
* 
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
* 
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

******************************************************************************/

/* ...number of DSP cores */
#define XF_CFG_CORES_NUM                4

/* ...maximal number of clients supported by proxy */
#define XF_CFG_PROXY_MAX_CLIENTS        256

/* ...size of the shared memory pool (in bytes) */
#define XF_CFG_REMOTE_IPC_POOL_SIZE     (256 << 10)

/* ...size of the component(DSP) local memory pool (in bytes) */
#define XF_CFG_LOCAL_POOL_SIZE          (1024<< 10)

/* ...alignment for shared buffers */
#define XF_PROXY_ALIGNMENT              64