diff options
Diffstat (limited to 'jacinto6/sgx_src/eurasia_km/services4/srvkm/devices/sgx/sgxreset.c')
| -rw-r--r-- | jacinto6/sgx_src/eurasia_km/services4/srvkm/devices/sgx/sgxreset.c | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/jacinto6/sgx_src/eurasia_km/services4/srvkm/devices/sgx/sgxreset.c b/jacinto6/sgx_src/eurasia_km/services4/srvkm/devices/sgx/sgxreset.c index dcdefae..2b7aa4c 100644 --- a/jacinto6/sgx_src/eurasia_km/services4/srvkm/devices/sgx/sgxreset.c +++ b/jacinto6/sgx_src/eurasia_km/services4/srvkm/devices/sgx/sgxreset.c @@ -191,7 +191,7 @@ static IMG_VOID SGXResetSetupBIFContexts(PVRSRV_SGXDEV_INFO *psDevInfo, ui32EDMDirListReg = EUR_CR_BIF_DIR_LIST_BASE1 + 4 * (SGX_BIF_DIR_LIST_INDEX_EDM - 1); #endif /* SGX_BIF_DIR_LIST_INDEX_EDM */ - ui32RegVal = psDevInfo->sKernelPDDevPAddr.uiAddr >> SGX_MMU_PDE_ADDR_ALIGNSHIFT; + ui32RegVal = (IMG_UINT32)(psDevInfo->sKernelPDDevPAddr.uiAddr >> SGX_MMU_PDE_ADDR_ALIGNSHIFT); #if defined(FIX_HW_BRN_28011) OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal); @@ -506,6 +506,16 @@ IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO *psDevInfo, /* enable 36bit addressing mode if the MMU supports it*/ OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_36BIT_ADDRESSING, EUR_CR_BIF_36BIT_ADDRESSING_ENABLE_MASK); PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_36BIT_ADDRESSING, EUR_CR_BIF_36BIT_ADDRESSING_ENABLE_MASK, ui32PDUMPFlags); +#else + #if defined(EUR_CR_BIF_36BIT_ADDRESSING) + OSWriteHWReg(psDevInfo->pvRegsBaseKM, + EUR_CR_BIF_36BIT_ADDRESSING, + 0); + PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, + EUR_CR_BIF_36BIT_ADDRESSING, + 0, + ui32PDUMPFlags); + #endif #endif SGXResetInitBIFContexts(psDevInfo, ui32PDUMPFlags); @@ -589,11 +599,11 @@ IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO *psDevInfo, SGXResetSoftReset(psDevInfo, IMG_TRUE, ui32PDUMPFlags, IMG_FALSE); /* Map in the dummy page. */ - psDevInfo->pui32BIFResetPD[ui32PDIndex] = (psDevInfo->sBIFResetPTDevPAddr.uiAddr + psDevInfo->pui32BIFResetPD[ui32PDIndex] = (IMG_UINT32)(psDevInfo->sBIFResetPTDevPAddr.uiAddr >>SGX_MMU_PDE_ADDR_ALIGNSHIFT) | SGX_MMU_PDE_PAGE_SIZE_4K | SGX_MMU_PDE_VALID; - psDevInfo->pui32BIFResetPT[ui32PTIndex] = (psDevInfo->sBIFResetPageDevPAddr.uiAddr + psDevInfo->pui32BIFResetPT[ui32PTIndex] = (IMG_UINT32)(psDevInfo->sBIFResetPageDevPAddr.uiAddr >>SGX_MMU_PTE_ADDR_ALIGNSHIFT) | SGX_MMU_PTE_VALID; @@ -715,7 +725,7 @@ IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO *psDevInfo, (4 << EUR_CR_MASTER_SLC_CTRL_ADDR_DECODE_MODE_SHIFT) | #endif #if defined(FIX_HW_BRN_33809) - (2 << EUR_CR_MASTER_SLC_CTRL_ADDR_DECODE_MODE_SHIFT) | + (1 << EUR_CR_MASTER_SLC_CTRL_ADDR_DECODE_MODE_SHIFT) | #endif (0xC << EUR_CR_MASTER_SLC_CTRL_ARB_PAGE_SIZE_SHIFT); OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SLC_CTRL, ui32RegVal); |