QNX IPC: Vayu - Add DSP1 MMU1 Programming

Currently, only MMU0 is being programmed for DSP1.
For EDMA traffic, there is a second MMU (MMU1), which
needs to be programmed.  DSP1 applications which
use EDMA would want to also have the MMU1 programmed
so that the address space is the same.

This patch adds programming of the DSP MMU1
with the same entries to match the programming
of the DSP MMU0.

Additionally, this patch attaches an interrupt
to the DSP1 MMU1 for notification of MMU events.
No default interrupt is programmed for DSP1 MMU1,
so an unused MPU interrupt is selected for use and
the interrupt crossbar is programmed accordingly.
The interrupt selected is MPU interrupt 143.

6 files changed, 394 insertions, 186 deletions

diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayudsp/VAYUDspHalReset.c b/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayudsp/VAYUDspHalReset.c
index 5e6bb19..6781bb2 100644
--- a/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayudsp/VAYUDspHalReset.c
+++ b/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayudsp/VAYUDspHalReset.c
@@ -213,10 +213,10 @@ VAYUDSP_halResetCtrl(Ptr halObj, VAYUDspHal_ResetCmd cmd)
             Osal_printf("DSP:RST2 released!\n");
             OUTREG32(addr, 0x2);
 
-            /* enable MMU0 through global system register */
+            /* enable MMU0 and MMU1 through global system register */
             val = INREG32(mmuSysBase + DSP_SYS_MMU_CONFIG_OFFSET);
-            OUTREG32(mmuSysBase + DSP_SYS_MMU_CONFIG_OFFSET, (val & ~0x1) | 0x1);
-            Osal_printf("DSP:SYS_MMU_CONFIG MMU0 enabled!\n");
+            OUTREG32(mmuSysBase + DSP_SYS_MMU_CONFIG_OFFSET, (val & ~0x11) | 0x11);
+            Osal_printf("DSP:SYS_MMU_CONFIG MMU0 and MMU1 enabled!\n");
         }
         break;
 
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayudsp/VAYUDspPhyShmem.c b/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayudsp/VAYUDspPhyShmem.c
index d8eec30..f531a92 100644
--- a/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayudsp/VAYUDspPhyShmem.c
+++ b/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayudsp/VAYUDspPhyShmem.c
@@ -190,8 +190,8 @@ VAYUDSP_phyShmemInit (Ptr halObj)
         halObject->prmBase = mapInfo.dst;
     }
 
-    mapInfo.src      = MMU_BASE;
-    mapInfo.size     = MMU_SIZE;
+    mapInfo.src      = MMU0_BASE;
+    mapInfo.size     = MMU0_SIZE;
     mapInfo.isCached = FALSE;
     status = Memory_map (&mapInfo);
     if (status < 0) {
@@ -199,11 +199,27 @@ VAYUDSP_phyShmemInit (Ptr halObj)
                              GT_4CLASS,
                              "VAYUDSP_phyShmemInit",
                              status,
-                             "Failure in Memory_map for MMU base registers");
-        halObject->mmuBase = 0;
+                             "Failure in Memory_map for MMU0 base registers");
+        halObject->mmu0Base = 0;
+    }
+    else {
+        halObject->mmu0Base = mapInfo.dst;
+    }
+
+    mapInfo.src      = MMU1_BASE;
+    mapInfo.size     = MMU1_SIZE;
+    mapInfo.isCached = FALSE;
+    status = Memory_map (&mapInfo);
+    if (status < 0) {
+        GT_setFailureReason (curTrace,
+                             GT_4CLASS,
+                             "VAYUDSP_phyShmemInit",
+                             status,
+                             "Failure in Memory_map for MMU1 base registers");
+        halObject->mmu1Base = 0;
     }
     else {
-        halObject->mmuBase = mapInfo.dst;
+        halObject->mmu1Base = mapInfo.dst;
     }
 
     mapInfo.src      = DSP_SYS_MMU_CONFIG_BASE;
@@ -281,8 +297,23 @@ VAYUDSP_phyShmemExit (Ptr halObj)
         halObject->ctrlModBase = 0 ;
     }
 
-    unmapInfo.addr = halObject->mmuBase;
-    unmapInfo.size = MMU_SIZE;
+    unmapInfo.addr = halObject->mmu1Base;
+    unmapInfo.size = MMU1_SIZE;
+    unmapInfo.isCached = FALSE;
+    if (unmapInfo.addr != 0) {
+        status = Memory_unmap (&unmapInfo);
+        if (status < 0) {
+            GT_setFailureReason (curTrace,
+                              GT_4CLASS,
+                              "VAYUDSP_phyShmemExit",
+                              status,
+                              "Failure in Memory_Unmap for MMU base registers");
+        }
+        halObject->mmu1Base = 0 ;
+    }
+
+    unmapInfo.addr = halObject->mmu0Base;
+    unmapInfo.size = MMU0_SIZE;
     unmapInfo.isCached = FALSE;
     if (unmapInfo.addr != 0) {
         status = Memory_unmap (&unmapInfo);
@@ -293,7 +324,7 @@ VAYUDSP_phyShmemExit (Ptr halObj)
                               status,
                               "Failure in Memory_Unmap for MMU base registers");
         }
-        halObject->mmuBase = 0 ;
+        halObject->mmu0Base = 0 ;
     }
 
     unmapInfo.addr = halObject->mmuSysBase;
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/vayu/vayudsp/VAYUDspEnabler.c b/qnx/src/ipc3x_dev/ti/syslink/family/vayu/vayudsp/VAYUDspEnabler.c
index f1343f0..94035b6 100644
--- a/qnx/src/ipc3x_dev/ti/syslink/family/vayu/vayudsp/VAYUDspEnabler.c
+++ b/qnx/src/ipc3x_dev/ti/syslink/family/vayu/vayudsp/VAYUDspEnabler.c
@@ -123,15 +123,14 @@ static UInt32 shm_phys_addr_dsp;
 #define SIZE 0x4
 
 static UInt32 iotlb_dump_cr (struct cr_regs *cr, char *buf);
-static Int load_iotlb_entry (VAYUDSP_HalObject * halObject,
-                             struct iotlb_entry *e);
+static Int load_iotlb_entry (UInt32 mmuBase, struct iotlb_entry *e);
 static Int iotlb_cr_valid (struct cr_regs *cr);
 
-static Int rproc_mem_map (VAYUDSP_HalObject * halObject,
+static Int rproc_mem_map (UInt32 mmuBase, struct pg_table_attrs * p_pt_attrs,
                           UInt32 mpu_addr, UInt32 ul_virt_addr,
                           UInt32 num_bytes, UInt32 map_attr);
-static Int rproc_mem_unmap (VAYUDSP_HalObject * halObject, UInt32 da,
-                            UInt32 num_bytes);
+static Int rproc_mem_unmap (UInt32 mmuBase, struct pg_table_attrs * p_pt_attrs,
+                            UInt32 da, UInt32 num_bytes);
 
 
 static Void iotlb_cr_to_e (struct cr_regs *cr, struct iotlb_entry *e)
@@ -146,56 +145,49 @@ static Void iotlb_cr_to_e (struct cr_regs *cr, struct iotlb_entry *e)
     e->mixed    = cr->ram & MMU_RAM_MIXED;
 }
 
-static Void iotlb_getLock (VAYUDSP_HalObject * halObject,
-                           struct iotlb_lock *l)
+static Void iotlb_getLock (UInt32 mmuBase, struct iotlb_lock *l)
 {
     ULONG reg;
-    VAYUDsp_MMURegs * mmuRegs =
-                                  (VAYUDsp_MMURegs *)halObject->mmuBase;
+    VAYUDsp_MMURegs * mmuRegs = (VAYUDsp_MMURegs *)mmuBase;
 
     reg = INREG32(&mmuRegs->LOCK);
     l->base = MMU_LOCK_BASE(reg);
     l->vict = MMU_LOCK_VICT(reg);
 }
 
-static Void iotlb_setLock (VAYUDSP_HalObject * halObject,
-                           struct iotlb_lock *l)
+static Void iotlb_setLock (UInt32 mmuBase, struct iotlb_lock *l)
 {
     ULONG reg;
-    VAYUDsp_MMURegs * mmuRegs =
-                                  (VAYUDsp_MMURegs *)halObject->mmuBase;
+    VAYUDsp_MMURegs * mmuRegs = (VAYUDsp_MMURegs *)mmuBase;
 
     reg = (l->base << MMU_LOCK_BASE_SHIFT);
     reg |= (l->vict << MMU_LOCK_VICT_SHIFT);
     OUTREG32(&mmuRegs->LOCK, reg);
 }
 
-static void omap4_tlb_read_cr (VAYUDSP_HalObject * halObject,
-                               struct cr_regs *cr)
+static void omap4_tlb_read_cr (UInt32 mmuBase, struct cr_regs *cr)
 {
-    VAYUDsp_MMURegs * mmuRegs =
-                                  (VAYUDsp_MMURegs *)halObject->mmuBase;
+    VAYUDsp_MMURegs * mmuRegs = (VAYUDsp_MMURegs *)mmuBase;
 
     cr->cam = INREG32(&mmuRegs->READ_CAM);
     cr->ram = INREG32(&mmuRegs->READ_RAM);
 }
 
 /* only used for iotlb iteration in for-loop */
-static struct cr_regs __iotlb_read_cr (VAYUDSP_HalObject * halObject,
-                                       int n)
+static struct cr_regs __iotlb_read_cr (UInt32 mmuBase, int n)
 {
      struct cr_regs cr;
      struct iotlb_lock l;
-     iotlb_getLock(halObject, &l);
+     iotlb_getLock(mmuBase, &l);
      l.vict = n;
-     iotlb_setLock(halObject, &l);
-     omap4_tlb_read_cr(halObject, &cr);
+     iotlb_setLock(mmuBase, &l);
+     omap4_tlb_read_cr(mmuBase, &cr);
      return cr;
 }
 
 #define for_each_iotlb_cr(n, __i, cr)                \
     for (__i = 0;                            \
-         (__i < (n)) && (cr = __iotlb_read_cr(halObject, __i), TRUE);    \
+         (__i < (n)) && (cr = __iotlb_read_cr(mmuBase, __i), TRUE);    \
          __i++)
 
 static Int save_tlbs (VAYUDSP_HalObject * halObject, UINT32 procId)
@@ -203,12 +195,24 @@ static Int save_tlbs (VAYUDSP_HalObject * halObject, UINT32 procId)
     Int i =0;
     struct cr_regs cr_tmp;
     struct iotlb_lock l;
+    UInt32 mmuBase;
 
-    iotlb_getLock(halObject, &l);
+    iotlb_getLock(halObject->mmu0Base, &l);
 
-    halObject->mmuObj.nrTlbs = l.base;
-    for_each_iotlb_cr(halObject->mmuObj.nrTlbs, i, cr_tmp) {
-        iotlb_cr_to_e(&cr_tmp, &halObject->mmuObj.tlbs[i]);
+    halObject->mmu0Obj.nrTlbs = l.base;
+    mmuBase = halObject->mmu0Base;
+
+    for_each_iotlb_cr(halObject->mmu0Obj.nrTlbs, i, cr_tmp) {
+        iotlb_cr_to_e(&cr_tmp, &halObject->mmu0Obj.tlbs[i]);
+    }
+
+    iotlb_getLock(halObject->mmu1Base, &l);
+
+    halObject->mmu1Obj.nrTlbs = l.base;
+    mmuBase = halObject->mmu1Base;
+
+    for_each_iotlb_cr(halObject->mmu1Obj.nrTlbs, i, cr_tmp) {
+        iotlb_cr_to_e(&cr_tmp, &halObject->mmu1Obj.tlbs[i]);
     }
 
     return 0;
@@ -224,16 +228,29 @@ static Int restore_tlbs (VAYUDSP_HalObject * halObject, UInt32 procId)
     /* Reset the base and victim values */
     save.base = 0;
     save.vict = 0;
-    iotlb_setLock(halObject, &save);
+    iotlb_setLock(halObject->mmu0Base, &save);
+    iotlb_setLock(halObject->mmu1Base, &save);
+
+    for (i = 0; i < halObject->mmu0Obj.nrTlbs; i++) {
+        status = load_iotlb_entry(halObject->mmu0Base, &halObject->mmu0Obj.tlbs[i]);
+        if (status < 0) {
+            GT_setFailureReason (curTrace,
+                                 GT_4CLASS,
+                                 "restore_tlbs",
+                                 status,
+                                 "Error restoring the mmu0 tlbs");
+            goto err;
+        }
+    }
 
-    for (i = 0; i < halObject->mmuObj.nrTlbs; i++) {
-        status = load_iotlb_entry(halObject, &halObject->mmuObj.tlbs[i]);
+    for (i = 0; i < halObject->mmu1Obj.nrTlbs; i++) {
+        status = load_iotlb_entry(halObject->mmu1Base, &halObject->mmu1Obj.tlbs[i]);
         if (status < 0) {
             GT_setFailureReason (curTrace,
                                  GT_4CLASS,
                                  "restore_tlbs",
                                  status,
-                                 "Error restoring the tlbs");
+                                 "Error restoring the mmu1 tlbs");
             goto err;
         }
     }
@@ -257,7 +274,7 @@ static Int save_mmu_regs (VAYUDSP_HalObject * halObject, UInt32 procId)
         return -ENOMEM;
     }
 
-    if (halObject->mmuBase == 0) {
+    if (halObject->mmu0Base == 0 || halObject->mmu1Base == 0) {
         GT_setFailureReason (curTrace,
                              GT_4CLASS,
                              "save_mmu_regs",
@@ -267,7 +284,8 @@ static Int save_mmu_regs (VAYUDSP_HalObject * halObject, UInt32 procId)
     }
 
     for (i = 0; i < MMU_REGS_SIZE; i++) {
-        halObject->mmuObj.mmuRegs[i] = INREG32(halObject->mmuBase + (i * 4));
+        halObject->mmu0Obj.mmuRegs[i] = INREG32(halObject->mmu0Base + (i * 4));
+        halObject->mmu1Obj.mmuRegs[i] = INREG32(halObject->mmu1Base + (i * 4));
     }
 
     return 0;
@@ -287,7 +305,7 @@ static Int restore_mmu_regs (VAYUDSP_HalObject * halObject,
         return -ENOMEM;
     }
 
-    if (halObject->mmuBase == 0) {
+    if (halObject->mmu0Base == 0 || halObject->mmu1Base == 0) {
         GT_setFailureReason (curTrace,
                              GT_4CLASS,
                              "restore_mmu_regs",
@@ -297,7 +315,8 @@ static Int restore_mmu_regs (VAYUDSP_HalObject * halObject,
     }
 
     for (i = 0; i < MMU_REGS_SIZE; i++) {
-        OUTREG32(halObject->mmuBase + (i * 4), halObject->mmuObj.mmuRegs[i]);
+        OUTREG32(halObject->mmu0Base + (i * 4), halObject->mmu0Obj.mmuRegs[i]);
+        OUTREG32(halObject->mmu1Base + (i * 4), halObject->mmu1Obj.mmuRegs[i]);
     }
 
     return 0;
@@ -595,7 +614,8 @@ static Int add_entry_ext (VAYUDSP_HalObject * halObject,
                 page_size = HW_PAGE_SIZE_4KB;
 
             if (status == 0) {
-                status = rproc_mem_map (halObject,
+                status = rproc_mem_map (halObject->mmu0Base,
+                                        halObject->mmu0Obj.pPtAttrs,
                                         *phys_addr,
                                         *dsp_addr,
                                         page_size,
@@ -605,7 +625,21 @@ static Int add_entry_ext (VAYUDSP_HalObject * halObject,
                                          GT_4CLASS,
                                          "add_entry_ext",
                                          status,
-                                         "benelli_mem_map failed");
+                                         "rproc_mem_map failed");
+                    break;
+                }
+                status = rproc_mem_map (halObject->mmu1Base,
+                                        halObject->mmu1Obj.pPtAttrs,
+                                        *phys_addr,
+                                        *dsp_addr,
+                                        page_size,
+                                        flags);
+                if (status < 0) {
+                    GT_setFailureReason (curTrace,
+                                         GT_4CLASS,
+                                         "add_entry_ext",
+                                         status,
+                                         "rproc_mem_map failed");
                     break;
                 }
                 mapped_size  += entry_size;
@@ -617,21 +651,20 @@ static Int add_entry_ext (VAYUDSP_HalObject * halObject,
     return status;
 }
 
-static Int __dump_tlb_entries (VAYUDSP_HalObject * halObject,
-                               struct cr_regs *crs, int num)
+static Int __dump_tlb_entries (UInt32 mmuBase, struct cr_regs *crs, int num)
 {
     int i;
     struct iotlb_lock saved;
     struct cr_regs tmp;
     struct cr_regs *p = crs;
 
-    iotlb_getLock(halObject, &saved);
+    iotlb_getLock(mmuBase, &saved);
     for_each_iotlb_cr(num, i, tmp) {
         if (!iotlb_cr_valid(&tmp))
             continue;
         *p++ = tmp;
     }
-    iotlb_setLock(halObject, &saved);
+    iotlb_setLock(mmuBase, &saved);
     return  p - crs;
 }
 
@@ -658,7 +691,8 @@ UInt32 get_DspVirtAdd(VAYUDSP_HalObject * halObject, UInt32 physAdd)
 
     memset(cr, 0, sizeof(struct cr_regs) * num);
 
-    num = __dump_tlb_entries(halObject, cr, num);
+    /* Since MMU0 and MMU1 are programmed with the same entries, can just check MMU0 */
+    num = __dump_tlb_entries(halObject->mmu0Base, cr, num);
     for (i = 0; i < num; i++)
     {
         p = cr + i;
@@ -678,8 +712,7 @@ UInt32 get_DspVirtAdd(VAYUDSP_HalObject * halObject, UInt32 physAdd)
  * @obj:    target iommu
  * @buf:    output buffer
  **/
-static UInt32 dump_tlb_entries (VAYUDSP_HalObject * halObject,
-                                char *buf, UInt32 bytes)
+static UInt32 dump_tlb_entries (UInt32 mmuBase, char *buf, UInt32 bytes)
 {
     Int i, num;
     struct cr_regs *cr;
@@ -700,7 +733,7 @@ static UInt32 dump_tlb_entries (VAYUDSP_HalObject * halObject,
     }
     memset(cr, 0, sizeof(struct cr_regs) * num);
 
-    num = __dump_tlb_entries(halObject, cr, num);
+    num = __dump_tlb_entries(mmuBase, cr, num);
     for (i = 0; i < num; i++)
         p += iotlb_dump_cr(cr + i, p);
     munmap(cr, sizeof(struct cr_regs) * num);
@@ -720,7 +753,8 @@ static Void rproc_tlb_dump (VAYUDSP_HalObject * halObject)
              0);
     if (MAP_FAILED != p)
     {
-        dump_tlb_entries(halObject, p, 1000);
+        dump_tlb_entries(halObject->mmu0Base, p, 1000);
+        dump_tlb_entries(halObject->mmu1Base, p, 1000);
         munmap(p, 1000);
     }
 
@@ -741,7 +775,8 @@ static Int rproc_mmu_init (VAYUDSP_HalObject * halObject,
     UInt32 i = 0;
     UInt32 virt_addr = 0;
     UInt32 reg;
-    VAYUDsp_MMURegs * mmuRegs = NULL;
+    VAYUDsp_MMURegs * mmuRegs0 = NULL;
+    VAYUDsp_MMURegs * mmuRegs1 = NULL;
 
     if (halObject == NULL) {
         ret_val = -ENOMEM;
@@ -753,7 +788,7 @@ static Int rproc_mmu_init (VAYUDSP_HalObject * halObject,
         goto error_exit;
     }
 
-    if (halObject->mmuBase == 0) {
+    if (halObject->mmu0Base == 0 || halObject->mmu1Base == 0) {
         ret_val = -ENOMEM;
         GT_setFailureReason (curTrace,
                              GT_4CLASS,
@@ -762,11 +797,16 @@ static Int rproc_mmu_init (VAYUDSP_HalObject * halObject,
                              "halObject->mmuBase is 0");
         goto error_exit;
     }
-    mmuRegs = (VAYUDsp_MMURegs *)halObject->mmuBase;
+    mmuRegs0 = (VAYUDsp_MMURegs *)halObject->mmu0Base;
+    mmuRegs1 = (VAYUDsp_MMURegs *)halObject->mmu1Base;
+
+    /*  Disable the MMU & TWL */
+    hw_mmu_disable(halObject->mmu0Base);
+    hw_mmu_twl_disable(halObject->mmu0Base);
 
     /*  Disable the MMU & TWL */
-    hw_mmu_disable(halObject->mmuBase);
-    hw_mmu_twl_disable(halObject->mmuBase);
+    hw_mmu_disable(halObject->mmu1Base);
+    hw_mmu_twl_disable(halObject->mmu1Base);
 
     printf("  Programming Dsp memory regions\n");
     printf("=========================================\n");
@@ -804,21 +844,30 @@ static Int rproc_mmu_init (VAYUDSP_HalObject * halObject,
     }
 
     /* Set the TTB to point to the L1 page table's physical address */
-    OUTREG32(&mmuRegs->TTB,
-           ((struct pg_table_attrs *)(halObject->mmuObj.pPtAttrs))->l1_base_pa);
+    OUTREG32(&mmuRegs0->TTB,
+           ((struct pg_table_attrs *)(halObject->mmu0Obj.pPtAttrs))->l1_base_pa);
+    OUTREG32(&mmuRegs1->TTB,
+           ((struct pg_table_attrs *)(halObject->mmu1Obj.pPtAttrs))->l1_base_pa);
 
     /* Enable the TWL */
-    hw_mmu_twl_enable(halObject->mmuBase);
+    hw_mmu_twl_enable(halObject->mmu0Base);
+    hw_mmu_twl_enable(halObject->mmu1Base);
 
-    hw_mmu_enable(halObject->mmuBase);
+    hw_mmu_enable(halObject->mmu0Base);
+    hw_mmu_enable(halObject->mmu1Base);
 
     rproc_tlb_dump(halObject);
 
     //Set the SYSCONFIG
-    reg = INREG32(halObject->mmuBase + 0x10);
+    reg = INREG32(halObject->mmu0Base + 0x10);
     reg&=0xFFFFFFEF;
     reg|=0x11;
-    OUTREG32(halObject->mmuBase+0x10, reg);
+    OUTREG32(halObject->mmu0Base+0x10, reg);
+
+    reg = INREG32(halObject->mmu1Base + 0x10);
+    reg&=0xFFFFFFEF;
+    reg|=0x11;
+    OUTREG32(halObject->mmu1Base+0x10, reg);
 
     return 0;
 error_exit:
@@ -833,30 +882,22 @@ error_exit:
 *
 *****************************************************/
 
-static Int rproc_set_twl (VAYUDSP_HalObject * halObject, Bool on)
+static Int rproc_set_twl (UInt32 mmuBase, Bool on)
 {
     Int status = 0;
     VAYUDsp_MMURegs * mmuRegs = NULL;
     ULONG reg;
 
-    if (halObject == NULL) {
-        status = -ENOMEM;
-        GT_setFailureReason (curTrace,
-                             GT_4CLASS,
-                             "benelli_set_twl",
-                             status,
-                             "halObject is NULL");
-    }
-    else if (halObject->mmuBase == 0) {
+    if (mmuBase == 0) {
         status = -ENOMEM;
         GT_setFailureReason (curTrace,
                              GT_4CLASS,
                              "benelli_set_twl",
                              status,
-                             "halObject->mmuBase is NULL");
+                             "mmuBase is NULL");
     }
     else {
-        mmuRegs = (VAYUDsp_MMURegs *)halObject->mmuBase;
+        mmuRegs = (VAYUDsp_MMURegs *)mmuBase;
 
         /* Setting MMU to Smart Idle Mode */
         reg = INREG32(&mmuRegs->SYSCONFIG);
@@ -1236,7 +1277,7 @@ static Int pte_update (UInt32 pa, UInt32 va, UInt32 size,
 * All address & size arguments are assumed to be page aligned (in proc.c)
  *
  */
-static Int rproc_mem_map (VAYUDSP_HalObject * halObject,
+static Int rproc_mem_map (UInt32 mmuBase, struct pg_table_attrs * p_pt_attrs,
                           UInt32 mpu_addr, UInt32 ul_virt_addr,
                           UInt32 num_bytes, UInt32 map_attr)
 {
@@ -1245,27 +1286,19 @@ static Int rproc_mem_map (VAYUDSP_HalObject * halObject,
     struct hw_mmu_map_attrs_t hw_attrs;
     Int pg_i = 0;
 
-    if (halObject == NULL) {
-        status = -ENOMEM;
-        GT_setFailureReason (curTrace,
-                             GT_4CLASS,
-                             "benelli_mem_map",
-                             status,
-                             "halObject is NULL");
-    }
-    else if (halObject->mmuBase == 0) {
+    if (mmuBase == 0) {
         status = -ENOMEM;
         GT_setFailureReason (curTrace,
                              GT_4CLASS,
-                             "benelli_mem_map",
+                             "rproc_mem_map",
                              status,
-                             "halObject->mmuBase is 0");
+                             "mmuBase is 0");
     }
     else if (num_bytes == 0) {
         status = -EINVAL;
         GT_setFailureReason (curTrace,
                              GT_4CLASS,
-                             "benelli_mem_map",
+                             "rproc_mem_map",
                              status,
                              "num_bytes is 0");
     }
@@ -1305,7 +1338,7 @@ static Int rproc_mem_map (VAYUDSP_HalObject * halObject,
                 status = -EINVAL;
                 GT_setFailureReason (curTrace,
                                      GT_4CLASS,
-                                     "benelli_mem_map",
+                                     "rproc_mem_map",
                                      status,
                                      "MMU element size is zero");
             }
@@ -1320,7 +1353,7 @@ static Int rproc_mem_map (VAYUDSP_HalObject * halObject,
             if ((attrs & DSP_MAPPHYSICALADDR)) {
                 status = pte_update(mpu_addr, ul_virt_addr, num_bytes,
                            &hw_attrs,
-                           (struct pg_table_attrs *)halObject->mmuObj.pPtAttrs);
+                           (struct pg_table_attrs *)p_pt_attrs);
             }
 
             /* Don't propogate Linux or HW status to upper layers */
@@ -1329,16 +1362,17 @@ static Int rproc_mem_map (VAYUDSP_HalObject * halObject,
                  * Roll out the mapped pages incase it failed in middle of
                  * mapping
                  */
-                if (pg_i)
-                    rproc_mem_unmap(halObject, ul_virt_addr,
+                if (pg_i) {
+                    rproc_mem_unmap(mmuBase, p_pt_attrs, ul_virt_addr,
                                     (pg_i * PAGE_SIZE));
+                }
             }
 
             /* In any case, flush the TLB
              * This is called from here instead from pte_update to avoid
              * unnecessary repetition while mapping non-contiguous physical
              * regions of a virtual region */
-            hw_mmu_tlb_flushAll(halObject->mmuBase);
+            hw_mmu_tlb_flushAll(mmuBase);
         }
     }
     return status;
@@ -1354,7 +1388,7 @@ static Int rproc_mem_map (VAYUDSP_HalObject * halObject,
  *      So, instead of looking up the PTE address for every 4K block,
  *      we clear consecutive PTEs until we unmap all the bytes
  */
-static Int rproc_mem_unmap (VAYUDSP_HalObject * halObject,
+static Int rproc_mem_unmap (UInt32 mmuBase, struct pg_table_attrs * p_pt_attrs,
                             UInt32 da, UInt32 num_bytes)
 {
     UInt32 L1_base_va;
@@ -1373,34 +1407,24 @@ static Int rproc_mem_unmap (VAYUDSP_HalObject * halObject,
     UInt32 temp;
     UInt32 pAddr;
     UInt32 numof4Kpages = 0;
-    struct pg_table_attrs * p_pt_attrs = NULL;
 
-    if (halObject == NULL) {
-        status = -ENOMEM;
-        GT_setFailureReason (curTrace,
-                             GT_4CLASS,
-                             "rproc_mem_unmap",
-                             status,
-                             "halObject is NULL");
-    }
-    else if (halObject->mmuBase == 0) {
+    if (mmuBase == 0) {
         status = -ENOMEM;
         GT_setFailureReason (curTrace,
                              GT_4CLASS,
                              "rproc_mem_unmap",
                              status,
-                             "halObject->mmuBase is 0");
+                             "mmuBase is 0");
     }
-    else if (halObject->mmuObj.pPtAttrs == NULL) {
+    else if (p_pt_attrs == NULL) {
         status = -ENOMEM;
         GT_setFailureReason (curTrace,
                              GT_4CLASS,
                              "rproc_mem_unmap",
                              status,
-                             "halObject->mmuObj.pPtAttrs is 0");
+                             "p_pt_attrs is NULL");
     }
     else {
-        p_pt_attrs = (struct pg_table_attrs *)halObject->mmuObj.pPtAttrs;
         vaCurr = da;
         rem_bytes = num_bytes;
         rem_bytes_l2 = 0;
@@ -1521,7 +1545,7 @@ static Int rproc_mem_unmap (VAYUDSP_HalObject * halObject,
      * get flushed
      */
 EXIT_LOOP:
-    hw_mmu_tlb_flushAll(halObject->mmuBase);
+    hw_mmu_tlb_flushAll(mmuBase);
     return status;
 }
 
@@ -1535,10 +1559,11 @@ Int rproc_dsp_setup (VAYUDSP_HalObject * halObject,
                      UInt32 numMemEntries)
 {
     Int ret_val = 0;
-    struct pg_table_attrs * p_pt_attrs = NULL;
+    struct pg_table_attrs * p_pt_attrs_0 = NULL;
+    struct pg_table_attrs * p_pt_attrs_1 = NULL;
 
-    p_pt_attrs = init_mmu_page_attribs(0x10000, 14, 128);
-    if (!p_pt_attrs) {
+    p_pt_attrs_0 = init_mmu_page_attribs(0x10000, 14, 128);
+    if (!p_pt_attrs_0) {
         GT_setFailureReason (curTrace,
                              GT_4CLASS,
                              "rproc_setup",
@@ -1546,42 +1571,76 @@ Int rproc_dsp_setup (VAYUDSP_HalObject * halObject,
                              "init_mmu_page_attribs failed");
     }
     else {
-        halObject->mmuObj.pPtAttrs = p_pt_attrs;
-        /* Disable TWL  */
-        ret_val = rproc_set_twl(halObject, FALSE);
-        if (ret_val < 0) {
+        halObject->mmu0Obj.pPtAttrs = p_pt_attrs_0;
+        p_pt_attrs_1 = init_mmu_page_attribs(0x10000, 14, 128);
+        if (!p_pt_attrs_1) {
             GT_setFailureReason (curTrace,
                                  GT_4CLASS,
-                                 "ipu_setup",
+                                 "rproc_setup",
                                  ret_val,
-                                 "benelli_set_twl to FALSE failed");
+                                 "init_mmu_page_attribs failed");
         }
         else {
-            ret_val = rproc_mmu_init (halObject, memEntries,
-                                      numMemEntries);
+            halObject->mmu1Obj.pPtAttrs = p_pt_attrs_1;
+
+            /* Disable TWL  */
+            ret_val = rproc_set_twl(halObject->mmu0Base, FALSE);
             if (ret_val < 0) {
                 GT_setFailureReason (curTrace,
                                      GT_4CLASS,
                                      "ipu_setup",
                                      ret_val,
-                                     "benelli_mmu_init failed");
+                                     "benelli_set_twl to FALSE failed");
             }
             else {
-                ret_val = rproc_set_twl(halObject, TRUE);
+                ret_val = rproc_set_twl(halObject->mmu1Base, FALSE);
                 if (ret_val < 0) {
                     GT_setFailureReason (curTrace,
                                          GT_4CLASS,
                                          "ipu_setup",
                                          ret_val,
-                                         "ducati_set_twl to TRUE failed");
+                                         "benelli_set_twl to FALSE failed");
+                }
+                else {
+                    ret_val = rproc_mmu_init (halObject, memEntries,
+                                              numMemEntries);
+                    if (ret_val < 0) {
+                        GT_setFailureReason (curTrace,
+                                             GT_4CLASS,
+                                             "ipu_setup",
+                                             ret_val,
+                                             "benelli_mmu_init failed");
+                    }
+                    else {
+                        ret_val = rproc_set_twl(halObject->mmu0Base, TRUE);
+                        if (ret_val < 0) {
+                            GT_setFailureReason (curTrace,
+                                                 GT_4CLASS,
+                                                 "ipu_setup",
+                                                 ret_val,
+                                                 "ducati_set_twl to TRUE failed");
+                        }
+                        else {
+                            ret_val = rproc_set_twl(halObject->mmu1Base, TRUE);
+                            if (ret_val < 0) {
+                                GT_setFailureReason (curTrace,
+                                                     GT_4CLASS,
+                                                     "ipu_setup",
+                                                     ret_val,
+                                                     "ducati_set_twl to TRUE failed");
+                            }
+                        }
+                    }
                 }
             }
         }
     }
 
     if (ret_val < 0) {
-        deinit_mmu_page_attribs(p_pt_attrs);
-        halObject->mmuObj.pPtAttrs = NULL;
+        deinit_mmu_page_attribs(p_pt_attrs_0);
+        deinit_mmu_page_attribs(p_pt_attrs_1);
+        halObject->mmu0Obj.pPtAttrs = NULL;
+        halObject->mmu1Obj.pPtAttrs = NULL;
     }
 
     return ret_val;
@@ -1593,19 +1652,22 @@ Void rproc_dsp_destroy(VAYUDSP_HalObject * halObject)
 {
     shm_phys_addr_dsp = 0;
 
-    if (halObject->mmuObj.pPtAttrs) {
-        deinit_mmu_page_attribs(halObject->mmuObj.pPtAttrs);
-        halObject->mmuObj.pPtAttrs = NULL;
+    if (halObject->mmu0Obj.pPtAttrs) {
+        deinit_mmu_page_attribs(halObject->mmu0Obj.pPtAttrs);
+        halObject->mmu0Obj.pPtAttrs = NULL;
+    }
+
+    if (halObject->mmu1Obj.pPtAttrs) {
+        deinit_mmu_page_attribs(halObject->mmu1Obj.pPtAttrs);
+        halObject->mmu1Obj.pPtAttrs = NULL;
     }
 }
 
 
-static Void iotlb_load_cr (VAYUDSP_HalObject * halObject,
-                           struct cr_regs *cr)
+static Void iotlb_load_cr (UInt32 mmuBase, struct cr_regs *cr)
 {
     ULONG reg;
-    VAYUDsp_MMURegs * mmuRegs =
-                                  (VAYUDsp_MMURegs *)halObject->mmuBase;
+    VAYUDsp_MMURegs * mmuRegs = (VAYUDsp_MMURegs *)mmuBase;
 
     reg = cr->cam | MMU_CAM_V;
     OUTREG32(&mmuRegs->CAM, reg);
@@ -1711,30 +1773,19 @@ static struct cr_regs *iotlb_alloc_cr (struct iotlb_entry *e)
  * @obj:    target iommu
  * @e:        an iommu tlb entry info
  **/
-static Int load_iotlb_entry (VAYUDSP_HalObject * halObject,
-                             struct iotlb_entry *e)
+static Int load_iotlb_entry (UInt32 mmuBase, struct iotlb_entry *e)
 {
     Int err = 0;
     struct iotlb_lock l;
     struct cr_regs *cr;
 
-    if (halObject == NULL) {
-        err = -EINVAL;
-        GT_setFailureReason (curTrace,
-                             GT_4CLASS,
-                             "load_iotlb_entry",
-                             err,
-                             "halObject is NULL");
-        goto out;
-    }
-
-    if (halObject->mmuBase == NULL) {
+    if (mmuBase == NULL) {
         err = -EINVAL;
         GT_setFailureReason (curTrace,
                              GT_4CLASS,
                              "load_iotlb_entry",
                              err,
-                             "halObject->mmuBase is NULL");
+                             "mmuBase is NULL");
         goto out;
     }
 
@@ -1748,7 +1799,7 @@ static Int load_iotlb_entry (VAYUDSP_HalObject * halObject,
         goto out;
     }
 
-    iotlb_getLock(halObject, &l);
+    iotlb_getLock(mmuBase, &l);
 
     if (l.base == 32) {
         err = -EBUSY;
@@ -1777,10 +1828,10 @@ static Int load_iotlb_entry (VAYUDSP_HalObject * halObject,
             goto out;
         }
 
-        iotlb_getLock(halObject, &l);
+        iotlb_getLock(mmuBase, &l);
     } else {
         l.vict = l.base;
-        iotlb_setLock(halObject, &l);
+        iotlb_setLock(mmuBase, &l);
     }
 
     cr = iotlb_alloc_cr(e);
@@ -1794,7 +1845,7 @@ static Int load_iotlb_entry (VAYUDSP_HalObject * halObject,
         goto out;
     }
 
-    iotlb_load_cr(halObject, cr);
+    iotlb_load_cr(mmuBase, cr);
     munmap(cr, sizeof(struct cr_regs));
 
     if (e->prsvd)
@@ -1802,7 +1853,7 @@ static Int load_iotlb_entry (VAYUDSP_HalObject * halObject,
     /* increment victim for next tlb load */
     if (++l.vict == 32)
         l.vict = l.base;
-    iotlb_setLock(halObject, &l);
+    iotlb_setLock(mmuBase, &l);
 
 out:
     return err;
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/vayu/vayudsp/VAYUDspHalMmu.c b/qnx/src/ipc3x_dev/ti/syslink/family/vayu/vayudsp/VAYUDspHalMmu.c
index e85d82c..47c92d6 100644
--- a/qnx/src/ipc3x_dev/ti/syslink/family/vayu/vayudsp/VAYUDspHalMmu.c
+++ b/qnx/src/ipc3x_dev/ti/syslink/family/vayu/vayudsp/VAYUDspHalMmu.c
@@ -87,10 +87,14 @@ extern "C" {
  */
 #define MMU_RAM_DEFAULT         0
 
+#define MPU_INT_OFFSET               32
+
 /*!
  *  @brief  Interrupt Id for DSP MMU faults
  */
-#define MMU_FAULT_INTERRUPT     60
+#define MMU_FAULT_INTR_DSP1_MMU0     60
+#define MMU_FAULT_INTR_DSP1_MMU1     143
+#define MMU_XBAR_INTR_DSP1_MMU1      145
 
 /*!
  *  @brief  CAM register field values
@@ -124,6 +128,28 @@ extern "C" {
 #define MMUPAGE_ALIGN(size, psz)  (((size) + psz - 1) & ~(psz -1))
 
 /*!
+ *  @brief  offset in ctrl module to MMR LOCK reg.
+ */
+#define CTRL_MODULE_MMR_OFFSET           0x544
+
+/*!
+ *  @brief  offset in ctrl module to MPU INTs.
+ */
+#define CTRL_MODULE_MPU_OFFSET           0xA4C
+
+/*!
+ *  @brief  interrupt num at offset.
+ */
+#define CTRL_MODULE_INT_BASE             0x8
+
+/*!
+ *  @brief  interrupt num at offset.
+ */
+#define CTRL_MODULE_INT_m_OFFSET(m)      CTRL_MODULE_MPU_OFFSET + \
+                                         ((((m) - CTRL_MODULE_INT_BASE) / 2) * 4) - \
+                                         (((m) > 131) ? 4 : 0)
+
+/*!
  *  @def    REG32
  *  @brief  Regsiter access method.
  */
@@ -371,20 +397,37 @@ Bool
 _VAYUDSP_halMmuCheckAndClearFunc (Ptr arg)
 {
     VAYUDSP_HalObject * halObject = (VAYUDSP_HalObject *)arg;
-    VAYUDSP_HalMmuObject * mmuObj = &(halObject->mmuObj);
+    VAYUDSP_HalMmuObject * mmuObj = &(halObject->mmu0Obj);
+    UInt32 mmuBase;
 
     /* Check the interrupt status */
-    mmuObj->mmuIrqStatus = REG32(halObject->mmuBase + MMU_MMU_IRQSTATUS_OFFSET);
+    mmuObj->mmuIrqStatus = REG32(halObject->mmu0Base + MMU_MMU_IRQSTATUS_OFFSET);
     mmuObj->mmuIrqStatus &= MMU_IRQ_MASK;
-    if (!(mmuObj->mmuIrqStatus))
-        return (FALSE);
+    if (!(mmuObj->mmuIrqStatus)) {
+        mmuObj = &(halObject->mmu1Obj);
+
+        /* Check the interrupt status */
+        mmuObj->mmuIrqStatus = REG32(halObject->mmu1Base + MMU_MMU_IRQSTATUS_OFFSET);
+        mmuObj->mmuIrqStatus &= MMU_IRQ_MASK;
+        if (!(mmuObj->mmuIrqStatus)) {
+            return (FALSE);
+        }
+        else {
+            mmuBase = halObject->mmu1Base;
+            GT_0trace (curTrace, GT_4CLASS,
+                       "****************** DSP-MMU1 Fault ******************");
+        }
+    }
+    else {
+        mmuBase = halObject->mmu0Base;
+        GT_0trace (curTrace, GT_4CLASS,
+                   "****************** DSP-MMU0 Fault ******************");
+    }
 
     /* Get the fault address. */
-    mmuObj->mmuFaultAddr = REG32(halObject->mmuBase + MMU_MMU_FAULT_AD_OFFSET);
+    mmuObj->mmuFaultAddr = REG32(mmuBase + MMU_MMU_FAULT_AD_OFFSET);
 
     /* Print the fault information */
-    GT_0trace (curTrace, GT_4CLASS,
-               "****************** DSP-MMU Fault ******************");
     GT_1trace (curTrace, GT_4CLASS,
                "****    addr: 0x%x", mmuObj->mmuFaultAddr);
     if (mmuObj->mmuIrqStatus & MMU_IRQ_TLBMISS)
@@ -401,8 +444,8 @@ _VAYUDSP_halMmuCheckAndClearFunc (Ptr arg)
                "**************************************************");
 
     /* Clear the interrupt and disable further interrupts. */
-    REG32(halObject->mmuBase + MMU_MMU_IRQENABLE_OFFSET) = 0x0;
-    REG32(halObject->mmuBase + MMU_MMU_IRQSTATUS_OFFSET) = mmuObj->mmuIrqStatus;
+    REG32(mmuBase + MMU_MMU_IRQENABLE_OFFSET) = 0x0;
+    REG32(mmuBase + MMU_MMU_IRQSTATUS_OFFSET) = mmuObj->mmuIrqStatus;
 
     /* This is not a shared interrupt, so interrupt has always occurred */
     /*! @retval TRUE Interrupt has occurred. */
@@ -452,8 +495,9 @@ _VAYUDSP_halMmuEnable (VAYUDSP_HalObject * halObject,
                        ProcMgr_AddrInfo *   memTable)
 {
     Int                           status    = PROCESSOR_SUCCESS;
-    VAYUDSP_HalMmuObject *        mmuObj;
+    VAYUDSP_HalMmuObject *        mmu0Obj, *mmu1Obj;
     OsalIsr_Params                isrParams;
+    UInt32 reg = 0;
 
     GT_3trace (curTrace, GT_ENTER, "_VAYUDSP_halMmuEnable",
                halObject, numMemEntries, memTable);
@@ -463,19 +507,39 @@ _VAYUDSP_halMmuEnable (VAYUDSP_HalObject * halObject,
      * configure any default regions.
      * memTable may also be NULL.
      */
-    mmuObj = &(halObject->mmuObj);
+    mmu0Obj = &(halObject->mmu0Obj);
+    mmu1Obj = &(halObject->mmu1Obj);
+
+    /* Program the MMR lock registers to access the SCM
+     * IRQ crossbar register address range */
+    REG32(halObject->ctrlModBase + CTRL_MODULE_MMR_OFFSET) = 0xF757FDC0;
+
+    /* Program the IntXbar */
+    reg = REG32(halObject->ctrlModBase + CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTR_DSP1_MMU1));
+    if ((MMU_FAULT_INTR_DSP1_MMU1 - CTRL_MODULE_INT_BASE) % 2) {
+        REG32(halObject->ctrlModBase + CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTR_DSP1_MMU1)) =
+            (reg & 0x0000FFFF) | (MMU_XBAR_INTR_DSP1_MMU1 << 16);
+    }
+    else {
+        REG32(halObject->ctrlModBase + CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTR_DSP1_MMU1)) =
+            (reg & 0xFFFF0000) | (MMU_XBAR_INTR_DSP1_MMU1);
+    }
 
     /* Create the ISR to listen for MMU Faults */
     isrParams.sharedInt        = FALSE;
     isrParams.checkAndClearFxn = &_VAYUDSP_halMmuCheckAndClearFunc;
     isrParams.fxnArgs          = halObject;
-    isrParams.intId            = MMU_FAULT_INTERRUPT;
-    mmuObj->isrHandle = OsalIsr_create (&_VAYUDSP_halMmuInt_isr,
+    isrParams.intId            = MMU_FAULT_INTR_DSP1_MMU0;
+    mmu0Obj->isrHandle = OsalIsr_create (&_VAYUDSP_halMmuInt_isr,
+                                        halObject,
+                                        &isrParams);
+    isrParams.intId            = MMU_FAULT_INTR_DSP1_MMU1;
+    mmu1Obj->isrHandle = OsalIsr_create (&_VAYUDSP_halMmuInt_isr,
                                         halObject,
                                         &isrParams);
 
 #if !defined(SYSLINK_BUILD_OPTIMIZE)
-    if (mmuObj->isrHandle == NULL) {
+    if (mmu0Obj->isrHandle == NULL || mmu1Obj->isrHandle == NULL) {
         /*! @retval PROCESSOR_E_FAIL OsalIsr_create failed */
         status = PROCESSOR_E_FAIL;
         GT_setFailureReason (curTrace,
@@ -487,7 +551,7 @@ _VAYUDSP_halMmuEnable (VAYUDSP_HalObject * halObject,
     else {
 #endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
 
-        status = OsalIsr_install (mmuObj->isrHandle);
+        status = OsalIsr_install (mmu0Obj->isrHandle);
 
 #if !defined(SYSLINK_BUILD_OPTIMIZE)
         if (status < 0) {
@@ -497,6 +561,20 @@ _VAYUDSP_halMmuEnable (VAYUDSP_HalObject * halObject,
                                  status,
                                  "OsalIsr_install failed");
         }
+        else {
+#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
+
+            status = OsalIsr_install (mmu1Obj->isrHandle);
+
+#if !defined(SYSLINK_BUILD_OPTIMIZE)
+            if (status < 0) {
+                GT_setFailureReason (curTrace,
+                                     GT_4CLASS,
+                                     "_VAYUDSP_halMmuEnable",
+                                     status,
+                                     "OsalIsr_install failed");
+            }
+        }
 #endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
 
         if ((status >= 0) && (numMemEntries != 0)) {
@@ -542,14 +620,15 @@ _VAYUDSP_halMmuDisable (VAYUDSP_HalObject * halObject)
 {
     Int                        status    = PROCESSOR_SUCCESS;
     Int                        tmpStatus = PROCESSOR_SUCCESS;
-    VAYUDSP_HalMmuObject *     mmuObj;
+    VAYUDSP_HalMmuObject *     mmu0Obj, *mmu1Obj;
 
     GT_1trace (curTrace, GT_ENTER, "_VAYUDSP_halMmuDisable", halObject);
 
     GT_assert (curTrace, (halObject != NULL));
-    mmuObj = &(halObject->mmuObj);
+    mmu0Obj = &(halObject->mmu0Obj);
+    mmu1Obj = &(halObject->mmu1Obj);
 
-    status = OsalIsr_uninstall (mmuObj->isrHandle);
+    status = OsalIsr_uninstall (mmu0Obj->isrHandle);
 #if !defined(SYSLINK_BUILD_OPTIMIZE)
     if (status < 0) {
         GT_setFailureReason (curTrace,
@@ -560,10 +639,36 @@ _VAYUDSP_halMmuDisable (VAYUDSP_HalObject * halObject)
     }
 #endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
 
+    status = OsalIsr_uninstall (mmu1Obj->isrHandle);
+#if !defined(SYSLINK_BUILD_OPTIMIZE)
+    if (status < 0) {
+        GT_setFailureReason (curTrace,
+                             GT_4CLASS,
+                             "_VAYUDSP_halMmuDisable",
+                             status,
+                             "OsalIsr_uninstall failed");
+    }
+#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
+
+#if !defined(SYSLINK_BUILD_OPTIMIZE)
+    tmpStatus =
+#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
+        OsalIsr_delete (&(mmu0Obj->isrHandle));
+#if !defined(SYSLINK_BUILD_OPTIMIZE)
+    if ((status >= 0) && (tmpStatus < 0)) {
+        status = tmpStatus;
+        GT_setFailureReason (curTrace,
+                             GT_4CLASS,
+                             "_VAYUDSP_halMmuDisable",
+                             status,
+                             "OsalIsr_delete failed");
+    }
+#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
+
 #if !defined(SYSLINK_BUILD_OPTIMIZE)
     tmpStatus =
 #endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
-        OsalIsr_delete (&(mmuObj->isrHandle));
+        OsalIsr_delete (&(mmu1Obj->isrHandle));
 #if !defined(SYSLINK_BUILD_OPTIMIZE)
     if ((status >= 0) && (tmpStatus < 0)) {
         status = tmpStatus;
@@ -735,7 +840,7 @@ _VAYUDSP_halMmuDeleteEntry (VAYUDSP_HalObject       * halObject,
     UInt32 *                    iopgd       = NULL;
     UInt32                      currentEntrySize;
     VAYUDSP_HalMmuEntryInfo     currentEntry;
-    VAYUDSP_HalMmuObject *      mmuObj;
+    VAYUDSP_HalMmuObject *      mmu0Obj, *mmu1Obj;
     //UInt32                      clearBytes = 0;
 
     GT_2trace (curTrace, GT_ENTER, "_VAYUDSP_halMmuDeleteEntry",
@@ -745,7 +850,8 @@ _VAYUDSP_halMmuDeleteEntry (VAYUDSP_HalObject       * halObject,
     GT_assert (curTrace, (entry                != NULL));
     GT_assert (curTrace, (entry->size          != 0));
 
-    mmuObj = &(halObject->mmuObj);
+    mmu0Obj = &(halObject->mmu0Obj);
+    mmu1Obj = &(halObject->mmu1Obj);
 
     /* Add the entry (or entries) */
     Memory_copy(&currentEntry,
@@ -917,15 +1023,17 @@ Int
 _VAYUDSP_halMmuPteSet (VAYUDSP_HalObject *      halObject,
                        VAYUDSP_HalMmuEntryInfo* setPteInfo)
 {
-    VAYUDSP_HalMmuObject *     mmuObj;
+    VAYUDSP_HalMmuObject *     mmu0Obj, *mmu1Obj;
     struct iotlb_entry tlb_entry;
     Int    status = PROCESSOR_SUCCESS;
 
     GT_assert (curTrace, (halObject  != NULL));
     GT_assert (curTrace, (setPteInfo != NULL));
 
-    mmuObj = &(halObject->mmuObj);
-    GT_assert(curTrace, (mmuObj != NULL));
+    mmu0Obj = &(halObject->mmu0Obj);
+    GT_assert(curTrace, (mmu0Obj != NULL));
+    mmu1Obj = &(halObject->mmu1Obj);
+    GT_assert(curTrace, (mmu1Obj != NULL));
 
     switch (setPteInfo->size) {
         case PAGE_SIZE_16MB:
@@ -1023,7 +1131,15 @@ _VAYUDSP_halMmuPteSet (VAYUDSP_HalObject *      halObject,
                 tlb_entry.da = setPteInfo->slaveVirtAddr;
                 tlb_entry.pa = setPteInfo->masterPhyAddr;
 
-                if (VAYUDSP_InternalMMU_PteSet(halObject->mmuBase, &tlb_entry)){
+                if (VAYUDSP_InternalMMU_PteSet(halObject->mmu0Base, &tlb_entry)){
+                    status = PROCESSOR_E_STOREENTERY;
+                    GT_setFailureReason (curTrace,
+                            GT_4CLASS,
+                            "_VAYUDSP_halMmuPteSet",
+                            status,
+                            "iopgtable_store_entry failed!");
+                }
+                if (VAYUDSP_InternalMMU_PteSet(halObject->mmu1Base, &tlb_entry)){
                     status = PROCESSOR_E_STOREENTERY;
                     GT_setFailureReason (curTrace,
                             GT_4CLASS,
diff --git a/qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUDspHal.h b/qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUDspHal.h
index 2f971f5..cc2fbfe 100644
--- a/qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUDspHal.h
+++ b/qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUDspHal.h
@@ -86,7 +86,9 @@ typedef struct VAYUDSP_HalObject_tag {
     /*!< Virtual base address of the General Control module. */
     UInt32                bootStatBase;
     /*!< Virtual base address of the General Control module. */
-    UInt32                mmuBase;
+    UInt32                mmu0Base;
+    /*!< Base address of the MMU module. */
+    UInt32                mmu1Base;
     /*!< Base address of the MMU module. */
     UInt32                mmuSysBase;
     /*!< Base address of the MMU module. */
@@ -94,7 +96,9 @@ typedef struct VAYUDSP_HalObject_tag {
     /*!< Base address of the control module. */
     UInt32                procId;
     /*!< Processor ID. */
-    VAYUDSP_HalMmuObject mmuObj;
+    VAYUDSP_HalMmuObject mmu0Obj;
+    /*!< MMU abstraction. */
+    VAYUDSP_HalMmuObject mmu1Obj;
     /*!< MMU abstraction. */
 } VAYUDSP_HalObject;
 
diff --git a/qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUDspPhyShmem.h b/qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUDspPhyShmem.h
index eb2bb61..5ce2cd7 100644
--- a/qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUDspPhyShmem.h
+++ b/qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUDspPhyShmem.h
@@ -118,11 +118,17 @@ extern "C" {
  */
 #define DSP_SYS_MMU_CONFIG_SIZE   0x1000
 
-#define MMU_BASE                0x40D01000
+#define MMU0_BASE                0x40D01000
 /*!
  *  @brief  size to be ioremapped.
  */
-#define MMU_SIZE                0x1000
+#define MMU0_SIZE                0x1000
+
+#define MMU1_BASE                0x40D02000
+/*!
+ *  @brief  size to be ioremapped.
+ */
+#define MMU1_SIZE                0x1000
 
 /*!
  *  @def    CTRL_MODULE_BASE