am65xx: Integrate sciclient for interrupt routing through system-fw3.50.01.01

- Adds dependency on sciclient part of the PDK package
- Add new module ti.sdo.ip.family.am65xx.NotifySciClient which
configures interrupt routes by communicating with system core using
sciclient module.
- removes old code which configured directly the interrupt routes to cpu

Signed-off-by: Sam Nelson <sam.nelson@ti.com>

9 files changed, 320 insertions, 131 deletions

diff --git a/ipc-bios.mak b/ipc-bios.mak
index 3877f47..b4e754a 100644
--- a/ipc-bios.mak
+++ b/ipc-bios.mak
@@ -119,6 +119,11 @@ LIST = $(shell $(XDCPKG) ./packages)
 # Set XDCPATH to contain necessary repositories.
 #
 XDCPATH = $(BIOS_INSTALL_DIR)/packages
+ifeq ($(PDK_INSTALL_DIR),)
+XDCPATH = $(BIOS_INSTALL_DIR)/packages
+else
+XDCPATH = $(BIOS_INSTALL_DIR)/packages;${PDK_INSTALL_DIR}/packages
+endif
 export XDCPATH
 
 #
diff --git a/packages/ti/sdo/ipc/Build.xs b/packages/ti/sdo/ipc/Build.xs
index 769ddb6..dabb6a6 100644
--- a/packages/ti/sdo/ipc/Build.xs
+++ b/packages/ti/sdo/ipc/Build.xs
@@ -582,6 +582,7 @@ var ARP32Sources = "ti/sdo/ipc/gates/GateHWSpinlock.c " +
 
 var A53FSources  = "ti/sdo/ipc/family/am65xx/InterruptHost.c " +
                    "ti/sdo/ipc/family/am65xx/NotifyDriverMbx.c " +
+                   "ti/sdo/ipc/family/am65xx/NotifySciClient.c " +
                    "ti/sdo/ipc/family/am65xx/NotifySetup.c " +
                    "ti/sdo/ipc/gates/GateHWSpinlock.c " +
                    "ti/sdo/ipc/gates/GateHWSem.c ";
@@ -589,6 +590,7 @@ var A53FSources  = "ti/sdo/ipc/family/am65xx/InterruptHost.c " +
 var R5FSources    = "ti/sdo/ipc/gates/GateHWSpinlock.c " +
                    "ti/sdo/ipc/family/am65xx/InterruptR5f.c " +
                    "ti/sdo/ipc/family/am65xx/NotifyDriverMbx.c " +
+                   "ti/sdo/ipc/family/am65xx/NotifySciClient.c " +
                    "ti/sdo/ipc/family/am65xx/NotifySetup.c " +
                    "ti/sdo/ipc/family/am65xx/Power.c " +
                    "ti/ipc/family/am65xx/VirtQueue.c ";
@@ -750,7 +752,6 @@ function getDefs()
         defs += xdc.module('ti.ipc.rpmsg.Build').getDefs();
     }
 
-    /* TODO: Need to clean up : Why is InterruptDucati added here which is platform specific */
     var InterruptDucati =
             xdc.module("ti.sdo.ipc.family.ti81xx.InterruptDucati");
 
diff --git a/packages/ti/sdo/ipc/family/am65xx/NotifySciClient.c b/packages/ti/sdo/ipc/family/am65xx/NotifySciClient.c
new file mode 100644
index 0000000..51b9b0b
--- /dev/null
+++ b/packages/ti/sdo/ipc/family/am65xx/NotifySciClient.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/* The following are required to avoid issues with types used in CSL */
+#undef xdc__strict
+/* Define SOC_AM65XX for header files below */
+#define SOC_AM65XX
+
+#include <ti/csl/csl_types.h>
+#include <ti/drv/sciclient/sciclient.h>
+
+#include "package/internal/NotifySciClient.xdc.h"
+
+/* Ideally want to use fixed timeout. Work around is to use wait forever */
+/* #define NOTIFY_SCICLIENT_RESP_TIMEOUT 100  */
+
+#define NOTIFY_SCICLIENT_RESP_TIMEOUT SCICLIENT_SERVICE_WAIT_FOREVER
+
+/*********************************************************************
+ * @fn      NotifySciClient_Init
+ *
+ * @brief   Initialises NotifySciclient
+ *          Currently only checking communication with system core.
+ *
+ *
+ * @return  0 : Success; -1 for failures
+ */
+Int32 NotifySciClient_Init(void)
+{
+    int32_t status = 0;
+
+    /* Setup Request for Version check */
+    const Sciclient_ReqPrm_t      reqPrm =
+    {
+        .messageType = TISCI_MSG_VERSION,
+        .flags = TISCI_MSG_FLAG_AOP,
+        .pReqPayload = NULL,
+        .reqPayloadSize = 0,
+        .timeout = NOTIFY_SCICLIENT_RESP_TIMEOUT
+    };
+
+    struct tisci_msg_version_resp response;
+    /* Setup Response parameters */
+    Sciclient_RespPrm_t           respPrm =
+    {
+        .flags = 0,
+        .pRespPayload = (uint8_t *) &response,
+        .respPayloadSize = sizeof (response)
+    };
+
+    /* Check version check to TISCI connection */
+    status = Sciclient_service(&reqPrm, &respPrm);
+    if (CSL_PASS == status)
+    {
+        if (respPrm.flags != TISCI_MSG_FLAG_ACK)
+        {
+            return -1;
+        }
+    } else {
+        return -1;
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      NotifySciClient_IrqSet
+ *
+ * @brief   Configures interrupt routes by requesting the system core
+ *          and polls for response. If no respone times out.
+ *
+ * @param1  memType: Memory type for self test
+ * @param2  testType: ECC Self test type
+ *
+ * @return  0 : Success; -1 for failures
+ */
+Int32 NotifySciClient_IrqSet(NotifySciClient_CoreIndex coreIndex,
+               NotifySciClient_SourceIdIndex mailboxClusterIndex,
+               NotifySciClient_MailboxIndex mailboxUserIndex,
+               UInt32 intNumber)
+{
+    int32_t status = 0;
+    struct tisci_msg_rm_irq_set_resp resp;
+
+    /* Indexed list of dst ids */
+    const int32_t map_dst_id[] =
+    {
+        /* NOTE: This list should match the Core index */
+        TISCI_DEV_GIC0,
+        TISCI_DEV_MCU_ARMSS0_CPU0,
+        TISCI_DEV_MCU_ARMSS0_CPU1
+    };
+    /* Indexed list of src ids */
+    const uint16_t map_src_id[] =
+    {
+        TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER0,
+        TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER1,
+        TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER2
+    };
+#if 0 /* Currently not used */
+    /* Indexed list of host ids */
+    const uint16_t map_host_id[] =
+    {
+        TISCI_HOST_ID_A53_0,
+        TISCI_HOST_ID_R5_0,
+        TISCI_HOST_ID_R5_1
+    };
+#endif
+    /* Sets bits src_id, src_index, dst_id, dst_host_irq */
+    struct tisci_msg_rm_irq_set_req irq_set_req =
+    {
+        .valid_params   = 0x0,
+        .src_id         = 0,
+        .src_index      = 0,
+        .dst_id         = 0,
+        .dst_host_irq   = 0,
+        .ia_id          = 0,
+        .vint           = 0,
+        .global_event   = 0,
+        .vint_status_bit_index = 0,
+        .secondary_host = 0
+    };
+
+    /* Request irq set for specified interrupt source */
+    irq_set_req.valid_params = 0x3 ; /* Sets bits dst_id, dst_host_irq */
+    irq_set_req.src_id = map_src_id[mailboxClusterIndex];
+    irq_set_req.src_index = mailboxUserIndex;
+    irq_set_req.dst_id = map_dst_id[coreIndex];
+    irq_set_req.dst_host_irq = intNumber;
+/*    irq_set_req.secondary_host = map_host_id[coreIndex];*/
+
+    /* Call irq Set */
+    if (CSL_PASS != Sciclient_rmIrqSet(&irq_set_req, &resp, NOTIFY_SCICLIENT_RESP_TIMEOUT ))
+    {
+        return -1;
+    }
+
+    return status;
+}
diff --git a/packages/ti/sdo/ipc/family/am65xx/NotifySciClient.xdc b/packages/ti/sdo/ipc/family/am65xx/NotifySciClient.xdc
new file mode 100644
index 0000000..24581f7
--- /dev/null
+++ b/packages/ti/sdo/ipc/family/am65xx/NotifySciClient.xdc
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+package ti.sdo.ipc.family.am65xx;
+
+module NotifySciClient
+{
+    enum CoreIndex {
+        A53_0_CORE_INDEX = 0,
+        /**< Core index for A53 core 0 */
+        R5F_0_CORE_INDEX,
+        /**< Core index for R5F core 0 */
+        R5F_1_CORE_INDEX
+        /**< Core index for R5F core 1 */
+    } ;
+
+    enum SourceIdIndex {
+        MAILBOX_CLUSTER0_SRC_ID_INDEX = 0,
+        /**< Source id index for mailbox cluster 0 */
+        MAILBOX_CLUSTER1_SRC_ID_INDEX,
+        /**< Source id index for mailbox cluster 1 */
+        MAILBOX_CLUSTER2_SRC_ID_INDEX
+        /**< Source id index for mailbox cluster 2 */
+    } ;
+
+    enum MailboxIndex {
+        MAILBOX_USER_0= 0,
+        /**< mailbox user 0 */
+        MAILBOX_USER_1,
+        /**<  mailbox user 1 */
+        MAILBOX_USER_2,
+        /**<  mailbox user 2 */
+        MAILBOX_USER_3
+        /**<  mailbox user 3 */
+    } ;
+
+    Int32 Init ();
+    Int32 IrqSet(CoreIndex coreIndex,
+                 SourceIdIndex mailboxClusterIndex,
+                 MailboxIndex mailboxUserIndex,
+                 UInt32 intNumber);
+};
diff --git a/packages/ti/sdo/ipc/family/am65xx/NotifySetup.c b/packages/ti/sdo/ipc/family/am65xx/NotifySetup.c
index 4f52eb2..a306d91 100644
--- a/packages/ti/sdo/ipc/family/am65xx/NotifySetup.c
+++ b/packages/ti/sdo/ipc/family/am65xx/NotifySetup.c
@@ -42,6 +42,7 @@
 #include <ti/sdo/ipc/family/am65xx/NotifyDriverMbx.h>
 #include <ti/sdo/ipc/notifyDrivers/NotifyDriverShm.h>
 #include <ti/sdo/utils/_MultiProc.h>
+#include <ti/sdo/ipc/family/am65xx/NotifySciClient.h>
 
 #if defined(xdc_target__isaCompatible_v7R)
 
@@ -57,9 +58,6 @@
 
 #include "package/internal/NotifySetup.xdc.h"
 
-
-#define EVENT_GROUP_SIZE 32
-
 /* register access methods */
 #define REG16(A)        (*(volatile UInt16 *)(A))
 #define REG32(A)        (*(volatile UInt32 *)(A))
@@ -90,75 +88,6 @@
 
 #define MBOX_MSG_COUNT(idx) (REG32(MAILBOX_STATUS((idx))))
 
-#define M2M_LVL_INT_RTR_BASE 0x00A10000
-#define M2M_LV_INT_ICR0_OFFSET 0x4
-#define NAVSS_INT_RTR_BASE 0x310E0000
-#define NAVSS_INT_ICR0_OFFSET 0x4
-
-/* Corresponds to VIM: 160 */
-#define M2M_LVL_INT_RTR_OUTPUT_R5F0_0 0
-/* Corresponds to VIM: 161 */
-#define M2M_LVL_INT_RTR_OUTPUT_R5F0_1 1
-/* Corresponds to VIM: 162 */
-#define M2M_LVL_INT_RTR_OUTPUT_R5F1_0 2
-/* Corresponds to VIM: 163 */
-#define M2M_LVL_INT_RTR_OUTPUT_R5F1_1 3
-
-#define NAVSS_INT_RTR_INPUT_MAILBOX0_USER0 436
-#define NAVSS_INT_RTR_INPUT_MAILBOX0_USER1 437
-
-#define NAVSS_INT_RTR_INPUT_MAILBOX1_USER0 432
-#define NAVSS_INT_RTR_INPUT_MAILBOX1_USER1 433
-
-#define NAVSS_INT_RTR_INPUT_MAILBOX2_USER0 428
-#define NAVSS_INT_RTR_INPUT_MAILBOX2_USER1 429
-
-/* Corresponds to GIC: 496 */
-#define NAVSS_INT_RTR_OUTPUT_A53_0    112
-/* Corresponds to GIC: 497 */
-#define NAVSS_INT_RTR_OUTPUT_A53_1    113
-
-#define NAVSS_INT_RTR_OUTPUT_R5F0_0 120
-#define NAVSS_INT_RTR_OUTPUT_R5F1_0 121
-#define NAVSS_INT_RTR_OUTPUT_R5F0_1 122
-#define NAVSS_INT_RTR_OUTPUT_R5F1_1 123
-
-/* The following INPUT is connected to NAVSS OUTPUT 120 */
-#define M2M_LVL_INT_RTR_INPUT_A53_PEND_120 184
-/* The following INPUT is connected to NAVSS OUTPUT 121 */
-#define M2M_LVL_INT_RTR_INPUT_A53_PEND_121 185
-
-/* The following INPUT is connected to NAVSS OUTPUT 122 */
-#define M2M_LVL_INT_RTR_INPUT_A53_PEND_122 186
-/* The following INPUT is connected to NAVSS OUTPUT 123 */
-#define M2M_LVL_INT_RTR_INPUT_A53_PEND_123 187
-
-static inline void connect_m2m_lvl_int_rtr(UInt32 input_evt, UInt32 output_line)
-{
-#ifdef INTERRUPT_ROUTING_THROUGH_DMSC
-    /* TODO: Need to add code to configure routing through DMSC */
-#else
-    /* TODO: Eventually the interrupt routing below cannot be done
-     * directly. Need to go through DMSC. Currently this is done
-     * directly to help Pre-silicon testing
-     */
-    *((UInt32 *)(M2M_LVL_INT_RTR_BASE + M2M_LV_INT_ICR0_OFFSET) + output_line) = input_evt;
-#endif
-}
-
-static inline void connect_navss_int_rtr(UInt32 input_evt, UInt32 output_line)
-{
-#ifdef INTERRUPT_ROUTING_THROUGH_DMSC
-    /* TODO: Need to add code to configure routing through DMSC */
-#else
-    /* TODO: Eventually the interrupt routing below cannot be done
-     * directly. Need to go through DMSC. Currently this is done
-     * directly to help Pre-silicon testing
-     */
-    *((UInt32 *)(NAVSS_INT_RTR_BASE + NAVSS_INT_ICR0_OFFSET) + output_line) = input_evt;
-#endif
-}
-
 /*
  *************************************************************************
  *                      Module functions
@@ -170,65 +99,9 @@ static inline void connect_navss_int_rtr(UInt32 input_evt, UInt32 output_line)
  */
 Int NotifySetup_Module_startup(Int phase)
 {
-#if defined(xdc_target__isaCompatible_v7R)
-    /* connect mailbox interrupts at startup */
-    if ((Core_getId() == 0)) {
-        /* R5F-0 */
-        /* Navss mailbox 0 User 1 */
-        /* Configure NAVSS interrupt router */
-        connect_navss_int_rtr(NAVSS_INT_RTR_INPUT_MAILBOX0_USER1,
-            NAVSS_INT_RTR_OUTPUT_R5F0_0);
-        /* Configure MCU level interrupt router */
-        connect_m2m_lvl_int_rtr(M2M_LVL_INT_RTR_INPUT_A53_PEND_120,
-            M2M_LVL_INT_RTR_OUTPUT_R5F0_0);
-
-        /* plug mbx2 only if R5F-1 exists */
-        if ((MultiProc_getId("R5F-1") != MultiProc_INVALIDID)) {
-            /* Navss mailbox 2 User 0 */
-            /* Configure NAVSS interrupt router */
-            connect_navss_int_rtr(NAVSS_INT_RTR_INPUT_MAILBOX2_USER0,
-                NAVSS_INT_RTR_OUTPUT_R5F0_1);
-            /* Configure MCU level interrupt router */
-            connect_m2m_lvl_int_rtr(M2M_LVL_INT_RTR_INPUT_A53_PEND_121,
-                M2M_LVL_INT_RTR_OUTPUT_R5F0_1);
-        }
-    }
-    else { /* R5F-1 */
-        /* Navss mailbox 1 User 1 */
-        /* Configure NAVSS interrupt router */
-        connect_navss_int_rtr(NAVSS_INT_RTR_INPUT_MAILBOX1_USER1,
-            NAVSS_INT_RTR_OUTPUT_R5F1_0);
-        /* Configure MCU level interrupt router */
-        connect_m2m_lvl_int_rtr(M2M_LVL_INT_RTR_INPUT_A53_PEND_122,
-            M2M_LVL_INT_RTR_OUTPUT_R5F1_1);
-
-        /* plug mbx2 only if R5F-0 exists */
-        if ((MultiProc_getId("R5F-0") != MultiProc_INVALIDID)) {
-            /* Navss mailbox 2 User 1 */
-            /* Configure NAVSS interrupt router */
-            connect_navss_int_rtr(NAVSS_INT_RTR_INPUT_MAILBOX2_USER1,
-                NAVSS_INT_RTR_OUTPUT_R5F1_1);
-            /* Configure MCU level interrupt router */
-            connect_m2m_lvl_int_rtr(M2M_LVL_INT_RTR_INPUT_A53_PEND_123,
-                M2M_LVL_INT_RTR_OUTPUT_R5F1_1);
-        }
-    }
-    return (Startup_DONE);
+    NotifySciClient_Init();
 
-#elif defined(xdc_target__isaCompatible_v8A)
-    /* Navss mailbox 0 User 0 */
-    /* Configure NAVSS interrupt router */
-    connect_navss_int_rtr(NAVSS_INT_RTR_INPUT_MAILBOX0_USER0,
-        NAVSS_INT_RTR_OUTPUT_A53_0);
-    /* Navss mailbox 1 User 0 */
-    /* Configure NAVSS interrupt router */
-    connect_navss_int_rtr(NAVSS_INT_RTR_INPUT_MAILBOX1_USER0,
-        NAVSS_INT_RTR_OUTPUT_A53_1);
     return (Startup_DONE);
-
-#else
-#error Invalid target
-#endif
 }
 
 /*
@@ -305,6 +178,60 @@ Void NotifySetup_plugHwi(UInt16 remoteProcId, Int cpuIntrNum,
 
     /* disable interrupts */
     key = Hwi_disable();
+#if defined(xdc_target__isaCompatible_v7R)
+    /* connect mailbox interrupts at startup */
+
+    if ((Core_getId() == 0)) {
+        /* R5F-0 */
+        if (remoteProcId == MultiProc_getId("R5F-1") ) {
+            /* Navss mailbox 2 User 0 */
+            /* Configure NAVSS & MCU Level Interrupt router */
+            NotifySciClient_IrqSet(NotifySciClient_R5F_0_CORE_INDEX,
+                                   NotifySciClient_MAILBOX_CLUSTER2_SRC_ID_INDEX,
+                                   NotifySciClient_MAILBOX_USER_0, cpuIntrNum);
+        } else { /* Host */
+            /* Navss mailbox 0 User 1 */
+            /* Configure NAVSS & MCU Level Interrupt router */
+            NotifySciClient_IrqSet(NotifySciClient_R5F_0_CORE_INDEX,
+                                   NotifySciClient_MAILBOX_CLUSTER0_SRC_ID_INDEX,
+                                   NotifySciClient_MAILBOX_USER_1, cpuIntrNum);
+         }
+    }
+    else { /* R5F-1 */
+        if (remoteProcId == MultiProc_getId("R5F-0") ) {
+            /* Navss mailbox 2 User 1 */
+            /* Configure NAVSS & MCU Level Interrupt router */
+            NotifySciClient_IrqSet(NotifySciClient_R5F_1_CORE_INDEX,
+                                   NotifySciClient_MAILBOX_CLUSTER2_SRC_ID_INDEX,
+                                   NotifySciClient_MAILBOX_USER_1, cpuIntrNum);
+
+        } else { /* Host */
+            /* Navss mailbox 1 User 1 */
+            /* Configure NAVSS & MCU Level Interrupt router */
+            NotifySciClient_IrqSet(NotifySciClient_R5F_1_CORE_INDEX,
+                                   NotifySciClient_MAILBOX_CLUSTER1_SRC_ID_INDEX,
+                                   NotifySciClient_MAILBOX_USER_1, cpuIntrNum);
+        }
+    }
+
+#elif defined(xdc_target__isaCompatible_v8A)
+       if (remoteProcId == MultiProc_getId("R5F-0") ) {
+           /* Navss mailbox 0 User 0 */
+           /* Configure NAVSS interrupt router */
+            NotifySciClient_IrqSet(NotifySciClient_A53_0_CORE_INDEX,
+                                   NotifySciClient_MAILBOX_CLUSTER0_SRC_ID_INDEX,
+                                   NotifySciClient_MAILBOX_USER_0, cpuIntrNum);
+
+       } else {
+           /* Navss mailbox 1 User 0 */
+           /* Configure NAVSS interrupt router */
+          NotifySciClient_IrqSet(NotifySciClient_A53_0_CORE_INDEX,
+                                 NotifySciClient_MAILBOX_CLUSTER1_SRC_ID_INDEX,
+                                 NotifySciClient_MAILBOX_USER_0, cpuIntrNum);
+       }
+#else
+#error Invalid target
+#endif
 
     /* map remote processor id to virtual id */
     srcVirtId = VIRTID(remoteProcId);
diff --git a/packages/ti/sdo/ipc/family/am65xx/NotifySetup.xs b/packages/ti/sdo/ipc/family/am65xx/NotifySetup.xs
index 35dc53c..f47be19 100644
--- a/packages/ti/sdo/ipc/family/am65xx/NotifySetup.xs
+++ b/packages/ti/sdo/ipc/family/am65xx/NotifySetup.xs
@@ -85,11 +85,26 @@ function module$use()
 {
     /* load modules needed in meta domain and in target domain */
     var TableInit = xdc.useModule("ti.sdo.ipc.family.am65xx.TableInit");
+    var NotifySciClient = xdc.useModule("ti.sdo.ipc.family.am65xx.NotifySciClient");
     MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
     xdc.useModule('xdc.runtime.Assert');
     xdc.useModule('xdc.runtime.Error');
     xdc.useModule('xdc.runtime.Startup');
 
+    /* The following csl & osal modules needed by sciclient module */
+    var devType              = "am65xx"
+    var Csl         	     = xdc.loadPackage('ti.csl');
+    Csl.Settings.deviceType  = devType;
+
+    var osType           = "tirtos";
+    var Osal             = xdc.loadPackage('ti.osal');
+    Osal.Settings.osType = osType;
+
+    /* sciclient needed for interrupt routing and other resource allocation */
+    var sciclientSettings = xdc.useModule ('ti.drv.sciclient.Settings');
+    sciclientSettings.socType = "am65xx";
+    sciclientSettings.boardType = "am65xx_evm";
+
     /* concatinate isa chain into single string for easier matching */
     isaChain = "#" + Program.build.target.getISAChain().join("#") + "#";
 
diff --git a/packages/ti/sdo/ipc/family/am65xx/package.bld b/packages/ti/sdo/ipc/family/am65xx/package.bld
index d963332..da735c3 100644
--- a/packages/ti/sdo/ipc/family/am65xx/package.bld
+++ b/packages/ti/sdo/ipc/family/am65xx/package.bld
@@ -39,7 +39,8 @@ var IpcBuild = xdc.loadCapsule("ti/sdo/ipc/Build.xs");
 
 var objList_common = [
     "NotifySetup.c",
-    "NotifyDriverMbx.c"
+    "NotifyDriverMbx.c",
+    "NotifySciClient.c"
 ];
 
 var objList_r5f = [
diff --git a/packages/ti/sdo/ipc/family/am65xx/package.xdc b/packages/ti/sdo/ipc/family/am65xx/package.xdc
index 8c978c4..989869a 100644
--- a/packages/ti/sdo/ipc/family/am65xx/package.xdc
+++ b/packages/ti/sdo/ipc/family/am65xx/package.xdc
@@ -45,6 +45,7 @@ requires ti.sdo.ipc;
  */
 package ti.sdo.ipc.family.am65xx [1,0,1] {
     module    TableInit;
+    module    NotifySciClient;
     module    NotifySetup;
     module    NotifyDriverMbx;
     module    InterruptR5f;
diff --git a/products.mak b/products.mak
index dddf237..c997e58 100644
--- a/products.mak
+++ b/products.mak
@@ -99,6 +99,7 @@ QNX_CFLAGS =
 #
 XDC_INSTALL_DIR = $(DEPOT)/_your_xdctools_install_
 BIOS_INSTALL_DIR = $(DEPOT)/_your_bios_install_
+PDK_INSTALL_DIR = $(DEPOT)/_your_pdk_install_
 
 # Do you want to build SMP-enabled libraries (if supported for your target)?
 # Set to either 0 (disabled) or 1 (enabled)