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| author | Sam Nelson <sam.nelson@ti.com> | 2018-03-27 08:43:34 -0400 |
|---|---|---|
| committer | Sam Nelson <sam.nelson@ti.com> | 2018-08-09 16:01:32 -0400 |
| commit | e8c3e35a110bca6fd4ba03dd3553953fffc8e540 (patch) | |
| tree | b1d3699f9a1841357f0796578ea36962cbfbe295 | |
| parent | 67e9c143d14dfd50ce18dc07d700bc71a6583500 (diff) | |
| download | ipc-e8c3e35a110bca6fd4ba03dd3553953fffc8e540.tar.gz | |
TMP: listMP: Add Cache operation for v8A
Ideally with the coherence working between A53 and R5F, there is no
cache operations required from A53 side. But the coherence operations
requires the ISC registers configured for R5F transactions to be non-
secure.
Adding this as temporary workaround.
Signed-off-by: Sam Nelson <sam.nelson@ti.com>
| -rw-r--r-- | packages/ti/sdo/ipc/ListMP.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/packages/ti/sdo/ipc/ListMP.c b/packages/ti/sdo/ipc/ListMP.c index 659757b..2f2bdb1 100644 --- a/packages/ti/sdo/ipc/ListMP.c +++ b/packages/ti/sdo/ipc/ListMP.c @@ -282,7 +282,7 @@ Bool ListMP_empty(ListMP_Handle handle) /* prevent another thread or processor from modifying the ListMP */ key = GateMP_enter((GateMP_Handle)obj->gate); -#ifdef xdc_target__isaCompatible_v7A +#if defined(xdc_target__isaCompatible_v7A) || defined(xdc_target__isaCompatible_v8A) /* ARM speculative execution might have pulled attrs into cache */ if (obj->cacheEnabled) { Cache_inv(attrs, sizeof(ti_sdo_ipc_ListMP_Attrs), Cache_Type_ALL, TRUE); @@ -340,7 +340,7 @@ Ptr ListMP_getHead(ListMP_Handle handle) /* prevent another thread or processor from modifying the ListMP */ key = GateMP_enter((GateMP_Handle)obj->gate); -#ifdef xdc_target__isaCompatible_v7A +#if defined(xdc_target__isaCompatible_v7A) || defined(xdc_target__isaCompatible_v8A) /* ARM speculative execution might have pulled attrs into cache */ if (obj->cacheEnabled) { Cache_inv(attrs, sizeof(ti_sdo_ipc_ListMP_Attrs), Cache_Type_ALL, TRUE); @@ -423,7 +423,7 @@ Ptr ListMP_getTail(ListMP_Handle handle) /* prevent another thread or processor from modifying the ListMP */ key = GateMP_enter((GateMP_Handle)obj->gate); -#ifdef xdc_target__isaCompatible_v7A +#if defined(xdc_target__isaCompatible_v7A) || defined(xdc_target__isaCompatible_v8A) /* ARM speculative execution might have pulled attrs into cache */ if (obj->cacheEnabled) { Cache_inv(attrs, sizeof(ti_sdo_ipc_ListMP_Attrs), Cache_Type_ALL, TRUE); @@ -655,7 +655,7 @@ Int ListMP_putHead(ListMP_Handle handle, ListMP_Elem *elem) /* prevent another thread or processor from modifying the ListMP */ key = GateMP_enter((GateMP_Handle)obj->gate); -#ifdef xdc_target__isaCompatible_v7A +#if defined(xdc_target__isaCompatible_v7A) || defined(xdc_target__isaCompatible_v8A) /* ARM speculative execution might have pulled attrs into cache */ if (obj->cacheEnabled) { Cache_inv(attrs, sizeof(ti_sdo_ipc_ListMP_Attrs), Cache_Type_ALL, TRUE); @@ -726,7 +726,7 @@ Int ListMP_putTail(ListMP_Handle handle, ListMP_Elem *elem) /* prevent another thread or processor from modifying the ListMP */ key = GateMP_enter((GateMP_Handle)obj->gate); -#ifdef xdc_target__isaCompatible_v7A +#if defined(xdc_target__isaCompatible_v7A) || defined(xdc_target__isaCompatible_v8A) /* ARM speculative execution might have pulled attrs into cache */ if (obj->cacheEnabled) { Cache_inv(attrs, sizeof(ti_sdo_ipc_ListMP_Attrs), Cache_Type_ALL, TRUE); @@ -859,7 +859,7 @@ Int ti_sdo_ipc_ListMP_Instance_init(ti_sdo_ipc_ListMP_Object *obj, obj->cacheEnabled = SharedRegion_isCacheEnabled(obj->regionId); obj->cacheLineSize = SharedRegion_getCacheLineSize(obj->regionId); -#ifdef xdc_target__isaCompatible_v7A +#if defined(xdc_target__isaCompatible_v7A) || defined(xdc_target__isaCompatible_v8A) /* ARM speculative execution might have pulled attrs into cache */ if (obj->cacheEnabled) { Cache_inv(obj->attrs, sizeof(ti_sdo_ipc_ListMP_Attrs), Cache_Type_ALL, |