diff options
Diffstat (limited to 'wl1271/external_drivers')
| -rw-r--r-- | wl1271/external_drivers/sdio/linux/SdioDrv.c (renamed from wl1271/external_drivers/zoom2/Linux/sdio/SdioDrv.c) | 667 | ||||
| -rw-r--r-- | wl1271/external_drivers/sdio/linux/SdioDrv.h (renamed from wl1271/external_drivers/zoom2/Linux/sdio/SdioDrv.h) | 2 | ||||
| -rw-r--r-- | wl1271/external_drivers/sdio/linux/SdioDrvDbg.h (renamed from wl1271/external_drivers/zoom2/Linux/sdio/SdioDrvDbg.h) | 0 | ||||
| -rw-r--r-- | wl1271/external_drivers/zoom2/Linux/sdio/Makefile | 55 |
4 files changed, 358 insertions, 366 deletions
diff --git a/wl1271/external_drivers/zoom2/Linux/sdio/SdioDrv.c b/wl1271/external_drivers/sdio/linux/SdioDrv.c index a8cb514e..8797d4e4 100644 --- a/wl1271/external_drivers/zoom2/Linux/sdio/SdioDrv.c +++ b/wl1271/external_drivers/sdio/linux/SdioDrv.c @@ -33,32 +33,54 @@ #include <linux/kernel.h> #include <linux/module.h> +#include <linux/version.h> #include <linux/moduleparam.h> #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/slab.h> -#include <mach/io.h> #include <linux/types.h> #include <linux/dma-mapping.h> -#include <mach/hardware.h> #include <linux/platform_device.h> -#include <mach/hardware.h> #include <linux/i2c/twl4030.h> -#include <mach/board.h> #include <linux/errno.h> #include <linux/clk.h> +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 31)) +#include <plat/hardware.h> +#include <plat/board.h> +#include <plat/clock.h> +#include <plat/dma.h> +#include <plat/io.h> +#include <plat/resource.h> +#define IO_ADDRESS(pa) OMAP2_L4_IO_ADDRESS(pa) +#else +#include <mach/hardware.h> +#include <mach/board.h> #include <mach/clock.h> #include <mach/dma.h> #include <mach/io.h> #include <mach/resource.h> -typedef void* TI_HANDLE; +#endif +typedef void *TI_HANDLE; #include "host_platform.h" #include "SdioDrvDbg.h" #include "SdioDrv.h" -#define TIWLAN_MMC_CONTROLLER 3 -#define TIWLAN_MMC_CONTROLLER_BASE_ADDR OMAP_HSMMC3_BASE -#define TIWLAN_MMC_CONTROLLER_BASE_SIZE 512 +/* #define TI_SDIO_DEBUG */ + +#ifndef CONFIG_MMC_EMBEDDED_SDIO + +#define SDIOWQ_NAME "sdio_wq" + +/* + * HSMMC Address and DMA Settings + */ +static unsigned long TIWLAN_MMC_CONTROLLER = 2; /* MMC3 */ +static unsigned long TIWLAN_MMC_CONTROLLER_BASE_ADDR = OMAP_HSMMC3_BASE; +#define TIWLAN_MMC_CONTROLLER_BASE_SIZE 512 +#define TIWLAN_MMC_MAX_DMA 8192 +static unsigned long TIWLAN_MMC_DMA_TX = OMAP34XX_DMA_MMC3_TX; +static unsigned long TIWLAN_MMC_DMA_RX = OMAP34XX_DMA_MMC3_RX; +static unsigned long OMAP_MMC_IRQ = INT_MMC3_IRQ; #define OMAP_MMC_MASTER_CLOCK 96000000 /* @@ -97,72 +119,70 @@ typedef void* TI_HANDLE; #define SDVSDET 0x00000400 #define SIDLE_MODE (0x2 << 3) #define AUTOIDLE 0x1 -#define SDBP (1 << 8) -#define DTO 0xE -#define ICE 0x1 -#define ICS 0x2 -#define CEN (1 << 2) -#define CLKD_MASK 0x0000FFC0 -#define IE_EN_MASK 0x317F0137 -#define INIT_STREAM (1 << 1) -#define DP_SELECT (1 << 21) -#define DDIR (1 << 4) -#define DMA_EN 0x1 +#define SDBP (1 << 8) +#define DTO 0xE +#define ICE 0x1 +#define ICS 0x2 +#define CEN (1 << 2) +#define CLKD_MASK 0x0000FFC0 +#define IE_EN_MASK 0x317F0137 +#define INIT_STREAM (1 << 1) +#define DP_SELECT (1 << 21) +#define DDIR (1 << 4) +#define DMA_EN 0x1 #define MSBS (1 << 5) -#define BCE (1 << 1) +#define BCE (1 << 1) #define ONE_BIT (~(0x2)) -#define EIGHT_BIT (~(0x20)) -#define CC 0x1 -#define TC 0x02 -#define OD 0x1 -#define BRW 0x400 -#define BRR 0x800 -#define BRE (1 << 11) -#define BWE (1 << 10) -#define SBGR (1 << 16) -#define CT (1 << 17) -#define SDIO_READ (1 << 31) -#define SDIO_BLKMODE (1 << 27) +#define EIGHT_BIT (~(0x20)) +#define CC 0x1 +#define TC 0x02 +#define OD 0x1 +#define BRW 0x400 +#define BRR 0x800 +#define BRE (1 << 11) +#define BWE (1 << 10) +#define SBGR (1 << 16) +#define CT (1 << 17) +#define SDIO_READ (1 << 31) +#define SDIO_BLKMODE (1 << 27) #define OMAP_HSMMC_ERR (1 << 15) /* Any error */ #define OMAP_HSMMC_CMD_TIMEOUT (1 << 16) /* Com mand response time-out */ #define OMAP_HSMMC_DATA_TIMEOUT (1 << 20) /* Data response time-out */ #define OMAP_HSMMC_CMD_CRC (1 << 17) /* Command CRC error */ #define OMAP_HSMMC_DATA_CRC (1 << 21) /* Date CRC error */ #define OMAP_HSMMC_CARD_ERR (1 << 28) /* Card ERR */ -#define OMAP_HSMMC_STAT_CLEAR 0xFFFFFFFF -#define INIT_STREAM_CMD 0x00000000 -#define INT_CLEAR 0x00000000 -#define BLK_CLEAR 0x00000000 +#define OMAP_HSMMC_STAT_CLEAR 0xFFFFFFFF +#define INIT_STREAM_CMD 0x00000000 +#define INT_CLEAR 0x00000000 +#define BLK_CLEAR 0x00000000 /* SCM CONTROL_DEVCONF1 MMC1 overwrite but */ -#define MMC1_ACTIVE_OVERWRITE (1 << 31) - -#define sdio_blkmode_regaddr 0x2000 -#define sdio_blkmode_mask 0xFF00 - -#define IO_RW_DIRECT_MASK 0xF000FF00 -#define IO_RW_DIRECT_ARG_MASK 0x80001A00 - -#define RMASK (MMC_RSP_MASK | MMC_RSP_CRC) +#define MMC1_ACTIVE_OVERWRITE (1 << 31) + +#define sdio_blkmode_regaddr 0x2000 +#define sdio_blkmode_mask 0xFF00 + +#define IO_RW_DIRECT_MASK 0xF000FF00 +#define IO_RW_DIRECT_ARG_MASK 0x80001A00 + +#define RMASK (MMC_RSP_MASK | MMC_RSP_CRC) #define MMC_TIMEOUT_MS 100 /*on the new 2430 it was 20, i changed back to 100*//* obc */ -#define MMCA_VSN_4 4 - -#define VMMC1_DEV_GRP 0x27 -#define P1_DEV_GRP 0x20 -#define VMMC1_DEDICATED 0x2A -#define VSEL_3V 0x02 -#define VSEL_18V 0x00 -#define PBIAS_3V 0x03 -#define PBIAS_18V 0x02 -#define PBIAS_LITE 0x04A0 -#define PBIAS_CLR 0x00 +#define MMCA_VSN_4 4 + +#define VMMC1_DEV_GRP 0x27 +#define P1_DEV_GRP 0x20 +#define VMMC1_DEDICATED 0x2A +#define VSEL_3V 0x02 +#define VSEL_18V 0x00 +#define PBIAS_3V 0x03 +#define PBIAS_18V 0x02 +#define PBIAS_LITE 0x04A0 +#define PBIAS_CLR 0x00 #define OMAP_MMC_REGS_BASE IO_ADDRESS(TIWLAN_MMC_CONTROLLER_BASE_ADDR) -#define INT_MMC3_IRQ 94 -#define OMAP_MMC_IRQ INT_MMC3_IRQ -/* +/* * MMC Host controller read/write API's. */ #define OMAP_HSMMC_READ_OFFSET(offset) (__raw_readl((OMAP_MMC_REGS_BASE) + (offset))) @@ -188,7 +208,7 @@ typedef void* TI_HANDLE; #define SDIO_CMD53_READ(v1,v2,v3,v4,v5,v6) (SDIO_RWFLAG(v1)|SDIO_FUNCN(v2)|SDIO_BLKM(v3)| SDIO_OPCODE(v4)|SDIO_ADDRREG(v5)|(v6&0x1ff)) #define SDIO_CMD53_WRITE(v1,v2,v3,v4,v5,v6) (SDIO_RWFLAG(v1)|SDIO_FUNCN(v2)|SDIO_BLKM(v3)| SDIO_OPCODE(v4)|SDIO_ADDRREG(v5)|(v6&0x1ff)) -#define SDIODRV_MAX_LOOPS 50000 +#define SDIODRV_MAX_LOOPS 50000 #define VMMC2_DEV_GRP 0x2B #define VMMC2_DEDICATED 0x2E @@ -201,15 +221,14 @@ typedef void* TI_HANDLE; #define VSIM_DEDICATED 0x3A #define TWL4030_MODULE_PM_RECIEVER 0x13 - typedef struct OMAP3430_sdiodrv { struct clk *fclk, *iclk, *dbclk; int ifclks_enabled; - spinlock_t clk_lock; + spinlock_t clk_lock; int dma_tx_channel; int dma_rx_channel; - int irq; + int irq; void (*BusTxnCB)(void* BusTxnHandle, int status); void* BusTxnHandle; unsigned int uBlkSize; @@ -222,7 +241,8 @@ typedef struct OMAP3430_sdiodrv size_t dma_read_size; dma_addr_t dma_write_addr; size_t dma_write_size; - struct workqueue_struct *pWorkQueue; + struct workqueue_struct *sdio_wq; /* Work Queue */ + struct work_struct sdiodrv_work; } OMAP3430_sdiodrv_t; struct omap_hsmmc_regs { @@ -236,18 +256,23 @@ struct omap_hsmmc_regs { }; static struct omap_hsmmc_regs hsmmc_ctx; +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 31)) +static struct platform_device dummy_pdev = { + .dev = { + .bus = &platform_bus_type, + }, +}; +#endif + #define SDIO_DRIVER_NAME "TIWLAN_SDIO" -#define SDIO_DRV_WK_NAME "ti_sdio_drv" module_param(g_sdio_debug_level, int, 0644); MODULE_PARM_DESC(g_sdio_debug_level, "debug level"); int g_sdio_debug_level = SDIO_DEBUGLEVEL_ERR; -EXPORT_SYMBOL( g_sdio_debug_level); +EXPORT_SYMBOL(g_sdio_debug_level); OMAP3430_sdiodrv_t g_drv; -struct work_struct sdiodrv_work; - static int sdiodrv_irq_requested = 0; static int sdiodrv_iclk_got = 0; static int sdiodrv_fclk_got = 0; @@ -256,18 +281,39 @@ static void sdioDrv_hsmmc_save_ctx(void); static void sdioDrv_hsmmc_restore_ctx(void); static void sdiodrv_dma_shutdown(void); +#ifndef TI_SDIO_STANDALONE +void sdio_init( int sdcnum ) +{ + if( sdcnum <= 0 ) + return; + TIWLAN_MMC_CONTROLLER = sdcnum - 1; + if( sdcnum == 2 ) { + TIWLAN_MMC_CONTROLLER_BASE_ADDR = OMAP_HSMMC2_BASE; + TIWLAN_MMC_DMA_TX = OMAP24XX_DMA_MMC2_TX; + TIWLAN_MMC_DMA_RX = OMAP24XX_DMA_MMC2_RX; + OMAP_MMC_IRQ = INT_MMC2_IRQ; + } + else if( sdcnum == 3 ) { + TIWLAN_MMC_CONTROLLER_BASE_ADDR = OMAP_HSMMC3_BASE; + TIWLAN_MMC_DMA_TX = OMAP34XX_DMA_MMC3_TX; + TIWLAN_MMC_DMA_RX = OMAP34XX_DMA_MMC3_RX; + OMAP_MMC_IRQ = INT_MMC3_IRQ; + } +} +#endif + static void sdioDrv_hsmmc_save_ctx(void) { - /* MMC : context save */ - hsmmc_ctx.hctl = OMAP_HSMMC_READ(HCTL); - hsmmc_ctx.capa = OMAP_HSMMC_READ(CAPA); - hsmmc_ctx.sysconfig = OMAP_HSMMC_READ(SYSCONFIG); - hsmmc_ctx.ise = OMAP_HSMMC_READ(ISE); - hsmmc_ctx.ie = OMAP_HSMMC_READ(IE); - hsmmc_ctx.con = OMAP_HSMMC_READ(CON); - hsmmc_ctx.sysctl = OMAP_HSMMC_READ(SYSCTL); - OMAP_HSMMC_WRITE(ISE, 0); - OMAP_HSMMC_WRITE(IE, 0); + /* MMC : context save */ + hsmmc_ctx.hctl = OMAP_HSMMC_READ(HCTL); + hsmmc_ctx.capa = OMAP_HSMMC_READ(CAPA); + hsmmc_ctx.sysconfig = OMAP_HSMMC_READ(SYSCONFIG); + hsmmc_ctx.ise = OMAP_HSMMC_READ(ISE); + hsmmc_ctx.ie = OMAP_HSMMC_READ(IE); + hsmmc_ctx.con = OMAP_HSMMC_READ(CON); + hsmmc_ctx.sysctl = OMAP_HSMMC_READ(SYSCTL); + OMAP_HSMMC_WRITE(ISE, 0); + OMAP_HSMMC_WRITE(IE, 0); } static void sdioDrv_hsmmc_restore_ctx(void) @@ -316,31 +362,17 @@ irqreturn_t sdiodrv_irq(int irq, void *drv) if (g_drv.async_status) { PERR("sdiodrv_irq: ERROR in STAT = 0x%x\n", status); } - - status = queue_work (g_drv.pWorkQueue, &sdiodrv_work); - if (!status) - { - printk("\n***Error sdiodrv_irq: failed to enqueue work,status = %d\n", status); - } - + queue_work(g_drv.sdio_wq, &g_drv.sdiodrv_work); return IRQ_HANDLED; } void sdiodrv_dma_read_cb(int lch, u16 ch_status, void *data) { - int status; - PDEBUG("sdiodrv_dma_read_cb() channel=%d status=0x%x\n", lch, (int)ch_status); g_drv.async_status = ch_status & (1 << 7); - status = queue_work (g_drv.pWorkQueue, &sdiodrv_work); - - if (! status ) - { - printk("\n***Error sdiodrv_dma_read_cb: failed to enqueue work ,status = %d\n", status); - } - + queue_work(g_drv.sdio_wq, &g_drv.sdiodrv_work); sdiodrv_dma_shutdown(); } @@ -353,27 +385,27 @@ int sdiodrv_dma_init(void) { int rc; - rc = omap_request_dma(OMAP34XX_DMA_MMC3_TX, "SDIO WRITE", sdiodrv_dma_write_cb, &g_drv, &g_drv.dma_tx_channel); + rc = omap_request_dma(TIWLAN_MMC_DMA_TX, "SDIO WRITE", sdiodrv_dma_write_cb, &g_drv, &g_drv.dma_tx_channel); if (rc != 0) { - PERR("sdiodrv_dma_init() omap_request_dma(OMAP34XX_DMA_MMC2_TX) FAILED\n"); + PERR("sdiodrv_dma_init() omap_request_dma(TIWLAN_MMC_DMA_TX) FAILED\n"); goto out; } - rc = omap_request_dma(OMAP34XX_DMA_MMC3_RX, "SDIO READ", sdiodrv_dma_read_cb, &g_drv, &g_drv.dma_rx_channel); + rc = omap_request_dma(TIWLAN_MMC_DMA_RX, "SDIO READ", sdiodrv_dma_read_cb, &g_drv, &g_drv.dma_rx_channel); if (rc != 0) { - PERR("sdiodrv_dma_init() omap_request_dma(OMAP24XX_DMA_MMC2_RX) FAILED\n"); + PERR("sdiodrv_dma_init() omap_request_dma(TIWLAN_MMC_DMA_RX) FAILED\n"); goto freetx; } omap_set_dma_src_params(g_drv.dma_rx_channel, 0, // src_port is only for OMAP1 OMAP_DMA_AMODE_CONSTANT, - (OMAP_HSMMC3_BASE) + OMAP_HSMMC_DATA, 0, 0); + (TIWLAN_MMC_CONTROLLER_BASE_ADDR) + OMAP_HSMMC_DATA, 0, 0); omap_set_dma_dest_params(g_drv.dma_tx_channel, 0, // dest_port is only for OMAP1 OMAP_DMA_AMODE_CONSTANT, - (OMAP_HSMMC3_BASE) + OMAP_HSMMC_DATA, 0, 0); + (TIWLAN_MMC_CONTROLLER_BASE_ADDR) + OMAP_HSMMC_DATA, 0, 0); return 0; @@ -385,20 +417,20 @@ out: static void sdiodrv_dma_shutdown(void) { - omap_free_dma(g_drv.dma_tx_channel); - omap_free_dma(g_drv.dma_rx_channel); + omap_free_dma(g_drv.dma_tx_channel); + omap_free_dma(g_drv.dma_rx_channel); } /* sdiodrv_dma_shutdown() */ static u32 sdiodrv_poll_status(u32 reg_offset, u32 stat, unsigned int msecs) { - u32 status=0, loops=0; + u32 status=0, loops=0; do { - status=OMAP_HSMMC_READ_OFFSET(reg_offset); - if(( status & stat)) + status = OMAP_HSMMC_READ_OFFSET(reg_offset); + if(( status & stat)) { - break; + break; } } while (loops++ < SDIODRV_MAX_LOOPS); @@ -439,7 +471,6 @@ static int sdiodrv_send_command(u32 cmdreg, u32 cmdarg) OMAP_HSMMC_SEND_COMMAND(cmdreg, cmdarg); return sdiodrv_poll_status(OMAP_HSMMC_STAT, CC, MMC_TIMEOUT_MS); - } /* sdiodrv_send_command() */ /* @@ -449,9 +480,9 @@ static void OMAP3430_mmc_stop_clock(void) { OMAP_HSMMC_WRITE(SYSCTL, OMAP_HSMMC_READ(SYSCTL) & ~CEN); if ((OMAP_HSMMC_READ(SYSCTL) & CEN) != 0x0) - { + { PERR("MMC clock not stoped, clock freq can not be altered\n"); - } + } } /* OMAP3430_mmc_stop_clock */ /* @@ -501,7 +532,7 @@ static void OMAP3430_mmc_set_clock(unsigned int clock, OMAP3430_sdiodrv_t *host) OMAP_HSMMC_WRITE(SYSCTL, regVal); OMAP_HSMMC_WRITE(SYSCTL, OMAP_HSMMC_READ(SYSCTL) | ICE);//internal clock enable. obc not mentioned in the spec /* - * wait till the the clock is stable (ICS) bit is set + * wait till the the clock is stable (ICS) bit is set */ status = sdiodrv_poll_status(OMAP_HSMMC_SYSCTL, ICS, MMC_TIMEOUT_MS); if(!(status & ICS)) { @@ -531,7 +562,7 @@ static void sdiodrv_free_resources(void) } if (sdiodrv_irq_requested) { - free_irq(g_drv.irq, &g_drv); + free_irq(OMAP_MMC_IRQ, &g_drv); sdiodrv_irq_requested = 0; } } @@ -539,7 +570,7 @@ static void sdiodrv_free_resources(void) int sdioDrv_InitHw(void) { return 0; -} /* sdiodrv_init */ +} /* sdioDrv_InitHw */ void sdiodrv_shutdown(void) { @@ -552,11 +583,11 @@ void sdiodrv_shutdown(void) static int sdiodrv_send_data_xfer_commad(u32 cmd, u32 cmdarg, int length, u32 buffer_enable_status, unsigned int bBlkMode) { - int status; + int status; PDEBUG("%s() writing CMD 0x%x ARG 0x%x\n",__FUNCTION__, cmd, cmdarg); - /* block mode */ + /* block mode */ if(bBlkMode) { /* * Bits 31:16 of BLK reg: NBLK Blocks count for current transfer. @@ -573,32 +604,32 @@ static int sdiodrv_send_data_xfer_commad(u32 cmd, u32 cmdarg, int length, u32 bu */ cmd |= MSBS | BCE ; } else { - OMAP_HSMMC_WRITE(BLK, length); - } + OMAP_HSMMC_WRITE(BLK, length); + } - status = sdiodrv_send_command(cmd, cmdarg); + status = sdiodrv_send_command(cmd, cmdarg); if(!(status & CC)) { - PERR("sdiodrv_send_data_xfer_commad() SDIO Command error! STAT = 0x%x\n", status); - return 0; + PERR("sdiodrv_send_data_xfer_commad() SDIO Command error! STAT = 0x%x\n", status); + return 0; } PDEBUG("%s() length = %d(%dw) BLK = 0x%x\n", __FUNCTION__, length,((length + 3) >> 2), OMAP_HSMMC_READ(BLK)); - return sdiodrv_poll_status(OMAP_HSMMC_PSTATE, buffer_enable_status, MMC_TIMEOUT_MS); + return sdiodrv_poll_status(OMAP_HSMMC_PSTATE, buffer_enable_status, MMC_TIMEOUT_MS); } /* sdiodrv_send_data_xfer_commad() */ int sdiodrv_data_xfer_sync(u32 cmd, u32 cmdarg, void *data, int length, u32 buffer_enable_status) { - u32 buf_start, buf_end, data32; + u32 buf_start, buf_end, data32; int status; - status = sdiodrv_send_data_xfer_commad(cmd, cmdarg, length, buffer_enable_status, 0); + status = sdiodrv_send_data_xfer_commad(cmd, cmdarg, length, buffer_enable_status, 0); if(!(status & buffer_enable_status)) - { - PERR("sdiodrv_data_xfer_sync() buffer disabled! length = %d BLK = 0x%x PSTATE = 0x%x\n", + { + PERR("sdiodrv_data_xfer_sync() buffer disabled! length = %d BLK = 0x%x PSTATE = 0x%x\n", length, OMAP_HSMMC_READ(BLK), status); - return -1; + return -1; } buf_end = (u32)data+(u32)length; @@ -615,7 +646,7 @@ int sdiodrv_data_xfer_sync(u32 cmd, u32 cmdarg, void *data, int length, u32 buff *((unsigned long*)(data)) = OMAP_HSMMC_READ(DATA); } } - else /* 2 bytes aligned */ + else /* 2 bytes aligned */ { for (buf_start = (u32)data; (u32)data < buf_end; data += sizeof(unsigned long)) { @@ -649,22 +680,14 @@ int sdiodrv_data_xfer_sync(u32 cmd, u32 cmdarg, void *data, int length, u32 buff status = sdiodrv_poll_status(OMAP_HSMMC_STAT, TC, MMC_TIMEOUT_MS); if(!(status & TC)) { - PERR("sdiodrv_data_xfer_sync() transfer error! STAT = 0x%x\n", status); - return -1; + PERR("sdiodrv_data_xfer_sync() transfer error! STAT = 0x%x\n", status); + return -1; } return 0; } /* sdiodrv_data_xfer_sync() */ -/*--------------------------------------------------------------------------------------*/ - -/********************************************************************/ -/* SDIO driver interface functions */ -/********************************************************************/ - -/*--------------------------------------------------------------------------------------*/ - int sdioDrv_ConnectBus (void * fCbFunc, void * hCbArg, unsigned int uBlkSizeShift, @@ -675,12 +698,11 @@ int sdioDrv_ConnectBus (void * fCbFunc, g_drv.uBlkSizeShift = uBlkSizeShift; g_drv.uBlkSize = 1 << uBlkSizeShift; - INIT_WORK(&sdiodrv_work, sdiodrv_task); + INIT_WORK(&g_drv.sdiodrv_work, sdiodrv_task); return sdioDrv_InitHw (); } - /*--------------------------------------------------------------------------------------*/ int sdioDrv_DisconnectBus (void) @@ -703,6 +725,8 @@ int sdioDrv_ExecuteCmd (unsigned int uCmd, PDEBUG("sdioDrv_ExecuteCmd() starting cmd %02x arg %08x\n", (int)uCmd, (int)uArg); + sdioDrv_clk_enable(); /* To make sure we have clocks enable */ + uCmdReg = (uCmd << 24) | (uRespType << 16) ; uStatus = sdiodrv_send_command(uCmdReg, uArg); @@ -714,11 +738,10 @@ int sdioDrv_ExecuteCmd (unsigned int uCmd, } if ((uLen > 0) && (uLen <= 4))/*obc - Len > 4 ? shouldn't read anything ? */ { - uResponse = OMAP_HSMMC_READ(RSP10); + uResponse = OMAP_HSMMC_READ(RSP10); memcpy (pResponse, (char *)&uResponse, uLen); PDEBUG("sdioDrv_ExecuteCmd() response = 0x%x\n", uResponse); } - return 0; } @@ -735,15 +758,22 @@ int sdioDrv_ReadSync (unsigned int uFunc, int iStatus; // printk(KERN_INFO "in sdioDrv_ReadSync\n"); - uCmdArg = SDIO_CMD53_READ(0, uFunc, 0, bIncAddr, uHwAddr, uLen); iStatus = sdiodrv_data_xfer_sync(OMAP_HSMMC_CMD53_READ, uCmdArg, pData, uLen, BRE); - if (iStatus != 0) - { + if (iStatus != 0) { PERR("sdioDrv_ReadSync() FAILED!!\n"); } - +#ifdef TI_SDIO_DEBUG + if (uLen == 1) + printk(KERN_INFO "R53: [0x%x](%u) = 0x%x\n", uHwAddr, uLen, (unsigned)(*(char *)pData)); + else if (uLen == 2) + printk(KERN_INFO "R53: [0x%x](%u) = 0x%x\n", uHwAddr, uLen, (unsigned)(*(short *)pData)); + else if (uLen == 4) + printk(KERN_INFO "R53: [0x%x](%u) = 0x%x\n", uHwAddr, uLen, (unsigned)(*(long *)pData)); + else + printk(KERN_INFO "R53: [0x%x](%u)\n", uHwAddr, uLen); +#endif return iStatus; } @@ -763,33 +793,37 @@ int sdioDrv_ReadAsync (unsigned int uFunc, unsigned int uNumOfElem; dma_addr_t dma_bus_address; - //printk(KERN_INFO "in sdioDrv_ReadAsync\n"); - - if (bBlkMode) - { - /* For block mode use number of blocks instead of length in bytes */ - uNumBlks = uLen >> g_drv.uBlkSizeShift; - uDmaBlockCount = uNumBlks; - /* due to the DMA config to 32Bit per element (OMAP_DMA_DATA_TYPE_S32) the division is by 4 */ - uNumOfElem = g_drv.uBlkSize >> 2; - } - else - { - uNumBlks = uLen; - uDmaBlockCount = 1; - uNumOfElem = (uLen + 3) >> 2; - } +#ifdef TI_SDIO_DEBUG + printk(KERN_INFO "R53: [0x%x](%u) F[%d]\n", uHwAddr, uLen, uFunc); +#endif - uCmdArg = SDIO_CMD53_READ(0, uFunc, bBlkMode, bIncAddr, uHwAddr, uNumBlks); + //printk(KERN_INFO "in sdioDrv_ReadAsync\n"); - iStatus = sdiodrv_send_data_xfer_commad(OMAP_HSMMC_CMD53_READ_DMA, uCmdArg, uNumBlks, BRE, bBlkMode); - - if (!(iStatus & BRE)) - { - PERR("sdioDrv_ReadAsync() buffer disabled! length = %d BLK = 0x%x PSTATE = 0x%x, BlkMode = %d\n", - uLen, OMAP_HSMMC_READ(BLK), iStatus, bBlkMode); - return -1; - } + if (bBlkMode) + { + /* For block mode use number of blocks instead of length in bytes */ + uNumBlks = uLen >> g_drv.uBlkSizeShift; + uDmaBlockCount = uNumBlks; + /* due to the DMA config to 32Bit per element (OMAP_DMA_DATA_TYPE_S32) the division is by 4 */ + uNumOfElem = g_drv.uBlkSize >> 2; + } + else + { + uNumBlks = uLen; + uDmaBlockCount = 1; + uNumOfElem = (uLen + 3) >> 2; + } + + uCmdArg = SDIO_CMD53_READ(0, uFunc, bBlkMode, bIncAddr, uHwAddr, uNumBlks); + + iStatus = sdiodrv_send_data_xfer_commad(OMAP_HSMMC_CMD53_READ_DMA, uCmdArg, uNumBlks, BRE, bBlkMode); + + if (!(iStatus & BRE)) + { + PERR("sdioDrv_ReadAsync() buffer disabled! length = %d BLK = 0x%x PSTATE = 0x%x, BlkMode = %d\n", + uLen, OMAP_HSMMC_READ(BLK), iStatus, bBlkMode); + goto err; + } sdiodrv_dma_init(); @@ -798,7 +832,7 @@ int sdioDrv_ReadAsync (unsigned int uFunc, dma_bus_address = dma_map_single(g_drv.dev, pData, uLen, DMA_FROM_DEVICE); if (!dma_bus_address) { PERR("sdioDrv_ReadAsync: dma_map_single failed\n"); - return -1; + goto err; } if (g_drv.dma_read_addr != 0) { @@ -809,18 +843,24 @@ int sdioDrv_ReadAsync (unsigned int uFunc, g_drv.dma_read_addr = dma_bus_address; g_drv.dma_read_size = uLen; - omap_set_dma_dest_params(g_drv.dma_rx_channel, - 0, // dest_port is only for OMAP1 - OMAP_DMA_AMODE_POST_INC, - dma_bus_address, - 0, 0); + omap_set_dma_dest_params (g_drv.dma_rx_channel, + 0, // dest_port is only for OMAP1 + OMAP_DMA_AMODE_POST_INC, + dma_bus_address, + 0, 0); - omap_set_dma_transfer_params(g_drv.dma_rx_channel, OMAP_DMA_DATA_TYPE_S32, uNumOfElem , uDmaBlockCount , OMAP_DMA_SYNC_FRAME, OMAP34XX_DMA_MMC3_RX, OMAP_DMA_SRC_SYNC); + omap_set_dma_transfer_params(g_drv.dma_rx_channel, OMAP_DMA_DATA_TYPE_S32, uNumOfElem , uDmaBlockCount , OMAP_DMA_SYNC_FRAME, TIWLAN_MMC_DMA_RX, OMAP_DMA_SRC_SYNC); omap_start_dma(g_drv.dma_rx_channel); /* Continued at sdiodrv_irq() after DMA transfer is finished */ +#ifdef TI_SDIO_DEBUG + printk(KERN_INFO "R53: [0x%x](%u) (A)\n", uHwAddr, uLen); +#endif return 0; +err: + return -1; + } @@ -835,6 +875,7 @@ int sdioDrv_WriteSync (unsigned int uFunc, { unsigned int uCmdArg; int iStatus; + // printk(KERN_INFO "in sdioDrv_WriteSync\n"); uCmdArg = SDIO_CMD53_WRITE(1, uFunc, 0, bIncAddr, uHwAddr, uLen); @@ -844,7 +885,16 @@ int sdioDrv_WriteSync (unsigned int uFunc, { PERR("sdioDrv_WriteSync() FAILED!!\n"); } - +#ifdef TI_SDIO_DEBUG + if (uLen == 1) + printk(KERN_INFO "W53: [0x%x](%u) < 0x%x\n", uHwAddr, uLen, (unsigned)(*(char *)pData)); + else if (uLen == 2) + printk(KERN_INFO "W53: [0x%x](%u) < 0x%x\n", uHwAddr, uLen, (unsigned)(*(short *)pData)); + else if (uLen == 4) + printk(KERN_INFO "W53: [0x%x](%u) < 0x%x\n", uHwAddr, uLen, (unsigned)(*(long *)pData)); + else + printk(KERN_INFO "W53: [0x%x](%u)\n", uHwAddr, uLen); +#endif return iStatus; } @@ -864,32 +914,35 @@ int sdioDrv_WriteAsync (unsigned int uFunc, unsigned int uNumOfElem; dma_addr_t dma_bus_address; -// printk(KERN_INFO "in sdioDrv_WriteAsync\n"); - - if (bBlkMode) - { - /* For block mode use number of blocks instead of length in bytes */ - uNumBlks = uLen >> g_drv.uBlkSizeShift; - uDmaBlockCount = uNumBlks; - /* due to the DMA config to 32Bit per element (OMAP_DMA_DATA_TYPE_S32) the division is by 4 */ - uNumOfElem = g_drv.uBlkSize >> 2; - } - else - { - uNumBlks = uLen; - uDmaBlockCount = 1; - uNumOfElem = (uLen + 3) >> 2; - } - - uCmdArg = SDIO_CMD53_WRITE(1, uFunc, bBlkMode, bIncAddr, uHwAddr, uNumBlks); +#ifdef TI_SDIO_DEBUG + printk(KERN_INFO "W53: [0x%x](%u) F[%d] B[%d] I[%d]\n", uHwAddr, uLen, uFunc, bBlkMode, bIncAddr); +#endif - iStatus = sdiodrv_send_data_xfer_commad(OMAP_HSMMC_CMD53_WRITE_DMA, uCmdArg, uNumBlks, BWE, bBlkMode); - if (!(iStatus & BWE)) - { - PERR("sdioDrv_WriteAsync() buffer disabled! length = %d, BLK = 0x%x, Status = 0x%x\n", - uLen, OMAP_HSMMC_READ(BLK), iStatus); - return -1; - } +// printk(KERN_INFO "in sdioDrv_WriteAsync\n"); + if (bBlkMode) + { + /* For block mode use number of blocks instead of length in bytes */ + uNumBlks = uLen >> g_drv.uBlkSizeShift; + uDmaBlockCount = uNumBlks; + /* due to the DMA config to 32Bit per element (OMAP_DMA_DATA_TYPE_S32) the division is by 4 */ + uNumOfElem = g_drv.uBlkSize >> 2; + } + else + { + uNumBlks = uLen; + uDmaBlockCount = 1; + uNumOfElem = (uLen + 3) >> 2; + } + + uCmdArg = SDIO_CMD53_WRITE(1, uFunc, bBlkMode, bIncAddr, uHwAddr, uNumBlks); + + iStatus = sdiodrv_send_data_xfer_commad(OMAP_HSMMC_CMD53_WRITE_DMA, uCmdArg, uNumBlks, BWE, bBlkMode); + if (!(iStatus & BWE)) + { + PERR("sdioDrv_WriteAsync() buffer disabled! length = %d, BLK = 0x%x, Status = 0x%x\n", + uLen, OMAP_HSMMC_READ(BLK), iStatus); + goto err; + } OMAP_HSMMC_WRITE(ISE, TC); @@ -898,7 +951,7 @@ int sdioDrv_WriteAsync (unsigned int uFunc, dma_bus_address = dma_map_single(g_drv.dev, pData, uLen, DMA_TO_DEVICE); if (!dma_bus_address) { PERR("sdioDrv_WriteAsync: dma_map_single failed\n"); - return -1; + goto err; } if (g_drv.dma_write_addr != 0) { @@ -909,18 +962,20 @@ int sdioDrv_WriteAsync (unsigned int uFunc, g_drv.dma_write_addr = dma_bus_address; g_drv.dma_write_size = uLen; - omap_set_dma_src_params(g_drv.dma_tx_channel, - 0, // src_port is only for OMAP1 - OMAP_DMA_AMODE_POST_INC, - dma_bus_address, - 0, 0); + omap_set_dma_src_params (g_drv.dma_tx_channel, + 0, // src_port is only for OMAP1 + OMAP_DMA_AMODE_POST_INC, + dma_bus_address, + 0, 0); - omap_set_dma_transfer_params(g_drv.dma_tx_channel, OMAP_DMA_DATA_TYPE_S32, uNumOfElem, uDmaBlockCount, OMAP_DMA_SYNC_FRAME, OMAP34XX_DMA_MMC3_TX, OMAP_DMA_DST_SYNC); + omap_set_dma_transfer_params(g_drv.dma_tx_channel, OMAP_DMA_DATA_TYPE_S32, uNumOfElem, uDmaBlockCount, OMAP_DMA_SYNC_FRAME, TIWLAN_MMC_DMA_TX, OMAP_DMA_DST_SYNC); omap_start_dma(g_drv.dma_tx_channel); /* Continued at sdiodrv_irq() after DMA transfer is finished */ return 0; +err: + return -1; } /*--------------------------------------------------------------------------------------*/ @@ -935,22 +990,21 @@ int sdioDrv_ReadSyncBytes (unsigned int uFunc, unsigned int i; int iStatus; - for (i = 0; i < uLen; i++) - { + for (i = 0; i < uLen; i++) { uCmdArg = SDIO_CMD52_READ(0, uFunc, 0, uHwAddr); iStatus = sdiodrv_send_command(OMAP_HSMMC_CMD52_READ, uCmdArg); - if (!(iStatus & CC)) - { + if (!(iStatus & CC)) { PERR("sdioDrv_ReadSyncBytes() SDIO Command error status = 0x%x\n", iStatus); return -1; } - else - { + else { *pData = (unsigned char)(OMAP_HSMMC_READ(RSP10)); } - +#ifdef TI_SDIO_DEBUG + printk(KERN_INFO "R52: [0x%x](%u) = 0x%x\n", uHwAddr, uLen, (unsigned)*pData); +#endif uHwAddr++; pData++; } @@ -970,18 +1024,17 @@ int sdioDrv_WriteSyncBytes (unsigned int uFunc, unsigned int i; int iStatus; - for (i = 0; i < uLen; i++) - { + for (i = 0; i < uLen; i++) { +#ifdef TI_SDIO_DEBUG + printk(KERN_INFO "W52: [0x%x](%u) < 0x%x\n", uHwAddr, uLen, (unsigned)*pData); +#endif uCmdArg = SDIO_CMD52_WRITE(1, uFunc, 0, uHwAddr, *pData); iStatus = sdiodrv_send_command(OMAP_HSMMC_CMD52_WRITE, uCmdArg); - - if (!(iStatus & CC)) - { + if (!(iStatus & CC)) { PERR("sdioDrv_WriteSyncBytes() SDIO Command error status = 0x%x\n", iStatus); return -1; } - uHwAddr++; pData++; } @@ -1007,7 +1060,7 @@ static int sdioDrv_probe(struct platform_device *pdev) if (g_drv.irq < 0) return -ENXIO; - rc= request_irq(g_drv.irq, sdiodrv_irq, 0, SDIO_DRIVER_NAME, &g_drv); + rc= request_irq(OMAP_MMC_IRQ, sdiodrv_irq, 0, SDIO_DRIVER_NAME, &g_drv); if (rc != 0) { PERR("sdioDrv_InitHw() - request_irq FAILED!!\n"); return rc; @@ -1015,8 +1068,14 @@ static int sdioDrv_probe(struct platform_device *pdev) sdiodrv_irq_requested = 1; spin_lock_init(&g_drv.clk_lock); - + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 31)) + dummy_pdev.id = TIWLAN_MMC_CONTROLLER; + dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%lu", TIWLAN_MMC_CONTROLLER); + g_drv.fclk = clk_get(&dummy_pdev.dev, "fck"); +#else g_drv.fclk = clk_get(&pdev->dev, "mmchs_fck"); +#endif if (IS_ERR(g_drv.fclk)) { rc = PTR_ERR(g_drv.fclk); PERR("clk_get(fclk) FAILED !!!\n"); @@ -1024,45 +1083,42 @@ static int sdioDrv_probe(struct platform_device *pdev) } sdiodrv_fclk_got = 1; +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 31)) + g_drv.iclk = clk_get(&dummy_pdev.dev, "ick"); +#else g_drv.iclk = clk_get(&pdev->dev, "mmchs_ick"); +#endif if (IS_ERR(g_drv.iclk)) { rc = PTR_ERR(g_drv.iclk); PERR("clk_get(iclk) FAILED !!!\n"); goto err; } sdiodrv_iclk_got = 1; - - rc = clk_enable(g_drv.iclk); - if(rc) { - PERR("clk_enable(iclk) FAILED !!!\n"); - goto err; - } - - rc = clk_enable(g_drv.fclk); - if (rc) { - PERR("clk_enable(fclk) FAILED !!!\n"); - goto err; - } - g_drv.ifclks_enabled = 1; + + rc = sdioDrv_clk_enable(); + if (rc) { + PERR("sdioDrv_probe : clk_enable FAILED !!!\n"); + goto err; + } OMAP3430_mmc_reset(); //obc - init sequence p. 3600,3617 /* 1.8V */ - OMAP_HSMMC_WRITE(CAPA, OMAP_HSMMC_READ(CAPA) | VS18); - OMAP_HSMMC_WRITE(HCTL, OMAP_HSMMC_READ(HCTL) | SDVS18);//SDVS fits p. 3650 + OMAP_HSMMC_WRITE(CAPA, OMAP_HSMMC_READ(CAPA) | VS18); + OMAP_HSMMC_WRITE(HCTL, OMAP_HSMMC_READ(HCTL) | SDVS18);//SDVS fits p. 3650 /* clock gating */ OMAP_HSMMC_WRITE(SYSCONFIG, OMAP_HSMMC_READ(SYSCONFIG) | AUTOIDLE); /* bus power */ - OMAP_HSMMC_WRITE(HCTL, OMAP_HSMMC_READ(HCTL) | SDBP);//SDBP fits p. 3650 + OMAP_HSMMC_WRITE(HCTL, OMAP_HSMMC_READ(HCTL) | SDBP);//SDBP fits p. 3650 /* interrupts */ - OMAP_HSMMC_WRITE(ISE, 0); - OMAP_HSMMC_WRITE(IE, IE_EN_MASK); + OMAP_HSMMC_WRITE(ISE, 0); + OMAP_HSMMC_WRITE(IE, IE_EN_MASK); //p. 3601 suggests moving to the end OMAP3430_mmc_set_clock(clock_rate, &g_drv); - printk("SDIO clock Configuration is now set to %dMhz\n",(int)clock_rate/1000000); + printk(KERN_INFO "SDIO clock Configuration is now set to %dMhz\n",(int)clock_rate/1000000); /* Bus width */ #ifdef SDIO_1_BIT /* see also in SdioAdapter.c */ @@ -1097,16 +1153,15 @@ err: static int sdioDrv_remove(struct platform_device *pdev) { printk(KERN_INFO "sdioDrv_remove: calling sdiodrv_shutdown\n"); - + sdiodrv_shutdown(); - + return 0; } #ifdef CONFIG_PM static int sdioDrv_suspend(struct platform_device *pdev, pm_message_t state) { - printk(KERN_INFO "TISDIO: sdioDrv is suspending\n"); return 0; } @@ -1118,8 +1173,8 @@ static int sdioDrv_resume(struct platform_device *pdev) return 0; } #else -#define sdioDrv_suspend NULL -#define sdioDrv_resume NULL +#define sdioDrv_suspend NULL +#define sdioDrv_resume NULL #endif static struct platform_driver sdioDrv_struct = { @@ -1139,97 +1194,91 @@ void sdioDrv_register_pm(int (*wlanDrvIf_Start)(void), g_drv.wlanDrvIf_pm_suspend = wlanDrvIf_Stop; } -#ifdef CONFIG_PM int sdioDrv_clk_enable(void) { - unsigned long flags; - int ret = 0; - - spin_lock_irqsave(&g_drv.clk_lock, flags); - if (g_drv.ifclks_enabled) - goto done; - ret = clk_enable(g_drv.iclk); - if (ret) - goto clk_en_err1; - ret = clk_enable(g_drv.fclk); - if (ret) - goto clk_en_err2; - g_drv.ifclks_enabled = 1; - - sdioDrv_hsmmc_restore_ctx(); + unsigned long flags; + int ret = 0; + + spin_lock_irqsave(&g_drv.clk_lock, flags); + if (g_drv.ifclks_enabled) + goto done; + + ret = clk_enable(g_drv.iclk); + if (ret) + goto clk_en_err1; + + ret = clk_enable(g_drv.fclk); + if (ret) + goto clk_en_err2; + g_drv.ifclks_enabled = 1; + + sdioDrv_hsmmc_restore_ctx(); done: - spin_unlock_irqrestore(&g_drv.clk_lock, flags); - return ret; + spin_unlock_irqrestore(&g_drv.clk_lock, flags); + return ret; clk_en_err2: - clk_disable(g_drv.iclk); -clk_en_err1: - spin_unlock_irqrestore(&g_drv.clk_lock, flags); - return ret; + clk_disable(g_drv.iclk); +clk_en_err1 : + spin_unlock_irqrestore(&g_drv.clk_lock, flags); + return ret; } void sdioDrv_clk_disable(void) { - unsigned long flags; - - spin_lock_irqsave(&g_drv.clk_lock, flags); - if (!g_drv.ifclks_enabled) - goto done; + unsigned long flags; - sdioDrv_hsmmc_save_ctx(); + spin_lock_irqsave(&g_drv.clk_lock, flags); + if (!g_drv.ifclks_enabled) + goto done; - clk_disable(g_drv.fclk); - clk_disable(g_drv.iclk); - g_drv.ifclks_enabled = 0; + sdioDrv_hsmmc_save_ctx(); + clk_disable(g_drv.fclk); + clk_disable(g_drv.iclk); + g_drv.ifclks_enabled = 0; done: - spin_unlock_irqrestore(&g_drv.clk_lock, flags); -} -#else -int sdioDrv_clk_enable(void) -{ - return 0; + spin_unlock_irqrestore(&g_drv.clk_lock, flags); } -void sdioDrv_clk_disable(void) -{ - return 0; -} +#ifdef TI_SDIO_STANDALONE +static int __init sdioDrv_init(void) +#else +int __init sdioDrv_init(int sdcnum) #endif - -int sdioDrv_init(void) { memset(&g_drv, 0, sizeof(g_drv)); memset(&hsmmc_ctx, 0, sizeof(hsmmc_ctx)); - g_drv.pWorkQueue = create_singlethread_workqueue (SDIO_DRV_WK_NAME); - printk(KERN_INFO "TIWLAN SDIO init\n"); - +#ifndef TI_SDIO_STANDALONE + sdio_init( sdcnum ); +#endif + g_drv.sdio_wq = create_freezeable_workqueue(SDIOWQ_NAME); + if (!g_drv.sdio_wq) { + printk("TISDIO: Fail to create SDIO WQ\n"); + return -EINVAL; + } /* Register the sdio driver */ return platform_driver_register(&sdioDrv_struct); } -void sdioDrv_exit(void) +#ifdef TI_SDIO_STANDALONE +static +#endif +void __exit sdioDrv_exit(void) { /* Unregister sdio driver */ platform_driver_unregister(&sdioDrv_struct); - if(g_drv.pWorkQueue) - { - flush_workqueue(g_drv.pWorkQueue); - destroy_workqueue(g_drv.pWorkQueue); - } + if (g_drv.sdio_wq) + destroy_workqueue(g_drv.sdio_wq); } -//module_init(sdioDrv_init); -//module_exit(sdioDrv_exit); - -EXPORT_SYMBOL(sdioDrv_clk_enable); -EXPORT_SYMBOL(sdioDrv_clk_disable); - -EXPORT_SYMBOL(sdioDrv_init); -EXPORT_SYMBOL(sdioDrv_exit); +#ifdef TI_SDIO_STANDALONE +module_init(sdioDrv_init); +module_exit(sdioDrv_exit); +#endif EXPORT_SYMBOL(sdioDrv_ConnectBus); EXPORT_SYMBOL(sdioDrv_DisconnectBus); @@ -1245,4 +1294,4 @@ MODULE_DESCRIPTION("TI WLAN SDIO driver"); MODULE_LICENSE("GPL"); MODULE_ALIAS(SDIO_DRIVER_NAME); MODULE_AUTHOR("Texas Instruments Inc"); - +#endif diff --git a/wl1271/external_drivers/zoom2/Linux/sdio/SdioDrv.h b/wl1271/external_drivers/sdio/linux/SdioDrv.h index dc2ccaa9..33837608 100644 --- a/wl1271/external_drivers/zoom2/Linux/sdio/SdioDrv.h +++ b/wl1271/external_drivers/sdio/linux/SdioDrv.h @@ -169,8 +169,6 @@ int sdioDrv_WriteSyncBytes (unsigned int uFunc, void sdioDrv_register_pm(int (*wlanDrvIf_Start)(void), int (*wlanDrvIf_Stop)(void)); -int sdioDrv_init(void); -void sdioDrv_exit(void); int sdioDrv_clk_enable(void); void sdioDrv_clk_disable(void); diff --git a/wl1271/external_drivers/zoom2/Linux/sdio/SdioDrvDbg.h b/wl1271/external_drivers/sdio/linux/SdioDrvDbg.h index 8d2bec55..8d2bec55 100644 --- a/wl1271/external_drivers/zoom2/Linux/sdio/SdioDrvDbg.h +++ b/wl1271/external_drivers/sdio/linux/SdioDrvDbg.h diff --git a/wl1271/external_drivers/zoom2/Linux/sdio/Makefile b/wl1271/external_drivers/zoom2/Linux/sdio/Makefile deleted file mode 100644 index 1b08a961..00000000 --- a/wl1271/external_drivers/zoom2/Linux/sdio/Makefile +++ /dev/null @@ -1,55 +0,0 @@ - -PWD := $(shell pwd) -DK_ROOT = ../../../.. - -EXTRA_CFLAGS += -I$(KERNEL_DIR) -I$(PWD)/$(DK_ROOT)/Txn -I$(PWD)/$(DK_ROOT)/external_drivers/zoom2/Linux/sdio -I$(PWD)/$(DK_ROOT)/platforms/hw/host_platform_zoom2/linux - -SDIO_IN_BAND ?= n -TRACE ?= n -STRIP = n - -ifeq ($(SDIO_IN_BAND),y) -EXTRA_CFLAGS += -DSDIO_IN_BAND_INTERRUPT -endif - -ifeq ($(KERNEL_DEBUGGER),y) - EXTRA_CFLAGS += -g -Os -endif -ifeq ($(DEBUG),y) - EXTRA_CFLAGS += -DSDIO_DEBUG -Os -else - EXTRA_CFLAGS += -Os - STRIP = y -endif - -ifneq ($(KERNELRELEASE),) - -obj-m := sdio.o -ifeq ($(TEST),y) -obj-m += testsdio.o -endif - -sdio-objs := SdioDrv.o -ifeq ($(TEST),y) -testsdio-objs += testdrv.o -endif -else - -PWD := $(shell pwd) -all: - pwd - @echo EXTRA_CFLAGS = $(EXTRA_CFLAGS) - $(MAKE) CROSS_COMPILE=$(CROSS_COMPILE) EXTRA_CFLAGS="$(EXTRA_CFLAGS)" ARCH=$(ARCH) -C $(KERNEL_DIR) M=$(PWD) modules -ifeq ($(STRIP),y) - @echo $(CROSS_COMPILE)strip -g sdio.ko - $(CROSS_COMPILE)strip -g sdio.ko -ifeq ($(TEST),y) - $(CROSS_COMPILE)strip -g testsdio.ko -endif -endif -endif - -clean: - rm -f *.o *~ *.~* core .depend dep - rm -rf *.o *~ core .depend .*.cmd *.ko *.mod.c .tmp_versions - |