diff options
| author | Jiyu Yang <Jiyu.Yang@amlogic.com> | 2017-10-28 17:44:03 +0800 |
|---|---|---|
| committer | Jiyu Yang <jiyu.yang@amlogic.com> | 2017-10-30 05:34:40 -0700 |
| commit | 4b2666e36fcbe489566ef787169e3a2f9203ee39 (patch) | |
| tree | 45f23ee6e8edcac17bd5e99479d6518c643fd6fe | |
| parent | 9f14619abff7cd4c51e8394af357afc9c57c1607 (diff) | |
| download | mali-driver-4b2666e36fcbe489566ef787169e3a2f9203ee39.tar.gz | |
gpu: seperately set gp0_pll before changed to 744M
PD#151164: seperately set gp0_pll before changed to 744M
Change-Id: I1550f2e5a3d2b0eea84770eacb36e81fe3a99248
Signed-off-by: Jiyu Yang <Jiyu.Yang@amlogic.com>
| -rw-r--r-- | utgard/platform/meson_bu/mali_clock.c | 33 | ||||
| -rw-r--r-- | utgard/platform/meson_bu/scaling.c | 16 |
2 files changed, 27 insertions, 22 deletions
diff --git a/utgard/platform/meson_bu/mali_clock.c b/utgard/platform/meson_bu/mali_clock.c index b4e22b4..81cce49 100644 --- a/utgard/platform/meson_bu/mali_clock.c +++ b/utgard/platform/meson_bu/mali_clock.c @@ -27,7 +27,7 @@ MODULE_PARM_DESC(gpu_dbg_level, "gpu debug level"); #define GPU_CLK_DBG(fmt, arg...) //disable print -#define _dev_info(...) +//#define _dev_info(...) //static DEFINE_SPINLOCK(lock); static mali_plat_info_t* pmali_plat = NULL; @@ -573,29 +573,22 @@ int mali_dt_info(struct platform_device *pdev, struct mali_plat_info_t *mpdata) if (ret) { dev_notice(&pdev->dev, "read clk_freq failed\n"); } -#if 0 -#ifdef MESON_CPU_VERSION_OPS - if (is_meson_gxbbm_cpu()) { - if (dvfs_tbl->clk_freq >= GXBBM_MAX_GPU_FREQ) - continue; - } -#endif -#endif -#if 0 + ret = of_property_read_string(gpu_clk_dn,"clk_parent", - &dvfs_tbl->clk_parent); + &dvfs_tbl->clk_parent); if (ret) { dev_notice(&pdev->dev, "read clk_parent failed\n"); + } else if (0 == strcmp(dvfs_tbl->clk_parent, "gp0_pll")) { + dvfs_tbl->clkp_handle = devm_clk_get(&pdev->dev, dvfs_tbl->clk_parent); + if (IS_ERR(dvfs_tbl->clkp_handle)) { + dev_notice(&pdev->dev, "failed to get %s's clock pointer\n", dvfs_tbl->clk_parent); + } + ret = of_property_read_u32(gpu_clk_dn,"clkp_freq", &dvfs_tbl->clkp_freq); + if (ret) { + dev_notice(&pdev->dev, "read clk_parent freq failed\n"); + } } - dvfs_tbl->clkp_handle = devm_clk_get(&pdev->dev, dvfs_tbl->clk_parent); - if (IS_ERR(dvfs_tbl->clkp_handle)) { - dev_notice(&pdev->dev, "failed to get %s's clock pointer\n", dvfs_tbl->clk_parent); - } - ret = of_property_read_u32(gpu_clk_dn,"clkp_freq", &dvfs_tbl->clkp_freq); - if (ret) { - dev_notice(&pdev->dev, "read clk_parent freq failed\n"); - } -#endif + ret = of_property_read_u32(gpu_clk_dn,"voltage", &dvfs_tbl->voltage); if (ret) { dev_notice(&pdev->dev, "read voltage failed\n"); diff --git a/utgard/platform/meson_bu/scaling.c b/utgard/platform/meson_bu/scaling.c index 8231217..489564f 100644 --- a/utgard/platform/meson_bu/scaling.c +++ b/utgard/platform/meson_bu/scaling.c @@ -63,9 +63,7 @@ static inline void mali_clk_exected(void) { mali_dvfs_threshold_table * pdvfs = pmali_plat->dvfs_table; uint32_t execStep = currentStep; -#if AMLOGIC_GPU_USE_GPPLL mali_dvfs_threshold_table *dvfs_tbl = &pmali_plat->dvfs_table[currentStep]; -#endif //if (pdvfs[currentStep].freq_index == pdvfs[lastStep].freq_index) return; if ((pdvfs[execStep].freq_index == pdvfs[lastStep].freq_index) || @@ -86,11 +84,25 @@ static inline void mali_clk_exected(void) is_gp_pll_put = 0; gp_pll_release(gp_pll_user_gpu); } +#else + if ((0 == strcmp(dvfs_tbl->clk_parent, "gp0_pll")) && + !IS_ERR(dvfs_tbl->clkp_handle) && + (0 != dvfs_tbl->clkp_freq)) { + clk_prepare_enable(dvfs_tbl->clkp_handle); + clk_set_rate(dvfs_tbl->clkp_handle, dvfs_tbl->clkp_freq); + } + #endif //mali_dev_pause(); mali_clock_set(pdvfs[execStep].freq_index); //mali_dev_resume(); +#if AMLOGIC_GPU_USE_GPPLL==0 + if ((0 == strcmp(pdvfs[lastStep].clk_parent,"gp0_pll")) && + (0 != strcmp(pdvfs[execStep].clk_parent, "gp0_pll"))) { + clk_disable_unprepare(pdvfs[lastStep].clkp_handle); + } +#endif lastStep = execStep; #if AMLOGIC_GPU_USE_GPPLL if (is_gp_pll_put) { |