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author | Weizhung Ding <weizhungding@google.com> | 2023-05-15 22:57:03 +0000 |
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committer | Android Partner Code Review <android-gerrit-partner@google.com> | 2023-05-15 22:57:03 +0000 |
commit | 4631ebc7c400d5101c953efd31d4bd33f40b6f66 (patch) | |
tree | 91f2991fd9a0ae575959eb981345f70eda129dc2 | |
parent | 44633276a8d058ac806ad84ce1c77ef751bd9ac7 (diff) | |
parent | 141371ec7d50c673047b7f600404cf695a50dbea (diff) | |
download | felix-4631ebc7c400d5101c953efd31d4bd33f40b6f66.tar.gz |
Merge changes If49437ba,I5b9b1755 into android13-gs-pixel-5.10-tm-qpr3android-13.0.0_r0.107android-13.0.0_r0.106android-13.0.0_r0.105android-13.0.0_r0.104android-13.0.0_r0.103android-13.0.0_r0.100
* changes:
panel: ana6707: adjust voltage during power on/off
panel: ana6707: use pixel_off cmd instead of DBV 0
-rw-r--r-- | display/panel-samsung-ana6707-f10.c | 113 |
1 files changed, 106 insertions, 7 deletions
diff --git a/display/panel-samsung-ana6707-f10.c b/display/panel-samsung-ana6707-f10.c index 917cd01..e3cd249 100644 --- a/display/panel-samsung-ana6707-f10.c +++ b/display/panel-samsung-ana6707-f10.c @@ -103,6 +103,11 @@ struct ana6707_f10_panel { bool delayed_idle; /** @tzd: thermal zone struct */ struct thermal_zone_device *tzd; + /** + * @is_pixel_off: pixel-off command is sent to panel. Only sending normal-on or resetting + * panel can recover to normal mode after entering pixel-off state. + */ + bool is_pixel_off; }; #define to_spanel(ctx) container_of(ctx, struct ana6707_f10_panel, base) @@ -138,14 +143,25 @@ static const u8 sleep_in[] = { MIPI_DCS_ENTER_SLEEP_MODE }; static const u8 early_exit_global_para[] = { 0xB0, 0x05 }; static const u8 mode_set_60hz[] = { 0x60, 0x08 }; static const u8 mode_set_120hz[] = { 0x60, 0x00 }; +static const u8 pixel_off[] = { 0x22 }; +static const u8 normal_on[] = { 0x13 }; static const struct exynos_dsi_cmd ana6707_f10_off_cmds[] = { - EXYNOS_DSI_CMD_SEQ(0xF0, 0x5A, 0x5A), - EXYNOS_DSI_CMD_SEQ(0xB0, 0x10), - EXYNOS_DSI_CMD_SEQ(0xEF, 0x03, 0x03), - EXYNOS_DSI_CMD_SEQ(0xF7, 0x07), - EXYNOS_DSI_CMD_SEQ(0xF0, 0xA5, 0xA5), - EXYNOS_DSI_CMD(display_off, 20), + EXYNOS_DSI_CMD_REV(display_off, 20, PANEL_REV_LT(PANEL_REV_DVT1)), + EXYNOS_DSI_CMD_REV(display_off, 0, PANEL_REV_GE(PANEL_REV_DVT1)), + EXYNOS_DSI_CMD_SEQ_REV(PANEL_REV_GE(PANEL_REV_DVT1), 0xB0, 0x0E), + EXYNOS_DSI_CMD_SEQ_REV(PANEL_REV_GE(PANEL_REV_DVT1), 0xF3, 0x10), + EXYNOS_DSI_CMD_SEQ_REV(PANEL_REV_GE(PANEL_REV_DVT1), 0xB0, 0x9B), + /* VLIN 7.9V */ + EXYNOS_DSI_CMD_SEQ_REV(PANEL_REV_GE(PANEL_REV_DVT1), 0xF3, 0x23, 0x02), + EXYNOS_DSI_CMD_SEQ_REV(PANEL_REV_GE(PANEL_REV_DVT1), 0xB0, 0x9A), + EXYNOS_DSI_CMD_SEQ_REV(PANEL_REV_GE(PANEL_REV_DVT1), 0xF3, 0xF6), + EXYNOS_DSI_CMD_SEQ_REV(PANEL_REV_GE(PANEL_REV_DVT1), 0xB0, 0x16), + /* VGH 7.4V */ + EXYNOS_DSI_CMD_SEQ_REV(PANEL_REV_GE(PANEL_REV_DVT1), 0xF4, 0x30, 0x22), + EXYNOS_DSI_CMD_SEQ_REV(PANEL_REV_GE(PANEL_REV_DVT1), 0xB0, 0x1B), + /* VREG 5.9V */ + EXYNOS_DSI_CMD_SEQ_DELAY_REV(PANEL_REV_GE(PANEL_REV_DVT1), 20, 0xF4, 0x0E), EXYNOS_DSI_CMD(sleep_in, 120), }; static DEFINE_EXYNOS_CMD_SET(ana6707_f10_off); @@ -346,6 +362,47 @@ static const struct ana6707_f10_mode_data ana6707_f10_mode_60 = { .manual_mode_hlpm_cmd_set = &ana6707_f10_60hz_manual_mode_hlpm_cmd_set, }; +static void ana6707_f10_set_voltage(struct exynos_panel *ctx, bool enable) +{ + if (ctx->panel_rev < PANEL_REV_DVT1) + return; + + dev_dbg(ctx->dev, "%s enable = %d\n", __func__, enable); + EXYNOS_DCS_WRITE_TABLE(ctx, unlock_cmd_f0); + + if (enable) { + EXYNOS_DCS_WRITE_SEQ(ctx, 0xB0, 0x0E); + EXYNOS_DCS_WRITE_SEQ(ctx, 0xF3, 0x10); + EXYNOS_DCS_WRITE_SEQ(ctx, 0xB0, 0x9B); + /* VLIN 7.3V */ + EXYNOS_DCS_WRITE_SEQ(ctx, 0xF3, 0x23, 0x0E); + EXYNOS_DCS_WRITE_SEQ(ctx, 0xB0, 0x9A); + EXYNOS_DCS_WRITE_SEQ(ctx, 0xF3, 0xF6); + EXYNOS_DCS_WRITE_SEQ(ctx, 0xB0, 0x16); + /* VGH 6.7V */ + EXYNOS_DCS_WRITE_SEQ(ctx, 0xF4, 0x00, 0xBB); + EXYNOS_DCS_WRITE_SEQ(ctx, 0xB0, 0x1B); + /* VREG 6.5V */ + EXYNOS_DCS_WRITE_SEQ(ctx, 0xF4, 0x14); + } else { + EXYNOS_DCS_WRITE_SEQ(ctx, 0xB0, 0x0E); + EXYNOS_DCS_WRITE_SEQ(ctx, 0xF3, 0x10); + EXYNOS_DCS_WRITE_SEQ(ctx, 0xB0, 0x9B); + /* VLIN 7.9V */ + EXYNOS_DCS_WRITE_SEQ(ctx, 0xF3, 0x23, 0x02); + EXYNOS_DCS_WRITE_SEQ(ctx, 0xB0, 0x9A); + EXYNOS_DCS_WRITE_SEQ(ctx, 0xF3, 0xF6); + EXYNOS_DCS_WRITE_SEQ(ctx, 0xB0, 0x16); + /* VGH 7.4V */ + EXYNOS_DCS_WRITE_SEQ(ctx, 0xF4, 0x30, 0x22); + EXYNOS_DCS_WRITE_SEQ(ctx, 0xB0, 0x1B); + /* VREG 5.9V */ + EXYNOS_DCS_WRITE_SEQ(ctx, 0xF4, 0x0E); + } + + EXYNOS_DCS_WRITE_TABLE(ctx, lock_cmd_f0); +} + static inline bool is_auto_mode_preferred(struct exynos_panel *ctx) { return ctx->panel_idle_enabled; @@ -652,6 +709,8 @@ static int ana6707_f10_enable(struct drm_panel *panel) EXYNOS_DCS_WRITE_SEQ_DELAY(ctx, 10, 0x11); /* sleep out: 10ms delay */ + ana6707_f10_set_voltage(ctx, false); + exynos_dcs_compression_mode(ctx, 0x1); /* DSC_DEC_ON */ EXYNOS_DCS_WRITE_TABLE(ctx, pps_setting); EXYNOS_DCS_WRITE_TABLE(ctx, update_key); @@ -697,6 +756,8 @@ static int ana6707_f10_enable(struct drm_panel *panel) EXYNOS_DCS_WRITE_SEQ_DELAY(ctx, delay, 0x53, 0x20); /* backlight control */ + ana6707_f10_set_voltage(ctx, true); + ctx->enabled = true; if (pmode->exynos_mode.is_lp_mode) { exynos_panel_set_lp_mode(ctx, pmode); @@ -1052,6 +1113,43 @@ static int ana6707_f10_set_power(struct exynos_panel *ctx, bool enable) return 0; } +static int ana6707_f10_set_brightness(struct exynos_panel *ctx, u16 br) +{ + u16 brightness; + struct ana6707_f10_panel *spanel = to_spanel(ctx); + + if (ctx->current_mode->exynos_mode.is_lp_mode) { + const struct exynos_panel_funcs *funcs; + + /* don't stay at pixel-off state in AOD, or black screen is possibly seen */ + if (spanel->is_pixel_off) { + EXYNOS_DCS_WRITE_TABLE(ctx, normal_on); + spanel->is_pixel_off = false; + } + funcs = ctx->desc->exynos_panel_func; + if (funcs && funcs->set_binned_lp) + funcs->set_binned_lp(ctx, br); + return 0; + } + + /* Use pixel off command instead of setting DBV 0 */ + if (!br) { + if (!spanel->is_pixel_off) { + EXYNOS_DCS_WRITE_TABLE(ctx, pixel_off); + spanel->is_pixel_off = true; + dev_dbg(ctx->dev, "%s: pixel off instead of dbv 0\n", __func__); + } + return 0; + } else if (br && spanel->is_pixel_off) { + EXYNOS_DCS_WRITE_TABLE(ctx, normal_on); + spanel->is_pixel_off = false; + } + + brightness = (br & 0xff) << 8 | br >> 8; + + return exynos_dcs_set_brightness(ctx, brightness); +} + static const struct exynos_display_underrun_param underrun_param = { .te_idle_us = 350, .te_var = 1, @@ -1234,6 +1332,7 @@ static int ana6707_f10_panel_probe(struct mipi_dsi_device *dsi) spanel->auto_mode_vrefresh = 0; spanel->delayed_idle = false; + spanel->is_pixel_off = false; spanel->tzd = thermal_zone_device_register("inner-disp", 0, 0, spanel, &spanel_tzd_ops, NULL, 0, 0); if (IS_ERR(spanel->tzd)) @@ -1258,7 +1357,7 @@ static const struct drm_panel_funcs ana6707_f10_drm_funcs = { }; static const struct exynos_panel_funcs ana6707_f10_exynos_funcs = { - .set_brightness = exynos_panel_set_brightness, + .set_brightness = ana6707_f10_set_brightness, .set_lp_mode = ana6707_f10_set_lp_mode, .set_binned_lp = exynos_panel_set_binned_lp, .set_nolp_mode = ana6707_f10_set_nolp_mode, |