panel: use 0x9Eh for PPS setting

update PPS setting for ana6707 and ea8182

Bug: 274534850
Test: boot, suspned/reusme
Change-Id: Id69d7fdd133d93def0af04014ff8f5cec7ad132d
Signed-off-by: Weizhung Ding <weizhungding@google.com>

2 files changed, 23 insertions, 27 deletions

diff --git a/display/panel-samsung-ana6707-f10.c b/display/panel-samsung-ana6707-f10.c
index c7456f1..343b047 100644
--- a/display/panel-samsung-ana6707-f10.c
+++ b/display/panel-samsung-ana6707-f10.c
@@ -107,8 +107,8 @@ struct ana6707_f10_panel {
 
 #define to_spanel(ctx) container_of(ctx, struct ana6707_f10_panel, base)
 
-static const unsigned char PPS_SETTING[] = {
-	0x11, 0x00, 0x00, 0x89, 0x30, 0x80, 0x08, 0xA0,
+static const u8 pps_setting[] = {
+	0x9E, 0x11, 0x00, 0x00, 0x89, 0x30, 0x80, 0x08, 0xA0,
 	0x07, 0x30, 0x00, 0x20, 0x03, 0x98, 0x03, 0x98,
 	0x02, 0x00, 0x03, 0x1A, 0x00, 0x20, 0x03, 0x87,
 	0x00, 0x0C, 0x00, 0x0E, 0x03, 0x9D, 0x01, 0xDA,
@@ -653,7 +653,7 @@ static int ana6707_f10_enable(struct drm_panel *panel)
 	EXYNOS_DCS_WRITE_SEQ_DELAY(ctx, 10, 0x11); /* sleep out: 10ms delay */
 
 	exynos_dcs_compression_mode(ctx, 0x1); /* DSC_DEC_ON */
-	EXYNOS_PPS_LONG_WRITE(ctx); /* PPS_SETTING */
+	EXYNOS_DCS_WRITE_TABLE(ctx, pps_setting);
 	EXYNOS_DCS_WRITE_TABLE(ctx, update_key);
 
 	EXYNOS_DCS_WRITE_SEQ(ctx, 0x35); /* TE on */
@@ -1305,8 +1305,6 @@ const struct brightness_capability ana6707_f10_brightness_capability = {
 };
 
 const struct exynos_panel_desc samsung_ana6707_f10 = {
-	.dsc_pps = PPS_SETTING,
-	.dsc_pps_len = ARRAY_SIZE(PPS_SETTING),
 	.data_lane_cnt = 4,
 	.max_brightness = 3320,
 	.min_brightness = 7,
diff --git a/display/panel-samsung-ea8182-f10.c b/display/panel-samsung-ea8182-f10.c
index 7e9af92..43b6ddf 100644
--- a/display/panel-samsung-ea8182-f10.c
+++ b/display/panel-samsung-ea8182-f10.c
@@ -16,29 +16,29 @@
 
 #include "samsung/panel/panel-samsung-drv.h"
 
-static const unsigned char PPS_SETTING[] = {
-     0x11, 0x00, 0x00, 0x89, 0x30, 0x80, 0x08, 0x2C,
-     0x04, 0x38, 0x02, 0x0B, 0x02, 0x1C, 0x02, 0x1C,
-     0x02, 0x00, 0x02, 0x0E, 0x00, 0x20, 0x32, 0x90,
-     0x00, 0x07, 0x00, 0x0C, 0x00, 0x30, 0x00, 0x32,
-     0x18, 0x00, 0x10, 0xF0, 0x03, 0x0C, 0x20, 0x00,
-     0x06, 0x0B, 0x0B, 0x33, 0x0E, 0x1C, 0x2A, 0x38,
-     0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7B,
-     0x7D, 0x7E, 0x01, 0x02, 0x01, 0x00, 0x09, 0x40,
-     0x09, 0xBE, 0x19, 0xFC, 0x19, 0xFA, 0x19, 0xF8,
-     0x1A, 0x38, 0x1A, 0x78, 0x1A, 0xB6, 0x2A, 0xF6,
-     0x2B, 0x34, 0x2B, 0x74, 0x3B, 0x74, 0x6B, 0xF4,
-     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-};
-
 #define EA8182_F10_WRCTRLD_DIMMING_BIT    0x08
 #define EA8182_F10_WRCTRLD_BCTRL_BIT      0x20
 #define EA8182_F10_WRCTRLD_HBM_BIT        0xE0
 
+static const u8 pps_setting[] = {
+	0x9E, 0x11, 0x00, 0x00, 0x89, 0x30, 0x80, 0x08, 0x2C,
+	0x04, 0x38, 0x02, 0x0B, 0x02, 0x1C, 0x02, 0x1C,
+	0x02, 0x00, 0x02, 0x0E, 0x00, 0x20, 0x32, 0x90,
+	0x00, 0x07, 0x00, 0x0C, 0x00, 0x30, 0x00, 0x32,
+	0x18, 0x00, 0x10, 0xF0, 0x03, 0x0C, 0x20, 0x00,
+	0x06, 0x0B, 0x0B, 0x33, 0x0E, 0x1C, 0x2A, 0x38,
+	0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7B,
+	0x7D, 0x7E, 0x01, 0x02, 0x01, 0x00, 0x09, 0x40,
+	0x09, 0xBE, 0x19, 0xFC, 0x19, 0xFA, 0x19, 0xF8,
+	0x1A, 0x38, 0x1A, 0x78, 0x1A, 0xB6, 0x2A, 0xF6,
+	0x2B, 0x34, 0x2B, 0x74, 0x3B, 0x74, 0x6B, 0xF4,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
+
 static const u8 display_off[] = { MIPI_DCS_SET_DISPLAY_OFF };
 static const u8 display_on[] = { MIPI_DCS_SET_DISPLAY_ON };
 static const u8 sleep_in[] = { MIPI_DCS_ENTER_SLEEP_MODE };
@@ -228,7 +228,7 @@ static int ea8182_f10_enable(struct drm_panel *panel)
 	ea8182_f10_panel_reset(ctx);
 
 	EXYNOS_DCS_WRITE_SEQ(ctx, 0x9D, 0x01);  /* Compression Enable */
-	EXYNOS_PPS_LONG_WRITE(ctx);             /* PPS_SETTING */
+	EXYNOS_DCS_WRITE_TABLE(ctx, pps_setting);
 	exynos_panel_send_cmd_set(ctx, &ea8182_f10_init_cmd_set);
 	usleep_range(90000, 90010);
 	EXYNOS_DCS_WRITE_TABLE(ctx, unlock_cmd_f0);
@@ -565,8 +565,6 @@ const struct brightness_capability ea8182_f10_brightness_capability = {
 };
 
 const struct exynos_panel_desc samsung_ea8182_f10 = {
-	.dsc_pps = PPS_SETTING,
-	.dsc_pps_len = ARRAY_SIZE(PPS_SETTING),
 	.data_lane_cnt = 4,
 	.max_brightness = 3584,
 	.min_brightness = 4,