diff options
author | Ken Lin <lyenting@google.com> | 2023-08-29 10:51:32 +0000 |
---|---|---|
committer | Ken Lin <lyenting@google.com> | 2023-09-07 02:57:34 +0000 |
commit | f17d954aa8ed5c8123c50d24f084316ab5871f97 (patch) | |
tree | f23813a935cca4d1cee9556b7e88be8a7c4c0881 | |
parent | cffadfc662bff25dffe342102593cb42e9340ff6 (diff) | |
download | display-f17d954aa8ed5c8123c50d24f084316ab5871f97.tar.gz |
Revert "drm: samsung: adjust DSC sequence while booting for RRS"
This reverts commit 4d002a328038987ba26b5a57e4fcaa3a1819b837.
Bug: 294185955
Test: Reboot and see if snowflakes happen after switching mode
Test: Switch resolution in Settings App
Change-Id: I71e0f185aa0f7dd8b0541ac04155fd04e15a3ee6
Signed-off-by: Ken Lin <lyenting@google.com>
-rw-r--r-- | samsung/cal_9865/decon_reg.c | 5 | ||||
-rw-r--r-- | samsung/exynos_drm_decon.c | 73 | ||||
-rw-r--r-- | samsung/exynos_drm_decon.h | 2 |
3 files changed, 27 insertions, 53 deletions
diff --git a/samsung/cal_9865/decon_reg.c b/samsung/cal_9865/decon_reg.c index 090ddb5..7364993 100644 --- a/samsung/cal_9865/decon_reg.c +++ b/samsung/cal_9865/decon_reg.c @@ -1462,7 +1462,10 @@ static void decon_reg_configure_lcd(u32 id, struct decon_config *config) decon_reg_set_data_path(id, config); - if (!config->dsc.enabled) { + if (config->dsc.enabled) { + /* call decon_reg_config_data_path_size () inside */ + decon_dsc_reg_init(id, config, overlap_w, 0); + } else { decon_reg_config_data_path_size(id, config->image_width, config->image_height, overlap_w, NULL, &config->dsc); diff --git a/samsung/exynos_drm_decon.c b/samsung/exynos_drm_decon.c index ddb98fa..e34302e 100644 --- a/samsung/exynos_drm_decon.c +++ b/samsung/exynos_drm_decon.c @@ -85,8 +85,6 @@ static bool decon_check_fs_pending_locked(struct decon_device *decon); #define FRAME_TIMEOUT msecs_to_jiffies(100) #endif -#define FIRST_TE_TIMEOUT msecs_to_jiffies(500) - /* wait at least one frame time on top of common timeout */ static inline unsigned long fps_timeout(int fps) { @@ -1243,27 +1241,19 @@ static void decon_exit_hibernation(struct decon_device *decon) static void decon_wait_for_te(struct decon_device *decon, int vrefresh) { - unsigned int timeout_ms = - vrefresh ? DIV_ROUND_UP(MSEC_PER_SEC, vrefresh) : FIRST_TE_TIMEOUT; + unsigned int te_period_ms = DIV_ROUND_UP(MSEC_PER_SEC, vrefresh); reinit_completion(&decon->te_rising); - decon_enable_te_irq(decon, true); - decon_info(decon, "%s: eneble te irq for timing control\n", __func__); - /* - * Wait for next TE rising. For the case of 1st TE after booting, the - * vrefresh may hasn't been determined, set a longer timeout since the - * 1st frame may come late. - */ DPU_ATRACE_BEGIN(__func__); - if (!wait_for_completion_timeout(&decon->te_rising, timeout_ms)) - decon_warn(decon, "%s: wait for TE timeout (%dms)\n", __func__, timeout_ms); - DPU_ATRACE_END(__func__); - decon_enable_te_irq(decon, false); + /* Wait for next TE rising or one TE period */ + if (!wait_for_completion_timeout(&decon->te_rising, te_period_ms)) + decon_debug(decon, "%s: exceed 1 TE period for %dhz\n", __func__, vrefresh); + + DPU_ATRACE_END(__func__); } -#define BOOT_DSC_REG_INIT_DELAY_US 10000 static void decon_enable(struct exynos_drm_crtc *exynos_crtc, struct drm_crtc_state *old_crtc_state) { const struct drm_crtc_state *crtc_state = exynos_crtc->base.state; @@ -1271,7 +1261,6 @@ static void decon_enable(struct exynos_drm_crtc *exynos_crtc, struct drm_crtc_st struct decon_device *decon = exynos_crtc->ctx; int vrefresh = drm_mode_vrefresh(&old_crtc_state->mode); unsigned long flags; - bool decon_init = decon->state == DECON_STATE_INIT; if (decon->state == DECON_STATE_ON) { decon_info(decon, "already enabled(%d)\n", decon->state); @@ -1325,12 +1314,8 @@ static void decon_enable(struct exynos_drm_crtc *exynos_crtc, struct drm_crtc_st } } - if (decon_is_te_enabled(decon)) { + if (decon_is_te_enabled(decon)) decon_request_te_irq(exynos_crtc, exynos_conn_state); - - if (decon_init) - decon->is_first_te_triggered = false; - } } pm_runtime_get_sync(decon->dev); @@ -1354,33 +1339,21 @@ static void decon_enable(struct exynos_drm_crtc *exynos_crtc, struct drm_crtc_st decon_info(decon, "%s -\n", __func__); ret: - if (decon->config.dsc.enabled) { - if (decon_init) { - /* - * The 1st TE period will be 16.6ms while booting because we only - * use 60Hz in the bootloader. Delay an estimated time after - * receiving the 1st TE then configure the DPU DSC so that the - * panel DSC and the 1st framestart can be within the same VSYNC. - */ - decon_wait_for_te(decon, vrefresh); - decon->is_first_te_triggered = true; - usleep_range(BOOT_DSC_REG_INIT_DELAY_US, - BOOT_DSC_REG_INIT_DELAY_US + 100); - } else if (decon->config.dsc.delay_reg_init_us) { - struct drm_atomic_state *state = old_crtc_state->state; - struct exynos_drm_connector_state *exynos_conn_state = - crtc_get_exynos_connector_state(state, crtc_state); - struct exynos_display_mode *exynos_mode = - &exynos_conn_state->exynos_mode; - unsigned int delay_us = decon->config.dsc.delay_reg_init_us; - - decon_wait_for_te(decon, vrefresh); - usleep_range(delay_us, delay_us + 100); - - /* remove the delay */ - exynos_mode->dsc.delay_reg_init_us = 0; - decon->config.dsc.delay_reg_init_us = 0; - } + if (decon->config.dsc.enabled && decon->config.dsc.delay_reg_init_us) { + struct drm_atomic_state *state = old_crtc_state->state; + struct exynos_drm_connector_state *exynos_conn_state = + crtc_get_exynos_connector_state(state, crtc_state); + struct exynos_display_mode *exynos_mode = &exynos_conn_state->exynos_mode; + unsigned int delay_us = decon->config.dsc.delay_reg_init_us; + unsigned int extra_delay_us = + DIV_ROUND_UP(MSEC_PER_SEC, vrefresh) * MSEC_PER_SEC - delay_us; + + decon_wait_for_te(decon, vrefresh); + usleep_range(extra_delay_us, extra_delay_us + 100); + + /* remove the delay */ + exynos_mode->dsc.delay_reg_init_us = 0; + decon->config.dsc.delay_reg_init_us = 0; decon_dsc_reg_init(decon->id, &decon->config, 0, 0); } @@ -2110,7 +2083,7 @@ static irqreturn_t decon_te_irq_handler(int irq, void *dev_id) } DPU_EVENT_LOG(DPU_EVT_TE_INTERRUPT, decon->id, NULL); - if (decon->config.dsc.delay_reg_init_us || !decon->is_first_te_triggered) + if (decon->config.dsc.delay_reg_init_us) complete_all(&decon->te_rising); if (decon->config.mode.op_mode == DECON_COMMAND_MODE) diff --git a/samsung/exynos_drm_decon.h b/samsung/exynos_drm_decon.h index e613dbc..6b91e8b 100644 --- a/samsung/exynos_drm_decon.h +++ b/samsung/exynos_drm_decon.h @@ -485,8 +485,6 @@ struct decon_device { int te_gpio; atomic_t te_ref; struct completion te_rising; /* signaled when irq_te is triggered */ - /* whether the first TE after booting is triggered */ - bool is_first_te_triggered; spinlock_t slock; |