1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
|
/* SPDX-License-Identifier: GPL-2.0-only
*
* Copyright (c) 2020 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Headef file for Display Quality Enhancer.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __EXYNOS_DRM_DQE_H__
#define __EXYNOS_DRM_DQE_H__
#include <drm/samsung_drm.h>
#include <dqe_cal.h>
#include <cal_config.h>
struct decon_device;
struct exynos_dqe;
struct exynos_dqe_state;
struct exynos_dqe_funcs {
void (*update)(struct exynos_dqe *dqe, struct exynos_dqe_state *state,
u32 width, u32 height);
};
enum histogram_run_state {
HSTATE_DISABLED, /* histogram is disabled */
HSTATE_HIBERNATION, /* histogram is disabled due hibernation */
HSTATE_PENDING_FRAMEDONE, /* histogram is enabled, can be read on frame done */
HSTATE_IDLE, /* histogram is enabled, can be read at any time*/
};
struct exynos_dqe_state {
const struct drm_color_lut *degamma_lut;
const struct exynos_matrix *linear_matrix;
const struct exynos_matrix *gamma_matrix;
const struct cgc_lut *cgc_lut;
struct drm_color_lut *regamma_lut;
struct dither_config *disp_dither_config;
struct dither_config *cgc_dither_config;
bool enabled;
bool rcd_enabled;
struct drm_gem_object *cgc_gem;
spinlock_t histogram_slock;
struct exynos_drm_pending_histogram_event *event;
struct histogram_roi *roi;
struct histogram_weights *weights;
struct histogram_bins *bins;
u32 histogram_threshold;
enum exynos_prog_pos histogram_pos;
enum histogram_state hist_state;
enum histogram_run_state hist_run_state;
struct histogram_bins histogram_cached_bins;
};
struct dither_debug_override {
bool force_en;
bool verbose;
struct dither_config val;
};
#define MAX_NAME_SIZE 32
struct debugfs_lut {
void *lut_ptr;
struct drm_color_lut *dlut_ptr;
char name[MAX_NAME_SIZE];
enum elem_size elem_size;
size_t count;
size_t pcount;
bool *dirty;
};
struct exynos_debug_info {
bool force_en;
bool verbose;
bool dirty;
};
struct degamma_debug_override {
struct exynos_debug_info info;
struct drm_color_lut force_lut[DEGAMMA_LUT_SIZE];
};
struct regamma_debug_override {
struct exynos_debug_info info;
struct drm_color_lut force_lut[REGAMMA_LUT_SIZE];
};
struct cgc_debug_override {
bool first_write;
u32 verbose_cnt;
struct exynos_debug_info info;
struct cgc_lut force_lut;
};
struct matrix_debug_override {
struct exynos_debug_info info;
struct exynos_matrix force_matrix;
};
enum dump_type {
DUMP_TYPE_CGC_DIHTER = 0,
DUMP_TYPE_DISP_DITHER,
DUMP_TYPE_DEGAMMA_LUT,
DUMP_TYPE_REGAMMA_LUT,
DUMP_TYPE_CGC_LUT,
DUMP_TYPE_LINEAR_MATRIX,
DUMP_TYPE_GAMMA_MATRIX,
DUMP_TYPE_HISTOGRAM,
DUMP_TYPE_ATC,
DUMP_TYPE_DQE_MAX = DUMP_TYPE_ATC,
DUMP_TYPE_HDR_EOTF,
DUMP_TYPE_HDR_OETF,
DUMP_TYPE_HDR_GAMMUT,
DUMP_TYPE_HDR_TONEMAP,
};
struct debugfs_dump {
enum dump_type type;
u32 id;
enum dqe_dither_type dither_type;
void *priv;
};
struct exynos_dqe {
void __iomem *regs;
bool initialized;
const struct exynos_dqe_funcs *funcs;
struct exynos_dqe_state state;
struct decon_device *decon;
struct class *dqe_class;
struct device *dev;
struct dither_debug_override cgc_dither_override;
struct dither_debug_override disp_dither_override;
struct degamma_debug_override degamma;
struct regamma_debug_override regamma;
struct cgc_debug_override cgc;
struct matrix_debug_override gamma;
struct matrix_debug_override linear;
bool verbose_hist;
bool force_disabled;
bool verbose_atc;
bool dstep_changed;
struct exynos_atc force_atc_config;
u32 lpd_atc_regs[LPD_ATC_REG_CNT];
};
int histogram_request_ioctl(struct drm_device *drm_dev, void *data,
struct drm_file *file);
int histogram_cancel_ioctl(struct drm_device *drm_dev, void *data,
struct drm_file *file);
void handle_histogram_event(struct exynos_dqe *dqe);
void exynos_dqe_update(struct exynos_dqe *dqe, struct exynos_dqe_state *state,
u32 width, u32 height);
void exynos_dqe_reset(struct exynos_dqe *dqe);
void exynos_dqe_hibernation_enter(struct exynos_dqe *dqe);
struct exynos_dqe *exynos_dqe_register(struct decon_device *decon);
void exynos_dqe_save_lpd_data(struct exynos_dqe *dqe);
void exynos_dqe_restore_lpd_data(struct exynos_dqe *dqe);
#endif /* __EXYNOS_DRM_DQE_H__ */
|
