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| author | Vamsidhar reddy Gaddam <gvamsi@google.com> | 2024-01-08 15:35:57 +0000 |
|---|---|---|
| committer | Vamsidhar reddy Gaddam <gvamsi@google.com> | 2024-01-10 06:53:31 +0000 |
| commit | 005bdac5fdb6b2a60b9f70478472269e15767837 (patch) | |
| tree | 4febf8e2eb94f62b9d00d888c09755e40e92e378 | |
| parent | c950dcc66f7f353263bd70e660c1636902359bad (diff) | |
| download | gpu-005bdac5fdb6b2a60b9f70478472269e15767837.tar.gz | |
Minor fixes for MIDCET-5076android-u-qpr3-beta-1_r0.7android-u-qpr3-beta-1_r0.5android-u-qpr3-beta-1_r0.4android-u-qpr3-beta-1_r0.3android-u-qpr3-beta-1_r0.2android-u-qpr3-beta-1_r0.1android-15-dp-1_r0.7android-15-dp-1_r0.5android-15-dp-1_r0.4android-15-dp-1_r0.3android-15-dp-1_r0.2android-15-dp-1_r0.1
In R47P0, MIDCET-5076 had a few issues. These are fixes on top of the
upstream driver.
Bug: 315967882
Test: Compile & Boot
Change-Id: I43707ff80a660455439c0ab5350e9ce192179af0
Signed-off-by: Vamsidhar reddy Gaddam <gvamsi@google.com>
| -rw-r--r-- | mali_kbase/mali_kbase_mem.c | 2 | ||||
| -rw-r--r-- | mali_kbase/mmu/mali_kbase_mmu_hw_direct.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/mali_kbase/mali_kbase_mem.c b/mali_kbase/mali_kbase_mem.c index a53fff1..afc5a30 100644 --- a/mali_kbase/mali_kbase_mem.c +++ b/mali_kbase/mali_kbase_mem.c @@ -2762,7 +2762,7 @@ static int kbase_jit_grow(struct kbase_context *kctx, const struct base_jit_allo kbase_mem_pool_lock(pool); } - if (reg->gpu_alloc->nents > info->commit_pages) { + if (reg->gpu_alloc->nents >= info->commit_pages) { kbase_mem_pool_unlock(pool); spin_unlock(&kctx->mem_partials_lock); dev_info( diff --git a/mali_kbase/mmu/mali_kbase_mmu_hw_direct.c b/mali_kbase/mmu/mali_kbase_mmu_hw_direct.c index bfe6527..25af427 100644 --- a/mali_kbase/mmu/mali_kbase_mmu_hw_direct.c +++ b/mali_kbase/mmu/mali_kbase_mmu_hw_direct.c @@ -215,7 +215,7 @@ static int write_cmd(struct kbase_device *kbdev, unsigned int as_nr, u32 cmd) #if MALI_USE_CSF static int wait_l2_power_trans_complete(struct kbase_device *kbdev) { - u32 val; + u64 val; const u32 timeout_us = kbase_get_timeout_ms(kbdev, MMU_AS_INACTIVE_WAIT_TIMEOUT) * USEC_PER_MSEC; const int err = kbase_reg_poll64_timeout(kbdev, GPU_CONTROL_ENUM(L2_PWRTRANS), val, |