diff options
| author | Vamsidhar reddy Gaddam <gvamsi@google.com> | 2024-01-22 09:44:16 +0000 |
|---|---|---|
| committer | Vamsidhar reddy Gaddam <gvamsi@google.com> | 2024-01-22 17:16:55 +0000 |
| commit | 972efb1d89dcae35bd6a3b4bc304b31847bf03c9 (patch) | |
| tree | 7522ea04360c7e017acbdaa268f2a6e2bf9f2ad7 | |
| parent | 3c7cacbd3ea54e3b94b3f51502593cfc7530a13c (diff) | |
| download | gpu-972efb1d89dcae35bd6a3b4bc304b31847bf03c9.tar.gz | |
Use the new way to access GPU registers
R47P0 refactored the way registers are accessed causing our additional
debug logging to access invalid addresses.
Bug: 321645561
Test: Locally verified by timeout on suspend.
Change-Id: I772601c08551a92916c03b2e0d24f5f1476f6cf6
Signed-off-by: Vamsidhar reddy Gaddam <gvamsi@google.com>
| -rw-r--r-- | mali_kbase/csf/mali_kbase_csf_reset_gpu.c | 6 | ||||
| -rw-r--r-- | mali_kbase/hw_access/regmap/mali_kbase_regmap_csf.c | 4 | ||||
| -rw-r--r-- | mali_kbase/hw_access/regmap/mali_kbase_regmap_csf_enums.h | 1 |
3 files changed, 6 insertions, 5 deletions
diff --git a/mali_kbase/csf/mali_kbase_csf_reset_gpu.c b/mali_kbase/csf/mali_kbase_csf_reset_gpu.c index 53f05fb..726cee2 100644 --- a/mali_kbase/csf/mali_kbase_csf_reset_gpu.c +++ b/mali_kbase/csf/mali_kbase_csf_reset_gpu.c @@ -238,8 +238,6 @@ static void kbase_csf_reset_end_hw_access(struct kbase_device *kbdev, int err_du void kbase_csf_debug_dump_registers(struct kbase_device *kbdev) { -#define DOORBELL_CFG_BASE 0x20000 -#define MCUC_DB_VALUE_0 0x80 struct kbase_csf_global_iface *global_iface = &kbdev->csf.global_iface; kbase_io_history_dump(kbdev); @@ -269,12 +267,10 @@ void kbase_csf_debug_dump_registers(struct kbase_device *kbdev) kbase_reg_read32(kbdev, GPU_CONTROL_ENUM(TILER_CONFIG))); } - dev_err(kbdev->dev, " MCU DB0: %x", kbase_reg_read32(kbdev, DOORBELL_CFG_BASE + MCUC_DB_VALUE_0)); + dev_err(kbdev->dev, " MCU DB0: %x", kbase_reg_read32(kbdev, DEBUG_MCUC_DB_VALUE_0)); dev_err(kbdev->dev, " MCU GLB_REQ %x GLB_ACK %x", kbase_csf_firmware_global_input_read(global_iface, GLB_REQ), kbase_csf_firmware_global_output(global_iface, GLB_ACK)); -#undef MCUC_DB_VALUE_0 -#undef DOORBELL_CFG_BASE } diff --git a/mali_kbase/hw_access/regmap/mali_kbase_regmap_csf.c b/mali_kbase/hw_access/regmap/mali_kbase_regmap_csf.c index 89997e9..7e1b4a1 100644 --- a/mali_kbase/hw_access/regmap/mali_kbase_regmap_csf.c +++ b/mali_kbase/hw_access/regmap/mali_kbase_regmap_csf.c @@ -683,6 +683,8 @@ static void kbase_regmap_v10_8_init(struct kbase_device *kbdev) KBASE_REGMAP_PERM_WRITE; kbdev->regmap.flags[DOORBELL_BLOCK_63__DOORBELL] = KBASE_REGMAP_WIDTH_32_BIT | KBASE_REGMAP_PERM_WRITE; + kbdev->regmap.flags[DEBUG_MCUC_DB_VALUE_0] = + KBASE_REGMAP_WIDTH_32_BIT | KBASE_REGMAP_PERM_READ | KBASE_REGMAP_PERM_WRITE; kbdev->regmap.regs[GPU_CONTROL__GPU_ID] = kbdev->reg + 0x0; kbdev->regmap.regs[GPU_CONTROL__L2_FEATURES] = kbdev->reg + 0x4; @@ -1003,6 +1005,7 @@ static void kbase_regmap_v10_8_init(struct kbase_device *kbdev) kbdev->regmap.regs[DOORBELL_BLOCK_61__DOORBELL] = kbdev->reg + 0x450000; kbdev->regmap.regs[DOORBELL_BLOCK_62__DOORBELL] = kbdev->reg + 0x460000; kbdev->regmap.regs[DOORBELL_BLOCK_63__DOORBELL] = kbdev->reg + 0x470000; + kbdev->regmap.regs[DEBUG_MCUC_DB_VALUE_0] = kbdev->reg + 0x20080; } static void kbase_regmap_v10_10_init(struct kbase_device *kbdev) @@ -1514,6 +1517,7 @@ static char *enum_strings[] = { [GPU_CONTROL__GPU_COMMAND_ARG1] = "GPU_CONTROL__GPU_COMMAND_ARG1", [GPU_CONTROL__MCU_FEATURES] = "GPU_CONTROL__MCU_FEATURES", [GPU_CONTROL__SHADER_PWRFEATURES] = "GPU_CONTROL__SHADER_PWRFEATURES", + [DEBUG_MCUC_DB_VALUE_0] = "DEBUG_MCUC_DB_VALUE_0", }; const char *kbase_reg_get_enum_string(u32 reg_enum) diff --git a/mali_kbase/hw_access/regmap/mali_kbase_regmap_csf_enums.h b/mali_kbase/hw_access/regmap/mali_kbase_regmap_csf_enums.h index e05af18..b030ffe 100644 --- a/mali_kbase/hw_access/regmap/mali_kbase_regmap_csf_enums.h +++ b/mali_kbase/hw_access/regmap/mali_kbase_regmap_csf_enums.h @@ -351,6 +351,7 @@ enum kbase_regmap_enum_v10_8 { DOORBELL_BLOCK_61__DOORBELL, /* (WO) 32-bit 0x450000 */ DOORBELL_BLOCK_62__DOORBELL, /* (WO) 32-bit 0x460000 */ DOORBELL_BLOCK_63__DOORBELL, /* (WO) 32-bit 0x470000 */ + DEBUG_MCUC_DB_VALUE_0, /* (RO) 32-bit 0x20080 */ NR_V10_8_REGS, }; |