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| author | Sidath Senanayake <sidaths@google.com> | 2018-12-06 09:09:59 +0100 |
|---|---|---|
| committer | Sidath Senanayake <sidaths@google.com> | 2018-12-06 09:09:59 +0100 |
| commit | a970431fa55f99aba31ea4263fdc8e70019a9ccd (patch) | |
| tree | 91bb7f49a4869c0385338fe144f53ac8b98468ea /mali_kbase/backend/gpu/mali_kbase_pm_ca.c | |
| parent | f10b3de5283d0c196459f18160161e48cfadae81 (diff) | |
| download | gpu-a970431fa55f99aba31ea4263fdc8e70019a9ccd.tar.gz | |
Mali Bifrost DDK r16p0 KMD
Provenance:
aa8b3ff0f (collaborate/EAC/b_r16p0)
BX304L01B-BU-00000-r16p0-01rel0
BX304L06A-BU-00000-r16p0-01rel0
BX304X07X-BU-00000-r16p0-01rel0
Signed-off-by: Sidath Senanayake <sidaths@google.com>
Change-Id: I96125862b7cf6596d1b7109853fb4ca39e851056
Diffstat (limited to 'mali_kbase/backend/gpu/mali_kbase_pm_ca.c')
| -rw-r--r-- | mali_kbase/backend/gpu/mali_kbase_pm_ca.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/mali_kbase/backend/gpu/mali_kbase_pm_ca.c b/mali_kbase/backend/gpu/mali_kbase_pm_ca.c index d4e8e42..2cb9452 100644 --- a/mali_kbase/backend/gpu/mali_kbase_pm_ca.c +++ b/mali_kbase/backend/gpu/mali_kbase_pm_ca.c @@ -30,15 +30,15 @@ int kbase_pm_ca_init(struct kbase_device *kbdev) { - struct kbase_pm_backend_data *pm_backend = &kbdev->pm.backend; #ifdef CONFIG_MALI_DEVFREQ + struct kbase_pm_backend_data *pm_backend = &kbdev->pm.backend; + if (kbdev->current_core_mask) pm_backend->ca_cores_enabled = kbdev->current_core_mask; else pm_backend->ca_cores_enabled = kbdev->gpu_props.props.raw_props.shader_present; #endif - pm_backend->ca_in_transition = false; return 0; } @@ -55,10 +55,17 @@ void kbase_devfreq_set_core_mask(struct kbase_device *kbdev, u64 core_mask) spin_lock_irqsave(&kbdev->hwaccess_lock, flags); + if (!(core_mask & kbdev->pm.debug_core_mask_all)) { + dev_err(kbdev->dev, "OPP core mask 0x%llX does not intersect with debug mask 0x%llX\n", + core_mask, kbdev->pm.debug_core_mask_all); + goto unlock; + } + pm_backend->ca_cores_enabled = core_mask; - kbase_pm_update_cores_state_nolock(kbdev); + kbase_pm_update_state(kbdev); +unlock: spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags); dev_dbg(kbdev->dev, "Devfreq policy : new core mask=%llX\n", @@ -89,19 +96,12 @@ KBASE_EXPORT_TEST_API(kbase_pm_ca_get_core_mask); void kbase_pm_ca_instr_enable(struct kbase_device *kbdev) { - unsigned long flags; - - spin_lock_irqsave(&kbdev->hwaccess_lock, flags); + lockdep_assert_held(&kbdev->hwaccess_lock); kbdev->pm.backend.instr_enabled = true; - - kbase_pm_update_cores_state_nolock(kbdev); - spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags); } void kbase_pm_ca_instr_disable(struct kbase_device *kbdev) { lockdep_assert_held(&kbdev->hwaccess_lock); kbdev->pm.backend.instr_enabled = false; - - kbase_pm_update_cores_state_nolock(kbdev); } |