diff options
| author | Varad Gautam <varadgautam@google.com> | 2023-01-09 13:11:50 +0000 |
|---|---|---|
| committer | TreeHugger Robot <treehugger-gerrit@google.com> | 2023-03-23 22:45:01 +0000 |
| commit | 8141064fa8984d1b2d25b9c4a84b5e5b7916b83b (patch) | |
| tree | 9adcdf9a5074547b525557a9305ec4b957018a51 /mali_kbase/backend | |
| parent | c79291e74ddfb1b157e18e9f698752e61357b348 (diff) | |
| download | gpu-8141064fa8984d1b2d25b9c4a84b5e5b7916b83b.tar.gz | |
Powercycle mali to recover from a PM timeout
The existing reset flow (kbase_pm_do_reset()) is:
1. Write to SOFT_RESET and wait for irq until timeout.
2. If RESET_COMPLETED irq timed out, write to HARD_RESET and wait for
irq until timeout.
3. If RESET_COMPLETED irq timed out, powercycle the GPU via
kbase_pm_hw_reset().
If a power transition timed out (ie, kbase_pm_timed_out()), writing to
SOFT/HARD_RESET regs is unreliable and can send the GPU into an
undefined state (eg, when writing to SOFT/HARD_RESET regs if L2 is
transitioning) and prevent recovery.
Introduce a RESET_FLAGS_FORCE_PM_HW_RESET flag to allow resetting the
GPU via powercycle, which currently only happens when soft/hard reset
both fail, and use only this method to reset the GPU from
kbase_pm_timed_out().
Note: Originally pushed as pa/Ic57680225, re-merge this patch per
go/p22-udc-gfx-rollout
kbase upstreaming: WIP: b/243522189#comment23
Change-Id: I5b8ca3b9e49cf355f665c0b56061e06ef3ed9e0b
Signed-off-by: Varad Gautam <varadgautam@google.com>
Bug: 241217496
Bug: 270305834
Test: (v2) SST ~5700h (b/271438225#comment14) / (v1) SST ~2500h (b/265003962)
Diffstat (limited to 'mali_kbase/backend')
| -rw-r--r-- | mali_kbase/backend/gpu/mali_kbase_pm_driver.c | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/mali_kbase/backend/gpu/mali_kbase_pm_driver.c b/mali_kbase/backend/gpu/mali_kbase_pm_driver.c index b046903..2bfc27a 100644 --- a/mali_kbase/backend/gpu/mali_kbase_pm_driver.c +++ b/mali_kbase/backend/gpu/mali_kbase_pm_driver.c @@ -2421,8 +2421,22 @@ static void kbase_pm_timed_out(struct kbase_device *kbdev) dev_err(kbdev->dev, "Power transition timed out unexpectedly\n"); kbase_gpu_timeout_debug_message(kbdev); dev_err(kbdev->dev, "Sending reset to GPU - all running jobs will be lost\n"); + + /* pixel: If either: + * 1. L2/MCU power transition timed out, or, + * 2. kbase state machine fell out of sync with the hw state, + * a soft/hard reset (ie writing to SOFT/HARD_RESET regs) is insufficient to resume + * operation. + * + * Besides, Odin TRM advises against touching SOFT/HARD_RESET + * regs if L2_PWRTRANS is 1 to avoid undefined state. + * + * We have already lost work if we end up here, so send a powercycle to reset the hw, + * which is more reliable. + */ if (kbase_prepare_to_reset_gpu(kbdev, - RESET_FLAGS_HWC_UNRECOVERABLE_ERROR)) + RESET_FLAGS_HWC_UNRECOVERABLE_ERROR | + RESET_FLAGS_FORCE_PM_HW_RESET)) kbase_reset_gpu(kbdev); } @@ -3179,6 +3193,14 @@ static int kbase_pm_do_reset(struct kbase_device *kbdev) struct kbasep_reset_timeout_data rtdata; int ret; +#if MALI_USE_CSF + if (kbdev->csf.reset.force_pm_hw_reset && kbdev->pm.backend.callback_hardware_reset) { + dev_err(kbdev->dev, "Power Cycle reset mali"); + kbdev->csf.reset.force_pm_hw_reset = false; + return kbase_pm_hw_reset(kbdev); + } +#endif + KBASE_KTRACE_ADD(kbdev, CORE_GPU_SOFT_RESET, NULL, 0); KBASE_TLSTREAM_JD_GPU_SOFT_RESET(kbdev, kbdev); |