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| author | Sidath Senanayake <sidaths@google.com> | 2019-04-10 14:37:00 +0200 |
|---|---|---|
| committer | Sidath Senanayake <sidaths@google.com> | 2019-04-10 14:37:00 +0200 |
| commit | e972f6531ef8c9d01eae567f52db4f0fd37d1428 (patch) | |
| tree | 52df0c2e2665e00e4fe5822ddb50df1a72e24cd0 /mali_kbase/mali_kbase_hw.c | |
| parent | a970431fa55f99aba31ea4263fdc8e70019a9ccd (diff) | |
| download | gpu-e972f6531ef8c9d01eae567f52db4f0fd37d1428.tar.gz | |
Mali Bifrost DDK r17p0 KMD
Provenance:
789dfe7c7 (collaborate/EAC/b_r17p0)
BX304L01B-BU-00000-r17p0-01rel0
BX304L06A-BU-00000-r17p0-01rel0
BX304X07X-BU-00000-r17p0-01rel0
Signed-off-by: Sidath Senanayake <sidaths@google.com>
Change-Id: Iff5bea2d96207a6e72d5e533e772c24a7adbdc31
Diffstat (limited to 'mali_kbase/mali_kbase_hw.c')
| -rw-r--r-- | mali_kbase/mali_kbase_hw.c | 27 |
1 files changed, 26 insertions, 1 deletions
diff --git a/mali_kbase/mali_kbase_hw.c b/mali_kbase/mali_kbase_hw.c index 450926c..1503469 100644 --- a/mali_kbase/mali_kbase_hw.c +++ b/mali_kbase/mali_kbase_hw.c @@ -1,6 +1,6 @@ /* * - * (C) COPYRIGHT 2012-2018 ARM Limited. All rights reserved. + * (C) COPYRIGHT 2012-2019 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the * GNU General Public License version 2 as published by the Free Software @@ -80,6 +80,9 @@ void kbase_hw_set_features_mask(struct kbase_device *kbdev) case GPU_ID2_PRODUCT_TULX: features = base_hw_features_tULx; break; + case GPU_ID2_PRODUCT_TDUX: + features = base_hw_features_tDUx; + break; case GPU_ID2_PRODUCT_TBOX: features = base_hw_features_tBOx; break; @@ -126,6 +129,19 @@ void kbase_hw_set_features_mask(struct kbase_device *kbdev) for (; *features != BASE_HW_FEATURE_END; features++) set_bit(*features, &kbdev->hw_features_mask[0]); + +#if defined(CONFIG_MALI_JOB_DUMP) || defined(CONFIG_MALI_VECTOR_DUMP) + /* When dumping is enabled, need to disable flush reduction optimization + * for GPUs on which it is safe to have only cache clean operation at + * the end of job chain. + * This is required to make job dumping work. There is some discrepancy + * in the implementation of flush reduction optimization due to + * unclear or ambiguous ARCH spec. + */ + if (kbase_hw_has_feature(kbdev, BASE_HW_FEATURE_CLEAN_ONLY_SAFE)) + clear_bit(BASE_HW_FEATURE_FLUSH_REDUCTION, + &kbdev->hw_features_mask[0]); +#endif } /** @@ -207,10 +223,12 @@ static const enum base_hw_issue *kbase_hw_get_issues_for_new_id( {GPU_ID2_PRODUCT_TTRX, {{GPU_ID2_VERSION_MAKE(0, 0, 0), base_hw_issues_tTRx_r0p0}, + {GPU_ID2_VERSION_MAKE(0, 0, 3), base_hw_issues_tTRx_r0p0}, {U32_MAX, NULL} } }, {GPU_ID2_PRODUCT_TNAX, {{GPU_ID2_VERSION_MAKE(0, 0, 0), base_hw_issues_tNAx_r0p0}, + {GPU_ID2_VERSION_MAKE(0, 0, 3), base_hw_issues_tNAx_r0p0}, {U32_MAX, NULL} } }, {GPU_ID2_PRODUCT_TBEX, @@ -221,6 +239,10 @@ static const enum base_hw_issue *kbase_hw_get_issues_for_new_id( {{GPU_ID2_VERSION_MAKE(0, 0, 0), base_hw_issues_tULx_r0p0}, {U32_MAX, NULL} } }, + {GPU_ID2_PRODUCT_TDUX, + {{GPU_ID2_VERSION_MAKE(0, 0, 0), base_hw_issues_tDUx_r0p0}, + {U32_MAX, NULL} } }, + {GPU_ID2_PRODUCT_TBOX, {{GPU_ID2_VERSION_MAKE(0, 0, 0), base_hw_issues_tBOx_r0p0}, {U32_MAX, NULL} } }, @@ -479,6 +501,9 @@ int kbase_hw_set_issues_mask(struct kbase_device *kbdev) case GPU_ID2_PRODUCT_TULX: issues = base_hw_issues_model_tULx; break; + case GPU_ID2_PRODUCT_TDUX: + issues = base_hw_issues_model_tDUx; + break; case GPU_ID2_PRODUCT_TBOX: issues = base_hw_issues_model_tBOx; break; |