diff options
| author | Jack Diver <diverj@google.com> | 2022-07-29 13:55:47 +0000 |
|---|---|---|
| committer | Jeremy Kemp <jeremykemp@google.com> | 2022-08-25 08:54:12 +0100 |
| commit | 1d2c310881826a7ddd94575a3bbbf2e484910be9 (patch) | |
| tree | 428c3d9045b039ebfda6a9b8dab95fefe68dd5a7 /mali_kbase/platform | |
| parent | db6b7b2a7c2fd649d7e9aabe5c358851240b84db (diff) | |
| download | gpu-1d2c310881826a7ddd94575a3bbbf2e484910be9.tar.gz | |
platform: Add STACKS PDCs to mali SSR
Bug: 156051622
Signed-off-by: Jack Diver <diverj@google.com>
Change-Id: If156d077e4267cfc19a6c3ef85b00a7018c3e73f
Diffstat (limited to 'mali_kbase/platform')
| -rw-r--r-- | mali_kbase/platform/pixel/pixel_gpu_debug.c | 41 | ||||
| -rw-r--r-- | mali_kbase/platform/pixel/pixel_gpu_debug.h | 2 |
2 files changed, 29 insertions, 14 deletions
diff --git a/mali_kbase/platform/pixel/pixel_gpu_debug.c b/mali_kbase/platform/pixel/pixel_gpu_debug.c index d969098..34b7c2c 100644 --- a/mali_kbase/platform/pixel/pixel_gpu_debug.c +++ b/mali_kbase/platform/pixel/pixel_gpu_debug.c @@ -13,6 +13,7 @@ #include "pixel_gpu_debug.h" #define GPU_DBG_LO 0x00000FE8 +#define PIXEL_STACK_PDC_ADDR 0x000770DB #define PIXEL_CG_PDC_ADDR 0x000760DB #define PIXEL_SC_PDC_ADDR 0x000740DB #define GPU_DBG_ACTIVE_BIT (1 << 31) @@ -52,14 +53,32 @@ static u32 gpu_debug_read_pdc(struct kbase_device *kbdev, u32 pdc_offset) return kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_DBG_LO)); } -void gpu_debug_read_pdc_status(struct kbase_device *kbdev, struct pixel_gpu_pdc_status *status) +static void gpu_debug_read_sparse_pdcs(struct kbase_device *kbdev, u32 *out, u64 available, + u64 offset, u64 logical_max) { int sparse_idx, logical_idx = 0; + + for (sparse_idx = 0; sparse_idx < BITS_PER_TYPE(u64) && logical_idx < logical_max; ++sparse_idx) { + /* Skip if we don't have this core in our configuration */ + if (!(available & BIT_ULL(sparse_idx))) + continue; + + /* GPU debug command expects the sparse core index */ + out[logical_idx] = gpu_debug_read_pdc(kbdev, offset + sparse_idx); + + ++logical_idx; + } +} + +void gpu_debug_read_pdc_status(struct kbase_device *kbdev, struct pixel_gpu_pdc_status *status) +{ + struct gpu_raw_gpu_props *raw_props; + lockdep_assert_held(&kbdev->hwaccess_lock); status->meta = (struct pixel_gpu_pdc_status_metadata) { .magic = "pdcs", - .version = 1, + .version = 2, }; /* If there's no external power we skip the register read/writes, @@ -70,17 +89,11 @@ void gpu_debug_read_pdc_status(struct kbase_device *kbdev, struct pixel_gpu_pdc_ return; } - status->state.core_group = gpu_debug_read_pdc(kbdev, PIXEL_CG_PDC_ADDR); - - for (sparse_idx = 0; sparse_idx < BITS_PER_TYPE(u64) && logical_idx < PIXEL_MALI_SC_COUNT; ++sparse_idx) { - /* Skip if we don't have this core in our configuration */ - if (!(kbdev->pm.backend.shaders_avail & BIT_ULL(sparse_idx))) - continue; + raw_props = &kbdev->gpu_props.props.raw_props; - /* GPU debug command expects the sparse core index */ - status->state.shader_cores[logical_idx] = - gpu_debug_read_pdc(kbdev, PIXEL_SC_PDC_ADDR + sparse_idx); - - ++logical_idx; - } + status->state.core_group = gpu_debug_read_pdc(kbdev, PIXEL_CG_PDC_ADDR); + gpu_debug_read_sparse_pdcs(kbdev, status->state.shader_cores, raw_props->shader_present, + PIXEL_SC_PDC_ADDR, PIXEL_MALI_SC_COUNT); + gpu_debug_read_sparse_pdcs(kbdev, status->state.stacks, raw_props->stack_present, + PIXEL_STACK_PDC_ADDR, PIXEL_MALI_STACK_COUNT); } diff --git a/mali_kbase/platform/pixel/pixel_gpu_debug.h b/mali_kbase/platform/pixel/pixel_gpu_debug.h index 290b78e..c4bcd4a 100644 --- a/mali_kbase/platform/pixel/pixel_gpu_debug.h +++ b/mali_kbase/platform/pixel/pixel_gpu_debug.h @@ -10,6 +10,7 @@ /* This is currently only supported for Odin */ #define PIXEL_MALI_SC_COUNT 0x7 +#define PIXEL_MALI_STACK_COUNT 0x3 /** * enum pixel_gpu_pdc_state - PDC internal state @@ -112,6 +113,7 @@ struct pixel_gpu_pdc_status { struct { uint32_t core_group; uint32_t shader_cores[PIXEL_MALI_SC_COUNT]; + uint32_t stacks[PIXEL_MALI_STACK_COUNT]; } state; } __attribute__((packed)); |