diff options
85 files changed, 1998 insertions, 7450 deletions
diff --git a/common/include/linux/memory_group_manager.h b/common/include/linux/memory_group_manager.h index 8b19786..b1ac253 100644 --- a/common/include/linux/memory_group_manager.h +++ b/common/include/linux/memory_group_manager.h @@ -23,16 +23,28 @@ #ifndef _MEMORY_GROUP_MANAGER_H_ #define _MEMORY_GROUP_MANAGER_H_ +#include <linux/mm.h> +#include <linux/of.h> +#include <linux/version.h> + +#if (KERNEL_VERSION(4, 17, 0) > LINUX_VERSION_CODE) +typedef int vm_fault_t; +#endif + #define MEMORY_GROUP_MANAGER_NR_GROUPS (16) struct memory_group_manager_device; +struct memory_group_manager_import_data; /** * struct memory_group_manager_ops - Callbacks for memory group manager * operations * - * @mgm_alloc_page: Callback to allocate physical memory in a group - * @mgm_free_page: Callback to free physical memory in a group + * @mgm_alloc_page: Callback to allocate physical memory in a group + * @mgm_free_page: Callback to free physical memory in a group + * @mgm_get_import_memory_id: Callback to get the group ID for imported memory + * @mgm_update_gpu_pte: Callback to modify a GPU page table entry + * @mgm_vmf_insert_pfn_prot: Callback to map a physical memory page for the CPU */ struct memory_group_manager_ops { /** @@ -72,6 +84,75 @@ struct memory_group_manager_ops { void (*mgm_free_page)( struct memory_group_manager_device *mgm_dev, int group_id, struct page *page, unsigned int order); + + /** + * mgm_get_import_memory_id - Get the physical memory group ID for the + * imported memory + * + * @mgm_dev: The memory group manager through which the request + * is being made. + * @import_data: Pointer to the data which describes imported memory. + * + * Note that provision of this call back is optional, where it is not + * provided this call back pointer must be set to NULL to indicate it + * is not in use. + * + * Return: The memory group ID to use when mapping pages from this + * imported memory. + */ + int (*mgm_get_import_memory_id)( + struct memory_group_manager_device *mgm_dev, + struct memory_group_manager_import_data *import_data); + + /** + * mgm_update_gpu_pte - Modify a GPU page table entry for a memory group + * + * @mgm_dev: The memory group manager through which the request + * is being made. + * @group_id: A physical memory group ID. The meaning of this is + * defined by the systems integrator. Its valid range is + * 0 .. MEMORY_GROUP_MANAGER_NR_GROUPS-1. + * @mmu_level: The level of the page table entry in @ate. + * @pte: The page table entry to modify, in LPAE or AArch64 format + * (depending on the driver's configuration). This should be + * decoded to determine the physical address and any other + * properties of the mapping the manager requires. + * + * This function allows the memory group manager to modify a GPU page + * table entry before it is stored by the kbase module (controller + * driver). It may set certain bits in the page table entry attributes + * or in the physical address, based on the physical memory group ID. + * + * Return: A modified GPU page table entry to be stored in a page table. + */ + u64 (*mgm_update_gpu_pte)(struct memory_group_manager_device *mgm_dev, + int group_id, int mmu_level, u64 pte); + + /** + * mgm_vmf_insert_pfn_prot - Map a physical page in a group for the CPU + * + * @mgm_dev: The memory group manager through which the request + * is being made. + * @group_id: A physical memory group ID. The meaning of this is + * defined by the systems integrator. Its valid range is + * 0 .. MEMORY_GROUP_MANAGER_NR_GROUPS-1. + * @vma: The virtual memory area to insert the page into. + * @addr: A virtual address (in @vma) to assign to the page. + * @pfn: The kernel Page Frame Number to insert at @addr in @vma. + * @pgprot: Protection flags for the inserted page. + * + * Called from a CPU virtual memory page fault handler. This function + * creates a page table entry from the given parameter values and stores + * it at the appropriate location (unlike mgm_update_gpu_pte, which + * returns a modified entry). + * + * Return: Type of fault that occurred or VM_FAULT_NOPAGE if the page + * table entry was successfully installed. + */ + vm_fault_t (*mgm_vmf_insert_pfn_prot)( + struct memory_group_manager_device *mgm_dev, int group_id, + struct vm_area_struct *vma, unsigned long addr, + unsigned long pfn, pgprot_t pgprot); }; /** @@ -91,6 +172,27 @@ struct memory_group_manager_ops { struct memory_group_manager_device { struct memory_group_manager_ops ops; void *data; + struct module *owner; +}; + + +enum memory_group_manager_import_type { + MEMORY_GROUP_MANAGER_IMPORT_TYPE_DMA_BUF +}; + +/** + * struct memory_group_manager_import_data - Structure describing the imported + * memory + * + * @type - type of imported memory + * @u - Union describing the imported memory + * + */ +struct memory_group_manager_import_data { + enum memory_group_manager_import_type type; + union { + struct dma_buf *dma_buf; + } u; }; #endif /* _MEMORY_GROUP_MANAGER_H_ */ diff --git a/mali_kbase/Kbuild b/mali_kbase/Kbuild index 0ec3721..75fcaba 100644 --- a/mali_kbase/Kbuild +++ b/mali_kbase/Kbuild @@ -1,5 +1,5 @@ # -# (C) COPYRIGHT 2012-2019 ARM Limited. All rights reserved. +# (C) COPYRIGHT 2012-2018 ARM Limited. All rights reserved. # # This program is free software and is provided to you under the terms of the # GNU General Public License version 2 as published by the Free Software @@ -21,7 +21,7 @@ # Driver version string which is returned to userspace via an ioctl -MALI_RELEASE_NAME ?= "r18p0-01rel0" +MALI_RELEASE_NAME ?= "r19p0-01rel0" # Paths required for build KBASE_PATH = $(src) @@ -35,8 +35,6 @@ MALI_UNIT_TEST ?= 0 MALI_KERNEL_TEST_API ?= 0 MALI_COVERAGE ?= 0 CONFIG_MALI_PLATFORM_NAME ?= "devicetree" -# MALI_CSF_LT_V10: Temporary for hybrid integration config -MALI_CSF_LT_V10 ?= 0 # Set up our defines, which will be passed to gcc DEFINES = \ @@ -45,7 +43,6 @@ DEFINES = \ -DMALI_KERNEL_TEST_API=$(MALI_KERNEL_TEST_API) \ -DMALI_UNIT_TEST=$(MALI_UNIT_TEST) \ -DMALI_COVERAGE=$(MALI_COVERAGE) \ - -DMALI_CSF_LT_V10=$(MALI_CSF_LT_V10) \ -DMALI_RELEASE_NAME=\"$(MALI_RELEASE_NAME)\" ifeq ($(KBUILD_EXTMOD),) @@ -96,12 +93,10 @@ SRC := \ mali_kbase_gpu_memory_debugfs.c \ mali_kbase_mem_linux.c \ mali_kbase_core_linux.c \ - mali_kbase_replay.c \ mali_kbase_mem_profile_debugfs.c \ mali_kbase_mmu_mode_lpae.c \ mali_kbase_mmu_mode_aarch64.c \ mali_kbase_disjoint_events.c \ - mali_kbase_gator_api.c \ mali_kbase_debug_mem_view.c \ mali_kbase_debug_job_fault.c \ mali_kbase_smc.c \ diff --git a/mali_kbase/Kconfig b/mali_kbase/Kconfig index 6a7d935..3d93aaa 100644 --- a/mali_kbase/Kconfig +++ b/mali_kbase/Kconfig @@ -156,6 +156,9 @@ config MALI_NO_MALI All calls to the simulated hardware will complete immediately as if the hardware completed the task. +config MALI_REAL_HW + def_bool !MALI_NO_MALI + config MALI_ERROR_INJECT bool "Error injection" depends on MALI_MIDGARD && MALI_EXPERT && MALI_NO_MALI @@ -208,7 +211,7 @@ config MALI_MEMORY_FULLY_BACKED config MALI_DMA_BUF_MAP_ON_DEMAND bool "Map imported dma-bufs on demand" - depends on DMA_SHARED_BUFFER && MALI_MIDGARD && MALI_EXPERT + depends on DMA_SHARED_BUFFER && MALI_MIDGARD default n help This option caused kbase to set up the GPU mapping of imported @@ -220,7 +223,7 @@ config MALI_DMA_BUF_MAP_ON_DEMAND config MALI_DMA_BUF_LEGACY_COMPAT bool "Enable legacy compatibility cache flush on dma-buf map" depends on MALI_MIDGARD && !MALI_DMA_BUF_MAP_ON_DEMAND - default n + default y help This option enables compatibility with legacy dma-buf mapping behavior, then the dma-buf is mapped on import, by adding cache diff --git a/mali_kbase/Mconfig b/mali_kbase/Mconfig index d0e78a2..60cb2a3 100644 --- a/mali_kbase/Mconfig +++ b/mali_kbase/Mconfig @@ -227,13 +227,18 @@ config MALI_DMA_BUF_MAP_ON_DEMAND config MALI_DMA_BUF_LEGACY_COMPAT bool "Enable legacy compatibility cache flush on dma-buf map" depends on MALI_MIDGARD && !MALI_DMA_BUF_MAP_ON_DEMAND - default n + default y help This option enables compatibility with legacy dma-buf mapping behavior, then the dma-buf is mapped on import, by adding cache maintenance where MALI_DMA_BUF_MAP_ON_DEMAND would do the mapping, including a cache flush. +config MALI_REAL_HW + bool + default y + default n if NO_MALI + # Instrumentation options. # config MALI_JOB_DUMP exists in the Kernel Kconfig but is configured using CINSTR_JOB_DUMP in Mconfig. diff --git a/mali_kbase/backend/gpu/mali_kbase_devfreq.c b/mali_kbase/backend/gpu/mali_kbase_devfreq.c index 8e8ac04..4e87c6a 100644 --- a/mali_kbase/backend/gpu/mali_kbase_devfreq.c +++ b/mali_kbase/backend/gpu/mali_kbase_devfreq.c @@ -22,7 +22,6 @@ #include <mali_kbase.h> #include <mali_kbase_tracepoints.h> -#include <mali_kbase_config_defaults.h> #include <backend/gpu/mali_kbase_pm_internal.h> #include <linux/of.h> @@ -54,29 +53,42 @@ * @kbdev: Device pointer * @freq: Nominal frequency * @core_mask: Pointer to u64 to store core mask to - * - * Return: Real target frequency + * @freqs: Pointer to array of frequencies + * @volts: Pointer to array of voltages * * This function will only perform translation if an operating-points-v2-mali * table is present in devicetree. If one is not present then it will return an * untranslated frequency and all cores enabled. */ -static unsigned long opp_translate(struct kbase_device *kbdev, - unsigned long freq, u64 *core_mask) +static void opp_translate(struct kbase_device *kbdev, unsigned long freq, + u64 *core_mask, unsigned long *freqs, unsigned long *volts) { - int i; + unsigned int i; for (i = 0; i < kbdev->num_opps; i++) { - if (kbdev->opp_table[i].opp_freq == freq) { - *core_mask = kbdev->opp_table[i].core_mask; - return kbdev->opp_table[i].real_freq; + if (kbdev->devfreq_table[i].opp_freq == freq) { + unsigned int j; + + *core_mask = kbdev->devfreq_table[i].core_mask; + for (j = 0; j < kbdev->nr_clocks; j++) { + freqs[j] = + kbdev->devfreq_table[i].real_freqs[j]; + volts[j] = + kbdev->devfreq_table[i].opp_volts[j]; + } + + break; } } - /* Failed to find OPP - return all cores enabled & nominal frequency */ - *core_mask = kbdev->gpu_props.props.raw_props.shader_present; - - return freq; + /* If failed to find OPP, return all cores enabled + * and nominal frequency + */ + if (i == kbdev->num_opps) { + *core_mask = kbdev->gpu_props.props.raw_props.shader_present; + for (i = 0; i < kbdev->nr_clocks; i++) + freqs[i] = freq; + } } static int @@ -85,18 +97,17 @@ kbase_devfreq_target(struct device *dev, unsigned long *target_freq, u32 flags) struct kbase_device *kbdev = dev_get_drvdata(dev); struct dev_pm_opp *opp; unsigned long nominal_freq; - unsigned long freq = 0; - unsigned long voltage; - int err; + unsigned long freqs[BASE_MAX_NR_CLOCKS_REGULATORS] = {0}; + unsigned long volts[BASE_MAX_NR_CLOCKS_REGULATORS] = {0}; + unsigned int i; u64 core_mask; - freq = *target_freq; + nominal_freq = *target_freq; #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 11, 0) rcu_read_lock(); #endif - opp = devfreq_recommended_opp(dev, &freq, flags); - voltage = dev_pm_opp_get_voltage(opp); + opp = devfreq_recommended_opp(dev, &nominal_freq, flags); #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 11, 0) rcu_read_unlock(); #endif @@ -108,8 +119,6 @@ kbase_devfreq_target(struct device *dev, unsigned long *target_freq, u32 flags) dev_pm_opp_put(opp); #endif - nominal_freq = freq; - /* * Only update if there is a change of frequency */ @@ -118,32 +127,72 @@ kbase_devfreq_target(struct device *dev, unsigned long *target_freq, u32 flags) return 0; } - freq = opp_translate(kbdev, nominal_freq, &core_mask); + opp_translate(kbdev, nominal_freq, &core_mask, freqs, volts); + #ifdef CONFIG_REGULATOR - if (kbdev->regulator && kbdev->current_voltage != voltage - && kbdev->current_freq < freq) { - err = regulator_set_voltage(kbdev->regulator, voltage, voltage); - if (err) { - dev_err(dev, "Failed to increase voltage (%d)\n", err); - return err; + /* Regulators and clocks work in pairs: every clock has a regulator, + * and we never expect to have more regulators than clocks. + * + * We always need to increase the voltage before increasing + * the frequency of a regulator/clock pair, otherwise the clock + * wouldn't have enough power to perform the transition. + * + * It's always safer to decrease the frequency before decreasing + * voltage of a regulator/clock pair, otherwise the clock could have + * problems operating if it is deprived of the necessary power + * to sustain its current frequency (even if that happens for a short + * transition interval). + */ + for (i = 0; i < kbdev->nr_clocks; i++) { + if (kbdev->regulators[i] && + kbdev->current_voltages[i] != volts[i] && + kbdev->current_freqs[i] < freqs[i]) { + int err; + + err = regulator_set_voltage(kbdev->regulators[i], + volts[i], volts[i]); + if (!err) { + kbdev->current_voltages[i] = volts[i]; + } else { + dev_err(dev, "Failed to increase voltage (%d) (target %lu)\n", + err, volts[i]); + return err; + } } } #endif - err = clk_set_rate(kbdev->clock, freq); - if (err) { - dev_err(dev, "Failed to set clock %lu (target %lu)\n", - freq, *target_freq); - return err; + for (i = 0; i < kbdev->nr_clocks; i++) { + if (kbdev->clocks[i]) { + int err; + + err = clk_set_rate(kbdev->clocks[i], freqs[i]); + if (!err) { + kbdev->current_freqs[i] = freqs[i]; + } else { + dev_err(dev, "Failed to set clock %lu (target %lu)\n", + freqs[i], *target_freq); + return err; + } + } } #ifdef CONFIG_REGULATOR - if (kbdev->regulator && kbdev->current_voltage != voltage - && kbdev->current_freq > freq) { - err = regulator_set_voltage(kbdev->regulator, voltage, voltage); - if (err) { - dev_err(dev, "Failed to decrease voltage (%d)\n", err); - return err; + for (i = 0; i < kbdev->nr_clocks; i++) { + if (kbdev->regulators[i] && + kbdev->current_voltages[i] != volts[i] && + kbdev->current_freqs[i] > freqs[i]) { + int err; + + err = regulator_set_voltage(kbdev->regulators[i], + volts[i], volts[i]); + if (!err) { + kbdev->current_voltages[i] = volts[i]; + } else { + dev_err(dev, "Failed to decrease voltage (%d) (target %lu)\n", + err, volts[i]); + return err; + } } } #endif @@ -151,14 +200,12 @@ kbase_devfreq_target(struct device *dev, unsigned long *target_freq, u32 flags) kbase_devfreq_set_core_mask(kbdev, core_mask); *target_freq = nominal_freq; - kbdev->current_voltage = voltage; kbdev->current_nominal_freq = nominal_freq; - kbdev->current_freq = freq; kbdev->current_core_mask = core_mask; KBASE_TLSTREAM_AUX_DEVFREQ_TARGET(kbdev, (u64)nominal_freq); - return err; + return 0; } static int @@ -238,11 +285,16 @@ static int kbase_devfreq_init_freq_table(struct kbase_device *kbdev, static void kbase_devfreq_term_freq_table(struct kbase_device *kbdev) { - struct devfreq_dev_profile *dp = kbdev->devfreq->profile; + struct devfreq_dev_profile *dp = &kbdev->devfreq_profile; kfree(dp->freq_table); } +static void kbase_devfreq_term_core_mask_table(struct kbase_device *kbdev) +{ + kfree(kbdev->devfreq_table); +} + static void kbase_devfreq_exit(struct device *dev) { struct kbase_device *kbdev = dev_get_drvdata(dev); @@ -252,6 +304,16 @@ static void kbase_devfreq_exit(struct device *dev) static int kbase_devfreq_init_core_mask_table(struct kbase_device *kbdev) { +#if KERNEL_VERSION(3, 18, 0) > LINUX_VERSION_CODE || !defined(CONFIG_OF) + /* OPP table initialization requires at least the capability to get + * regulators and clocks from the device tree, as well as parsing + * arrays of unsigned integer values. + * + * The whole initialization process shall simply be skipped if the + * minimum capability is not available. + */ + return 0; +#else struct device_node *opp_node = of_parse_phandle(kbdev->dev->of_node, "operating-points-v2", 0); struct device_node *node; @@ -265,22 +327,50 @@ static int kbase_devfreq_init_core_mask_table(struct kbase_device *kbdev) return 0; count = dev_pm_opp_get_opp_count(kbdev->dev); - kbdev->opp_table = kmalloc_array(count, + kbdev->devfreq_table = kmalloc_array(count, sizeof(struct kbase_devfreq_opp), GFP_KERNEL); - if (!kbdev->opp_table) + if (!kbdev->devfreq_table) return -ENOMEM; for_each_available_child_of_node(opp_node, node) { - u64 core_mask; - u64 opp_freq, real_freq; const void *core_count_p; + u64 core_mask, opp_freq, + real_freqs[BASE_MAX_NR_CLOCKS_REGULATORS]; + int err; +#ifdef CONFIG_REGULATOR + u32 opp_volts[BASE_MAX_NR_CLOCKS_REGULATORS]; +#endif - if (of_property_read_u64(node, "opp-hz", &opp_freq)) { - dev_warn(kbdev->dev, "OPP is missing required opp-hz property\n"); + err = of_property_read_u64(node, "opp-hz", &opp_freq); + if (err) { + dev_warn(kbdev->dev, "Failed to read opp-hz property with error %d\n", + err); continue; } - if (of_property_read_u64(node, "opp-hz-real", &real_freq)) - real_freq = opp_freq; + + +#if BASE_MAX_NR_CLOCKS_REGULATORS > 1 + err = of_property_read_u64_array(node, "opp-hz-real", + real_freqs, kbdev->nr_clocks); +#else + WARN_ON(kbdev->nr_clocks != 1); + err = of_property_read_u64(node, "opp-hz-real", real_freqs); +#endif + if (err < 0) { + dev_warn(kbdev->dev, "Failed to read opp-hz-real property with error %d\n", + err); + continue; + } +#ifdef CONFIG_REGULATOR + err = of_property_read_u32_array(node, + "opp-microvolt", opp_volts, kbdev->nr_regulators); + if (err < 0) { + dev_warn(kbdev->dev, "Failed to read opp-microvolt property with error %d\n", + err); + continue; + } +#endif + if (of_property_read_u64(node, "opp-core-mask", &core_mask)) core_mask = shader_present; if (core_mask != shader_present && @@ -319,12 +409,27 @@ static int kbase_devfreq_init_core_mask_table(struct kbase_device *kbdev) return -ENODEV; } - kbdev->opp_table[i].opp_freq = opp_freq; - kbdev->opp_table[i].real_freq = real_freq; - kbdev->opp_table[i].core_mask = core_mask; + kbdev->devfreq_table[i].opp_freq = opp_freq; + kbdev->devfreq_table[i].core_mask = core_mask; + if (kbdev->nr_clocks > 0) { + int j; - dev_info(kbdev->dev, "OPP %d : opp_freq=%llu real_freq=%llu core_mask=%llx\n", - i, opp_freq, real_freq, core_mask); + for (j = 0; j < kbdev->nr_clocks; j++) + kbdev->devfreq_table[i].real_freqs[j] = + real_freqs[j]; + } +#ifdef CONFIG_REGULATOR + if (kbdev->nr_regulators > 0) { + int j; + + for (j = 0; j < kbdev->nr_regulators; j++) + kbdev->devfreq_table[i].opp_volts[j] = + opp_volts[j]; + } +#endif + + dev_info(kbdev->dev, "OPP %d : opp_freq=%llu core_mask=%llx\n", + i, opp_freq, core_mask); i++; } @@ -332,6 +437,7 @@ static int kbase_devfreq_init_core_mask_table(struct kbase_device *kbdev) kbdev->num_opps = i; return 0; +#endif /* KERNEL_VERSION(3, 18, 0) > LINUX_VERSION_CODE */ } #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0) @@ -437,18 +543,25 @@ int kbase_devfreq_init(struct kbase_device *kbdev) { struct devfreq_dev_profile *dp; int err; + unsigned int i; - if (!kbdev->clock) { + if (kbdev->nr_clocks == 0) { dev_err(kbdev->dev, "Clock not available for devfreq\n"); return -ENODEV; } - kbdev->current_freq = clk_get_rate(kbdev->clock); - kbdev->current_nominal_freq = kbdev->current_freq; + for (i = 0; i < kbdev->nr_clocks; i++) { + if (kbdev->clocks[i]) + kbdev->current_freqs[i] = + clk_get_rate(kbdev->clocks[i]); + else + kbdev->current_freqs[i] = 0; + } + kbdev->current_nominal_freq = kbdev->current_freqs[0]; dp = &kbdev->devfreq_profile; - dp->initial_freq = kbdev->current_freq; + dp->initial_freq = kbdev->current_freqs[0]; dp->polling_ms = 100; dp->target = kbase_devfreq_target; dp->get_dev_status = kbase_devfreq_status; @@ -465,12 +578,15 @@ int kbase_devfreq_init(struct kbase_device *kbdev) }; err = kbase_devfreq_init_core_mask_table(kbdev); - if (err) + if (err) { + kbase_devfreq_term_freq_table(kbdev); return err; + } /* Initialise devfreq suspend/resume workqueue */ err = kbase_devfreq_work_init(kbdev); if (err) { + kbase_devfreq_term_freq_table(kbdev); dev_err(kbdev->dev, "Devfreq initialization failed"); return err; } @@ -478,7 +594,6 @@ int kbase_devfreq_init(struct kbase_device *kbdev) kbdev->devfreq = devfreq_add_device(kbdev->dev, dp, "simple_ondemand", NULL); if (IS_ERR(kbdev->devfreq)) { - kfree(dp->freq_table); err = PTR_ERR(kbdev->devfreq); goto add_device_failed; } @@ -528,6 +643,8 @@ opp_notifier_failed: add_device_failed: kbase_devfreq_work_term(kbdev); + kbase_devfreq_term_freq_table(kbdev); + return err; } @@ -552,7 +669,7 @@ void kbase_devfreq_term(struct kbase_device *kbdev) else kbdev->devfreq = NULL; - kfree(kbdev->opp_table); + kbase_devfreq_term_core_mask_table(kbdev); kbase_devfreq_work_term(kbdev); } diff --git a/mali_kbase/backend/gpu/mali_kbase_device_hw.c b/mali_kbase/backend/gpu/mali_kbase_device_hw.c index 5dd059f..567ebf1 100644 --- a/mali_kbase/backend/gpu/mali_kbase_device_hw.c +++ b/mali_kbase/backend/gpu/mali_kbase_device_hw.c @@ -1,6 +1,6 @@ /* * - * (C) COPYRIGHT 2014-2016,2018 ARM Limited. All rights reserved. + * (C) COPYRIGHT 2014-2016, 2018-2019 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the * GNU General Public License version 2 as published by the Free Software @@ -29,7 +29,6 @@ #include <backend/gpu/mali_kbase_pm_internal.h> #include <backend/gpu/mali_kbase_device_internal.h> -#include <mali_kbase_config_defaults.h> #if !defined(CONFIG_MALI_NO_MALI) @@ -326,15 +325,25 @@ void kbase_gpu_interrupt(struct kbase_device *kbdev, u32 val) if (val & CLEAN_CACHES_COMPLETED) kbase_clean_caches_done(kbdev); - /* When 'platform_power_down_only' is enabled, the L2 cache is not - * powered down, but flushed before the GPU power down (which is done - * by the platform code). So the L2 state machine requests a cache - * flush. And when that flush completes, the L2 state machine needs to - * be re-invoked to proceed with the GPU power down. - */ - if (val & POWER_CHANGED_ALL || - (platform_power_down_only && (val & CLEAN_CACHES_COMPLETED))) + if (val & POWER_CHANGED_ALL) { kbase_pm_power_changed(kbdev); + } else if (val & CLEAN_CACHES_COMPLETED) { + /* When 'platform_power_down_only' is enabled, the L2 cache is + * not powered down, but flushed before the GPU power down + * (which is done by the platform code). So the L2 state machine + * requests a cache flush. And when that flush completes, the L2 + * state machine needs to be re-invoked to proceed with the GPU + * power down. + * If cache line evict messages can be lost when shader cores + * power down then we need to flush the L2 cache before powering + * down cores. When the flush completes, the shaders' state + * machine needs to be re-invoked to proceed with powering down + * cores. + */ + if (platform_power_down_only || + kbase_hw_has_issue(kbdev, BASE_HW_ISSUE_TTRX_921)) + kbase_pm_power_changed(kbdev); + } KBASE_TRACE_ADD(kbdev, CORE_GPU_IRQ_DONE, NULL, NULL, 0u, val); } diff --git a/mali_kbase/backend/gpu/mali_kbase_gpu.c b/mali_kbase/backend/gpu/mali_kbase_gpu.c index c9c10e6..97dd09a 100644 --- a/mali_kbase/backend/gpu/mali_kbase_gpu.c +++ b/mali_kbase/backend/gpu/mali_kbase_gpu.c @@ -26,6 +26,7 @@ */ #include <mali_kbase.h> #include <mali_kbase_hwaccess_backend.h> +#include <mali_kbase_reset_gpu.h> #include <backend/gpu/mali_kbase_irq_internal.h> #include <backend/gpu/mali_kbase_jm_internal.h> #include <backend/gpu/mali_kbase_js_internal.h> @@ -88,6 +89,10 @@ int kbase_backend_late_init(struct kbase_device *kbdev) if (err) return err; + err = kbase_reset_gpu_init(kbdev); + if (err) + goto fail_reset_gpu_init; + err = kbase_hwaccess_pm_powerup(kbdev, PM_HW_ISSUES_DETECT); if (err) goto fail_pm_powerup; @@ -145,6 +150,8 @@ fail_interrupt_test: fail_timer: kbase_hwaccess_pm_halt(kbdev); fail_pm_powerup: + kbase_reset_gpu_term(kbdev); +fail_reset_gpu_init: kbase_hwaccess_pm_late_term(kbdev); return err; @@ -157,5 +164,6 @@ void kbase_backend_late_term(struct kbase_device *kbdev) kbase_job_slot_term(kbdev); kbase_backend_timer_term(kbdev); kbase_hwaccess_pm_halt(kbdev); + kbase_reset_gpu_term(kbdev); kbase_hwaccess_pm_late_term(kbdev); } diff --git a/mali_kbase/backend/gpu/mali_kbase_instr_backend.c b/mali_kbase/backend/gpu/mali_kbase_instr_backend.c index 31633ec..5494c49 100644 --- a/mali_kbase/backend/gpu/mali_kbase_instr_backend.c +++ b/mali_kbase/backend/gpu/mali_kbase_instr_backend.c @@ -1,6 +1,6 @@ /* * - * (C) COPYRIGHT 2014-2018 ARM Limited. All rights reserved. + * (C) COPYRIGHT 2014-2019 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the * GNU General Public License version 2 as published by the Free Software @@ -30,7 +30,6 @@ #include <mali_midg_regmap.h> #include <mali_kbase_hwaccess_instr.h> #include <backend/gpu/mali_kbase_device_internal.h> -#include <backend/gpu/mali_kbase_pm_internal.h> #include <backend/gpu/mali_kbase_instr_internal.h> int kbase_instr_hwcnt_enable_internal(struct kbase_device *kbdev, diff --git a/mali_kbase/backend/gpu/mali_kbase_irq_linux.c b/mali_kbase/backend/gpu/mali_kbase_irq_linux.c index dd0279a..643f450 100644 --- a/mali_kbase/backend/gpu/mali_kbase_irq_linux.c +++ b/mali_kbase/backend/gpu/mali_kbase_irq_linux.c @@ -1,6 +1,6 @@ /* * - * (C) COPYRIGHT 2014-2016,2018 ARM Limited. All rights reserved. + * (C) COPYRIGHT 2014-2016,2018-2019 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the * GNU General Public License version 2 as published by the Free Software @@ -49,12 +49,11 @@ static irqreturn_t kbase_job_irq_handler(int irq, void *data) struct kbase_device *kbdev = kbase_untag(data); u32 val; - spin_lock_irqsave(&kbdev->pm.backend.gpu_powered_lock, flags); + spin_lock_irqsave(&kbdev->hwaccess_lock, flags); if (!kbdev->pm.backend.gpu_powered) { /* GPU is turned off - IRQ is not for us */ - spin_unlock_irqrestore(&kbdev->pm.backend.gpu_powered_lock, - flags); + spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags); return IRQ_NONE; } @@ -65,15 +64,18 @@ static irqreturn_t kbase_job_irq_handler(int irq, void *data) dev_warn(kbdev->dev, "%s: irq %d irqstatus 0x%x before driver is ready\n", __func__, irq, val); #endif /* CONFIG_MALI_DEBUG */ - spin_unlock_irqrestore(&kbdev->pm.backend.gpu_powered_lock, flags); - if (!val) + if (!val) { + spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags); return IRQ_NONE; + } dev_dbg(kbdev->dev, "%s: irq %d irqstatus 0x%x\n", __func__, irq, val); kbase_job_done(kbdev, val); + spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags); + return IRQ_HANDLED; } @@ -85,12 +87,11 @@ static irqreturn_t kbase_mmu_irq_handler(int irq, void *data) struct kbase_device *kbdev = kbase_untag(data); u32 val; - spin_lock_irqsave(&kbdev->pm.backend.gpu_powered_lock, flags); + spin_lock_irqsave(&kbdev->hwaccess_lock, flags); if (!kbdev->pm.backend.gpu_powered) { /* GPU is turned off - IRQ is not for us */ - spin_unlock_irqrestore(&kbdev->pm.backend.gpu_powered_lock, - flags); + spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags); return IRQ_NONE; } @@ -103,7 +104,7 @@ static irqreturn_t kbase_mmu_irq_handler(int irq, void *data) dev_warn(kbdev->dev, "%s: irq %d irqstatus 0x%x before driver is ready\n", __func__, irq, val); #endif /* CONFIG_MALI_DEBUG */ - spin_unlock_irqrestore(&kbdev->pm.backend.gpu_powered_lock, flags); + spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags); if (!val) { atomic_dec(&kbdev->faults_pending); @@ -125,12 +126,11 @@ static irqreturn_t kbase_gpu_irq_handler(int irq, void *data) struct kbase_device *kbdev = kbase_untag(data); u32 val; - spin_lock_irqsave(&kbdev->pm.backend.gpu_powered_lock, flags); + spin_lock_irqsave(&kbdev->hwaccess_lock, flags); if (!kbdev->pm.backend.gpu_powered) { /* GPU is turned off - IRQ is not for us */ - spin_unlock_irqrestore(&kbdev->pm.backend.gpu_powered_lock, - flags); + spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags); return IRQ_NONE; } @@ -141,7 +141,7 @@ static irqreturn_t kbase_gpu_irq_handler(int irq, void *data) dev_dbg(kbdev->dev, "%s: irq %d irqstatus 0x%x before driver is ready\n", __func__, irq, val); #endif /* CONFIG_MALI_DEBUG */ - spin_unlock_irqrestore(&kbdev->pm.backend.gpu_powered_lock, flags); + spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags); if (!val) return IRQ_NONE; @@ -230,18 +230,17 @@ static irqreturn_t kbase_job_irq_test_handler(int irq, void *data) struct kbase_device *kbdev = kbase_untag(data); u32 val; - spin_lock_irqsave(&kbdev->pm.backend.gpu_powered_lock, flags); + spin_lock_irqsave(&kbdev->hwaccess_lock, flags); if (!kbdev->pm.backend.gpu_powered) { /* GPU is turned off - IRQ is not for us */ - spin_unlock_irqrestore(&kbdev->pm.backend.gpu_powered_lock, - flags); + spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags); return IRQ_NONE; } val = kbase_reg_read(kbdev, JOB_CONTROL_REG(JOB_IRQ_STATUS)); - spin_unlock_irqrestore(&kbdev->pm.backend.gpu_powered_lock, flags); + spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags); if (!val) return IRQ_NONE; @@ -262,18 +261,17 @@ static irqreturn_t kbase_mmu_irq_test_handler(int irq, void *data) struct kbase_device *kbdev = kbase_untag(data); u32 val; - spin_lock_irqsave(&kbdev->pm.backend.gpu_powered_lock, flags); + spin_lock_irqsave(&kbdev->hwaccess_lock, flags); if (!kbdev->pm.backend.gpu_powered) { /* GPU is turned off - IRQ is not for us */ - spin_unlock_irqrestore(&kbdev->pm.backend.gpu_powered_lock, - flags); + spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags); return IRQ_NONE; } val = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_STATUS)); - spin_unlock_irqrestore(&kbdev->pm.backend.gpu_powered_lock, flags); + spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags); if (!val) return IRQ_NONE; diff --git a/mali_kbase/backend/gpu/mali_kbase_jm_hw.c b/mali_kbase/backend/gpu/mali_kbase_jm_hw.c index 26e9fcf..794abbf 100644 --- a/mali_kbase/backend/gpu/mali_kbase_jm_hw.c +++ b/mali_kbase/backend/gpu/mali_kbase_jm_hw.c @@ -30,6 +30,7 @@ #include <mali_kbase_tracepoints.h> #include <mali_kbase_hw.h> #include <mali_kbase_hwaccess_jm.h> +#include <mali_kbase_reset_gpu.h> #include <mali_kbase_ctx_sched.h> #include <mali_kbase_hwcnt_context.h> #include <backend/gpu/mali_kbase_device_internal.h> @@ -39,9 +40,7 @@ #define beenthere(kctx, f, a...) \ dev_dbg(kctx->kbdev->dev, "%s:" f, __func__, ##a) -static void kbasep_try_reset_gpu_early(struct kbase_device *kbdev); -static void kbasep_reset_timeout_worker(struct work_struct *data); -static enum hrtimer_restart kbasep_reset_timer_callback(struct hrtimer *timer); +static void kbasep_try_reset_gpu_early_locked(struct kbase_device *kbdev); static inline int kbasep_jm_is_js_free(struct kbase_device *kbdev, int js, struct kbase_context *kctx) @@ -270,16 +269,17 @@ static void kbasep_trace_tl_event_lpu_softstop(struct kbase_device *kbdev, void kbase_job_done(struct kbase_device *kbdev, u32 done) { - unsigned long flags; int i; u32 count = 0; - ktime_t end_timestamp = ktime_get(); + ktime_t end_timestamp; + + lockdep_assert_held(&kbdev->hwaccess_lock); KBASE_DEBUG_ASSERT(kbdev); KBASE_TRACE_ADD(kbdev, JM_IRQ, NULL, NULL, 0, done); - spin_lock_irqsave(&kbdev->hwaccess_lock, flags); + end_timestamp = ktime_get(); while (done) { u32 failed = done >> 16; @@ -338,9 +338,8 @@ void kbase_job_done(struct kbase_device *kbdev, u32 done) * allowing any other jobs on the slot to continue. */ if (kbase_hw_has_issue(kbdev, BASE_HW_ISSUE_TTRX_3076)) { if (completion_code == BASE_JD_EVENT_JOB_BUS_FAULT) { - if (kbase_prepare_to_reset_gpu_locked(kbdev)) { + if (kbase_prepare_to_reset_gpu_locked(kbdev)) kbase_reset_gpu_locked(kbdev); - } } } } @@ -468,18 +467,16 @@ void kbase_job_done(struct kbase_device *kbdev, u32 done) end_timestamp); } - spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags); if (atomic_read(&kbdev->hwaccess.backend.reset_gpu) == KBASE_RESET_GPU_COMMITTED) { /* If we're trying to reset the GPU then we might be able to do * it early (without waiting for a timeout) because some jobs * have completed */ - kbasep_try_reset_gpu_early(kbdev); + kbasep_try_reset_gpu_early_locked(kbdev); } KBASE_TRACE_ADD(kbdev, JM_IRQ_END, NULL, NULL, 0, count); } -KBASE_EXPORT_TEST_API(kbase_job_done); static bool kbasep_soft_stop_allowed(struct kbase_device *kbdev, struct kbase_jd_atom *katom) @@ -732,11 +729,14 @@ void kbase_backend_jm_kill_jobs_from_kctx(struct kbase_context *kctx) mutex_lock(&kctx->jctx.lock); spin_lock_irqsave(&kbdev->hwaccess_lock, flags); - /* Invalidate all jobs in context, to prevent re-submitting */ + /* Invalidate all incomplete jobs in context to prevent resubmitting */ for (i = 0; i < BASE_JD_ATOM_COUNT; i++) { - if (!work_pending(&kctx->jctx.atoms[i].work)) - kctx->jctx.atoms[i].event_code = - BASE_JD_EVENT_JOB_CANCELLED; + struct kbase_jd_atom *katom = &kctx->jctx.atoms[i]; + + if ((katom->status != KBASE_JD_ATOM_STATE_COMPLETED) && + (katom->status != + KBASE_JD_ATOM_STATE_HW_COMPLETED)) + katom->event_code = BASE_JD_EVENT_JOB_CANCELLED; } for (i = 0; i < kbdev->gpu_props.num_job_slots; i++) @@ -811,9 +811,7 @@ void kbase_jm_wait_for_zero_jobs(struct kbase_context *kctx) } /* Wait for the reset to complete */ - wait_event(kbdev->hwaccess.backend.reset_wait, - atomic_read(&kbdev->hwaccess.backend.reset_gpu) - == KBASE_RESET_GPU_NOT_PENDING); + kbase_reset_gpu_wait(kbdev); exit: dev_dbg(kbdev->dev, "Zap: Finished Context %p", kctx); @@ -841,19 +839,7 @@ u32 kbase_backend_get_current_flush_id(struct kbase_device *kbdev) int kbase_job_slot_init(struct kbase_device *kbdev) { - kbdev->hwaccess.backend.reset_workq = alloc_workqueue( - "Mali reset workqueue", 0, 1); - if (NULL == kbdev->hwaccess.backend.reset_workq) - return -EINVAL; - - INIT_WORK(&kbdev->hwaccess.backend.reset_work, - kbasep_reset_timeout_worker); - - hrtimer_init(&kbdev->hwaccess.backend.reset_timer, CLOCK_MONOTONIC, - HRTIMER_MODE_REL); - kbdev->hwaccess.backend.reset_timer.function = - kbasep_reset_timer_callback; - + CSTD_UNUSED(kbdev); return 0; } KBASE_EXPORT_TEST_API(kbase_job_slot_init); @@ -865,7 +851,7 @@ void kbase_job_slot_halt(struct kbase_device *kbdev) void kbase_job_slot_term(struct kbase_device *kbdev) { - destroy_workqueue(kbdev->hwaccess.backend.reset_workq); + CSTD_UNUSED(kbdev); } KBASE_EXPORT_TEST_API(kbase_job_slot_term); @@ -1460,7 +1446,7 @@ int kbase_reset_gpu_silent(struct kbase_device *kbdev) return 0; } -bool kbase_reset_gpu_active(struct kbase_device *kbdev) +bool kbase_reset_gpu_is_active(struct kbase_device *kbdev) { if (atomic_read(&kbdev->hwaccess.backend.reset_gpu) == KBASE_RESET_GPU_NOT_PENDING) @@ -1468,3 +1454,37 @@ bool kbase_reset_gpu_active(struct kbase_device *kbdev) return true; } + +int kbase_reset_gpu_wait(struct kbase_device *kbdev) +{ + wait_event(kbdev->hwaccess.backend.reset_wait, + atomic_read(&kbdev->hwaccess.backend.reset_gpu) + == KBASE_RESET_GPU_NOT_PENDING); + + return 0; +} +KBASE_EXPORT_TEST_API(kbase_reset_gpu_wait); + +int kbase_reset_gpu_init(struct kbase_device *kbdev) +{ + kbdev->hwaccess.backend.reset_workq = alloc_workqueue( + "Mali reset workqueue", 0, 1); + if (kbdev->hwaccess.backend.reset_workq == NULL) + return -ENOMEM; + + INIT_WORK(&kbdev->hwaccess.backend.reset_work, + kbasep_reset_timeout_worker); + + hrtimer_init(&kbdev->hwaccess.backend.reset_timer, CLOCK_MONOTONIC, + HRTIMER_MODE_REL); + kbdev->hwaccess.backend.reset_timer.function = + kbasep_reset_timer_callback; + + return 0; +} + +void kbase_reset_gpu_term(struct kbase_device *kbdev) +{ + destroy_workqueue(kbdev->hwaccess.backend.reset_workq); +} + diff --git a/mali_kbase/backend/gpu/mali_kbase_jm_rb.c b/mali_kbase/backend/gpu/mali_kbase_jm_rb.c index eec8765..7cdaf98 100644 --- a/mali_kbase/backend/gpu/mali_kbase_jm_rb.c +++ b/mali_kbase/backend/gpu/mali_kbase_jm_rb.c @@ -32,6 +32,7 @@ #include <mali_kbase_tracepoints.h> #include <mali_kbase_hwcnt_context.h> #include <mali_kbase_10969_workaround.h> +#include <mali_kbase_reset_gpu.h> #include <backend/gpu/mali_kbase_cache_policy_backend.h> #include <backend/gpu/mali_kbase_device_internal.h> #include <backend/gpu/mali_kbase_jm_internal.h> @@ -344,14 +345,18 @@ static void kbase_gpu_release_atom(struct kbase_device *kbdev, (katom->protected_state.enter != KBASE_ATOM_ENTER_PROTECTED_CHECK) && (katom->protected_state.enter != - KBASE_ATOM_ENTER_PROTECTED_HWCNT)) + KBASE_ATOM_ENTER_PROTECTED_HWCNT)) { kbase_pm_protected_override_disable(kbdev); + kbase_pm_update_cores_state_nolock(kbdev); + } if (!kbase_jd_katom_is_protected(katom) && (katom->protected_state.exit != KBASE_ATOM_EXIT_PROTECTED_CHECK) && (katom->protected_state.exit != - KBASE_ATOM_EXIT_PROTECTED_RESET_WAIT)) + KBASE_ATOM_EXIT_PROTECTED_RESET_WAIT)) { kbase_pm_protected_override_disable(kbdev); + kbase_pm_update_cores_state_nolock(kbdev); + } if (katom->protected_state.enter != KBASE_ATOM_ENTER_PROTECTED_CHECK || @@ -849,7 +854,7 @@ void kbase_backend_slot_update(struct kbase_device *kbdev) lockdep_assert_held(&kbdev->hwaccess_lock); - if (kbase_reset_gpu_active(kbdev)) + if (kbase_reset_gpu_is_active(kbdev)) return; for (js = 0; js < kbdev->gpu_props.num_job_slots; js++) { @@ -1012,7 +1017,7 @@ void kbase_backend_slot_update(struct kbase_device *kbdev) if ((kbdev->serialize_jobs & KBASE_SERIALIZE_RESET) && - kbase_reset_gpu_active(kbdev)) + kbase_reset_gpu_is_active(kbdev)) break; /* Check if this job needs the cycle counter diff --git a/mali_kbase/backend/gpu/mali_kbase_js_backend.c b/mali_kbase/backend/gpu/mali_kbase_js_backend.c index 7307be4..1ffaa23 100644 --- a/mali_kbase/backend/gpu/mali_kbase_js_backend.c +++ b/mali_kbase/backend/gpu/mali_kbase_js_backend.c @@ -1,6 +1,6 @@ /* * - * (C) COPYRIGHT 2014-2018 ARM Limited. All rights reserved. + * (C) COPYRIGHT 2014-2019 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the * GNU General Public License version 2 as published by the Free Software @@ -27,6 +27,7 @@ #include <mali_kbase.h> #include <mali_kbase_hwaccess_jm.h> +#include <mali_kbase_reset_gpu.h> #include <backend/gpu/mali_kbase_jm_internal.h> #include <backend/gpu/mali_kbase_js_internal.h> diff --git a/mali_kbase/backend/gpu/mali_kbase_pm_backend.c b/mali_kbase/backend/gpu/mali_kbase_pm_backend.c index e04ab73..d9fc761 100644 --- a/mali_kbase/backend/gpu/mali_kbase_pm_backend.c +++ b/mali_kbase/backend/gpu/mali_kbase_pm_backend.c @@ -1,4 +1,4 @@ -/* + /* * * (C) COPYRIGHT 2010-2019 ARM Limited. All rights reserved. * @@ -150,7 +150,6 @@ int kbase_hwaccess_pm_early_init(struct kbase_device *kbdev) kbdev->pm.active_count = 0; spin_lock_init(&kbdev->pm.backend.gpu_cycle_counter_requests_lock); - spin_lock_init(&kbdev->pm.backend.gpu_powered_lock); init_waitqueue_head(&kbdev->pm.backend.poweroff_wait); @@ -333,13 +332,8 @@ void kbase_pm_do_poweroff(struct kbase_device *kbdev, bool is_suspend) spin_lock_irqsave(&kbdev->hwaccess_lock, flags); - spin_lock(&kbdev->pm.backend.gpu_powered_lock); - if (!kbdev->pm.backend.gpu_powered) { - spin_unlock(&kbdev->pm.backend.gpu_powered_lock); + if (!kbdev->pm.backend.gpu_powered) goto unlock_hwaccess; - } else { - spin_unlock(&kbdev->pm.backend.gpu_powered_lock); - } if (kbdev->pm.backend.poweroff_wait_in_progress) goto unlock_hwaccess; @@ -426,9 +420,7 @@ int kbase_hwaccess_pm_powerup(struct kbase_device *kbdev, /* We are ready to receive IRQ's now as power policy is set up, so * enable them now. */ #ifdef CONFIG_MALI_DEBUG - spin_lock_irqsave(&kbdev->pm.backend.gpu_powered_lock, irq_flags); kbdev->pm.backend.driver_ready_for_irqs = true; - spin_unlock_irqrestore(&kbdev->pm.backend.gpu_powered_lock, irq_flags); #endif kbase_pm_enable_interrupts(kbdev); diff --git a/mali_kbase/backend/gpu/mali_kbase_pm_defs.h b/mali_kbase/backend/gpu/mali_kbase_pm_defs.h index 1a865d5..42d3cb0 100644 --- a/mali_kbase/backend/gpu/mali_kbase_pm_defs.h +++ b/mali_kbase/backend/gpu/mali_kbase_pm_defs.h @@ -84,14 +84,9 @@ enum kbase_pm_core_type { * are unknown */ enum kbase_l2_core_state { - KBASE_L2_OFF = 0, - KBASE_L2_PEND_ON, - KBASE_L2_ON_HWCNT_ENABLE, - KBASE_L2_ON, - KBASE_L2_ON_HWCNT_DISABLE, - KBASE_L2_POWER_DOWN, - KBASE_L2_PEND_OFF, - KBASE_L2_RESET_WAIT +#define KBASEP_L2_STATE(n) KBASE_L2_ ## n, +#include "mali_kbase_pm_l2_states.h" +#undef KBASEP_L2_STATE }; /** @@ -113,6 +108,10 @@ enum kbase_l2_core_state { * power off, but they remain on for the * duration of the hysteresis timer * @KBASE_SHADERS_WAIT_FINISHED_CORESTACK_ON: The hysteresis timer has expired + * @KBASE_SHADERS_L2_FLUSHING_CORESTACK_ON: The core stacks are on and the + * level 2 cache is being flushed. + * @KBASE_SHADERS_READY_OFF_CORESTACK_ON: The core stacks are on and the shaders + * are ready to be powered off. * @KBASE_SHADERS_PEND_OFF_CORESTACK_ON: The core stacks are on, and the shaders * have been requested to power off * @KBASE_SHADERS_OFF_CORESTACK_PEND_OFF: The shaders are off, and the core stacks @@ -125,17 +124,9 @@ enum kbase_l2_core_state { * states are unknown */ enum kbase_shader_core_state { - KBASE_SHADERS_OFF_CORESTACK_OFF = 0, - KBASE_SHADERS_OFF_CORESTACK_PEND_ON, - KBASE_SHADERS_PEND_ON_CORESTACK_ON, - KBASE_SHADERS_ON_CORESTACK_ON, - KBASE_SHADERS_ON_CORESTACK_ON_RECHECK, - KBASE_SHADERS_WAIT_OFF_CORESTACK_ON, - KBASE_SHADERS_WAIT_FINISHED_CORESTACK_ON, - KBASE_SHADERS_PEND_OFF_CORESTACK_ON, - KBASE_SHADERS_OFF_CORESTACK_PEND_OFF, - KBASE_SHADERS_OFF_CORESTACK_OFF_TIMER_PEND_OFF, - KBASE_SHADERS_RESET_WAIT +#define KBASEP_SHADER_STATE(n) KBASE_SHADERS_ ## n, +#include "mali_kbase_pm_shader_states.h" +#undef KBASEP_SHADER_STATE }; /** @@ -256,7 +247,10 @@ union kbase_pm_policy_data { * state according to the L2 and shader power state * machines * @gpu_powered: Set to true when the GPU is powered and register - * accesses are possible, false otherwise + * accesses are possible, false otherwise. Access to this + * variable should be protected by: both the hwaccess_lock + * spinlock and the pm.lock mutex for writes; or at least + * one of either lock for reads. * @pm_shaders_core_mask: Shader PM state synchronised shaders core mask. It * holds the cores enabled in a hardware counters dump, * and may differ from @shaders_avail when under different @@ -266,8 +260,6 @@ union kbase_pm_policy_data { * @driver_ready_for_irqs: Debug state indicating whether sufficient * initialization of the driver has occurred to handle * IRQs - * @gpu_powered_lock: Spinlock that must be held when writing @gpu_powered or - * accessing @driver_ready_for_irqs * @metrics: Structure to hold metrics for the GPU * @shader_tick_timer: Structure to hold the shader poweroff tick timer state * @poweroff_wait_in_progress: true if a wait for GPU power off is in progress. @@ -354,8 +346,6 @@ struct kbase_pm_backend_data { bool driver_ready_for_irqs; #endif /* CONFIG_MALI_DEBUG */ - spinlock_t gpu_powered_lock; - struct kbasep_pm_metrics_state metrics; struct kbasep_pm_tick_timer_state shader_tick_timer; diff --git a/mali_kbase/backend/gpu/mali_kbase_pm_driver.c b/mali_kbase/backend/gpu/mali_kbase_pm_driver.c index 1172f12..d97ec23 100644 --- a/mali_kbase/backend/gpu/mali_kbase_pm_driver.c +++ b/mali_kbase/backend/gpu/mali_kbase_pm_driver.c @@ -34,6 +34,7 @@ #include <mali_kbase_config_defaults.h> #include <mali_kbase_smc.h> #include <mali_kbase_hwaccess_jm.h> +#include <mali_kbase_reset_gpu.h> #include <mali_kbase_ctx_sched.h> #include <mali_kbase_hwcnt_context.h> #include <backend/gpu/mali_kbase_cache_policy_backend.h> @@ -486,6 +487,19 @@ static void kbase_pm_l2_config_override(struct kbase_device *kbdev) kbase_reg_write(kbdev, GPU_CONTROL_REG(L2_CONFIG), val); } +static const char *kbase_l2_core_state_to_string(enum kbase_l2_core_state state) +{ + const char *const strings[] = { +#define KBASEP_L2_STATE(n) #n, +#include "mali_kbase_pm_l2_states.h" +#undef KBASEP_L2_STATE + }; + if (WARN_ON((size_t)state >= ARRAY_SIZE(strings))) + return "Bad level 2 cache state"; + else + return strings[state]; +} + static u64 kbase_pm_l2_update_state(struct kbase_device *kbdev) { struct kbase_pm_backend_data *backend = &kbdev->pm.backend; @@ -690,6 +704,13 @@ static u64 kbase_pm_l2_update_state(struct kbase_device *kbdev) WARN(1, "Invalid state in l2_state: %d", backend->l2_state); } + + if (backend->l2_state != prev_state) + dev_dbg(kbdev->dev, "L2 state transition: %s to %s\n", + kbase_l2_core_state_to_string(prev_state), + kbase_l2_core_state_to_string( + backend->l2_state)); + } while (backend->l2_state != prev_state); if (kbdev->pm.backend.invoke_poweroff_wait_wq_when_l2_off && @@ -763,6 +784,20 @@ static void shader_poweroff_timer_queue_cancel(struct kbase_device *kbdev) } } +static const char *kbase_shader_core_state_to_string( + enum kbase_shader_core_state state) +{ + const char *const strings[] = { +#define KBASEP_SHADER_STATE(n) #n, +#include "mali_kbase_pm_shader_states.h" +#undef KBASEP_SHADER_STATE + }; + if (WARN_ON((size_t)state >= ARRAY_SIZE(strings))) + return "Bad shader core state"; + else + return strings[state]; +} + static void kbase_pm_shaders_update_state(struct kbase_device *kbdev) { struct kbase_pm_backend_data *backend = &kbdev->pm.backend; @@ -932,7 +967,24 @@ static void kbase_pm_shaders_update_state(struct kbase_device *kbdev) case KBASE_SHADERS_WAIT_FINISHED_CORESTACK_ON: shader_poweroff_timer_queue_cancel(kbdev); + if (kbase_hw_has_issue(kbdev, BASE_HW_ISSUE_TTRX_921)) { + kbase_gpu_start_cache_clean_nolock(kbdev); + backend->shaders_state = + KBASE_SHADERS_L2_FLUSHING_CORESTACK_ON; + } else { + backend->shaders_state = + KBASE_SHADERS_READY_OFF_CORESTACK_ON; + } + break; + + case KBASE_SHADERS_L2_FLUSHING_CORESTACK_ON: + if (!kbdev->cache_clean_in_progress) + backend->shaders_state = + KBASE_SHADERS_READY_OFF_CORESTACK_ON; + break; + + case KBASE_SHADERS_READY_OFF_CORESTACK_ON: if (!platform_power_down_only) kbase_pm_invoke(kbdev, KBASE_PM_CORE_SHADER, shaders_ready, ACTION_PWROFF); @@ -980,6 +1032,13 @@ static void kbase_pm_shaders_update_state(struct kbase_device *kbdev) backend->shaders_state = KBASE_SHADERS_OFF_CORESTACK_OFF_TIMER_PEND_OFF; break; } + + if (backend->shaders_state != prev_state) + dev_dbg(kbdev->dev, "Shader state transition: %s to %s\n", + kbase_shader_core_state_to_string(prev_state), + kbase_shader_core_state_to_string( + backend->shaders_state)); + } while (backend->shaders_state != prev_state); } @@ -1372,9 +1431,7 @@ void kbase_pm_clock_on(struct kbase_device *kbdev, bool is_resume) } spin_lock_irqsave(&kbdev->hwaccess_lock, flags); - spin_lock(&kbdev->pm.backend.gpu_powered_lock); kbdev->pm.backend.gpu_powered = true; - spin_unlock(&kbdev->pm.backend.gpu_powered_lock); spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags); if (reset_required) { @@ -1428,12 +1485,10 @@ bool kbase_pm_clock_off(struct kbase_device *kbdev, bool is_suspend) kbase_synchronize_irqs(kbdev); spin_lock_irqsave(&kbdev->hwaccess_lock, flags); - spin_lock(&kbdev->pm.backend.gpu_powered_lock); if (atomic_read(&kbdev->faults_pending)) { /* Page/bus faults are still being processed. The GPU can not * be powered off until they have completed */ - spin_unlock(&kbdev->pm.backend.gpu_powered_lock); spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags); return false; } @@ -1442,7 +1497,6 @@ bool kbase_pm_clock_off(struct kbase_device *kbdev, bool is_suspend) /* The GPU power may be turned off from this point */ kbdev->pm.backend.gpu_powered = false; - spin_unlock(&kbdev->pm.backend.gpu_powered_lock); spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags); if (is_suspend && kbdev->pm.backend.callback_power_suspend) @@ -1502,7 +1556,6 @@ static enum hrtimer_restart kbasep_reset_timeout(struct hrtimer *timer) static void kbase_pm_hw_issues_detect(struct kbase_device *kbdev) { struct device_node *np = kbdev->dev->of_node; - u32 jm_values[4]; const u32 gpu_id = kbdev->gpu_props.props.raw_props.gpu_id; const u32 prod_id = (gpu_id & GPU_ID_VERSION_PRODUCT_ID) >> GPU_ID_VERSION_PRODUCT_ID_SHIFT; @@ -1566,17 +1619,15 @@ static void kbase_pm_hw_issues_detect(struct kbase_device *kbdev) kbdev->hw_quirks_jm = 0; /* Only for T86x/T88x-based products after r2p0 */ if (prod_id >= 0x860 && prod_id <= 0x880 && major >= 2) { + u32 jm_values[4] = {0u, 0u, 0u, JM_MAX_JOB_THROTTLE_LIMIT}; - if (of_property_read_u32_array(np, + /* If entry not in device tree (return value of this func != 0), + * use defaults from jm_values[]'s initializer + */ + (void)of_property_read_u32_array(np, "jm_config", &jm_values[0], - ARRAY_SIZE(jm_values))) { - /* Entry not in device tree, use defaults */ - jm_values[0] = 0; - jm_values[1] = 0; - jm_values[2] = 0; - jm_values[3] = JM_MAX_JOB_THROTTLE_LIMIT; - } + ARRAY_SIZE(jm_values)); /* Limit throttle limit to 6 bits*/ if (jm_values[3] > JM_MAX_JOB_THROTTLE_LIMIT) { @@ -1802,11 +1853,7 @@ int kbase_pm_init_hw(struct kbase_device *kbdev, unsigned int flags) if (kbdev->pm.backend.callback_power_on) kbdev->pm.backend.callback_power_on(kbdev); - spin_lock_irqsave(&kbdev->pm.backend.gpu_powered_lock, - irq_flags); kbdev->pm.backend.gpu_powered = true; - spin_unlock_irqrestore(&kbdev->pm.backend.gpu_powered_lock, - irq_flags); } /* Ensure interrupts are off to begin with, this also clears any diff --git a/mali_kbase/backend/gpu/mali_kbase_pm_l2_states.h b/mali_kbase/backend/gpu/mali_kbase_pm_l2_states.h new file mode 100644 index 0000000..94bad77 --- /dev/null +++ b/mali_kbase/backend/gpu/mali_kbase_pm_l2_states.h @@ -0,0 +1,36 @@ +/* + * + * (C) COPYRIGHT 2019 ARM Limited. All rights reserved. + * + * This program is free software and is provided to you under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation, and any use by you of this program is subject to the terms + * of such GNU licence. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, you can access it online at + * http://www.gnu.org/licenses/gpl-2.0.html. + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +/* + * Backend-specific Power Manager level 2 cache state definitions. + * The function-like macro KBASEP_L2_STATE() must be defined before including + * this header file. This header file can be included multiple times in the + * same compilation unit with different definitions of KBASEP_L2_STATE(). + */ +KBASEP_L2_STATE(OFF) +KBASEP_L2_STATE(PEND_ON) +KBASEP_L2_STATE(ON_HWCNT_ENABLE) +KBASEP_L2_STATE(ON) +KBASEP_L2_STATE(ON_HWCNT_DISABLE) +KBASEP_L2_STATE(POWER_DOWN) +KBASEP_L2_STATE(PEND_OFF) +KBASEP_L2_STATE(RESET_WAIT) diff --git a/mali_kbase/backend/gpu/mali_kbase_pm_policy.c b/mali_kbase/backend/gpu/mali_kbase_pm_policy.c index 795b99f..3152424 100644 --- a/mali_kbase/backend/gpu/mali_kbase_pm_policy.c +++ b/mali_kbase/backend/gpu/mali_kbase_pm_policy.c @@ -27,7 +27,6 @@ #include <mali_kbase.h> #include <mali_midg_regmap.h> #include <mali_kbase_pm.h> -#include <mali_kbase_config_defaults.h> #include <backend/gpu/mali_kbase_pm_internal.h> static const struct kbase_pm_policy *const all_policy_list[] = { diff --git a/mali_kbase/backend/gpu/mali_kbase_pm_shader_states.h b/mali_kbase/backend/gpu/mali_kbase_pm_shader_states.h new file mode 100644 index 0000000..3f89eb5 --- /dev/null +++ b/mali_kbase/backend/gpu/mali_kbase_pm_shader_states.h @@ -0,0 +1,42 @@ +/* + * + * (C) COPYRIGHT 2019 ARM Limited. All rights reserved. + * + * This program is free software and is provided to you under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation, and any use by you of this program is subject to the terms + * of such GNU licence. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, you can access it online at + * http://www.gnu.org/licenses/gpl-2.0.html. + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +/* + * Backend-specific Power Manager shader core state definitions. + * The function-like macro KBASEP_SHADER_STATE() must be defined before + * including this header file. This header file can be included multiple + * times in the same compilation unit with different definitions of + * KBASEP_SHADER_STATE(). + */ +KBASEP_SHADER_STATE(OFF_CORESTACK_OFF) +KBASEP_SHADER_STATE(OFF_CORESTACK_PEND_ON) +KBASEP_SHADER_STATE(PEND_ON_CORESTACK_ON) +KBASEP_SHADER_STATE(ON_CORESTACK_ON) +KBASEP_SHADER_STATE(ON_CORESTACK_ON_RECHECK) +KBASEP_SHADER_STATE(WAIT_OFF_CORESTACK_ON) +KBASEP_SHADER_STATE(WAIT_FINISHED_CORESTACK_ON) +KBASEP_SHADER_STATE(L2_FLUSHING_CORESTACK_ON) +KBASEP_SHADER_STATE(READY_OFF_CORESTACK_ON) +KBASEP_SHADER_STATE(PEND_OFF_CORESTACK_ON) +KBASEP_SHADER_STATE(OFF_CORESTACK_PEND_OFF) +KBASEP_SHADER_STATE(OFF_CORESTACK_OFF_TIMER_PEND_OFF) +KBASEP_SHADER_STATE(RESET_WAIT) diff --git a/mali_kbase/build.bp b/mali_kbase/build.bp index b388f23..666f500 100644 --- a/mali_kbase/build.bp +++ b/mali_kbase/build.bp @@ -19,6 +19,9 @@ bob_defaults { no_mali: { kbuild_options: ["CONFIG_MALI_NO_MALI=y"], }, + mali_real_hw: { + kbuild_options: ["CONFIG_MALI_REAL_HW=y"], + }, mali_devfreq: { kbuild_options: ["CONFIG_MALI_DEVFREQ=y"], }, @@ -55,12 +58,13 @@ bob_defaults { mali_dma_buf_map_on_demand: { kbuild_options: ["CONFIG_MALI_DMA_BUF_MAP_ON_DEMAND=y"], }, + mali_dma_buf_legacy_compat: { + kbuild_options: ["CONFIG_MALI_DMA_BUF_LEGACY_COMPAT=y"], + }, kbuild_options: [ "MALI_UNIT_TEST={{.unit_test_code}}", "MALI_CUSTOMER_RELEASE={{.release}}", "MALI_USE_CSF={{.gpu_has_csf}}", - /* MALI_CSF_LT_V10: Temporary for hybrid integration config */ - "MALI_CSF_LT_V10={{.base_hybrid_csf_lt_v10}}", "MALI_KERNEL_TEST_API={{.debug}}", ], defaults: ["kernel_defaults"], diff --git a/mali_kbase/ipa/mali_kbase_ipa.c b/mali_kbase/ipa/mali_kbase_ipa.c index 9da2878..65b4edf 100644 --- a/mali_kbase/ipa/mali_kbase_ipa.c +++ b/mali_kbase/ipa/mali_kbase_ipa.c @@ -1,6 +1,6 @@ /* * - * (C) COPYRIGHT 2016-2018 ARM Limited. All rights reserved. + * (C) COPYRIGHT 2016-2019 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the * GNU General Public License version 2 as published by the Free Software @@ -46,7 +46,8 @@ static const struct kbase_ipa_model_ops *kbase_ipa_all_model_ops[] = { &kbase_g76_ipa_model_ops, &kbase_g52_ipa_model_ops, &kbase_g52_r1_ipa_model_ops, - &kbase_g51_ipa_model_ops + &kbase_g51_ipa_model_ops, + &kbase_g77_ipa_model_ops }; int kbase_ipa_model_recalculate(struct kbase_ipa_model *model) @@ -107,6 +108,8 @@ const char *kbase_ipa_model_name_from_id(u32 gpu_id) return "mali-g52-power-model"; else return "mali-g52_r1-power-model"; + case GPU_ID2_PRODUCT_TTRX: + return "mali-g77-power-model"; default: return KBASE_IPA_FALLBACK_MODEL_NAME; } diff --git a/mali_kbase/ipa/mali_kbase_ipa.h b/mali_kbase/ipa/mali_kbase_ipa.h index 7462048..81cafc8 100644 --- a/mali_kbase/ipa/mali_kbase_ipa.h +++ b/mali_kbase/ipa/mali_kbase_ipa.h @@ -1,6 +1,6 @@ /* * - * (C) COPYRIGHT 2016-2018 ARM Limited. All rights reserved. + * (C) COPYRIGHT 2016-2019 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the * GNU General Public License version 2 as published by the Free Software @@ -208,6 +208,7 @@ extern const struct kbase_ipa_model_ops kbase_g76_ipa_model_ops; extern const struct kbase_ipa_model_ops kbase_g52_ipa_model_ops; extern const struct kbase_ipa_model_ops kbase_g52_r1_ipa_model_ops; extern const struct kbase_ipa_model_ops kbase_g51_ipa_model_ops; +extern const struct kbase_ipa_model_ops kbase_g77_ipa_model_ops; /** * kbase_get_real_power() - get the real power consumption of the GPU diff --git a/mali_kbase/ipa/mali_kbase_ipa_debugfs.c b/mali_kbase/ipa/mali_kbase_ipa_debugfs.c index bc247f2..30a3b7d 100644 --- a/mali_kbase/ipa/mali_kbase_ipa_debugfs.c +++ b/mali_kbase/ipa/mali_kbase_ipa_debugfs.c @@ -141,6 +141,7 @@ end: } static const struct file_operations fops_string = { + .owner = THIS_MODULE, .read = param_string_get, .write = param_string_set, .open = simple_open, @@ -222,8 +223,12 @@ static int current_power_get(void *data, u64 *val) u32 power; kbase_pm_context_active(kbdev); + /* The current model assumes that there's no more than one voltage + * regulator currently available in the system. + */ kbase_get_real_power(df, &power, - kbdev->current_nominal_freq, (kbdev->current_voltage / 1000)); + kbdev->current_nominal_freq, + (kbdev->current_voltages[0] / 1000)); kbase_pm_context_idle(kbdev); *val = power; diff --git a/mali_kbase/ipa/mali_kbase_ipa_vinstr_g7x.c b/mali_kbase/ipa/mali_kbase_ipa_vinstr_g7x.c index 6365d2f..a3d1fae 100644 --- a/mali_kbase/ipa/mali_kbase_ipa_vinstr_g7x.c +++ b/mali_kbase/ipa/mali_kbase_ipa_vinstr_g7x.c @@ -1,6 +1,6 @@ /* * - * (C) COPYRIGHT 2016-2018 ARM Limited. All rights reserved. + * (C) COPYRIGHT 2016-2019 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the * GNU General Public License version 2 as published by the Free Software @@ -23,7 +23,6 @@ #include "mali_kbase_ipa_vinstr_common.h" #include "mali_kbase.h" -#include "mali_kbase_ipa_debugfs.h" /* Performance counter blocks base offsets */ @@ -43,7 +42,10 @@ /* SC counter block offsets */ #define SC_FRAG_ACTIVE (KBASE_IPA_NR_BYTES_PER_CNT * 4) #define SC_EXEC_CORE_ACTIVE (KBASE_IPA_NR_BYTES_PER_CNT * 26) +#define SC_EXEC_INSTR_FMA (KBASE_IPA_NR_BYTES_PER_CNT * 27) #define SC_EXEC_INSTR_COUNT (KBASE_IPA_NR_BYTES_PER_CNT * 28) +#define SC_EXEC_INSTR_MSG (KBASE_IPA_NR_BYTES_PER_CNT * 30) +#define SC_TEX_FILT_NUM_OPERATIONS (KBASE_IPA_NR_BYTES_PER_CNT * 39) #define SC_TEX_COORD_ISSUE (KBASE_IPA_NR_BYTES_PER_CNT * 40) #define SC_TEX_TFCH_NUM_OPERATIONS (KBASE_IPA_NR_BYTES_PER_CNT * 42) #define SC_VARY_INSTR (KBASE_IPA_NR_BYTES_PER_CNT * 49) @@ -347,6 +349,40 @@ static const struct kbase_ipa_group ipa_groups_def_g51[] = { }, }; +static const struct kbase_ipa_group ipa_groups_def_g77[] = { + { + .name = "l2_access", + .default_value = 710800, + .op = kbase_g7x_sum_all_memsys_blocks, + .counter_block_offset = MEMSYS_L2_ANY_LOOKUP, + }, + { + .name = "exec_instr_msg", + .default_value = 2375300, + .op = kbase_g7x_sum_all_shader_cores, + .counter_block_offset = SC_EXEC_INSTR_MSG, + }, + { + .name = "exec_instr_fma", + .default_value = 656100, + .op = kbase_g7x_sum_all_shader_cores, + .counter_block_offset = SC_EXEC_INSTR_FMA, + }, + { + .name = "tex_filt_num_operations", + .default_value = 318800, + .op = kbase_g7x_sum_all_shader_cores, + .counter_block_offset = SC_TEX_FILT_NUM_OPERATIONS, + }, + { + .name = "gpu_active", + .default_value = 172800, + .op = kbase_g7x_jm_single_counter, + .counter_block_offset = JM_GPU_ACTIVE, + }, +}; + + #define IPA_POWER_MODEL_OPS(gpu, init_token) \ const struct kbase_ipa_model_ops kbase_ ## gpu ## _ipa_model_ops = { \ .name = "mali-" #gpu "-power-model", \ @@ -378,6 +414,7 @@ STANDARD_POWER_MODEL(g72, 800); STANDARD_POWER_MODEL(g76, 800); STANDARD_POWER_MODEL(g52_r1, 1000); STANDARD_POWER_MODEL(g51, 1000); +STANDARD_POWER_MODEL(g77, 1000); /* g52 is an alias of g76 (TNOX) for IPA */ ALIAS_POWER_MODEL(g52, g76); diff --git a/mali_kbase/mali_base_hwconfig_features.h b/mali_kbase/mali_base_hwconfig_features.h index 78dc8db..bf27180 100644 --- a/mali_kbase/mali_base_hwconfig_features.h +++ b/mali_kbase/mali_base_hwconfig_features.h @@ -353,33 +353,6 @@ static const enum base_hw_feature base_hw_features_tGOx[] = { BASE_HW_FEATURE_END }; -static const enum base_hw_feature base_hw_features_tKAx[] = { - BASE_HW_FEATURE_JOBCHAIN_DISAMBIGUATION, - BASE_HW_FEATURE_PWRON_DURING_PWROFF_TRANS, - BASE_HW_FEATURE_XAFFINITY, - BASE_HW_FEATURE_WARPING, - BASE_HW_FEATURE_INTERPIPE_REG_ALIASING, - BASE_HW_FEATURE_32_BIT_UNIFORM_ADDRESS, - BASE_HW_FEATURE_ATTR_AUTO_TYPE_INFERRAL, - BASE_HW_FEATURE_BRNDOUT_CC, - BASE_HW_FEATURE_BRNDOUT_KILL, - BASE_HW_FEATURE_LD_ST_LEA_TEX, - BASE_HW_FEATURE_LD_ST_TILEBUFFER, - BASE_HW_FEATURE_LINEAR_FILTER_FLOAT, - BASE_HW_FEATURE_MRT, - BASE_HW_FEATURE_MSAA_16X, - BASE_HW_FEATURE_NEXT_INSTRUCTION_TYPE, - BASE_HW_FEATURE_OUT_OF_ORDER_EXEC, - BASE_HW_FEATURE_T7XX_PAIRING_RULES, - BASE_HW_FEATURE_TEST4_DATUM_MODE, - BASE_HW_FEATURE_FLUSH_REDUCTION, - BASE_HW_FEATURE_PROTECTED_MODE, - BASE_HW_FEATURE_PROTECTED_DEBUG_MODE, - BASE_HW_FEATURE_COHERENCY_REG, - BASE_HW_FEATURE_AARCH64_MMU, - BASE_HW_FEATURE_END -}; - static const enum base_hw_feature base_hw_features_tTRx[] = { BASE_HW_FEATURE_JOBCHAIN_DISAMBIGUATION, BASE_HW_FEATURE_PWRON_DURING_PWROFF_TRANS, @@ -523,7 +496,7 @@ static const enum base_hw_feature base_hw_features_tDUx[] = { BASE_HW_FEATURE_END }; -static const enum base_hw_feature base_hw_features_tBOx[] = { +static const enum base_hw_feature base_hw_features_tODx[] = { BASE_HW_FEATURE_JOBCHAIN_DISAMBIGUATION, BASE_HW_FEATURE_PWRON_DURING_PWROFF_TRANS, BASE_HW_FEATURE_XAFFINITY, @@ -548,6 +521,7 @@ static const enum base_hw_feature base_hw_features_tBOx[] = { BASE_HW_FEATURE_COHERENCY_REG, BASE_HW_FEATURE_AARCH64_MMU, BASE_HW_FEATURE_IDVS_GROUP_SIZE, + BASE_HW_FEATURE_L2_CONFIG, BASE_HW_FEATURE_END }; @@ -576,7 +550,6 @@ static const enum base_hw_feature base_hw_features_tIDx[] = { BASE_HW_FEATURE_COHERENCY_REG, BASE_HW_FEATURE_AARCH64_MMU, BASE_HW_FEATURE_IDVS_GROUP_SIZE, - BASE_HW_FEATURE_L2_CONFIG, BASE_HW_FEATURE_END }; diff --git a/mali_kbase/mali_base_hwconfig_issues.h b/mali_kbase/mali_base_hwconfig_issues.h index 59610b4..7964c22 100644 --- a/mali_kbase/mali_base_hwconfig_issues.h +++ b/mali_kbase/mali_base_hwconfig_issues.h @@ -91,8 +91,6 @@ enum base_hw_issue { BASE_HW_ISSUE_10984, BASE_HW_ISSUE_10995, BASE_HW_ISSUE_11012, - BASE_HW_ISSUE_11020, - BASE_HW_ISSUE_11024, BASE_HW_ISSUE_11035, BASE_HW_ISSUE_11042, BASE_HW_ISSUE_11051, @@ -132,6 +130,7 @@ enum base_hw_issue { BASE_HW_ISSUE_TSIX_1792, BASE_HW_ISSUE_TTRX_2968_TTRX_3162, BASE_HW_ISSUE_TTRX_3076, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -194,7 +193,6 @@ static const enum base_hw_issue base_hw_issues_t60x_r0p0_15dev0[] = { BASE_HW_ISSUE_10984, BASE_HW_ISSUE_10995, BASE_HW_ISSUE_11012, - BASE_HW_ISSUE_11020, BASE_HW_ISSUE_11035, BASE_HW_ISSUE_11051, BASE_HW_ISSUE_11054, @@ -236,7 +234,6 @@ static const enum base_hw_issue base_hw_issues_t60x_r0p0_eac[] = { BASE_HW_ISSUE_10946, BASE_HW_ISSUE_10969, BASE_HW_ISSUE_11012, - BASE_HW_ISSUE_11020, BASE_HW_ISSUE_11035, BASE_HW_ISSUE_11051, BASE_HW_ISSUE_11054, @@ -274,7 +271,6 @@ static const enum base_hw_issue base_hw_issues_t60x_r0p1[] = { BASE_HW_ISSUE_10931, BASE_HW_ISSUE_10946, BASE_HW_ISSUE_11012, - BASE_HW_ISSUE_11020, BASE_HW_ISSUE_11035, BASE_HW_ISSUE_11051, BASE_HW_ISSUE_11054, @@ -308,8 +304,6 @@ static const enum base_hw_issue base_hw_issues_t62x_r0p1[] = { BASE_HW_ISSUE_10946, BASE_HW_ISSUE_10959, BASE_HW_ISSUE_11012, - BASE_HW_ISSUE_11020, - BASE_HW_ISSUE_11024, BASE_HW_ISSUE_11035, BASE_HW_ISSUE_11042, BASE_HW_ISSUE_11051, @@ -334,8 +328,6 @@ static const enum base_hw_issue base_hw_issues_t62x_r1p0[] = { BASE_HW_ISSUE_10946, BASE_HW_ISSUE_10959, BASE_HW_ISSUE_11012, - BASE_HW_ISSUE_11020, - BASE_HW_ISSUE_11024, BASE_HW_ISSUE_11042, BASE_HW_ISSUE_11051, BASE_HW_ISSUE_11054, @@ -375,8 +367,6 @@ static const enum base_hw_issue base_hw_issues_t76x_r0p0[] = { BASE_HW_ISSUE_10821, BASE_HW_ISSUE_10883, BASE_HW_ISSUE_10946, - BASE_HW_ISSUE_11020, - BASE_HW_ISSUE_11024, BASE_HW_ISSUE_11042, BASE_HW_ISSUE_11051, BASE_HW_ISSUE_11054, @@ -395,6 +385,7 @@ static const enum base_hw_issue base_hw_issues_t76x_r0p0[] = { BASE_HW_ISSUE_T76X_3979, BASE_HW_ISSUE_TMIX_7891, BASE_HW_ISSUE_TMIX_8438, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -403,8 +394,6 @@ static const enum base_hw_issue base_hw_issues_t76x_r0p1[] = { BASE_HW_ISSUE_10821, BASE_HW_ISSUE_10883, BASE_HW_ISSUE_10946, - BASE_HW_ISSUE_11020, - BASE_HW_ISSUE_11024, BASE_HW_ISSUE_11042, BASE_HW_ISSUE_11051, BASE_HW_ISSUE_11054, @@ -423,6 +412,7 @@ static const enum base_hw_issue base_hw_issues_t76x_r0p1[] = { BASE_HW_ISSUE_T76X_3979, BASE_HW_ISSUE_TMIX_7891, BASE_HW_ISSUE_TMIX_8438, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -449,6 +439,7 @@ static const enum base_hw_issue base_hw_issues_t76x_r0p1_50rel0[] = { BASE_HW_ISSUE_T76X_3979, BASE_HW_ISSUE_TMIX_7891, BASE_HW_ISSUE_TMIX_8438, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -457,8 +448,6 @@ static const enum base_hw_issue base_hw_issues_t76x_r0p2[] = { BASE_HW_ISSUE_10821, BASE_HW_ISSUE_10883, BASE_HW_ISSUE_10946, - BASE_HW_ISSUE_11020, - BASE_HW_ISSUE_11024, BASE_HW_ISSUE_11042, BASE_HW_ISSUE_11051, BASE_HW_ISSUE_11054, @@ -477,6 +466,7 @@ static const enum base_hw_issue base_hw_issues_t76x_r0p2[] = { BASE_HW_ISSUE_T76X_3979, BASE_HW_ISSUE_TMIX_7891, BASE_HW_ISSUE_TMIX_8438, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -503,6 +493,7 @@ static const enum base_hw_issue base_hw_issues_t76x_r0p3[] = { BASE_HW_ISSUE_T76X_3979, BASE_HW_ISSUE_TMIX_7891, BASE_HW_ISSUE_TMIX_8438, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -526,6 +517,7 @@ static const enum base_hw_issue base_hw_issues_t76x_r1p0[] = { BASE_HW_ISSUE_T76X_3979, BASE_HW_ISSUE_TMIX_7891, BASE_HW_ISSUE_TMIX_8438, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -613,8 +605,6 @@ static const enum base_hw_issue base_hw_issues_model_t72x[] = { static const enum base_hw_issue base_hw_issues_model_t76x[] = { BASE_HW_ISSUE_5736, BASE_HW_ISSUE_9435, - BASE_HW_ISSUE_11020, - BASE_HW_ISSUE_11024, BASE_HW_ISSUE_11042, BASE_HW_ISSUE_11051, BASE_HW_ISSUE_T76X_1909, @@ -638,8 +628,6 @@ static const enum base_hw_issue base_hw_issues_model_t60x[] = { BASE_HW_ISSUE_10649, BASE_HW_ISSUE_10931, BASE_HW_ISSUE_11012, - BASE_HW_ISSUE_11020, - BASE_HW_ISSUE_11024, BASE_HW_ISSUE_11051, BASE_HW_ISSUE_T76X_1909, BASE_HW_ISSUE_T76X_1963, @@ -656,8 +644,6 @@ static const enum base_hw_issue base_hw_issues_model_t62x[] = { BASE_HW_ISSUE_10649, BASE_HW_ISSUE_10931, BASE_HW_ISSUE_11012, - BASE_HW_ISSUE_11020, - BASE_HW_ISSUE_11024, BASE_HW_ISSUE_11042, BASE_HW_ISSUE_11051, BASE_HW_ISSUE_T76X_1909, @@ -686,6 +672,7 @@ static const enum base_hw_issue base_hw_issues_tFRx_r0p1[] = { BASE_HW_ISSUE_T76X_3979, BASE_HW_ISSUE_TMIX_7891, BASE_HW_ISSUE_TMIX_8438, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -707,6 +694,7 @@ static const enum base_hw_issue base_hw_issues_tFRx_r0p2[] = { BASE_HW_ISSUE_T76X_3979, BASE_HW_ISSUE_TMIX_7891, BASE_HW_ISSUE_TMIX_8438, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -726,6 +714,7 @@ static const enum base_hw_issue base_hw_issues_tFRx_r1p0[] = { BASE_HW_ISSUE_T76X_3979, BASE_HW_ISSUE_TMIX_7891, BASE_HW_ISSUE_TMIX_8438, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -745,6 +734,7 @@ static const enum base_hw_issue base_hw_issues_tFRx_r2p0[] = { BASE_HW_ISSUE_T76X_3979, BASE_HW_ISSUE_TMIX_7891, BASE_HW_ISSUE_TMIX_8438, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -781,6 +771,7 @@ static const enum base_hw_issue base_hw_issues_t86x_r0p2[] = { BASE_HW_ISSUE_T76X_3979, BASE_HW_ISSUE_TMIX_7891, BASE_HW_ISSUE_TMIX_8438, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -800,6 +791,7 @@ static const enum base_hw_issue base_hw_issues_t86x_r1p0[] = { BASE_HW_ISSUE_T76X_3979, BASE_HW_ISSUE_TMIX_7891, BASE_HW_ISSUE_TMIX_8438, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -819,6 +811,7 @@ static const enum base_hw_issue base_hw_issues_t86x_r2p0[] = { BASE_HW_ISSUE_T76X_3979, BASE_HW_ISSUE_TMIX_7891, BASE_HW_ISSUE_TMIX_8438, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -855,6 +848,7 @@ static const enum base_hw_issue base_hw_issues_t83x_r0p1[] = { BASE_HW_ISSUE_T83X_817, BASE_HW_ISSUE_TMIX_7891, BASE_HW_ISSUE_TMIX_8438, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -876,6 +870,7 @@ static const enum base_hw_issue base_hw_issues_t83x_r1p0[] = { BASE_HW_ISSUE_T83X_817, BASE_HW_ISSUE_TMIX_7891, BASE_HW_ISSUE_TMIX_8438, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -916,6 +911,7 @@ static const enum base_hw_issue base_hw_issues_t82x_r0p0[] = { BASE_HW_ISSUE_T83X_817, BASE_HW_ISSUE_TMIX_7891, BASE_HW_ISSUE_TMIX_8438, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -938,6 +934,7 @@ static const enum base_hw_issue base_hw_issues_t82x_r0p1[] = { BASE_HW_ISSUE_T83X_817, BASE_HW_ISSUE_TMIX_7891, BASE_HW_ISSUE_TMIX_8438, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -959,6 +956,7 @@ static const enum base_hw_issue base_hw_issues_t82x_r1p0[] = { BASE_HW_ISSUE_T83X_817, BASE_HW_ISSUE_TMIX_7891, BASE_HW_ISSUE_TMIX_8438, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -992,6 +990,7 @@ static const enum base_hw_issue base_hw_issues_tMIx_r0p0_05dev0[] = { BASE_HW_ISSUE_TMIX_8456, BASE_HW_ISSUE_TMIX_8438, BASE_HW_ISSUE_TSIX_2033, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -1010,6 +1009,7 @@ static const enum base_hw_issue base_hw_issues_tMIx_r0p0[] = { BASE_HW_ISSUE_TMIX_8456, BASE_HW_ISSUE_TMIX_8438, BASE_HW_ISSUE_TSIX_2033, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -1028,6 +1028,7 @@ static const enum base_hw_issue base_hw_issues_tMIx_r0p1[] = { BASE_HW_ISSUE_TMIX_8456, BASE_HW_ISSUE_TMIX_8438, BASE_HW_ISSUE_TSIX_2033, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -1054,6 +1055,7 @@ static const enum base_hw_issue base_hw_issues_tHEx_r0p0[] = { BASE_HW_ISSUE_TMIX_8042, BASE_HW_ISSUE_TMIX_8133, BASE_HW_ISSUE_TSIX_2033, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -1065,6 +1067,7 @@ static const enum base_hw_issue base_hw_issues_tHEx_r0p1[] = { BASE_HW_ISSUE_TMIX_8042, BASE_HW_ISSUE_TMIX_8133, BASE_HW_ISSUE_TSIX_2033, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -1076,6 +1079,7 @@ static const enum base_hw_issue base_hw_issues_tHEx_r0p2[] = { BASE_HW_ISSUE_TMIX_8042, BASE_HW_ISSUE_TMIX_8133, BASE_HW_ISSUE_TSIX_2033, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -1086,6 +1090,7 @@ static const enum base_hw_issue base_hw_issues_tHEx_r0p3[] = { BASE_HW_ISSUE_TMIX_8042, BASE_HW_ISSUE_TMIX_8133, BASE_HW_ISSUE_TSIX_2033, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -1106,6 +1111,7 @@ static const enum base_hw_issue base_hw_issues_tSIx_r0p0[] = { BASE_HW_ISSUE_TSIX_1116, BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TSIX_1792, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -1116,6 +1122,7 @@ static const enum base_hw_issue base_hw_issues_tSIx_r0p1[] = { BASE_HW_ISSUE_TSIX_1116, BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TSIX_1792, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -1125,6 +1132,7 @@ static const enum base_hw_issue base_hw_issues_tSIx_r1p0[] = { BASE_HW_ISSUE_TMIX_8133, BASE_HW_ISSUE_TSIX_1116, BASE_HW_ISSUE_TSIX_2033, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -1133,6 +1141,7 @@ static const enum base_hw_issue base_hw_issues_tSIx_r1p1[] = { BASE_HW_ISSUE_TMIX_8133, BASE_HW_ISSUE_TSIX_1116, BASE_HW_ISSUE_TSIX_2033, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -1150,6 +1159,7 @@ static const enum base_hw_issue base_hw_issues_tDVx_r0p0[] = { BASE_HW_ISSUE_TMIX_8133, BASE_HW_ISSUE_TSIX_1116, BASE_HW_ISSUE_TSIX_2033, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -1168,6 +1178,7 @@ static const enum base_hw_issue base_hw_issues_tNOx_r0p0[] = { BASE_HW_ISSUE_TSIX_1116, BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TNOX_1194, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -1186,6 +1197,7 @@ static const enum base_hw_issue base_hw_issues_tGOx_r0p0[] = { BASE_HW_ISSUE_TSIX_1116, BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TNOX_1194, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -1195,6 +1207,7 @@ static const enum base_hw_issue base_hw_issues_tGOx_r1p0[] = { BASE_HW_ISSUE_TSIX_1116, BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TGOX_R1_1234, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -1207,23 +1220,6 @@ static const enum base_hw_issue base_hw_issues_model_tGOx[] = { BASE_HW_ISSUE_END }; -static const enum base_hw_issue base_hw_issues_tKAx_r0p0[] = { - BASE_HW_ISSUE_9435, - BASE_HW_ISSUE_TMIX_8133, - BASE_HW_ISSUE_TSIX_1116, - BASE_HW_ISSUE_TSIX_2033, - BASE_HW_ISSUE_END -}; - -static const enum base_hw_issue base_hw_issues_model_tKAx[] = { - BASE_HW_ISSUE_5736, - BASE_HW_ISSUE_9435, - BASE_HW_ISSUE_TMIX_8133, - BASE_HW_ISSUE_TSIX_1116, - BASE_HW_ISSUE_TSIX_2033, - BASE_HW_ISSUE_END -}; - static const enum base_hw_issue base_hw_issues_tTRx_r0p0[] = { BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TMIX_8133, @@ -1231,6 +1227,7 @@ static const enum base_hw_issue base_hw_issues_tTRx_r0p0[] = { BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TTRX_2968_TTRX_3162, BASE_HW_ISSUE_TTRX_3076, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -1241,6 +1238,7 @@ static const enum base_hw_issue base_hw_issues_tTRx_r0p1[] = { BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TTRX_2968_TTRX_3162, BASE_HW_ISSUE_TTRX_3076, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -1260,6 +1258,7 @@ static const enum base_hw_issue base_hw_issues_tNAx_r0p0[] = { BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TTRX_2968_TTRX_3162, BASE_HW_ISSUE_TTRX_3076, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -1270,6 +1269,7 @@ static const enum base_hw_issue base_hw_issues_tNAx_r0p1[] = { BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TTRX_2968_TTRX_3162, BASE_HW_ISSUE_TTRX_3076, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -1288,6 +1288,7 @@ static const enum base_hw_issue base_hw_issues_tBEx_r0p0[] = { BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TTRX_2968_TTRX_3162, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -1305,6 +1306,7 @@ static const enum base_hw_issue base_hw_issues_tULx_r0p0[] = { BASE_HW_ISSUE_TMIX_8133, BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_1337, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -1322,6 +1324,7 @@ static const enum base_hw_issue base_hw_issues_tDUx_r0p0[] = { BASE_HW_ISSUE_TMIX_8133, BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_1337, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; @@ -1334,20 +1337,18 @@ static const enum base_hw_issue base_hw_issues_model_tDUx[] = { BASE_HW_ISSUE_END }; -static const enum base_hw_issue base_hw_issues_tBOx_r0p0[] = { +static const enum base_hw_issue base_hw_issues_tODx_r0p0[] = { BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TMIX_8133, - BASE_HW_ISSUE_TSIX_1116, BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_END }; -static const enum base_hw_issue base_hw_issues_model_tBOx[] = { +static const enum base_hw_issue base_hw_issues_model_tODx[] = { BASE_HW_ISSUE_5736, BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TMIX_8133, - BASE_HW_ISSUE_TSIX_1116, BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_END @@ -1392,6 +1393,7 @@ static const enum base_hw_issue base_hw_issues_tEGx_r0p0[] = { BASE_HW_ISSUE_TMIX_8133, BASE_HW_ISSUE_TSIX_1116, BASE_HW_ISSUE_TSIX_2033, + BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_END }; diff --git a/mali_kbase/mali_base_kernel.h b/mali_kbase/mali_base_kernel.h index 0beb62c..6caf36c 100644 --- a/mali_kbase/mali_base_kernel.h +++ b/mali_kbase/mali_base_kernel.h @@ -663,43 +663,8 @@ typedef u32 base_jd_core_req; #define BASE_JD_REQ_SOFT_FENCE_TRIGGER (BASE_JD_REQ_SOFT_JOB | 0x2) #define BASE_JD_REQ_SOFT_FENCE_WAIT (BASE_JD_REQ_SOFT_JOB | 0x3) -/** - * SW Only requirement : Replay job. - * - * If the preceding job fails, the replay job will cause the jobs specified in - * the list of base_jd_replay_payload pointed to by the jc pointer to be - * replayed. - * - * A replay job will only cause jobs to be replayed up to BASEP_JD_REPLAY_LIMIT - * times. If a job fails more than BASEP_JD_REPLAY_LIMIT times then the replay - * job is failed, as well as any following dependencies. - * - * The replayed jobs will require a number of atom IDs. If there are not enough - * free atom IDs then the replay job will fail. - * - * If the preceding job does not fail, then the replay job is returned as - * completed. - * - * The replayed jobs will never be returned to userspace. The preceding failed - * job will be returned to userspace as failed; the status of this job should - * be ignored. Completion should be determined by the status of the replay soft - * job. - * - * In order for the jobs to be replayed, the job headers will have to be - * modified. The Status field will be reset to NOT_STARTED. If the Job Type - * field indicates a Vertex Shader Job then it will be changed to Null Job. - * - * The replayed jobs have the following assumptions : - * - * - No external resources. Any required external resources will be held by the - * replay atom. - * - Pre-dependencies are created based on job order. - * - Atom numbers are automatically assigned. - * - device_nr is set to 0. This is not relevant as - * BASE_JD_REQ_SPECIFIC_COHERENT_GROUP should not be set. - * - Priority is inherited from the replay job. - */ -#define BASE_JD_REQ_SOFT_REPLAY (BASE_JD_REQ_SOFT_JOB | 0x4) +/* 0x4 RESERVED for now */ + /** * SW only requirement: event wait/trigger job. * @@ -1226,7 +1191,6 @@ typedef enum base_jd_event_code { BASE_JD_EVENT_JOB_CANCELLED = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x002, BASE_JD_EVENT_JOB_INVALID = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x003, BASE_JD_EVENT_PM_EVENT = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x004, - BASE_JD_EVENT_FORCE_REPLAY = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x005, BASE_JD_EVENT_BAG_INVALID = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_BAG | 0x003, @@ -1786,76 +1750,6 @@ static inline int base_context_mmu_group_id_get( * @{ */ -/** - * @brief The payload for a replay job. This must be in GPU memory. - */ -typedef struct base_jd_replay_payload { - /** - * Pointer to the first entry in the base_jd_replay_jc list. These - * will be replayed in @b reverse order (so that extra ones can be added - * to the head in future soft jobs without affecting this soft job) - */ - u64 tiler_jc_list; - - /** - * Pointer to the fragment job chain. - */ - u64 fragment_jc; - - /** - * Pointer to the tiler heap free FBD field to be modified. - */ - u64 tiler_heap_free; - - /** - * Hierarchy mask for the replayed fragment jobs. May be zero. - */ - u16 fragment_hierarchy_mask; - - /** - * Hierarchy mask for the replayed tiler jobs. May be zero. - */ - u16 tiler_hierarchy_mask; - - /** - * Default weight to be used for hierarchy levels not in the original - * mask. - */ - u32 hierarchy_default_weight; - - /** - * Core requirements for the tiler job chain - */ - base_jd_core_req tiler_core_req; - - /** - * Core requirements for the fragment job chain - */ - base_jd_core_req fragment_core_req; -} base_jd_replay_payload; - -/** - * @brief An entry in the linked list of job chains to be replayed. This must - * be in GPU memory. - */ -typedef struct base_jd_replay_jc { - /** - * Pointer to next entry in the list. A setting of NULL indicates the - * end of the list. - */ - u64 next; - - /** - * Pointer to the job chain. - */ - u64 jc; - -} base_jd_replay_jc; - -/* Maximum number of jobs allowed in a fragment chain in the payload of a - * replay job */ -#define BASE_JD_REPLAY_F_CHAIN_JOB_LIMIT 256 - /** @} end group base_api */ /* Enable additional tracepoints for latency measurements (TL_ATOM_READY, diff --git a/mali_kbase/mali_kbase.h b/mali_kbase/mali_kbase.h index a5cdd2a..e3f209c 100644 --- a/mali_kbase/mali_kbase.h +++ b/mali_kbase/mali_kbase.h @@ -82,6 +82,11 @@ #define u64_to_user_ptr(x) ((void __user *)(uintptr_t)x) #endif + +/* Physical memory group ID for a special page which can alias several regions. + */ +#define KBASE_MEM_GROUP_SINK BASE_MEM_GROUP_DEFAULT + /* * Kernel-side Base (KBase) APIs */ @@ -109,7 +114,6 @@ int kbase_device_has_feature(struct kbase_device *kbdev, u32 feature); struct kbase_device *kbase_find_device(int minor); void kbase_release_device(struct kbase_device *kbdev); - /** * kbase_context_get_unmapped_area() - get an address range which is currently * unmapped. @@ -201,6 +205,16 @@ bool jd_submit_atom(struct kbase_context *kctx, struct kbase_jd_atom *katom); void kbase_jd_dep_clear_locked(struct kbase_jd_atom *katom); +/** + * kbase_job_done - Process completed jobs from job interrupt + * @kbdev: Pointer to the kbase device. + * @done: Bitmask of done or failed jobs, from JOB_IRQ_STAT register + * + * This function processes the completed, or failed, jobs from the GPU job + * slots, for the bits set in the @done bitmask. + * + * The hwaccess_lock must be held when calling this function. + */ void kbase_job_done(struct kbase_device *kbdev, u32 done); /** @@ -314,8 +328,6 @@ int kbase_soft_event_update(struct kbase_context *kctx, u64 event, unsigned char new_status); -bool kbase_replay_process(struct kbase_jd_atom *katom); - void kbasep_soft_job_timeout_worker(struct timer_list *timer); void kbasep_complete_triggered_soft_events(struct kbase_context *kctx, u64 evt); @@ -405,9 +417,8 @@ static inline struct kbase_jd_atom *kbase_jd_atom_from_id( * the counter during disjoint events we also increment the counter when jobs may be affected * by what the GPU is currently doing. To facilitate this we have the concept of disjoint state. * - * Disjoint state is entered during GPU reset and for the entire time that an atom is replaying - * (as part of the replay workaround). Increasing the disjoint state also increases the count of - * disjoint events. + * Disjoint state is entered during GPU reset. Increasing the disjoint state also increases + * the count of disjoint events. * * The disjoint state is then used to increase the count of disjoint events during job submission * and job completion. Any atom submitted or completed while the disjoint state is greater than diff --git a/mali_kbase/mali_kbase_as_fault_debugfs.c b/mali_kbase/mali_kbase_as_fault_debugfs.c index 4cc93a9..6f638cc 100644 --- a/mali_kbase/mali_kbase_as_fault_debugfs.c +++ b/mali_kbase/mali_kbase_as_fault_debugfs.c @@ -1,6 +1,6 @@ /* * - * (C) COPYRIGHT 2016-2018 ARM Limited. All rights reserved. + * (C) COPYRIGHT 2016-2019 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the * GNU General Public License version 2 as published by the Free Software @@ -64,6 +64,7 @@ static int kbase_as_fault_debugfs_open(struct inode *in, struct file *file) } static const struct file_operations as_fault_fops = { + .owner = THIS_MODULE, .open = kbase_as_fault_debugfs_open, .read = seq_read, .llseek = seq_lseek, diff --git a/mali_kbase/mali_kbase_context.c b/mali_kbase/mali_kbase_context.c index d4cbb8b..ed482e1 100644 --- a/mali_kbase/mali_kbase_context.c +++ b/mali_kbase/mali_kbase_context.c @@ -121,7 +121,7 @@ kbase_create_context(struct kbase_device *kbdev, bool is_compat, goto term_dma_fence; p = kbase_mem_alloc_page( - &kctx->mem_pools.small[BASE_MEM_GROUP_DEFAULT]); + &kctx->mem_pools.small[KBASE_MEM_GROUP_SINK]); if (!p) goto no_sink_page; kctx->aliasing_sink_page = as_tagged(page_to_phys(p)); @@ -185,7 +185,7 @@ no_sticky: kbase_region_tracker_term(kctx); no_region_tracker: kbase_mem_pool_free( - &kctx->mem_pools.small[BASE_MEM_GROUP_DEFAULT], p, false); + &kctx->mem_pools.small[KBASE_MEM_GROUP_SINK], p, false); no_sink_page: kbase_mmu_term(kbdev, &kctx->mmu); term_dma_fence: @@ -282,7 +282,7 @@ void kbase_destroy_context(struct kbase_context *kctx) /* drop the aliasing sink page now that it can't be mapped anymore */ p = as_page(kctx->aliasing_sink_page); - kbase_mem_pool_free(&kctx->mem_pools.small[BASE_MEM_GROUP_DEFAULT], + kbase_mem_pool_free(&kctx->mem_pools.small[KBASE_MEM_GROUP_SINK], p, false); /* free pending region setups */ diff --git a/mali_kbase/mali_kbase_core_linux.c b/mali_kbase/mali_kbase_core_linux.c index d0d584e..b2b5a08 100644 --- a/mali_kbase/mali_kbase_core_linux.c +++ b/mali_kbase/mali_kbase_core_linux.c @@ -48,8 +48,8 @@ #include <mali_kbase_hwaccess_backend.h> #include <mali_kbase_hwaccess_jm.h> #include <mali_kbase_ctx_sched.h> +#include <mali_kbase_reset_gpu.h> #include <backend/gpu/mali_kbase_device_internal.h> -#include <backend/gpu/mali_kbase_pm_internal.h> #include "mali_kbase_ioctl.h" #include "mali_kbase_hwcnt_context.h" #include "mali_kbase_hwcnt_virtualizer.h" @@ -83,6 +83,7 @@ #include <mali_kbase_sync.h> #endif /* CONFIG_SYNC || CONFIG_SYNC_FILE */ #include <linux/clk.h> +#include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/log2.h> @@ -467,6 +468,7 @@ void kbase_release_device(struct kbase_device *kbdev) } EXPORT_SYMBOL(kbase_release_device); +#ifdef CONFIG_DEBUG_FS #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 6, 0) && \ !(LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 28) && \ LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)) @@ -521,6 +523,7 @@ static ssize_t read_ctx_infinite_cache(struct file *f, char __user *ubuf, size_t } static const struct file_operations kbase_infinite_cache_fops = { + .owner = THIS_MODULE, .open = simple_open, .write = write_ctx_infinite_cache, .read = read_ctx_infinite_cache, @@ -570,10 +573,12 @@ static ssize_t read_ctx_force_same_va(struct file *f, char __user *ubuf, } static const struct file_operations kbase_force_same_va_fops = { + .owner = THIS_MODULE, .open = simple_open, .write = write_ctx_force_same_va, .read = read_ctx_force_same_va, }; +#endif /* CONFIG_DEBUG_FS */ static int kbase_file_create_kctx(struct kbase_file *const kfile, base_context_create_flags const flags) @@ -1291,6 +1296,7 @@ static int kbase_api_tlstream_stats(struct kbase_context *kctx, int ret, err; \ BUILD_BUG_ON(_IOC_DIR(cmd) != _IOC_READ); \ BUILD_BUG_ON(sizeof(param) != _IOC_SIZE(cmd)); \ + memset(¶m, 0, sizeof(param)); \ ret = function(arg, ¶m); \ err = copy_to_user(uarg, ¶m, sizeof(param)); \ if (err) \ @@ -2320,109 +2326,6 @@ static ssize_t show_js_scheduling_period(struct device *dev, static DEVICE_ATTR(js_scheduling_period, S_IRUGO | S_IWUSR, show_js_scheduling_period, set_js_scheduling_period); -#if !MALI_CUSTOMER_RELEASE -/** - * set_force_replay - Store callback for the force_replay sysfs file. - * - * @dev: The device with sysfs file is for - * @attr: The attributes of the sysfs file - * @buf: The value written to the sysfs file - * @count: The number of bytes written to the sysfs file - * - * Return: @count if the function succeeded. An error code on failure. - */ -static ssize_t set_force_replay(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) -{ - struct kbase_device *kbdev; - - kbdev = to_kbase_device(dev); - if (!kbdev) - return -ENODEV; - - if (!strncmp("limit=", buf, MIN(6, count))) { - int force_replay_limit; - int items = sscanf(buf, "limit=%u", &force_replay_limit); - - if (items == 1) { - kbdev->force_replay_random = false; - kbdev->force_replay_limit = force_replay_limit; - kbdev->force_replay_count = 0; - - return count; - } - } else if (!strncmp("random_limit", buf, MIN(12, count))) { - kbdev->force_replay_random = true; - kbdev->force_replay_count = 0; - - return count; - } else if (!strncmp("norandom_limit", buf, MIN(14, count))) { - kbdev->force_replay_random = false; - kbdev->force_replay_limit = KBASEP_FORCE_REPLAY_DISABLED; - kbdev->force_replay_count = 0; - - return count; - } else if (!strncmp("core_req=", buf, MIN(9, count))) { - unsigned int core_req; - int items = sscanf(buf, "core_req=%x", &core_req); - - if (items == 1) { - kbdev->force_replay_core_req = (base_jd_core_req)core_req; - - return count; - } - } - dev_err(kbdev->dev, "Couldn't process force_replay write operation.\nPossible settings: limit=<limit>, random_limit, norandom_limit, core_req=<core_req>\n"); - return -EINVAL; -} - -/** - * show_force_replay - Show callback for the force_replay sysfs file. - * - * This function is called to get the contents of the force_replay sysfs - * file. It returns the last set value written to the force_replay sysfs file. - * If the file didn't get written yet, the values will be 0. - * - * @dev: The device this sysfs file is for - * @attr: The attributes of the sysfs file - * @buf: The output buffer for the sysfs file contents - * - * Return: The number of bytes output to @buf. - */ -static ssize_t show_force_replay(struct device *dev, - struct device_attribute *attr, char * const buf) -{ - struct kbase_device *kbdev; - ssize_t ret; - - kbdev = to_kbase_device(dev); - if (!kbdev) - return -ENODEV; - - if (kbdev->force_replay_random) - ret = scnprintf(buf, PAGE_SIZE, - "limit=0\nrandom_limit\ncore_req=%x\n", - kbdev->force_replay_core_req); - else - ret = scnprintf(buf, PAGE_SIZE, - "limit=%u\nnorandom_limit\ncore_req=%x\n", - kbdev->force_replay_limit, - kbdev->force_replay_core_req); - - if (ret >= PAGE_SIZE) { - buf[PAGE_SIZE - 2] = '\n'; - buf[PAGE_SIZE - 1] = '\0'; - ret = PAGE_SIZE - 1; - } - - return ret; -} - -/* - * The sysfs file force_replay. - */ -static DEVICE_ATTR(force_replay, S_IRUGO | S_IWUSR, show_force_replay, - set_force_replay); -#endif /* !MALI_CUSTOMER_RELEASE */ #ifdef CONFIG_MALI_DEBUG static ssize_t set_js_softstop_always(struct device *dev, @@ -2626,6 +2529,8 @@ static ssize_t kbase_show_gpuinfo(struct device *dev, .name = "Mali-G31" }, { .id = GPU_ID2_PRODUCT_TGOX >> GPU_ID_VERSION_PRODUCT_ID_SHIFT, .name = "Mali-G52" }, + { .id = GPU_ID2_PRODUCT_TTRX >> GPU_ID_VERSION_PRODUCT_ID_SHIFT, + .name = "Mali-G77" }, }; const char *product_name = "(Unknown Mali GPU)"; struct kbase_device *kbdev; @@ -3141,6 +3046,8 @@ static ssize_t set_js_ctx_scheduling_mode(struct device *dev, static DEVICE_ATTR(js_ctx_scheduling_mode, S_IRUGO | S_IWUSR, show_js_ctx_scheduling_mode, set_js_ctx_scheduling_mode); + +#ifdef MALI_KBASE_BUILD #ifdef CONFIG_DEBUG_FS /* Number of entries in serialize_jobs_settings[] */ @@ -3257,6 +3164,7 @@ static int kbasep_serialize_jobs_debugfs_open(struct inode *in, } static const struct file_operations kbasep_serialize_jobs_debugfs_fops = { + .owner = THIS_MODULE, .open = kbasep_serialize_jobs_debugfs_open, .read = seq_read, .write = kbasep_serialize_jobs_debugfs_write, @@ -3265,6 +3173,7 @@ static const struct file_operations kbasep_serialize_jobs_debugfs_fops = { }; #endif /* CONFIG_DEBUG_FS */ +#endif /* MALI_KBASE_BUILD */ static void kbasep_protected_mode_hwcnt_disable_worker(struct work_struct *data) { @@ -3462,101 +3371,168 @@ static void registers_unmap(struct kbase_device *kbdev) static int power_control_init(struct platform_device *pdev) { +#if KERNEL_VERSION(3, 18, 0) > LINUX_VERSION_CODE || !defined(CONFIG_OF) + /* Power control initialization requires at least the capability to get + * regulators and clocks from the device tree, as well as parsing + * arrays of unsigned integer values. + * + * The whole initialization process shall simply be skipped if the + * minimum capability is not available. + */ + return 0; +#else struct kbase_device *kbdev = to_kbase_device(&pdev->dev); int err = 0; + unsigned int i; +#if defined(CONFIG_REGULATOR) + static const char *regulator_names[] = { + "mali", "shadercores" + }; + BUILD_BUG_ON(ARRAY_SIZE(regulator_names) < BASE_MAX_NR_CLOCKS_REGULATORS); +#endif /* CONFIG_REGULATOR */ if (!kbdev) return -ENODEV; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 12, 0)) && defined(CONFIG_OF) \ - && defined(CONFIG_REGULATOR) - kbdev->regulator = regulator_get_optional(kbdev->dev, "mali"); - if (IS_ERR_OR_NULL(kbdev->regulator)) { - err = PTR_ERR(kbdev->regulator); - kbdev->regulator = NULL; - if (err == -EPROBE_DEFER) { - dev_err(&pdev->dev, "Failed to get regulator\n"); - return err; +#if defined(CONFIG_REGULATOR) + /* Since the error code EPROBE_DEFER causes the entire probing + * procedure to be restarted from scratch at a later time, + * all regulators will be released before returning. + * + * Any other error is ignored and the driver will continue + * operating with a partial initialization of regulators. + */ + for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { + kbdev->regulators[i] = regulator_get_optional(kbdev->dev, + regulator_names[i]); + if (IS_ERR_OR_NULL(kbdev->regulators[i])) { + err = PTR_ERR(kbdev->regulators[i]); + kbdev->regulators[i] = NULL; + break; } - dev_info(kbdev->dev, - "Continuing without Mali regulator control\n"); - /* Allow probe to continue without regulator */ } -#endif /* LINUX_VERSION_CODE >= 3, 12, 0 */ + if (err == -EPROBE_DEFER) { + while ((i > 0) && (i < BASE_MAX_NR_CLOCKS_REGULATORS)) + regulator_put(kbdev->regulators[--i]); + return err; + } + + kbdev->nr_regulators = i; + dev_dbg(&pdev->dev, "Regulators probed: %u\n", kbdev->nr_regulators); +#endif - kbdev->clock = of_clk_get(kbdev->dev->of_node, 0); - if (IS_ERR_OR_NULL(kbdev->clock)) { - err = PTR_ERR(kbdev->clock); - kbdev->clock = NULL; - if (err == -EPROBE_DEFER) { - dev_err(&pdev->dev, "Failed to get clock\n"); - goto fail; + /* Having more clocks than regulators is acceptable, while the + * opposite shall not happen. + * + * Since the error code EPROBE_DEFER causes the entire probing + * procedure to be restarted from scratch at a later time, + * all clocks and regulators will be released before returning. + * + * Any other error is ignored and the driver will continue + * operating with a partial initialization of clocks. + */ + for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { + kbdev->clocks[i] = of_clk_get(kbdev->dev->of_node, i); + if (IS_ERR_OR_NULL(kbdev->clocks[i])) { + err = PTR_ERR(kbdev->clocks[i]); + kbdev->clocks[i] = NULL; + break; } - dev_info(kbdev->dev, "Continuing without Mali clock control\n"); - /* Allow probe to continue without clock. */ - } else { - err = clk_prepare_enable(kbdev->clock); + + err = clk_prepare_enable(kbdev->clocks[i]); if (err) { dev_err(kbdev->dev, "Failed to prepare and enable clock (%d)\n", err); - goto fail; + clk_put(kbdev->clocks[i]); + break; + } + } + if (err == -EPROBE_DEFER) { + while ((i > 0) && (i < BASE_MAX_NR_CLOCKS_REGULATORS)) { + clk_disable_unprepare(kbdev->clocks[--i]); + clk_put(kbdev->clocks[i]); } + goto clocks_probe_defer; } -#if defined(CONFIG_OF) && defined(CONFIG_PM_OPP) - /* Register the OPPs if they are available in device tree */ -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) \ - || defined(LSK_OPPV2_BACKPORT) - err = dev_pm_opp_of_add_table(kbdev->dev); -#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0)) + kbdev->nr_clocks = i; + dev_dbg(&pdev->dev, "Clocks probed: %u\n", kbdev->nr_clocks); + + /* Any error in parsing the OPP table from the device file + * shall be ignored. The fact that the table may be absent or wrong + * on the device tree of the platform shouldn't prevent the driver + * from completing its initialization. + */ +#if (KERNEL_VERSION(4, 4, 0) > LINUX_VERSION_CODE && \ + !defined(LSK_OPPV2_BACKPORT)) err = of_init_opp_table(kbdev->dev); + CSTD_UNUSED(err); #else - err = 0; -#endif /* LINUX_VERSION_CODE */ - if (err) - dev_dbg(kbdev->dev, "OPP table not found\n"); -#endif /* CONFIG_OF && CONFIG_PM_OPP */ - return 0; - -fail: +#if defined(CONFIG_PM_OPP) +#if ((KERNEL_VERSION(4, 10, 0) <= LINUX_VERSION_CODE) && \ + defined(CONFIG_REGULATOR)) + if (kbdev->nr_regulators > 0) { + kbdev->opp_table = dev_pm_opp_set_regulators(kbdev->dev, + regulator_names, BASE_MAX_NR_CLOCKS_REGULATORS); + } +#endif /* (KERNEL_VERSION(4, 10, 0) <= LINUX_VERSION_CODE */ + err = dev_pm_opp_of_add_table(kbdev->dev); + CSTD_UNUSED(err); +#endif /* CONFIG_PM_OPP */ -if (kbdev->clock != NULL) { - clk_put(kbdev->clock); - kbdev->clock = NULL; -} +#endif /* KERNEL_VERSION(4, 4, 0) > LINUX_VERSION_CODE */ + return 0; -#ifdef CONFIG_REGULATOR - if (NULL != kbdev->regulator) { - regulator_put(kbdev->regulator); - kbdev->regulator = NULL; - } +clocks_probe_defer: +#if defined(CONFIG_REGULATOR) + for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) + regulator_put(kbdev->regulators[i]); #endif - return err; +#endif /* KERNEL_VERSION(3, 18, 0) > LINUX_VERSION_CODE */ } static void power_control_term(struct kbase_device *kbdev) { -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) || \ - defined(LSK_OPPV2_BACKPORT) - dev_pm_opp_of_remove_table(kbdev->dev); -#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) + unsigned int i; + +#if (KERNEL_VERSION(4, 4, 0) > LINUX_VERSION_CODE && \ + !defined(LSK_OPPV2_BACKPORT)) +#if KERNEL_VERSION(3, 19, 0) <= LINUX_VERSION_CODE of_free_opp_table(kbdev->dev); #endif +#else - if (kbdev->clock) { - clk_disable_unprepare(kbdev->clock); - clk_put(kbdev->clock); - kbdev->clock = NULL; +#if defined(CONFIG_PM_OPP) + dev_pm_opp_of_remove_table(kbdev->dev); +#if ((KERNEL_VERSION(4, 10, 0) <= LINUX_VERSION_CODE) && \ + defined(CONFIG_REGULATOR)) + if (!IS_ERR_OR_NULL(kbdev->opp_table)) + dev_pm_opp_put_regulators(kbdev->opp_table); +#endif /* (KERNEL_VERSION(4, 10, 0) <= LINUX_VERSION_CODE */ +#endif /* CONFIG_PM_OPP */ + +#endif /* KERNEL_VERSION(4, 4, 0) > LINUX_VERSION_CODE */ + + for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { + if (kbdev->clocks[i]) { + if (__clk_is_enabled(kbdev->clocks[i])) + clk_disable_unprepare(kbdev->clocks[i]); + clk_put(kbdev->clocks[i]); + kbdev->clocks[i] = NULL; + } else + break; } #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 12, 0)) && defined(CONFIG_OF) \ && defined(CONFIG_REGULATOR) - if (kbdev->regulator) { - regulator_put(kbdev->regulator); - kbdev->regulator = NULL; + for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { + if (kbdev->regulators[i]) { + regulator_put(kbdev->regulators[i]); + kbdev->regulators[i] = NULL; + } } #endif /* LINUX_VERSION_CODE >= 3, 12, 0 */ } @@ -3564,8 +3540,6 @@ static void power_control_term(struct kbase_device *kbdev) #ifdef MALI_KBASE_BUILD #ifdef CONFIG_DEBUG_FS -#include <mali_kbase_hwaccess_jm.h> - static void trigger_quirks_reload(struct kbase_device *kbdev) { kbase_pm_context_active(kbdev); @@ -3637,6 +3611,7 @@ static ssize_t debugfs_protected_debug_mode_read(struct file *file, * Contains the file operations for the "protected_debug_mode" debugfs file */ static const struct file_operations fops_protected_debug_mode = { + .owner = THIS_MODULE, .open = simple_open, .read = debugfs_protected_debug_mode_read, .llseek = default_llseek, @@ -3764,11 +3739,10 @@ static int kbase_device_debugfs_init(struct kbase_device *kbdev) #endif /* CONFIG_DEVFREQ_THERMAL */ #endif /* CONFIG_MALI_DEVFREQ */ -#ifdef CONFIG_DEBUG_FS debugfs_create_file("serialize_jobs", S_IRUGO | S_IWUSR, kbdev->mali_debugfs_directory, kbdev, &kbasep_serialize_jobs_debugfs_fops); -#endif /* CONFIG_DEBUG_FS */ + return 0; @@ -3868,9 +3842,6 @@ static struct attribute *kbase_attrs[] = { &dev_attr_debug_command.attr, &dev_attr_js_softstop_always.attr, #endif -#if !MALI_CUSTOMER_RELEASE - &dev_attr_force_replay.attr, -#endif &dev_attr_js_timeouts.attr, &dev_attr_soft_job_timeout.attr, &dev_attr_gpuinfo.attr, diff --git a/mali_kbase/mali_kbase_debug_job_fault.c b/mali_kbase/mali_kbase_debug_job_fault.c index 88bb0d3..4873474 100644 --- a/mali_kbase/mali_kbase_debug_job_fault.c +++ b/mali_kbase/mali_kbase_debug_job_fault.c @@ -1,6 +1,6 @@ /* * - * (C) COPYRIGHT 2012-2016, 2018 ARM Limited. All rights reserved. + * (C) COPYRIGHT 2012-2016, 2018-2019 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the * GNU General Public License version 2 as published by the Free Software @@ -86,6 +86,20 @@ static bool kbase_ctx_has_no_event_pending(struct kbase_context *kctx) return true; } +static int wait_for_job_fault(struct kbase_device *kbdev) +{ +#if KERNEL_VERSION(4, 7, 0) <= LINUX_VERSION_CODE && \ + KERNEL_VERSION(4, 15, 0) > LINUX_VERSION_CODE + if (!kbase_is_job_fault_event_pending(kbdev)) + return -EAGAIN; + else + return 0; +#else + return wait_event_interruptible(kbdev->job_fault_wq, + kbase_is_job_fault_event_pending(kbdev)); +#endif +} + /* wait until the fault happen and copy the event */ static int kbase_job_fault_event_wait(struct kbase_device *kbdev, struct base_job_fault_event *event) @@ -96,10 +110,14 @@ static int kbase_job_fault_event_wait(struct kbase_device *kbdev, spin_lock_irqsave(&kbdev->job_fault_event_lock, flags); while (list_empty(event_list)) { + int err; + spin_unlock_irqrestore(&kbdev->job_fault_event_lock, flags); - if (wait_event_interruptible(kbdev->job_fault_wq, - kbase_is_job_fault_event_pending(kbdev))) - return -ERESTARTSYS; + + err = wait_for_job_fault(kbdev); + if (err) + return err; + spin_lock_irqsave(&kbdev->job_fault_event_lock, flags); } @@ -440,6 +458,7 @@ static int debug_job_fault_release(struct inode *in, struct file *file) } static const struct file_operations kbasep_debug_job_fault_fops = { + .owner = THIS_MODULE, .open = debug_job_fault_open, .read = seq_read, .llseek = seq_lseek, diff --git a/mali_kbase/mali_kbase_debug_mem_view.c b/mali_kbase/mali_kbase_debug_mem_view.c index 5cfc6d1..c091f16 100644 --- a/mali_kbase/mali_kbase_debug_mem_view.c +++ b/mali_kbase/mali_kbase_debug_mem_view.c @@ -284,6 +284,7 @@ static int debug_mem_release(struct inode *inode, struct file *file) } static const struct file_operations kbase_debug_mem_view_fops = { + .owner = THIS_MODULE, .open = debug_mem_open, .release = debug_mem_release, .read = seq_read, diff --git a/mali_kbase/mali_kbase_debugfs_helper.c b/mali_kbase/mali_kbase_debugfs_helper.c index 747364d..0df75dd 100644 --- a/mali_kbase/mali_kbase_debugfs_helper.c +++ b/mali_kbase/mali_kbase_debugfs_helper.c @@ -147,7 +147,7 @@ int kbase_debugfs_helper_seq_write(struct file *const file, return -EINVAL; buf = kmalloc(count + 1, GFP_KERNEL); - if (ZERO_OR_NULL_PTR(buf)) + if (buf == NULL) return -ENOMEM; if (copy_from_user(buf, ubuf, count)) { diff --git a/mali_kbase/mali_kbase_defs.h b/mali_kbase/mali_kbase_defs.h index 93edef1..afd7545 100644 --- a/mali_kbase/mali_kbase_defs.h +++ b/mali_kbase/mali_kbase_defs.h @@ -165,11 +165,6 @@ #include "mali_kbase_js_defs.h" #include "mali_kbase_hwaccess_defs.h" -#define KBASEP_FORCE_REPLAY_DISABLED 0 - -/* Maximum force replay limit when randomization is enabled */ -#define KBASEP_FORCE_REPLAY_RANDOM_LIMIT 16 - /* Maximum number of pages of memory that require a permanent mapping, per * kbase_context */ @@ -238,6 +233,18 @@ */ #define KBASE_HWCNT_GPU_VIRTUALIZER_DUMP_THRESHOLD_NS (200 * NSEC_PER_USEC) +/* Maximum number of clock/regulator pairs that may be referenced by + * the device node. + * This is dependent on support for of_property_read_u64_array() in the + * kernel. + */ +#if (KERNEL_VERSION(4, 0, 0) <= LINUX_VERSION_CODE) || \ + defined(LSK_OPPV2_BACKPORT) +#define BASE_MAX_NR_CLOCKS_REGULATORS (2) +#else +#define BASE_MAX_NR_CLOCKS_REGULATORS (1) +#endif + /* Forward declarations */ struct kbase_context; struct kbase_device; @@ -549,8 +556,6 @@ struct kbase_ext_res { * @slot_nr: Job slot chosen for the atom. * @atom_flags: bitmask of KBASE_KATOM_FLAG* flags capturing the exact * low level state of the atom. - * @retry_count: Number of times this atom has been retried. Used by replay - * soft job. * @gpu_rb_state: bitmnask of KBASE_ATOM_GPU_RB_* flags, precisely tracking * atom's state after it has entered Job scheduler on becoming * runnable. Atom could be blocked due to cross slot dependency @@ -1164,15 +1169,17 @@ struct kbase_mem_pool_group_config { /** * struct kbase_devfreq_opp - Lookup table for converting between nominal OPP - * frequency, and real frequency and core mask + * frequency, real frequencies and core mask + * @real_freqs: Real GPU frequencies. + * @opp_volts: OPP voltages. * @opp_freq: Nominal OPP frequency - * @real_freq: Real GPU frequency * @core_mask: Shader core mask */ struct kbase_devfreq_opp { u64 opp_freq; - u64 real_freq; u64 core_mask; + u64 real_freqs[BASE_MAX_NR_CLOCKS_REGULATORS]; + u32 opp_volts[BASE_MAX_NR_CLOCKS_REGULATORS]; }; /* MMU mode flags */ @@ -1205,10 +1212,10 @@ struct kbase_mmu_mode { struct kbase_mmu_setup * const setup); void (*disable_as)(struct kbase_device *kbdev, int as_nr); phys_addr_t (*pte_to_phy_addr)(u64 entry); - int (*ate_is_valid)(u64 ate, unsigned int level); - int (*pte_is_valid)(u64 pte, unsigned int level); + int (*ate_is_valid)(u64 ate, int level); + int (*pte_is_valid)(u64 pte, int level); void (*entry_set_ate)(u64 *entry, struct tagged_addr phy, - unsigned long flags, unsigned int level); + unsigned long flags, int level); void (*entry_set_pte)(u64 *entry, phys_addr_t phy); void (*entry_invalidate)(u64 *entry); unsigned long flags; @@ -1278,10 +1285,15 @@ struct kbase_devfreq_queue_info { * @irqs: Array containing IRQ resource info for 3 types of * interrupts : Job scheduling, MMU & GPU events (like * power management, cache etc.) - * @clock: Pointer to the input clock resource (having an id of 0), - * referenced by the GPU device node. - * @regulator: Pointer to the struct corresponding to the regulator - * for GPU device + * @clocks: Pointer to the input clock resources referenced by + * the GPU device node. + * @nr_clocks: Number of clocks set in the clocks array. + * @regulators: Pointer to the structs corresponding to the + * regulators referenced by the GPU device node. + * @nr_regulators: Number of regulators set in the regulators array. + * @opp_table: Pointer to the device OPP structure maintaining the + * link to OPPs attached to a device. This is obtained + * after setting regulator names for the device. * @devname: string containing the name used for GPU device instance, * miscellaneous device is registered using the same name. * @id: Unique identifier for the device, indicates the number of @@ -1377,24 +1389,27 @@ struct kbase_devfreq_queue_info { * GPU device. * @devfreq: Pointer to devfreq structure for Mali GPU device, * returned on the call to devfreq_add_device(). - * @current_freq: The real frequency, corresponding to @current_nominal_freq, - * at which the Mali GPU device is currently operating, as - * retrieved from @opp_table in the target callback of + * @current_freqs: The real frequencies, corresponding to + * @current_nominal_freq, at which the Mali GPU device + * is currently operating, as retrieved from + * @devfreq_table in the target callback of * @devfreq_profile. * @current_nominal_freq: The nominal frequency currently used for the Mali GPU * device as retrieved through devfreq_recommended_opp() * using the freq value passed as an argument to target * callback of @devfreq_profile - * @current_voltage: The voltage corresponding to @current_nominal_freq, as - * retrieved through dev_pm_opp_get_voltage(). + * @current_voltages: The voltages corresponding to @current_nominal_freq, + * as retrieved from @devfreq_table in the target + * callback of @devfreq_profile. * @current_core_mask: bitmask of shader cores that are currently desired & * enabled, corresponding to @current_nominal_freq as - * retrieved from @opp_table in the target callback of - * @devfreq_profile. - * @opp_table: Pointer to the lookup table for converting between nominal - * OPP (operating performance point) frequency, and real - * frequency and core mask. This table is constructed according - * to operating-points-v2-mali table in devicetree. + * retrieved from @devfreq_table in the target callback + * of @devfreq_profile. + * @devfreq_table: Pointer to the lookup table for converting between + * nominal OPP (operating performance point) frequency, + * and real frequency and core mask. This table is + * constructed according to operating-points-v2-mali + * table in devicetree. * @num_opps: Number of operating performance points available for the Mali * GPU device. * @devfreq_queue: Per device object for storing data that manages devfreq @@ -1428,18 +1443,6 @@ struct kbase_devfreq_queue_info { * @job_fault_event_lock: Lock to protect concurrent accesses to @job_fault_event_list * @regs_dump_debugfs_data: Contains the offset of register to be read through debugfs * file "read_register". - * @force_replay_limit: Number of gpu jobs, having replay atoms associated with them, - * that are run before a job is forced to fail and replay. - * Set to 0 to disable forced failures. - * @force_replay_count: Count of gpu jobs, having replay atoms associated with them, - * between forced failures. Incremented on each gpu job which - * has replay atoms dependent on it. A gpu job is forced to - * fail once this is greater than or equal to @force_replay_limit - * @force_replay_core_req: Core requirements, set through the sysfs file, for the replay - * job atoms to consider the associated gpu job for forceful - * failure and replay. May be zero - * @force_replay_random: Set to 1 to randomize the @force_replay_limit, in the - * range of 1 - KBASEP_FORCE_REPLAY_RANDOM_LIMIT. * @ctx_num: Total number of contexts created for the device. * @io_history: Pointer to an object keeping a track of all recent * register accesses. The history of register accesses @@ -1520,10 +1523,15 @@ struct kbase_device { int flags; } irqs[3]; - struct clk *clock; + struct clk *clocks[BASE_MAX_NR_CLOCKS_REGULATORS]; + unsigned int nr_clocks; #ifdef CONFIG_REGULATOR - struct regulator *regulator; -#endif + struct regulator *regulators[BASE_MAX_NR_CLOCKS_REGULATORS]; + unsigned int nr_regulators; +#if (KERNEL_VERSION(4, 10, 0) <= LINUX_VERSION_CODE) + struct opp_table *opp_table; +#endif /* (KERNEL_VERSION(4, 10, 0) <= LINUX_VERSION_CODE */ +#endif /* CONFIG_REGULATOR */ char devname[DEVNAME_SIZE]; u32 id; @@ -1604,11 +1612,11 @@ struct kbase_device { #ifdef CONFIG_MALI_DEVFREQ struct devfreq_dev_profile devfreq_profile; struct devfreq *devfreq; - unsigned long current_freq; + unsigned long current_freqs[BASE_MAX_NR_CLOCKS_REGULATORS]; unsigned long current_nominal_freq; - unsigned long current_voltage; + unsigned long current_voltages[BASE_MAX_NR_CLOCKS_REGULATORS]; u64 current_core_mask; - struct kbase_devfreq_opp *opp_table; + struct kbase_devfreq_opp *devfreq_table; int num_opps; struct kbasep_pm_metrics last_devfreq_metrics; @@ -1666,14 +1674,6 @@ struct kbase_device { #endif /* !MALI_CUSTOMER_RELEASE */ #endif /* CONFIG_DEBUG_FS */ - -#if MALI_CUSTOMER_RELEASE == 0 - int force_replay_limit; - int force_replay_count; - base_jd_core_req force_replay_core_req; - bool force_replay_random; -#endif - atomic_t ctx_num; #ifdef CONFIG_DEBUG_FS @@ -1923,8 +1923,7 @@ struct kbase_sub_alloc { * should stop posting events and also inform event handling * thread that context termination is in progress. * @event_workq: Workqueue for processing work items corresponding to atoms - * that do not return an event to Userspace or have to perform - * a replay job + * that do not return an event to userspace. * @event_count: Count of the posted events to be consumed by Userspace. * @event_coalesce_count: Count of the events present in @event_coalesce_list. * @flags: bitmap of enums from kbase_context_flags, indicating the @@ -2350,9 +2349,6 @@ static inline bool kbase_device_is_cpu_coherent(struct kbase_device *kbdev) /* Maximum number of loops polling the GPU for an AS command to complete before we assume the GPU has hung */ #define KBASE_AS_INACTIVE_MAX_LOOPS 100000 -/* Maximum number of times a job can be replayed */ -#define BASEP_JD_REPLAY_LIMIT 15 - /* JobDescriptorHeader - taken from the architecture specifications, the layout * is currently identical for all GPU archs. */ struct job_descriptor_header { diff --git a/mali_kbase/mali_kbase_device.c b/mali_kbase/mali_kbase_device.c index 16535ec..a265082 100644 --- a/mali_kbase/mali_kbase_device.c +++ b/mali_kbase/mali_kbase_device.c @@ -68,21 +68,11 @@ struct kbase_device *kbase_device_alloc(void) static int kbase_device_as_init(struct kbase_device *kbdev, int i) { - const char format[] = "mali_mmu%d"; - char name[sizeof(format)]; - const char poke_format[] = "mali_mmu%d_poker"; - char poke_name[sizeof(poke_format)]; - - if (kbase_hw_has_issue(kbdev, BASE_HW_ISSUE_8316)) - snprintf(poke_name, sizeof(poke_name), poke_format, i); - - snprintf(name, sizeof(name), format, i); - kbdev->as[i].number = i; kbdev->as[i].bf_data.addr = 0ULL; kbdev->as[i].pf_data.addr = 0ULL; - kbdev->as[i].pf_wq = alloc_workqueue(name, 0, 1); + kbdev->as[i].pf_wq = alloc_workqueue("mali_mmu%d", 0, 1, i); if (!kbdev->as[i].pf_wq) return -EINVAL; @@ -93,7 +83,8 @@ static int kbase_device_as_init(struct kbase_device *kbdev, int i) struct hrtimer *poke_timer = &kbdev->as[i].poke_timer; struct work_struct *poke_work = &kbdev->as[i].poke_work; - kbdev->as[i].poke_wq = alloc_workqueue(poke_name, 0, 1); + kbdev->as[i].poke_wq = + alloc_workqueue("mali_mmu%d_poker", 0, 1, i); if (!kbdev->as[i].poke_wq) { destroy_workqueue(kbdev->as[i].pf_wq); return -EINVAL; @@ -502,6 +493,7 @@ static int kbasep_trace_debugfs_open(struct inode *inode, struct file *file) } static const struct file_operations kbasep_trace_debugfs_fops = { + .owner = THIS_MODULE, .open = kbasep_trace_debugfs_open, .read = seq_read, .llseek = seq_lseek, diff --git a/mali_kbase/mali_kbase_fence.c b/mali_kbase/mali_kbase_fence.c index 3272836..96a6ab9 100644 --- a/mali_kbase/mali_kbase_fence.c +++ b/mali_kbase/mali_kbase_fence.c @@ -1,6 +1,6 @@ /* * - * (C) COPYRIGHT 2011-2018 ARM Limited. All rights reserved. + * (C) COPYRIGHT 2011-2019 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the * GNU General Public License version 2 as published by the Free Software @@ -67,7 +67,11 @@ kbase_fence_fence_value_str(struct fence *fence, char *str, int size) kbase_fence_fence_value_str(struct dma_fence *fence, char *str, int size) #endif { +#if (KERNEL_VERSION(5, 1, 0) > LINUX_VERSION_CODE) snprintf(str, size, "%u", fence->seqno); +#else + snprintf(str, size, "%llu", fence->seqno); +#endif } #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 10, 0)) diff --git a/mali_kbase/mali_kbase_gator_api.c b/mali_kbase/mali_kbase_gator_api.c deleted file mode 100644 index 1d97662..0000000 --- a/mali_kbase/mali_kbase_gator_api.c +++ /dev/null @@ -1,394 +0,0 @@ -/* - * - * (C) COPYRIGHT 2014-2018 ARM Limited. All rights reserved. - * - * This program is free software and is provided to you under the terms of the - * GNU General Public License version 2 as published by the Free Software - * Foundation, and any use by you of this program is subject to the terms - * of such GNU licence. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you can access it online at - * http://www.gnu.org/licenses/gpl-2.0.html. - * - * SPDX-License-Identifier: GPL-2.0 - * - */ - -#include "mali_kbase.h" -#include "mali_kbase_hw.h" -#include "mali_kbase_mem_linux.h" -#include "mali_kbase_gator_api.h" -#include "mali_kbase_gator_hwcnt_names.h" -#include "mali_kbase_hwcnt_types.h" -#include "mali_kbase_hwcnt_gpu.h" -#include "mali_kbase_hwcnt_virtualizer.h" - -#define MALI_MAX_CORES_PER_GROUP 4 -#define MALI_MAX_NUM_BLOCKS_PER_GROUP 8 -#define MALI_COUNTERS_PER_BLOCK 64 -#define MALI_BYTES_PER_COUNTER 4 - -struct kbase_gator_hwcnt_handles { - struct kbase_device *kbdev; - struct kbase_hwcnt_virtualizer_client *hvcli; - struct kbase_hwcnt_enable_map enable_map; - struct kbase_hwcnt_dump_buffer dump_buf; - struct work_struct dump_work; - int dump_complete; - spinlock_t dump_lock; -}; - -static void dump_worker(struct work_struct *work); - -const char * const *kbase_gator_hwcnt_init_names(uint32_t *total_counters) -{ - const char * const *hardware_counters; - struct kbase_device *kbdev; - uint32_t product_id; - uint32_t count; - - if (!total_counters) - return NULL; - - /* Get the first device - it doesn't matter in this case */ - kbdev = kbase_find_device(-1); - if (!kbdev) - return NULL; - - product_id = kbdev->gpu_props.props.core_props.product_id; - - if (GPU_ID_IS_NEW_FORMAT(product_id)) { - switch (GPU_ID2_MODEL_MATCH_VALUE(product_id)) { - case GPU_ID2_PRODUCT_TMIX: - hardware_counters = hardware_counters_mali_tMIx; - count = ARRAY_SIZE(hardware_counters_mali_tMIx); - break; - case GPU_ID2_PRODUCT_THEX: - hardware_counters = hardware_counters_mali_tHEx; - count = ARRAY_SIZE(hardware_counters_mali_tHEx); - break; - case GPU_ID2_PRODUCT_TSIX: - hardware_counters = hardware_counters_mali_tSIx; - count = ARRAY_SIZE(hardware_counters_mali_tSIx); - break; - case GPU_ID2_PRODUCT_TDVX: - hardware_counters = hardware_counters_mali_tSIx; - count = ARRAY_SIZE(hardware_counters_mali_tSIx); - break; - case GPU_ID2_PRODUCT_TNOX: - hardware_counters = hardware_counters_mali_tNOx; - count = ARRAY_SIZE(hardware_counters_mali_tNOx); - break; - case GPU_ID2_PRODUCT_TGOX: - hardware_counters = hardware_counters_mali_tGOx; - count = ARRAY_SIZE(hardware_counters_mali_tGOx); - break; - case GPU_ID2_PRODUCT_TTRX: - hardware_counters = hardware_counters_mali_tTRx; - count = ARRAY_SIZE(hardware_counters_mali_tTRx); - break; - case GPU_ID2_PRODUCT_TNAX: - hardware_counters = hardware_counters_mali_tNAx; - count = ARRAY_SIZE(hardware_counters_mali_tNAx); - break; - case GPU_ID2_PRODUCT_TBEX: - hardware_counters = hardware_counters_mali_tBEx; - count = ARRAY_SIZE(hardware_counters_mali_tBEx); - break; - default: - hardware_counters = NULL; - count = 0; - dev_err(kbdev->dev, "Unrecognized product ID: %u\n", - product_id); - break; - } - } else { - switch (product_id) { - /* If we are using a Mali-T60x device */ - case GPU_ID_PI_T60X: - hardware_counters = hardware_counters_mali_t60x; - count = ARRAY_SIZE(hardware_counters_mali_t60x); - break; - /* If we are using a Mali-T62x device */ - case GPU_ID_PI_T62X: - hardware_counters = hardware_counters_mali_t62x; - count = ARRAY_SIZE(hardware_counters_mali_t62x); - break; - /* If we are using a Mali-T72x device */ - case GPU_ID_PI_T72X: - hardware_counters = hardware_counters_mali_t72x; - count = ARRAY_SIZE(hardware_counters_mali_t72x); - break; - /* If we are using a Mali-T76x device */ - case GPU_ID_PI_T76X: - hardware_counters = hardware_counters_mali_t76x; - count = ARRAY_SIZE(hardware_counters_mali_t76x); - break; - /* If we are using a Mali-T82x device */ - case GPU_ID_PI_T82X: - hardware_counters = hardware_counters_mali_t82x; - count = ARRAY_SIZE(hardware_counters_mali_t82x); - break; - /* If we are using a Mali-T83x device */ - case GPU_ID_PI_T83X: - hardware_counters = hardware_counters_mali_t83x; - count = ARRAY_SIZE(hardware_counters_mali_t83x); - break; - /* If we are using a Mali-T86x device */ - case GPU_ID_PI_T86X: - hardware_counters = hardware_counters_mali_t86x; - count = ARRAY_SIZE(hardware_counters_mali_t86x); - break; - /* If we are using a Mali-T88x device */ - case GPU_ID_PI_TFRX: - hardware_counters = hardware_counters_mali_t88x; - count = ARRAY_SIZE(hardware_counters_mali_t88x); - break; - default: - hardware_counters = NULL; - count = 0; - dev_err(kbdev->dev, "Unrecognized product ID: %u\n", - product_id); - break; - } - } - - /* Release the kbdev reference. */ - kbase_release_device(kbdev); - - *total_counters = count; - - /* If we return a string array take a reference on the module (or fail). */ - if (hardware_counters && !try_module_get(THIS_MODULE)) - return NULL; - - return hardware_counters; -} -KBASE_EXPORT_SYMBOL(kbase_gator_hwcnt_init_names); - -void kbase_gator_hwcnt_term_names(void) -{ - /* Release the module reference. */ - module_put(THIS_MODULE); -} -KBASE_EXPORT_SYMBOL(kbase_gator_hwcnt_term_names); - -struct kbase_gator_hwcnt_handles *kbase_gator_hwcnt_init(struct kbase_gator_hwcnt_info *in_out_info) -{ - int errcode; - struct kbase_gator_hwcnt_handles *hand; - const struct kbase_hwcnt_metadata *metadata; - struct kbase_hwcnt_physical_enable_map phys_map; - uint32_t dump_size = 0, i = 0; - - if (!in_out_info) - return NULL; - - hand = kzalloc(sizeof(*hand), GFP_KERNEL); - if (!hand) - return NULL; - - INIT_WORK(&hand->dump_work, dump_worker); - spin_lock_init(&hand->dump_lock); - - /* Get the first device */ - hand->kbdev = kbase_find_device(-1); - if (!hand->kbdev) - goto free_hand; - - metadata = kbase_hwcnt_virtualizer_metadata( - hand->kbdev->hwcnt_gpu_virt); - if (!metadata) - goto release_device; - - errcode = kbase_hwcnt_enable_map_alloc(metadata, &hand->enable_map); - if (errcode) - goto release_device; - - errcode = kbase_hwcnt_dump_buffer_alloc(metadata, &hand->dump_buf); - if (errcode) - goto free_enable_map; - - in_out_info->kernel_dump_buffer = hand->dump_buf.dump_buf; - - in_out_info->nr_cores = hand->kbdev->gpu_props.num_cores; - in_out_info->nr_core_groups = hand->kbdev->gpu_props.num_core_groups; - in_out_info->gpu_id = hand->kbdev->gpu_props.props.core_props.product_id; - - /* If we are using a v4 device (Mali-T6xx or Mali-T72x) */ - if (kbase_hw_has_feature(hand->kbdev, BASE_HW_FEATURE_V4)) { - uint32_t cg, j; - uint64_t core_mask; - - /* There are 8 hardware counters blocks per core group */ - in_out_info->hwc_layout = kmalloc(sizeof(enum hwc_type) * - MALI_MAX_NUM_BLOCKS_PER_GROUP * - in_out_info->nr_core_groups, GFP_KERNEL); - - if (!in_out_info->hwc_layout) - goto free_dump_buf; - - dump_size = in_out_info->nr_core_groups * - MALI_MAX_NUM_BLOCKS_PER_GROUP * - MALI_COUNTERS_PER_BLOCK * - MALI_BYTES_PER_COUNTER; - - for (cg = 0; cg < in_out_info->nr_core_groups; cg++) { - core_mask = hand->kbdev->gpu_props.props.coherency_info.group[cg].core_mask; - - for (j = 0; j < MALI_MAX_CORES_PER_GROUP; j++) { - if (core_mask & (1u << j)) - in_out_info->hwc_layout[i++] = SHADER_BLOCK; - else - in_out_info->hwc_layout[i++] = RESERVED_BLOCK; - } - - in_out_info->hwc_layout[i++] = TILER_BLOCK; - in_out_info->hwc_layout[i++] = MMU_L2_BLOCK; - - in_out_info->hwc_layout[i++] = RESERVED_BLOCK; - - if (0 == cg) - in_out_info->hwc_layout[i++] = JM_BLOCK; - else - in_out_info->hwc_layout[i++] = RESERVED_BLOCK; - } - /* If we are using any other device */ - } else { - uint32_t nr_l2, nr_sc_bits, j; - uint64_t core_mask; - - nr_l2 = hand->kbdev->gpu_props.props.l2_props.num_l2_slices; - - core_mask = hand->kbdev->gpu_props.props.coherency_info.group[0].core_mask; - - nr_sc_bits = fls64(core_mask); - - /* The job manager and tiler sets of counters - * are always present */ - in_out_info->hwc_layout = kmalloc(sizeof(enum hwc_type) * (2 + nr_sc_bits + nr_l2), GFP_KERNEL); - - if (!in_out_info->hwc_layout) - goto free_dump_buf; - - dump_size = (2 + nr_sc_bits + nr_l2) * MALI_COUNTERS_PER_BLOCK * MALI_BYTES_PER_COUNTER; - - in_out_info->hwc_layout[i++] = JM_BLOCK; - in_out_info->hwc_layout[i++] = TILER_BLOCK; - - for (j = 0; j < nr_l2; j++) - in_out_info->hwc_layout[i++] = MMU_L2_BLOCK; - - while (core_mask != 0ull) { - if ((core_mask & 1ull) != 0ull) - in_out_info->hwc_layout[i++] = SHADER_BLOCK; - else - in_out_info->hwc_layout[i++] = RESERVED_BLOCK; - core_mask >>= 1; - } - } - - /* Calculated dump size must be the same as real dump size */ - if (WARN_ON(dump_size != metadata->dump_buf_bytes)) - goto free_layout; - - in_out_info->nr_hwc_blocks = i; - in_out_info->size = dump_size; - - phys_map.jm_bm = in_out_info->bitmask[JM_BLOCK]; - phys_map.tiler_bm = in_out_info->bitmask[TILER_BLOCK]; - phys_map.shader_bm = in_out_info->bitmask[SHADER_BLOCK]; - phys_map.mmu_l2_bm = in_out_info->bitmask[MMU_L2_BLOCK]; - kbase_hwcnt_gpu_enable_map_from_physical(&hand->enable_map, &phys_map); - errcode = kbase_hwcnt_virtualizer_client_create( - hand->kbdev->hwcnt_gpu_virt, &hand->enable_map, &hand->hvcli); - if (errcode) { - dev_err(hand->kbdev->dev, - "Failed to register gator with hwcnt virtualizer core"); - goto free_layout; - } - - return hand; - -free_layout: - kfree(in_out_info->hwc_layout); -free_dump_buf: - kbase_hwcnt_dump_buffer_free(&hand->dump_buf); -free_enable_map: - kbase_hwcnt_enable_map_free(&hand->enable_map); -release_device: - kbase_release_device(hand->kbdev); -free_hand: - kfree(hand); - return NULL; -} -KBASE_EXPORT_SYMBOL(kbase_gator_hwcnt_init); - -void kbase_gator_hwcnt_term(struct kbase_gator_hwcnt_info *in_out_info, struct kbase_gator_hwcnt_handles *opaque_handles) -{ - if (in_out_info) - kfree(in_out_info->hwc_layout); - - if (opaque_handles) { - cancel_work_sync(&opaque_handles->dump_work); - kbase_hwcnt_virtualizer_client_destroy(opaque_handles->hvcli); - kbase_hwcnt_dump_buffer_free(&opaque_handles->dump_buf); - kbase_hwcnt_enable_map_free(&opaque_handles->enable_map); - kbase_release_device(opaque_handles->kbdev); - kfree(opaque_handles); - } -} -KBASE_EXPORT_SYMBOL(kbase_gator_hwcnt_term); - -static void dump_worker(struct work_struct *work) -{ - int errcode; - u64 ts_start_ns; - u64 ts_end_ns; - struct kbase_gator_hwcnt_handles *hand; - - hand = container_of(work, struct kbase_gator_hwcnt_handles, dump_work); - errcode = kbase_hwcnt_virtualizer_client_dump( - hand->hvcli, &ts_start_ns, &ts_end_ns, &hand->dump_buf); - if (!errcode) { - /* Patch the header to hide other client's counter choices */ - kbase_hwcnt_gpu_patch_dump_headers( - &hand->dump_buf, &hand->enable_map); - /* Zero all non-enabled counters (currently undefined values) */ - kbase_hwcnt_dump_buffer_zero_non_enabled( - &hand->dump_buf, &hand->enable_map); - spin_lock_bh(&hand->dump_lock); - hand->dump_complete = 1; - spin_unlock_bh(&hand->dump_lock); - } else { - schedule_work(&hand->dump_work); - } -} - -uint32_t kbase_gator_instr_hwcnt_dump_complete( - struct kbase_gator_hwcnt_handles *opaque_handles, - uint32_t * const success) -{ - - if (opaque_handles && success) { - *success = opaque_handles->dump_complete; - opaque_handles->dump_complete = 0; - return *success; - } - return 0; -} -KBASE_EXPORT_SYMBOL(kbase_gator_instr_hwcnt_dump_complete); - -uint32_t kbase_gator_instr_hwcnt_dump_irq(struct kbase_gator_hwcnt_handles *opaque_handles) -{ - if (opaque_handles) - schedule_work(&opaque_handles->dump_work); - return 0; -} -KBASE_EXPORT_SYMBOL(kbase_gator_instr_hwcnt_dump_irq); diff --git a/mali_kbase/mali_kbase_gator_api.h b/mali_kbase/mali_kbase_gator_api.h deleted file mode 100644 index d57a418..0000000 --- a/mali_kbase/mali_kbase_gator_api.h +++ /dev/null @@ -1,225 +0,0 @@ -/* - * - * (C) COPYRIGHT 2014-2015, 2019 ARM Limited. All rights reserved. - * - * This program is free software and is provided to you under the terms of the - * GNU General Public License version 2 as published by the Free Software - * Foundation, and any use by you of this program is subject to the terms - * of such GNU licence. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you can access it online at - * http://www.gnu.org/licenses/gpl-2.0.html. - * - * SPDX-License-Identifier: GPL-2.0 - * - */ - -#ifndef _KBASE_GATOR_API_H_ -#define _KBASE_GATOR_API_H_ - -/** - * @brief This file describes the API used by Gator to fetch hardware counters. - */ - -/* This define is used by the gator kernel module compile to select which DDK - * API calling convention to use. If not defined (legacy DDK) gator assumes - * version 1. The version to DDK release mapping is: - * Version 1 API: DDK versions m_r1px, m_r2px - * Version 2 API: DDK versions m_r3px, m_r4px - * Version 3 API: DDK versions m_r5px-m_r28px and b_r1px-b_r16px - * Version 4 API: DDK versions b_r17p0 and newer - * - * API Usage - * ========= - * - * 1] Call kbase_gator_hwcnt_init_names() to return the list of short counter - * names for the GPU present in this device. - * - * 2] Create a kbase_gator_hwcnt_info structure and set the counter enables for - * the counters you want enabled. The enables can all be set for simplicity in - * most use cases, but disabling some will let you minimize bandwidth impact. - * - * 3] Call kbase_gator_hwcnt_init() using the above structure, to create a - * counter context. On successful return the DDK will have populated the - * structure with a variety of useful information. - * - * 4] Call kbase_gator_hwcnt_dump_irq() to queue a non-blocking request for a - * counter dump. If this returns a non-zero value the request has been queued, - * otherwise the driver has been unable to do so (typically because of another - * user of the instrumentation exists concurrently). - * - * 5] Call kbase_gator_hwcnt_dump_complete() to test whether the previously - * requested dump has been succesful. If this returns non-zero the counter dump - * has resolved, but the value of *success must also be tested as the dump - * may have not been successful. If it returns zero the counter dump was - * abandoned due to the device being busy (typically because of another - * user of the instrumentation exists concurrently). - * - * 6] Process the counters stored in the buffer pointed to by ... - * - * kbase_gator_hwcnt_info->kernel_dump_buffer - * - * In pseudo code you can find all of the counters via this approach: - * - * - * hwcnt_info # pointer to kbase_gator_hwcnt_info structure - * hwcnt_name # pointer to name list - * - * u32 * hwcnt_data = (u32*)hwcnt_info->kernel_dump_buffer - * - * # Iterate over each 64-counter block in this GPU configuration - * for( i = 0; i < hwcnt_info->nr_hwc_blocks; i++) { - * hwc_type type = hwcnt_info->hwc_layout[i]; - * - * # Skip reserved type blocks - they contain no counters at all - * if( type == RESERVED_BLOCK ) { - * continue; - * } - * - * size_t name_offset = type * 64; - * size_t data_offset = i * 64; - * - * # Iterate over the names of the counters in this block type - * for( j = 0; j < 64; j++) { - * const char * name = hwcnt_name[name_offset+j]; - * - * # Skip empty name strings - there is no counter here - * if( name[0] == '\0' ) { - * continue; - * } - * - * u32 data = hwcnt_data[data_offset+j]; - * - * printk( "COUNTER: %s DATA: %u\n", name, data ); - * } - * } - * - * - * Note that in most implementations you typically want to either SUM or - * AVERAGE multiple instances of the same counter if, for example, you have - * multiple shader cores or multiple L2 caches. The most sensible view for - * analysis is to AVERAGE shader core counters, but SUM L2 cache and MMU - * counters. - * - * 7] Goto 4, repeating until you want to stop collecting counters. - * - * 8] Release the dump resources by calling kbase_gator_hwcnt_term(). - * - * 9] Release the name table resources by calling - * kbase_gator_hwcnt_term_names(). This function must only be called if - * init_names() returned a non-NULL value. - **/ - -#define MALI_DDK_GATOR_API_VERSION 4 - -enum hwc_type { - JM_BLOCK = 0, - TILER_BLOCK, - SHADER_BLOCK, - MMU_L2_BLOCK, - RESERVED_BLOCK -}; - -struct kbase_gator_hwcnt_info { - /* Passed from Gator to kbase */ - - /* the bitmask of enabled hardware counters for each counter block */ - uint16_t bitmask[4]; - - /* Passed from kbase to Gator */ - - /* ptr to counter dump memory */ - void *kernel_dump_buffer; - - /* size of counter dump memory */ - uint32_t size; - - /* the ID of the Mali device */ - uint32_t gpu_id; - - /* the number of shader cores in the GPU */ - uint32_t nr_cores; - - /* the number of core groups */ - uint32_t nr_core_groups; - - /* the memory layout of the performance counters */ - enum hwc_type *hwc_layout; - - /* the total number of hardware couter blocks */ - uint32_t nr_hwc_blocks; -}; - -/** - * @brief Opaque block of Mali data which Gator needs to return to the API later. - */ -struct kbase_gator_hwcnt_handles; - -/** - * @brief Initialize the resources Gator needs for performance profiling. - * - * @param in_out_info A pointer to a structure containing the enabled counters passed from Gator and all the Mali - * specific information that will be returned to Gator. On entry Gator must have populated the - * 'bitmask' field with the counters it wishes to enable for each class of counter block. - * Each entry in the array corresponds to a single counter class based on the "hwc_type" - * enumeration, and each bit corresponds to an enable for 4 sequential counters (LSB enables - * the first 4 counters in the block, and so on). See the GPU counter array as returned by - * kbase_gator_hwcnt_get_names() for the index values of each counter for the curernt GPU. - * - * @return Pointer to an opaque handle block on success, NULL on error. - */ -extern struct kbase_gator_hwcnt_handles *kbase_gator_hwcnt_init(struct kbase_gator_hwcnt_info *in_out_info); - -/** - * @brief Free all resources once Gator has finished using performance counters. - * - * @param in_out_info A pointer to a structure containing the enabled counters passed from Gator and all the - * Mali specific information that will be returned to Gator. - * @param opaque_handles A wrapper structure for kbase structures. - */ -extern void kbase_gator_hwcnt_term(struct kbase_gator_hwcnt_info *in_out_info, struct kbase_gator_hwcnt_handles *opaque_handles); - -/** - * @brief Poll whether a counter dump is successful. - * - * @param opaque_handles A wrapper structure for kbase structures. - * @param[out] success Non-zero on success, zero on failure. - * - * @return Zero if the dump is still pending, non-zero if the dump has completed. Note that a - * completed dump may not have dumped succesfully, so the caller must test for both - * a completed and successful dump before processing counters. - */ -extern uint32_t kbase_gator_instr_hwcnt_dump_complete(struct kbase_gator_hwcnt_handles *opaque_handles, uint32_t * const success); - -/** - * @brief Request the generation of a new counter dump. - * - * @param opaque_handles A wrapper structure for kbase structures. - * - * @return Zero if the hardware device is busy and cannot handle the request, non-zero otherwise. - */ -extern uint32_t kbase_gator_instr_hwcnt_dump_irq(struct kbase_gator_hwcnt_handles *opaque_handles); - -/** - * @brief This function is used to fetch the names table based on the Mali device in use. - * - * @param[out] total_counters The total number of counters short names in the Mali devices' list. - * - * @return Pointer to an array of strings of length *total_counters. - */ -extern const char * const *kbase_gator_hwcnt_init_names(uint32_t *total_counters); - -/** - * @brief This function is used to terminate the use of the names table. - * - * This function must only be called if the initial call to kbase_gator_hwcnt_init_names returned a non-NULL value. - */ -extern void kbase_gator_hwcnt_term_names(void); - -#endif diff --git a/mali_kbase/mali_kbase_gator_hwcnt_names.h b/mali_kbase/mali_kbase_gator_hwcnt_names.h deleted file mode 100644 index 764c9d1..0000000 --- a/mali_kbase/mali_kbase_gator_hwcnt_names.h +++ /dev/null @@ -1,2180 +0,0 @@ -/* - * - * (C) COPYRIGHT 2014-2018 ARM Limited. All rights reserved. - * - * This program is free software and is provided to you under the terms of the - * GNU General Public License version 2 as published by the Free Software - * Foundation, and any use by you of this program is subject to the terms - * of such GNU licence. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you can access it online at - * http://www.gnu.org/licenses/gpl-2.0.html. - * - * SPDX-License-Identifier: GPL-2.0 - * - */ - -#ifndef _KBASE_GATOR_HWCNT_NAMES_H_ -#define _KBASE_GATOR_HWCNT_NAMES_H_ - -/* - * "Short names" for hardware counters used by Streamline. Counters names are - * stored in accordance with their memory layout in the binary counter block - * emitted by the Mali GPU. Each "master" in the GPU emits a fixed-size block - * of 64 counters, and each GPU implements the same set of "masters" although - * the counters each master exposes within its block of 64 may vary. - * - * Counters which are an empty string are simply "holes" in the counter memory - * where no counter exists. - */ - -static const char * const hardware_counters_mali_t60x[] = { - /* Job Manager */ - "", - "", - "", - "", - "T60x_MESSAGES_SENT", - "T60x_MESSAGES_RECEIVED", - "T60x_GPU_ACTIVE", - "T60x_IRQ_ACTIVE", - "T60x_JS0_JOBS", - "T60x_JS0_TASKS", - "T60x_JS0_ACTIVE", - "", - "T60x_JS0_WAIT_READ", - "T60x_JS0_WAIT_ISSUE", - "T60x_JS0_WAIT_DEPEND", - "T60x_JS0_WAIT_FINISH", - "T60x_JS1_JOBS", - "T60x_JS1_TASKS", - "T60x_JS1_ACTIVE", - "", - "T60x_JS1_WAIT_READ", - "T60x_JS1_WAIT_ISSUE", - "T60x_JS1_WAIT_DEPEND", - "T60x_JS1_WAIT_FINISH", - "T60x_JS2_JOBS", - "T60x_JS2_TASKS", - "T60x_JS2_ACTIVE", - "", - "T60x_JS2_WAIT_READ", - "T60x_JS2_WAIT_ISSUE", - "T60x_JS2_WAIT_DEPEND", - "T60x_JS2_WAIT_FINISH", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - - /*Tiler */ - "", - "", - "", - "T60x_TI_JOBS_PROCESSED", - "T60x_TI_TRIANGLES", - "T60x_TI_QUADS", - "T60x_TI_POLYGONS", - "T60x_TI_POINTS", - "T60x_TI_LINES", - "T60x_TI_VCACHE_HIT", - "T60x_TI_VCACHE_MISS", - "T60x_TI_FRONT_FACING", - "T60x_TI_BACK_FACING", - "T60x_TI_PRIM_VISIBLE", - "T60x_TI_PRIM_CULLED", - "T60x_TI_PRIM_CLIPPED", - "T60x_TI_LEVEL0", - "T60x_TI_LEVEL1", - "T60x_TI_LEVEL2", - "T60x_TI_LEVEL3", - "T60x_TI_LEVEL4", - "T60x_TI_LEVEL5", - "T60x_TI_LEVEL6", - "T60x_TI_LEVEL7", - "T60x_TI_COMMAND_1", - "T60x_TI_COMMAND_2", - "T60x_TI_COMMAND_3", - "T60x_TI_COMMAND_4", - "T60x_TI_COMMAND_4_7", - "T60x_TI_COMMAND_8_15", - "T60x_TI_COMMAND_16_63", - "T60x_TI_COMMAND_64", - "T60x_TI_COMPRESS_IN", - "T60x_TI_COMPRESS_OUT", - "T60x_TI_COMPRESS_FLUSH", - "T60x_TI_TIMESTAMPS", - "T60x_TI_PCACHE_HIT", - "T60x_TI_PCACHE_MISS", - "T60x_TI_PCACHE_LINE", - "T60x_TI_PCACHE_STALL", - "T60x_TI_WRBUF_HIT", - "T60x_TI_WRBUF_MISS", - "T60x_TI_WRBUF_LINE", - "T60x_TI_WRBUF_PARTIAL", - "T60x_TI_WRBUF_STALL", - "T60x_TI_ACTIVE", - "T60x_TI_LOADING_DESC", - "T60x_TI_INDEX_WAIT", - "T60x_TI_INDEX_RANGE_WAIT", - "T60x_TI_VERTEX_WAIT", - "T60x_TI_PCACHE_WAIT", - "T60x_TI_WRBUF_WAIT", - "T60x_TI_BUS_READ", - "T60x_TI_BUS_WRITE", - "", - "", - "", - "", - "", - "T60x_TI_UTLB_STALL", - "T60x_TI_UTLB_REPLAY_MISS", - "T60x_TI_UTLB_REPLAY_FULL", - "T60x_TI_UTLB_NEW_MISS", - "T60x_TI_UTLB_HIT", - - /* Shader Core */ - "", - "", - "", - "", - "T60x_FRAG_ACTIVE", - "T60x_FRAG_PRIMITIVES", - "T60x_FRAG_PRIMITIVES_DROPPED", - "T60x_FRAG_CYCLES_DESC", - "T60x_FRAG_CYCLES_PLR", - "T60x_FRAG_CYCLES_VERT", - "T60x_FRAG_CYCLES_TRISETUP", - "T60x_FRAG_CYCLES_RAST", - "T60x_FRAG_THREADS", - "T60x_FRAG_DUMMY_THREADS", - "T60x_FRAG_QUADS_RAST", - "T60x_FRAG_QUADS_EZS_TEST", - "T60x_FRAG_QUADS_EZS_KILLED", - "T60x_FRAG_THREADS_LZS_TEST", - "T60x_FRAG_THREADS_LZS_KILLED", - "T60x_FRAG_CYCLES_NO_TILE", - "T60x_FRAG_NUM_TILES", - "T60x_FRAG_TRANS_ELIM", - "T60x_COMPUTE_ACTIVE", - "T60x_COMPUTE_TASKS", - "T60x_COMPUTE_THREADS", - "T60x_COMPUTE_CYCLES_DESC", - "T60x_TRIPIPE_ACTIVE", - "T60x_ARITH_WORDS", - "T60x_ARITH_CYCLES_REG", - "T60x_ARITH_CYCLES_L0", - "T60x_ARITH_FRAG_DEPEND", - "T60x_LS_WORDS", - "T60x_LS_ISSUES", - "T60x_LS_RESTARTS", - "T60x_LS_REISSUES_MISS", - "T60x_LS_REISSUES_VD", - "T60x_LS_REISSUE_ATTRIB_MISS", - "T60x_LS_NO_WB", - "T60x_TEX_WORDS", - "T60x_TEX_BUBBLES", - "T60x_TEX_WORDS_L0", - "T60x_TEX_WORDS_DESC", - "T60x_TEX_ISSUES", - "T60x_TEX_RECIRC_FMISS", - "T60x_TEX_RECIRC_DESC", - "T60x_TEX_RECIRC_MULTI", - "T60x_TEX_RECIRC_PMISS", - "T60x_TEX_RECIRC_CONF", - "T60x_LSC_READ_HITS", - "T60x_LSC_READ_MISSES", - "T60x_LSC_WRITE_HITS", - "T60x_LSC_WRITE_MISSES", - "T60x_LSC_ATOMIC_HITS", - "T60x_LSC_ATOMIC_MISSES", - "T60x_LSC_LINE_FETCHES", - "T60x_LSC_DIRTY_LINE", - "T60x_LSC_SNOOPS", - "T60x_AXI_TLB_STALL", - "T60x_AXI_TLB_MISS", - "T60x_AXI_TLB_TRANSACTION", - "T60x_LS_TLB_MISS", - "T60x_LS_TLB_HIT", - "T60x_AXI_BEATS_READ", - "T60x_AXI_BEATS_WRITTEN", - - /*L2 and MMU */ - "", - "", - "", - "", - "T60x_MMU_HIT", - "T60x_MMU_NEW_MISS", - "T60x_MMU_REPLAY_FULL", - "T60x_MMU_REPLAY_MISS", - "T60x_MMU_TABLE_WALK", - "", - "", - "", - "", - "", - "", - "", - "T60x_UTLB_HIT", - "T60x_UTLB_NEW_MISS", - "T60x_UTLB_REPLAY_FULL", - "T60x_UTLB_REPLAY_MISS", - "T60x_UTLB_STALL", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "T60x_L2_EXT_WRITE_BEATS", - "T60x_L2_EXT_READ_BEATS", - "T60x_L2_ANY_LOOKUP", - "T60x_L2_READ_LOOKUP", - "T60x_L2_SREAD_LOOKUP", - "T60x_L2_READ_REPLAY", - "T60x_L2_READ_SNOOP", - "T60x_L2_READ_HIT", - "T60x_L2_CLEAN_MISS", - "T60x_L2_WRITE_LOOKUP", - "T60x_L2_SWRITE_LOOKUP", - "T60x_L2_WRITE_REPLAY", - "T60x_L2_WRITE_SNOOP", - "T60x_L2_WRITE_HIT", - "T60x_L2_EXT_READ_FULL", - "T60x_L2_EXT_READ_HALF", - "T60x_L2_EXT_WRITE_FULL", - "T60x_L2_EXT_WRITE_HALF", - "T60x_L2_EXT_READ", - "T60x_L2_EXT_READ_LINE", - "T60x_L2_EXT_WRITE", - "T60x_L2_EXT_WRITE_LINE", - "T60x_L2_EXT_WRITE_SMALL", - "T60x_L2_EXT_BARRIER", - "T60x_L2_EXT_AR_STALL", - "T60x_L2_EXT_R_BUF_FULL", - "T60x_L2_EXT_RD_BUF_FULL", - "T60x_L2_EXT_R_RAW", - "T60x_L2_EXT_W_STALL", - "T60x_L2_EXT_W_BUF_FULL", - "T60x_L2_EXT_R_W_HAZARD", - "T60x_L2_TAG_HAZARD", - "T60x_L2_SNOOP_FULL", - "T60x_L2_REPLAY_FULL" -}; -static const char * const hardware_counters_mali_t62x[] = { - /* Job Manager */ - "", - "", - "", - "", - "T62x_MESSAGES_SENT", - "T62x_MESSAGES_RECEIVED", - "T62x_GPU_ACTIVE", - "T62x_IRQ_ACTIVE", - "T62x_JS0_JOBS", - "T62x_JS0_TASKS", - "T62x_JS0_ACTIVE", - "", - "T62x_JS0_WAIT_READ", - "T62x_JS0_WAIT_ISSUE", - "T62x_JS0_WAIT_DEPEND", - "T62x_JS0_WAIT_FINISH", - "T62x_JS1_JOBS", - "T62x_JS1_TASKS", - "T62x_JS1_ACTIVE", - "", - "T62x_JS1_WAIT_READ", - "T62x_JS1_WAIT_ISSUE", - "T62x_JS1_WAIT_DEPEND", - "T62x_JS1_WAIT_FINISH", - "T62x_JS2_JOBS", - "T62x_JS2_TASKS", - "T62x_JS2_ACTIVE", - "", - "T62x_JS2_WAIT_READ", - "T62x_JS2_WAIT_ISSUE", - "T62x_JS2_WAIT_DEPEND", - "T62x_JS2_WAIT_FINISH", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - - /*Tiler */ - "", - "", - "", - "T62x_TI_JOBS_PROCESSED", - "T62x_TI_TRIANGLES", - "T62x_TI_QUADS", - "T62x_TI_POLYGONS", - "T62x_TI_POINTS", - "T62x_TI_LINES", - "T62x_TI_VCACHE_HIT", - "T62x_TI_VCACHE_MISS", - "T62x_TI_FRONT_FACING", - "T62x_TI_BACK_FACING", - "T62x_TI_PRIM_VISIBLE", - "T62x_TI_PRIM_CULLED", - "T62x_TI_PRIM_CLIPPED", - "T62x_TI_LEVEL0", - "T62x_TI_LEVEL1", - "T62x_TI_LEVEL2", - "T62x_TI_LEVEL3", - "T62x_TI_LEVEL4", - "T62x_TI_LEVEL5", - "T62x_TI_LEVEL6", - "T62x_TI_LEVEL7", - "T62x_TI_COMMAND_1", - "T62x_TI_COMMAND_2", - "T62x_TI_COMMAND_3", - "T62x_TI_COMMAND_4", - "T62x_TI_COMMAND_5_7", - "T62x_TI_COMMAND_8_15", - "T62x_TI_COMMAND_16_63", - "T62x_TI_COMMAND_64", - "T62x_TI_COMPRESS_IN", - "T62x_TI_COMPRESS_OUT", - "T62x_TI_COMPRESS_FLUSH", - "T62x_TI_TIMESTAMPS", - "T62x_TI_PCACHE_HIT", - "T62x_TI_PCACHE_MISS", - "T62x_TI_PCACHE_LINE", - "T62x_TI_PCACHE_STALL", - "T62x_TI_WRBUF_HIT", - "T62x_TI_WRBUF_MISS", - "T62x_TI_WRBUF_LINE", - "T62x_TI_WRBUF_PARTIAL", - "T62x_TI_WRBUF_STALL", - "T62x_TI_ACTIVE", - "T62x_TI_LOADING_DESC", - "T62x_TI_INDEX_WAIT", - "T62x_TI_INDEX_RANGE_WAIT", - "T62x_TI_VERTEX_WAIT", - "T62x_TI_PCACHE_WAIT", - "T62x_TI_WRBUF_WAIT", - "T62x_TI_BUS_READ", - "T62x_TI_BUS_WRITE", - "", - "", - "", - "", - "", - "T62x_TI_UTLB_STALL", - "T62x_TI_UTLB_REPLAY_MISS", - "T62x_TI_UTLB_REPLAY_FULL", - "T62x_TI_UTLB_NEW_MISS", - "T62x_TI_UTLB_HIT", - - /* Shader Core */ - "", - "", - "", - "T62x_SHADER_CORE_ACTIVE", - "T62x_FRAG_ACTIVE", - "T62x_FRAG_PRIMITIVES", - "T62x_FRAG_PRIMITIVES_DROPPED", - "T62x_FRAG_CYCLES_DESC", - "T62x_FRAG_CYCLES_FPKQ_ACTIVE", - "T62x_FRAG_CYCLES_VERT", - "T62x_FRAG_CYCLES_TRISETUP", - "T62x_FRAG_CYCLES_EZS_ACTIVE", - "T62x_FRAG_THREADS", - "T62x_FRAG_DUMMY_THREADS", - "T62x_FRAG_QUADS_RAST", - "T62x_FRAG_QUADS_EZS_TEST", - "T62x_FRAG_QUADS_EZS_KILLED", - "T62x_FRAG_THREADS_LZS_TEST", - "T62x_FRAG_THREADS_LZS_KILLED", - "T62x_FRAG_CYCLES_NO_TILE", - "T62x_FRAG_NUM_TILES", - "T62x_FRAG_TRANS_ELIM", - "T62x_COMPUTE_ACTIVE", - "T62x_COMPUTE_TASKS", - "T62x_COMPUTE_THREADS", - "T62x_COMPUTE_CYCLES_DESC", - "T62x_TRIPIPE_ACTIVE", - "T62x_ARITH_WORDS", - "T62x_ARITH_CYCLES_REG", - "T62x_ARITH_CYCLES_L0", - "T62x_ARITH_FRAG_DEPEND", - "T62x_LS_WORDS", - "T62x_LS_ISSUES", - "T62x_LS_RESTARTS", - "T62x_LS_REISSUES_MISS", - "T62x_LS_REISSUES_VD", - "T62x_LS_REISSUE_ATTRIB_MISS", - "T62x_LS_NO_WB", - "T62x_TEX_WORDS", - "T62x_TEX_BUBBLES", - "T62x_TEX_WORDS_L0", - "T62x_TEX_WORDS_DESC", - "T62x_TEX_ISSUES", - "T62x_TEX_RECIRC_FMISS", - "T62x_TEX_RECIRC_DESC", - "T62x_TEX_RECIRC_MULTI", - "T62x_TEX_RECIRC_PMISS", - "T62x_TEX_RECIRC_CONF", - "T62x_LSC_READ_HITS", - "T62x_LSC_READ_MISSES", - "T62x_LSC_WRITE_HITS", - "T62x_LSC_WRITE_MISSES", - "T62x_LSC_ATOMIC_HITS", - "T62x_LSC_ATOMIC_MISSES", - "T62x_LSC_LINE_FETCHES", - "T62x_LSC_DIRTY_LINE", - "T62x_LSC_SNOOPS", - "T62x_AXI_TLB_STALL", - "T62x_AXI_TLB_MISS", - "T62x_AXI_TLB_TRANSACTION", - "T62x_LS_TLB_MISS", - "T62x_LS_TLB_HIT", - "T62x_AXI_BEATS_READ", - "T62x_AXI_BEATS_WRITTEN", - - /*L2 and MMU */ - "", - "", - "", - "", - "T62x_MMU_HIT", - "T62x_MMU_NEW_MISS", - "T62x_MMU_REPLAY_FULL", - "T62x_MMU_REPLAY_MISS", - "T62x_MMU_TABLE_WALK", - "", - "", - "", - "", - "", - "", - "", - "T62x_UTLB_HIT", - "T62x_UTLB_NEW_MISS", - "T62x_UTLB_REPLAY_FULL", - "T62x_UTLB_REPLAY_MISS", - "T62x_UTLB_STALL", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "T62x_L2_EXT_WRITE_BEATS", - "T62x_L2_EXT_READ_BEATS", - "T62x_L2_ANY_LOOKUP", - "T62x_L2_READ_LOOKUP", - "T62x_L2_SREAD_LOOKUP", - "T62x_L2_READ_REPLAY", - "T62x_L2_READ_SNOOP", - "T62x_L2_READ_HIT", - "T62x_L2_CLEAN_MISS", - "T62x_L2_WRITE_LOOKUP", - "T62x_L2_SWRITE_LOOKUP", - "T62x_L2_WRITE_REPLAY", - "T62x_L2_WRITE_SNOOP", - "T62x_L2_WRITE_HIT", - "T62x_L2_EXT_READ_FULL", - "T62x_L2_EXT_READ_HALF", - "T62x_L2_EXT_WRITE_FULL", - "T62x_L2_EXT_WRITE_HALF", - "T62x_L2_EXT_READ", - "T62x_L2_EXT_READ_LINE", - "T62x_L2_EXT_WRITE", - "T62x_L2_EXT_WRITE_LINE", - "T62x_L2_EXT_WRITE_SMALL", - "T62x_L2_EXT_BARRIER", - "T62x_L2_EXT_AR_STALL", - "T62x_L2_EXT_R_BUF_FULL", - "T62x_L2_EXT_RD_BUF_FULL", - "T62x_L2_EXT_R_RAW", - "T62x_L2_EXT_W_STALL", - "T62x_L2_EXT_W_BUF_FULL", - "T62x_L2_EXT_R_W_HAZARD", - "T62x_L2_TAG_HAZARD", - "T62x_L2_SNOOP_FULL", - "T62x_L2_REPLAY_FULL" -}; - -static const char * const hardware_counters_mali_t72x[] = { - /* Job Manager */ - "", - "", - "", - "", - "T72x_GPU_ACTIVE", - "T72x_IRQ_ACTIVE", - "T72x_JS0_JOBS", - "T72x_JS0_TASKS", - "T72x_JS0_ACTIVE", - "T72x_JS1_JOBS", - "T72x_JS1_TASKS", - "T72x_JS1_ACTIVE", - "T72x_JS2_JOBS", - "T72x_JS2_TASKS", - "T72x_JS2_ACTIVE", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - - /*Tiler */ - "", - "", - "", - "T72x_TI_JOBS_PROCESSED", - "T72x_TI_TRIANGLES", - "T72x_TI_QUADS", - "T72x_TI_POLYGONS", - "T72x_TI_POINTS", - "T72x_TI_LINES", - "T72x_TI_FRONT_FACING", - "T72x_TI_BACK_FACING", - "T72x_TI_PRIM_VISIBLE", - "T72x_TI_PRIM_CULLED", - "T72x_TI_PRIM_CLIPPED", - "", - "", - "", - "", - "", - "", - "", - "", - "T72x_TI_ACTIVE", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - - /* Shader Core */ - "", - "", - "", - "", - "T72x_FRAG_ACTIVE", - "T72x_FRAG_PRIMITIVES", - "T72x_FRAG_PRIMITIVES_DROPPED", - "T72x_FRAG_THREADS", - "T72x_FRAG_DUMMY_THREADS", - "T72x_FRAG_QUADS_RAST", - "T72x_FRAG_QUADS_EZS_TEST", - "T72x_FRAG_QUADS_EZS_KILLED", - "T72x_FRAG_THREADS_LZS_TEST", - "T72x_FRAG_THREADS_LZS_KILLED", - "T72x_FRAG_CYCLES_NO_TILE", - "T72x_FRAG_NUM_TILES", - "T72x_FRAG_TRANS_ELIM", - "T72x_COMPUTE_ACTIVE", - "T72x_COMPUTE_TASKS", - "T72x_COMPUTE_THREADS", - "T72x_TRIPIPE_ACTIVE", - "T72x_ARITH_WORDS", - "T72x_ARITH_CYCLES_REG", - "T72x_LS_WORDS", - "T72x_LS_ISSUES", - "T72x_LS_RESTARTS", - "T72x_LS_REISSUES_MISS", - "T72x_TEX_WORDS", - "T72x_TEX_BUBBLES", - "T72x_TEX_ISSUES", - "T72x_LSC_READ_HITS", - "T72x_LSC_READ_MISSES", - "T72x_LSC_WRITE_HITS", - "T72x_LSC_WRITE_MISSES", - "T72x_LSC_ATOMIC_HITS", - "T72x_LSC_ATOMIC_MISSES", - "T72x_LSC_LINE_FETCHES", - "T72x_LSC_DIRTY_LINE", - "T72x_LSC_SNOOPS", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - - /*L2 and MMU */ - "", - "", - "", - "", - "T72x_L2_EXT_WRITE_BEAT", - "T72x_L2_EXT_READ_BEAT", - "T72x_L2_READ_SNOOP", - "T72x_L2_READ_HIT", - "T72x_L2_WRITE_SNOOP", - "T72x_L2_WRITE_HIT", - "T72x_L2_EXT_WRITE_SMALL", - "T72x_L2_EXT_BARRIER", - "T72x_L2_EXT_AR_STALL", - "T72x_L2_EXT_W_STALL", - "T72x_L2_SNOOP_FULL", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "" -}; - -static const char * const hardware_counters_mali_t76x[] = { - /* Job Manager */ - "", - "", - "", - "", - "T76x_MESSAGES_SENT", - "T76x_MESSAGES_RECEIVED", - "T76x_GPU_ACTIVE", - "T76x_IRQ_ACTIVE", - "T76x_JS0_JOBS", - "T76x_JS0_TASKS", - "T76x_JS0_ACTIVE", - "", - "T76x_JS0_WAIT_READ", - "T76x_JS0_WAIT_ISSUE", - "T76x_JS0_WAIT_DEPEND", - "T76x_JS0_WAIT_FINISH", - "T76x_JS1_JOBS", - "T76x_JS1_TASKS", - "T76x_JS1_ACTIVE", - "", - "T76x_JS1_WAIT_READ", - "T76x_JS1_WAIT_ISSUE", - "T76x_JS1_WAIT_DEPEND", - "T76x_JS1_WAIT_FINISH", - "T76x_JS2_JOBS", - "T76x_JS2_TASKS", - "T76x_JS2_ACTIVE", - "", - "T76x_JS2_WAIT_READ", - "T76x_JS2_WAIT_ISSUE", - "T76x_JS2_WAIT_DEPEND", - "T76x_JS2_WAIT_FINISH", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - - /*Tiler */ - "", - "", - "", - "T76x_TI_JOBS_PROCESSED", - "T76x_TI_TRIANGLES", - "T76x_TI_QUADS", - "T76x_TI_POLYGONS", - "T76x_TI_POINTS", - "T76x_TI_LINES", - "T76x_TI_VCACHE_HIT", - "T76x_TI_VCACHE_MISS", - "T76x_TI_FRONT_FACING", - "T76x_TI_BACK_FACING", - "T76x_TI_PRIM_VISIBLE", - "T76x_TI_PRIM_CULLED", - "T76x_TI_PRIM_CLIPPED", - "T76x_TI_LEVEL0", - "T76x_TI_LEVEL1", - "T76x_TI_LEVEL2", - "T76x_TI_LEVEL3", - "T76x_TI_LEVEL4", - "T76x_TI_LEVEL5", - "T76x_TI_LEVEL6", - "T76x_TI_LEVEL7", - "T76x_TI_COMMAND_1", - "T76x_TI_COMMAND_2", - "T76x_TI_COMMAND_3", - "T76x_TI_COMMAND_4", - "T76x_TI_COMMAND_5_7", - "T76x_TI_COMMAND_8_15", - "T76x_TI_COMMAND_16_63", - "T76x_TI_COMMAND_64", - "T76x_TI_COMPRESS_IN", - "T76x_TI_COMPRESS_OUT", - "T76x_TI_COMPRESS_FLUSH", - "T76x_TI_TIMESTAMPS", - "T76x_TI_PCACHE_HIT", - "T76x_TI_PCACHE_MISS", - "T76x_TI_PCACHE_LINE", - "T76x_TI_PCACHE_STALL", - "T76x_TI_WRBUF_HIT", - "T76x_TI_WRBUF_MISS", - "T76x_TI_WRBUF_LINE", - "T76x_TI_WRBUF_PARTIAL", - "T76x_TI_WRBUF_STALL", - "T76x_TI_ACTIVE", - "T76x_TI_LOADING_DESC", - "T76x_TI_INDEX_WAIT", - "T76x_TI_INDEX_RANGE_WAIT", - "T76x_TI_VERTEX_WAIT", - "T76x_TI_PCACHE_WAIT", - "T76x_TI_WRBUF_WAIT", - "T76x_TI_BUS_READ", - "T76x_TI_BUS_WRITE", - "", - "", - "", - "", - "", - "T76x_TI_UTLB_HIT", - "T76x_TI_UTLB_NEW_MISS", - "T76x_TI_UTLB_REPLAY_FULL", - "T76x_TI_UTLB_REPLAY_MISS", - "T76x_TI_UTLB_STALL", - - /* Shader Core */ - "", - "", - "", - "", - "T76x_FRAG_ACTIVE", - "T76x_FRAG_PRIMITIVES", - "T76x_FRAG_PRIMITIVES_DROPPED", - "T76x_FRAG_CYCLES_DESC", - "T76x_FRAG_CYCLES_FPKQ_ACTIVE", - "T76x_FRAG_CYCLES_VERT", - "T76x_FRAG_CYCLES_TRISETUP", - "T76x_FRAG_CYCLES_EZS_ACTIVE", - "T76x_FRAG_THREADS", - "T76x_FRAG_DUMMY_THREADS", - "T76x_FRAG_QUADS_RAST", - "T76x_FRAG_QUADS_EZS_TEST", - "T76x_FRAG_QUADS_EZS_KILLED", - "T76x_FRAG_THREADS_LZS_TEST", - "T76x_FRAG_THREADS_LZS_KILLED", - "T76x_FRAG_CYCLES_NO_TILE", - "T76x_FRAG_NUM_TILES", - "T76x_FRAG_TRANS_ELIM", - "T76x_COMPUTE_ACTIVE", - "T76x_COMPUTE_TASKS", - "T76x_COMPUTE_THREADS", - "T76x_COMPUTE_CYCLES_DESC", - "T76x_TRIPIPE_ACTIVE", - "T76x_ARITH_WORDS", - "T76x_ARITH_CYCLES_REG", - "T76x_ARITH_CYCLES_L0", - "T76x_ARITH_FRAG_DEPEND", - "T76x_LS_WORDS", - "T76x_LS_ISSUES", - "T76x_LS_REISSUE_ATTR", - "T76x_LS_REISSUES_VARY", - "T76x_LS_VARY_RV_MISS", - "T76x_LS_VARY_RV_HIT", - "T76x_LS_NO_UNPARK", - "T76x_TEX_WORDS", - "T76x_TEX_BUBBLES", - "T76x_TEX_WORDS_L0", - "T76x_TEX_WORDS_DESC", - "T76x_TEX_ISSUES", - "T76x_TEX_RECIRC_FMISS", - "T76x_TEX_RECIRC_DESC", - "T76x_TEX_RECIRC_MULTI", - "T76x_TEX_RECIRC_PMISS", - "T76x_TEX_RECIRC_CONF", - "T76x_LSC_READ_HITS", - "T76x_LSC_READ_OP", - "T76x_LSC_WRITE_HITS", - "T76x_LSC_WRITE_OP", - "T76x_LSC_ATOMIC_HITS", - "T76x_LSC_ATOMIC_OP", - "T76x_LSC_LINE_FETCHES", - "T76x_LSC_DIRTY_LINE", - "T76x_LSC_SNOOPS", - "T76x_AXI_TLB_STALL", - "T76x_AXI_TLB_MISS", - "T76x_AXI_TLB_TRANSACTION", - "T76x_LS_TLB_MISS", - "T76x_LS_TLB_HIT", - "T76x_AXI_BEATS_READ", - "T76x_AXI_BEATS_WRITTEN", - - /*L2 and MMU */ - "", - "", - "", - "", - "T76x_MMU_HIT", - "T76x_MMU_NEW_MISS", - "T76x_MMU_REPLAY_FULL", - "T76x_MMU_REPLAY_MISS", - "T76x_MMU_TABLE_WALK", - "T76x_MMU_REQUESTS", - "", - "", - "T76x_UTLB_HIT", - "T76x_UTLB_NEW_MISS", - "T76x_UTLB_REPLAY_FULL", - "T76x_UTLB_REPLAY_MISS", - "T76x_UTLB_STALL", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "T76x_L2_EXT_WRITE_BEATS", - "T76x_L2_EXT_READ_BEATS", - "T76x_L2_ANY_LOOKUP", - "T76x_L2_READ_LOOKUP", - "T76x_L2_SREAD_LOOKUP", - "T76x_L2_READ_REPLAY", - "T76x_L2_READ_SNOOP", - "T76x_L2_READ_HIT", - "T76x_L2_CLEAN_MISS", - "T76x_L2_WRITE_LOOKUP", - "T76x_L2_SWRITE_LOOKUP", - "T76x_L2_WRITE_REPLAY", - "T76x_L2_WRITE_SNOOP", - "T76x_L2_WRITE_HIT", - "T76x_L2_EXT_READ_FULL", - "", - "T76x_L2_EXT_WRITE_FULL", - "T76x_L2_EXT_R_W_HAZARD", - "T76x_L2_EXT_READ", - "T76x_L2_EXT_READ_LINE", - "T76x_L2_EXT_WRITE", - "T76x_L2_EXT_WRITE_LINE", - "T76x_L2_EXT_WRITE_SMALL", - "T76x_L2_EXT_BARRIER", - "T76x_L2_EXT_AR_STALL", - "T76x_L2_EXT_R_BUF_FULL", - "T76x_L2_EXT_RD_BUF_FULL", - "T76x_L2_EXT_R_RAW", - "T76x_L2_EXT_W_STALL", - "T76x_L2_EXT_W_BUF_FULL", - "T76x_L2_EXT_R_BUF_FULL", - "T76x_L2_TAG_HAZARD", - "T76x_L2_SNOOP_FULL", - "T76x_L2_REPLAY_FULL" -}; - -static const char * const hardware_counters_mali_t82x[] = { - /* Job Manager */ - "", - "", - "", - "", - "T82x_MESSAGES_SENT", - "T82x_MESSAGES_RECEIVED", - "T82x_GPU_ACTIVE", - "T82x_IRQ_ACTIVE", - "T82x_JS0_JOBS", - "T82x_JS0_TASKS", - "T82x_JS0_ACTIVE", - "", - "T82x_JS0_WAIT_READ", - "T82x_JS0_WAIT_ISSUE", - "T82x_JS0_WAIT_DEPEND", - "T82x_JS0_WAIT_FINISH", - "T82x_JS1_JOBS", - "T82x_JS1_TASKS", - "T82x_JS1_ACTIVE", - "", - "T82x_JS1_WAIT_READ", - "T82x_JS1_WAIT_ISSUE", - "T82x_JS1_WAIT_DEPEND", - "T82x_JS1_WAIT_FINISH", - "T82x_JS2_JOBS", - "T82x_JS2_TASKS", - "T82x_JS2_ACTIVE", - "", - "T82x_JS2_WAIT_READ", - "T82x_JS2_WAIT_ISSUE", - "T82x_JS2_WAIT_DEPEND", - "T82x_JS2_WAIT_FINISH", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - - /*Tiler */ - "", - "", - "", - "T82x_TI_JOBS_PROCESSED", - "T82x_TI_TRIANGLES", - "T82x_TI_QUADS", - "T82x_TI_POLYGONS", - "T82x_TI_POINTS", - "T82x_TI_LINES", - "T82x_TI_FRONT_FACING", - "T82x_TI_BACK_FACING", - "T82x_TI_PRIM_VISIBLE", - "T82x_TI_PRIM_CULLED", - "T82x_TI_PRIM_CLIPPED", - "", - "", - "", - "", - "", - "", - "", - "", - "T82x_TI_ACTIVE", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - - /* Shader Core */ - "", - "", - "", - "", - "T82x_FRAG_ACTIVE", - "T82x_FRAG_PRIMITIVES", - "T82x_FRAG_PRIMITIVES_DROPPED", - "T82x_FRAG_CYCLES_DESC", - "T82x_FRAG_CYCLES_FPKQ_ACTIVE", - "T82x_FRAG_CYCLES_VERT", - "T82x_FRAG_CYCLES_TRISETUP", - "T82x_FRAG_CYCLES_EZS_ACTIVE", - "T82x_FRAG_THREADS", - "T82x_FRAG_DUMMY_THREADS", - "T82x_FRAG_QUADS_RAST", - "T82x_FRAG_QUADS_EZS_TEST", - "T82x_FRAG_QUADS_EZS_KILLED", - "T82x_FRAG_THREADS_LZS_TEST", - "T82x_FRAG_THREADS_LZS_KILLED", - "T82x_FRAG_CYCLES_NO_TILE", - "T82x_FRAG_NUM_TILES", - "T82x_FRAG_TRANS_ELIM", - "T82x_COMPUTE_ACTIVE", - "T82x_COMPUTE_TASKS", - "T82x_COMPUTE_THREADS", - "T82x_COMPUTE_CYCLES_DESC", - "T82x_TRIPIPE_ACTIVE", - "T82x_ARITH_WORDS", - "T82x_ARITH_CYCLES_REG", - "T82x_ARITH_CYCLES_L0", - "T82x_ARITH_FRAG_DEPEND", - "T82x_LS_WORDS", - "T82x_LS_ISSUES", - "T82x_LS_REISSUE_ATTR", - "T82x_LS_REISSUES_VARY", - "T82x_LS_VARY_RV_MISS", - "T82x_LS_VARY_RV_HIT", - "T82x_LS_NO_UNPARK", - "T82x_TEX_WORDS", - "T82x_TEX_BUBBLES", - "T82x_TEX_WORDS_L0", - "T82x_TEX_WORDS_DESC", - "T82x_TEX_ISSUES", - "T82x_TEX_RECIRC_FMISS", - "T82x_TEX_RECIRC_DESC", - "T82x_TEX_RECIRC_MULTI", - "T82x_TEX_RECIRC_PMISS", - "T82x_TEX_RECIRC_CONF", - "T82x_LSC_READ_HITS", - "T82x_LSC_READ_OP", - "T82x_LSC_WRITE_HITS", - "T82x_LSC_WRITE_OP", - "T82x_LSC_ATOMIC_HITS", - "T82x_LSC_ATOMIC_OP", - "T82x_LSC_LINE_FETCHES", - "T82x_LSC_DIRTY_LINE", - "T82x_LSC_SNOOPS", - "T82x_AXI_TLB_STALL", - "T82x_AXI_TLB_MISS", - "T82x_AXI_TLB_TRANSACTION", - "T82x_LS_TLB_MISS", - "T82x_LS_TLB_HIT", - "T82x_AXI_BEATS_READ", - "T82x_AXI_BEATS_WRITTEN", - - /*L2 and MMU */ - "", - "", - "", - "", - "T82x_MMU_HIT", - "T82x_MMU_NEW_MISS", - "T82x_MMU_REPLAY_FULL", - "T82x_MMU_REPLAY_MISS", - "T82x_MMU_TABLE_WALK", - "T82x_MMU_REQUESTS", - "", - "", - "T82x_UTLB_HIT", - "T82x_UTLB_NEW_MISS", - "T82x_UTLB_REPLAY_FULL", - "T82x_UTLB_REPLAY_MISS", - "T82x_UTLB_STALL", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "T82x_L2_EXT_WRITE_BEATS", - "T82x_L2_EXT_READ_BEATS", - "T82x_L2_ANY_LOOKUP", - "T82x_L2_READ_LOOKUP", - "T82x_L2_SREAD_LOOKUP", - "T82x_L2_READ_REPLAY", - "T82x_L2_READ_SNOOP", - "T82x_L2_READ_HIT", - "T82x_L2_CLEAN_MISS", - "T82x_L2_WRITE_LOOKUP", - "T82x_L2_SWRITE_LOOKUP", - "T82x_L2_WRITE_REPLAY", - "T82x_L2_WRITE_SNOOP", - "T82x_L2_WRITE_HIT", - "T82x_L2_EXT_READ_FULL", - "", - "T82x_L2_EXT_WRITE_FULL", - "T82x_L2_EXT_R_W_HAZARD", - "T82x_L2_EXT_READ", - "T82x_L2_EXT_READ_LINE", - "T82x_L2_EXT_WRITE", - "T82x_L2_EXT_WRITE_LINE", - "T82x_L2_EXT_WRITE_SMALL", - "T82x_L2_EXT_BARRIER", - "T82x_L2_EXT_AR_STALL", - "T82x_L2_EXT_R_BUF_FULL", - "T82x_L2_EXT_RD_BUF_FULL", - "T82x_L2_EXT_R_RAW", - "T82x_L2_EXT_W_STALL", - "T82x_L2_EXT_W_BUF_FULL", - "T82x_L2_EXT_R_BUF_FULL", - "T82x_L2_TAG_HAZARD", - "T82x_L2_SNOOP_FULL", - "T82x_L2_REPLAY_FULL" -}; - -static const char * const hardware_counters_mali_t83x[] = { - /* Job Manager */ - "", - "", - "", - "", - "T83x_MESSAGES_SENT", - "T83x_MESSAGES_RECEIVED", - "T83x_GPU_ACTIVE", - "T83x_IRQ_ACTIVE", - "T83x_JS0_JOBS", - "T83x_JS0_TASKS", - "T83x_JS0_ACTIVE", - "", - "T83x_JS0_WAIT_READ", - "T83x_JS0_WAIT_ISSUE", - "T83x_JS0_WAIT_DEPEND", - "T83x_JS0_WAIT_FINISH", - "T83x_JS1_JOBS", - "T83x_JS1_TASKS", - "T83x_JS1_ACTIVE", - "", - "T83x_JS1_WAIT_READ", - "T83x_JS1_WAIT_ISSUE", - "T83x_JS1_WAIT_DEPEND", - "T83x_JS1_WAIT_FINISH", - "T83x_JS2_JOBS", - "T83x_JS2_TASKS", - "T83x_JS2_ACTIVE", - "", - "T83x_JS2_WAIT_READ", - "T83x_JS2_WAIT_ISSUE", - "T83x_JS2_WAIT_DEPEND", - "T83x_JS2_WAIT_FINISH", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - - /*Tiler */ - "", - "", - "", - "T83x_TI_JOBS_PROCESSED", - "T83x_TI_TRIANGLES", - "T83x_TI_QUADS", - "T83x_TI_POLYGONS", - "T83x_TI_POINTS", - "T83x_TI_LINES", - "T83x_TI_FRONT_FACING", - "T83x_TI_BACK_FACING", - "T83x_TI_PRIM_VISIBLE", - "T83x_TI_PRIM_CULLED", - "T83x_TI_PRIM_CLIPPED", - "", - "", - "", - "", - "", - "", - "", - "", - "T83x_TI_ACTIVE", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - - /* Shader Core */ - "", - "", - "", - "", - "T83x_FRAG_ACTIVE", - "T83x_FRAG_PRIMITIVES", - "T83x_FRAG_PRIMITIVES_DROPPED", - "T83x_FRAG_CYCLES_DESC", - "T83x_FRAG_CYCLES_FPKQ_ACTIVE", - "T83x_FRAG_CYCLES_VERT", - "T83x_FRAG_CYCLES_TRISETUP", - "T83x_FRAG_CYCLES_EZS_ACTIVE", - "T83x_FRAG_THREADS", - "T83x_FRAG_DUMMY_THREADS", - "T83x_FRAG_QUADS_RAST", - "T83x_FRAG_QUADS_EZS_TEST", - "T83x_FRAG_QUADS_EZS_KILLED", - "T83x_FRAG_THREADS_LZS_TEST", - "T83x_FRAG_THREADS_LZS_KILLED", - "T83x_FRAG_CYCLES_NO_TILE", - "T83x_FRAG_NUM_TILES", - "T83x_FRAG_TRANS_ELIM", - "T83x_COMPUTE_ACTIVE", - "T83x_COMPUTE_TASKS", - "T83x_COMPUTE_THREADS", - "T83x_COMPUTE_CYCLES_DESC", - "T83x_TRIPIPE_ACTIVE", - "T83x_ARITH_WORDS", - "T83x_ARITH_CYCLES_REG", - "T83x_ARITH_CYCLES_L0", - "T83x_ARITH_FRAG_DEPEND", - "T83x_LS_WORDS", - "T83x_LS_ISSUES", - "T83x_LS_REISSUE_ATTR", - "T83x_LS_REISSUES_VARY", - "T83x_LS_VARY_RV_MISS", - "T83x_LS_VARY_RV_HIT", - "T83x_LS_NO_UNPARK", - "T83x_TEX_WORDS", - "T83x_TEX_BUBBLES", - "T83x_TEX_WORDS_L0", - "T83x_TEX_WORDS_DESC", - "T83x_TEX_ISSUES", - "T83x_TEX_RECIRC_FMISS", - "T83x_TEX_RECIRC_DESC", - "T83x_TEX_RECIRC_MULTI", - "T83x_TEX_RECIRC_PMISS", - "T83x_TEX_RECIRC_CONF", - "T83x_LSC_READ_HITS", - "T83x_LSC_READ_OP", - "T83x_LSC_WRITE_HITS", - "T83x_LSC_WRITE_OP", - "T83x_LSC_ATOMIC_HITS", - "T83x_LSC_ATOMIC_OP", - "T83x_LSC_LINE_FETCHES", - "T83x_LSC_DIRTY_LINE", - "T83x_LSC_SNOOPS", - "T83x_AXI_TLB_STALL", - "T83x_AXI_TLB_MISS", - "T83x_AXI_TLB_TRANSACTION", - "T83x_LS_TLB_MISS", - "T83x_LS_TLB_HIT", - "T83x_AXI_BEATS_READ", - "T83x_AXI_BEATS_WRITTEN", - - /*L2 and MMU */ - "", - "", - "", - "", - "T83x_MMU_HIT", - "T83x_MMU_NEW_MISS", - "T83x_MMU_REPLAY_FULL", - "T83x_MMU_REPLAY_MISS", - "T83x_MMU_TABLE_WALK", - "T83x_MMU_REQUESTS", - "", - "", - "T83x_UTLB_HIT", - "T83x_UTLB_NEW_MISS", - "T83x_UTLB_REPLAY_FULL", - "T83x_UTLB_REPLAY_MISS", - "T83x_UTLB_STALL", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "T83x_L2_EXT_WRITE_BEATS", - "T83x_L2_EXT_READ_BEATS", - "T83x_L2_ANY_LOOKUP", - "T83x_L2_READ_LOOKUP", - "T83x_L2_SREAD_LOOKUP", - "T83x_L2_READ_REPLAY", - "T83x_L2_READ_SNOOP", - "T83x_L2_READ_HIT", - "T83x_L2_CLEAN_MISS", - "T83x_L2_WRITE_LOOKUP", - "T83x_L2_SWRITE_LOOKUP", - "T83x_L2_WRITE_REPLAY", - "T83x_L2_WRITE_SNOOP", - "T83x_L2_WRITE_HIT", - "T83x_L2_EXT_READ_FULL", - "", - "T83x_L2_EXT_WRITE_FULL", - "T83x_L2_EXT_R_W_HAZARD", - "T83x_L2_EXT_READ", - "T83x_L2_EXT_READ_LINE", - "T83x_L2_EXT_WRITE", - "T83x_L2_EXT_WRITE_LINE", - "T83x_L2_EXT_WRITE_SMALL", - "T83x_L2_EXT_BARRIER", - "T83x_L2_EXT_AR_STALL", - "T83x_L2_EXT_R_BUF_FULL", - "T83x_L2_EXT_RD_BUF_FULL", - "T83x_L2_EXT_R_RAW", - "T83x_L2_EXT_W_STALL", - "T83x_L2_EXT_W_BUF_FULL", - "T83x_L2_EXT_R_BUF_FULL", - "T83x_L2_TAG_HAZARD", - "T83x_L2_SNOOP_FULL", - "T83x_L2_REPLAY_FULL" -}; - -static const char * const hardware_counters_mali_t86x[] = { - /* Job Manager */ - "", - "", - "", - "", - "T86x_MESSAGES_SENT", - "T86x_MESSAGES_RECEIVED", - "T86x_GPU_ACTIVE", - "T86x_IRQ_ACTIVE", - "T86x_JS0_JOBS", - "T86x_JS0_TASKS", - "T86x_JS0_ACTIVE", - "", - "T86x_JS0_WAIT_READ", - "T86x_JS0_WAIT_ISSUE", - "T86x_JS0_WAIT_DEPEND", - "T86x_JS0_WAIT_FINISH", - "T86x_JS1_JOBS", - "T86x_JS1_TASKS", - "T86x_JS1_ACTIVE", - "", - "T86x_JS1_WAIT_READ", - "T86x_JS1_WAIT_ISSUE", - "T86x_JS1_WAIT_DEPEND", - "T86x_JS1_WAIT_FINISH", - "T86x_JS2_JOBS", - "T86x_JS2_TASKS", - "T86x_JS2_ACTIVE", - "", - "T86x_JS2_WAIT_READ", - "T86x_JS2_WAIT_ISSUE", - "T86x_JS2_WAIT_DEPEND", - "T86x_JS2_WAIT_FINISH", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - - /*Tiler */ - "", - "", - "", - "T86x_TI_JOBS_PROCESSED", - "T86x_TI_TRIANGLES", - "T86x_TI_QUADS", - "T86x_TI_POLYGONS", - "T86x_TI_POINTS", - "T86x_TI_LINES", - "T86x_TI_VCACHE_HIT", - "T86x_TI_VCACHE_MISS", - "T86x_TI_FRONT_FACING", - "T86x_TI_BACK_FACING", - "T86x_TI_PRIM_VISIBLE", - "T86x_TI_PRIM_CULLED", - "T86x_TI_PRIM_CLIPPED", - "T86x_TI_LEVEL0", - "T86x_TI_LEVEL1", - "T86x_TI_LEVEL2", - "T86x_TI_LEVEL3", - "T86x_TI_LEVEL4", - "T86x_TI_LEVEL5", - "T86x_TI_LEVEL6", - "T86x_TI_LEVEL7", - "T86x_TI_COMMAND_1", - "T86x_TI_COMMAND_2", - "T86x_TI_COMMAND_3", - "T86x_TI_COMMAND_4", - "T86x_TI_COMMAND_5_7", - "T86x_TI_COMMAND_8_15", - "T86x_TI_COMMAND_16_63", - "T86x_TI_COMMAND_64", - "T86x_TI_COMPRESS_IN", - "T86x_TI_COMPRESS_OUT", - "T86x_TI_COMPRESS_FLUSH", - "T86x_TI_TIMESTAMPS", - "T86x_TI_PCACHE_HIT", - "T86x_TI_PCACHE_MISS", - "T86x_TI_PCACHE_LINE", - "T86x_TI_PCACHE_STALL", - "T86x_TI_WRBUF_HIT", - "T86x_TI_WRBUF_MISS", - "T86x_TI_WRBUF_LINE", - "T86x_TI_WRBUF_PARTIAL", - "T86x_TI_WRBUF_STALL", - "T86x_TI_ACTIVE", - "T86x_TI_LOADING_DESC", - "T86x_TI_INDEX_WAIT", - "T86x_TI_INDEX_RANGE_WAIT", - "T86x_TI_VERTEX_WAIT", - "T86x_TI_PCACHE_WAIT", - "T86x_TI_WRBUF_WAIT", - "T86x_TI_BUS_READ", - "T86x_TI_BUS_WRITE", - "", - "", - "", - "", - "", - "T86x_TI_UTLB_HIT", - "T86x_TI_UTLB_NEW_MISS", - "T86x_TI_UTLB_REPLAY_FULL", - "T86x_TI_UTLB_REPLAY_MISS", - "T86x_TI_UTLB_STALL", - - /* Shader Core */ - "", - "", - "", - "", - "T86x_FRAG_ACTIVE", - "T86x_FRAG_PRIMITIVES", - "T86x_FRAG_PRIMITIVES_DROPPED", - "T86x_FRAG_CYCLES_DESC", - "T86x_FRAG_CYCLES_FPKQ_ACTIVE", - "T86x_FRAG_CYCLES_VERT", - "T86x_FRAG_CYCLES_TRISETUP", - "T86x_FRAG_CYCLES_EZS_ACTIVE", - "T86x_FRAG_THREADS", - "T86x_FRAG_DUMMY_THREADS", - "T86x_FRAG_QUADS_RAST", - "T86x_FRAG_QUADS_EZS_TEST", - "T86x_FRAG_QUADS_EZS_KILLED", - "T86x_FRAG_THREADS_LZS_TEST", - "T86x_FRAG_THREADS_LZS_KILLED", - "T86x_FRAG_CYCLES_NO_TILE", - "T86x_FRAG_NUM_TILES", - "T86x_FRAG_TRANS_ELIM", - "T86x_COMPUTE_ACTIVE", - "T86x_COMPUTE_TASKS", - "T86x_COMPUTE_THREADS", - "T86x_COMPUTE_CYCLES_DESC", - "T86x_TRIPIPE_ACTIVE", - "T86x_ARITH_WORDS", - "T86x_ARITH_CYCLES_REG", - "T86x_ARITH_CYCLES_L0", - "T86x_ARITH_FRAG_DEPEND", - "T86x_LS_WORDS", - "T86x_LS_ISSUES", - "T86x_LS_REISSUE_ATTR", - "T86x_LS_REISSUES_VARY", - "T86x_LS_VARY_RV_MISS", - "T86x_LS_VARY_RV_HIT", - "T86x_LS_NO_UNPARK", - "T86x_TEX_WORDS", - "T86x_TEX_BUBBLES", - "T86x_TEX_WORDS_L0", - "T86x_TEX_WORDS_DESC", - "T86x_TEX_ISSUES", - "T86x_TEX_RECIRC_FMISS", - "T86x_TEX_RECIRC_DESC", - "T86x_TEX_RECIRC_MULTI", - "T86x_TEX_RECIRC_PMISS", - "T86x_TEX_RECIRC_CONF", - "T86x_LSC_READ_HITS", - "T86x_LSC_READ_OP", - "T86x_LSC_WRITE_HITS", - "T86x_LSC_WRITE_OP", - "T86x_LSC_ATOMIC_HITS", - "T86x_LSC_ATOMIC_OP", - "T86x_LSC_LINE_FETCHES", - "T86x_LSC_DIRTY_LINE", - "T86x_LSC_SNOOPS", - "T86x_AXI_TLB_STALL", - "T86x_AXI_TLB_MISS", - "T86x_AXI_TLB_TRANSACTION", - "T86x_LS_TLB_MISS", - "T86x_LS_TLB_HIT", - "T86x_AXI_BEATS_READ", - "T86x_AXI_BEATS_WRITTEN", - - /*L2 and MMU */ - "", - "", - "", - "", - "T86x_MMU_HIT", - "T86x_MMU_NEW_MISS", - "T86x_MMU_REPLAY_FULL", - "T86x_MMU_REPLAY_MISS", - "T86x_MMU_TABLE_WALK", - "T86x_MMU_REQUESTS", - "", - "", - "T86x_UTLB_HIT", - "T86x_UTLB_NEW_MISS", - "T86x_UTLB_REPLAY_FULL", - "T86x_UTLB_REPLAY_MISS", - "T86x_UTLB_STALL", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "T86x_L2_EXT_WRITE_BEATS", - "T86x_L2_EXT_READ_BEATS", - "T86x_L2_ANY_LOOKUP", - "T86x_L2_READ_LOOKUP", - "T86x_L2_SREAD_LOOKUP", - "T86x_L2_READ_REPLAY", - "T86x_L2_READ_SNOOP", - "T86x_L2_READ_HIT", - "T86x_L2_CLEAN_MISS", - "T86x_L2_WRITE_LOOKUP", - "T86x_L2_SWRITE_LOOKUP", - "T86x_L2_WRITE_REPLAY", - "T86x_L2_WRITE_SNOOP", - "T86x_L2_WRITE_HIT", - "T86x_L2_EXT_READ_FULL", - "", - "T86x_L2_EXT_WRITE_FULL", - "T86x_L2_EXT_R_W_HAZARD", - "T86x_L2_EXT_READ", - "T86x_L2_EXT_READ_LINE", - "T86x_L2_EXT_WRITE", - "T86x_L2_EXT_WRITE_LINE", - "T86x_L2_EXT_WRITE_SMALL", - "T86x_L2_EXT_BARRIER", - "T86x_L2_EXT_AR_STALL", - "T86x_L2_EXT_R_BUF_FULL", - "T86x_L2_EXT_RD_BUF_FULL", - "T86x_L2_EXT_R_RAW", - "T86x_L2_EXT_W_STALL", - "T86x_L2_EXT_W_BUF_FULL", - "T86x_L2_EXT_R_BUF_FULL", - "T86x_L2_TAG_HAZARD", - "T86x_L2_SNOOP_FULL", - "T86x_L2_REPLAY_FULL" -}; - -static const char * const hardware_counters_mali_t88x[] = { - /* Job Manager */ - "", - "", - "", - "", - "T88x_MESSAGES_SENT", - "T88x_MESSAGES_RECEIVED", - "T88x_GPU_ACTIVE", - "T88x_IRQ_ACTIVE", - "T88x_JS0_JOBS", - "T88x_JS0_TASKS", - "T88x_JS0_ACTIVE", - "", - "T88x_JS0_WAIT_READ", - "T88x_JS0_WAIT_ISSUE", - "T88x_JS0_WAIT_DEPEND", - "T88x_JS0_WAIT_FINISH", - "T88x_JS1_JOBS", - "T88x_JS1_TASKS", - "T88x_JS1_ACTIVE", - "", - "T88x_JS1_WAIT_READ", - "T88x_JS1_WAIT_ISSUE", - "T88x_JS1_WAIT_DEPEND", - "T88x_JS1_WAIT_FINISH", - "T88x_JS2_JOBS", - "T88x_JS2_TASKS", - "T88x_JS2_ACTIVE", - "", - "T88x_JS2_WAIT_READ", - "T88x_JS2_WAIT_ISSUE", - "T88x_JS2_WAIT_DEPEND", - "T88x_JS2_WAIT_FINISH", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - - /*Tiler */ - "", - "", - "", - "T88x_TI_JOBS_PROCESSED", - "T88x_TI_TRIANGLES", - "T88x_TI_QUADS", - "T88x_TI_POLYGONS", - "T88x_TI_POINTS", - "T88x_TI_LINES", - "T88x_TI_VCACHE_HIT", - "T88x_TI_VCACHE_MISS", - "T88x_TI_FRONT_FACING", - "T88x_TI_BACK_FACING", - "T88x_TI_PRIM_VISIBLE", - "T88x_TI_PRIM_CULLED", - "T88x_TI_PRIM_CLIPPED", - "T88x_TI_LEVEL0", - "T88x_TI_LEVEL1", - "T88x_TI_LEVEL2", - "T88x_TI_LEVEL3", - "T88x_TI_LEVEL4", - "T88x_TI_LEVEL5", - "T88x_TI_LEVEL6", - "T88x_TI_LEVEL7", - "T88x_TI_COMMAND_1", - "T88x_TI_COMMAND_2", - "T88x_TI_COMMAND_3", - "T88x_TI_COMMAND_4", - "T88x_TI_COMMAND_5_7", - "T88x_TI_COMMAND_8_15", - "T88x_TI_COMMAND_16_63", - "T88x_TI_COMMAND_64", - "T88x_TI_COMPRESS_IN", - "T88x_TI_COMPRESS_OUT", - "T88x_TI_COMPRESS_FLUSH", - "T88x_TI_TIMESTAMPS", - "T88x_TI_PCACHE_HIT", - "T88x_TI_PCACHE_MISS", - "T88x_TI_PCACHE_LINE", - "T88x_TI_PCACHE_STALL", - "T88x_TI_WRBUF_HIT", - "T88x_TI_WRBUF_MISS", - "T88x_TI_WRBUF_LINE", - "T88x_TI_WRBUF_PARTIAL", - "T88x_TI_WRBUF_STALL", - "T88x_TI_ACTIVE", - "T88x_TI_LOADING_DESC", - "T88x_TI_INDEX_WAIT", - "T88x_TI_INDEX_RANGE_WAIT", - "T88x_TI_VERTEX_WAIT", - "T88x_TI_PCACHE_WAIT", - "T88x_TI_WRBUF_WAIT", - "T88x_TI_BUS_READ", - "T88x_TI_BUS_WRITE", - "", - "", - "", - "", - "", - "T88x_TI_UTLB_HIT", - "T88x_TI_UTLB_NEW_MISS", - "T88x_TI_UTLB_REPLAY_FULL", - "T88x_TI_UTLB_REPLAY_MISS", - "T88x_TI_UTLB_STALL", - - /* Shader Core */ - "", - "", - "", - "", - "T88x_FRAG_ACTIVE", - "T88x_FRAG_PRIMITIVES", - "T88x_FRAG_PRIMITIVES_DROPPED", - "T88x_FRAG_CYCLES_DESC", - "T88x_FRAG_CYCLES_FPKQ_ACTIVE", - "T88x_FRAG_CYCLES_VERT", - "T88x_FRAG_CYCLES_TRISETUP", - "T88x_FRAG_CYCLES_EZS_ACTIVE", - "T88x_FRAG_THREADS", - "T88x_FRAG_DUMMY_THREADS", - "T88x_FRAG_QUADS_RAST", - "T88x_FRAG_QUADS_EZS_TEST", - "T88x_FRAG_QUADS_EZS_KILLED", - "T88x_FRAG_THREADS_LZS_TEST", - "T88x_FRAG_THREADS_LZS_KILLED", - "T88x_FRAG_CYCLES_NO_TILE", - "T88x_FRAG_NUM_TILES", - "T88x_FRAG_TRANS_ELIM", - "T88x_COMPUTE_ACTIVE", - "T88x_COMPUTE_TASKS", - "T88x_COMPUTE_THREADS", - "T88x_COMPUTE_CYCLES_DESC", - "T88x_TRIPIPE_ACTIVE", - "T88x_ARITH_WORDS", - "T88x_ARITH_CYCLES_REG", - "T88x_ARITH_CYCLES_L0", - "T88x_ARITH_FRAG_DEPEND", - "T88x_LS_WORDS", - "T88x_LS_ISSUES", - "T88x_LS_REISSUE_ATTR", - "T88x_LS_REISSUES_VARY", - "T88x_LS_VARY_RV_MISS", - "T88x_LS_VARY_RV_HIT", - "T88x_LS_NO_UNPARK", - "T88x_TEX_WORDS", - "T88x_TEX_BUBBLES", - "T88x_TEX_WORDS_L0", - "T88x_TEX_WORDS_DESC", - "T88x_TEX_ISSUES", - "T88x_TEX_RECIRC_FMISS", - "T88x_TEX_RECIRC_DESC", - "T88x_TEX_RECIRC_MULTI", - "T88x_TEX_RECIRC_PMISS", - "T88x_TEX_RECIRC_CONF", - "T88x_LSC_READ_HITS", - "T88x_LSC_READ_OP", - "T88x_LSC_WRITE_HITS", - "T88x_LSC_WRITE_OP", - "T88x_LSC_ATOMIC_HITS", - "T88x_LSC_ATOMIC_OP", - "T88x_LSC_LINE_FETCHES", - "T88x_LSC_DIRTY_LINE", - "T88x_LSC_SNOOPS", - "T88x_AXI_TLB_STALL", - "T88x_AXI_TLB_MISS", - "T88x_AXI_TLB_TRANSACTION", - "T88x_LS_TLB_MISS", - "T88x_LS_TLB_HIT", - "T88x_AXI_BEATS_READ", - "T88x_AXI_BEATS_WRITTEN", - - /*L2 and MMU */ - "", - "", - "", - "", - "T88x_MMU_HIT", - "T88x_MMU_NEW_MISS", - "T88x_MMU_REPLAY_FULL", - "T88x_MMU_REPLAY_MISS", - "T88x_MMU_TABLE_WALK", - "T88x_MMU_REQUESTS", - "", - "", - "T88x_UTLB_HIT", - "T88x_UTLB_NEW_MISS", - "T88x_UTLB_REPLAY_FULL", - "T88x_UTLB_REPLAY_MISS", - "T88x_UTLB_STALL", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "T88x_L2_EXT_WRITE_BEATS", - "T88x_L2_EXT_READ_BEATS", - "T88x_L2_ANY_LOOKUP", - "T88x_L2_READ_LOOKUP", - "T88x_L2_SREAD_LOOKUP", - "T88x_L2_READ_REPLAY", - "T88x_L2_READ_SNOOP", - "T88x_L2_READ_HIT", - "T88x_L2_CLEAN_MISS", - "T88x_L2_WRITE_LOOKUP", - "T88x_L2_SWRITE_LOOKUP", - "T88x_L2_WRITE_REPLAY", - "T88x_L2_WRITE_SNOOP", - "T88x_L2_WRITE_HIT", - "T88x_L2_EXT_READ_FULL", - "", - "T88x_L2_EXT_WRITE_FULL", - "T88x_L2_EXT_R_W_HAZARD", - "T88x_L2_EXT_READ", - "T88x_L2_EXT_READ_LINE", - "T88x_L2_EXT_WRITE", - "T88x_L2_EXT_WRITE_LINE", - "T88x_L2_EXT_WRITE_SMALL", - "T88x_L2_EXT_BARRIER", - "T88x_L2_EXT_AR_STALL", - "T88x_L2_EXT_R_BUF_FULL", - "T88x_L2_EXT_RD_BUF_FULL", - "T88x_L2_EXT_R_RAW", - "T88x_L2_EXT_W_STALL", - "T88x_L2_EXT_W_BUF_FULL", - "T88x_L2_EXT_R_BUF_FULL", - "T88x_L2_TAG_HAZARD", - "T88x_L2_SNOOP_FULL", - "T88x_L2_REPLAY_FULL" -}; - -#include "mali_kbase_gator_hwcnt_names_tmix.h" - -#include "mali_kbase_gator_hwcnt_names_thex.h" - -#include "mali_kbase_gator_hwcnt_names_tsix.h" - -#include "mali_kbase_gator_hwcnt_names_tnox.h" - -#include "mali_kbase_gator_hwcnt_names_tgox.h" - -#include "mali_kbase_gator_hwcnt_names_ttrx.h" - -#include "mali_kbase_gator_hwcnt_names_tnax.h" - -#include "mali_kbase_gator_hwcnt_names_tbex.h" - -#endif diff --git a/mali_kbase/mali_kbase_gator_hwcnt_names_tbex.h b/mali_kbase/mali_kbase_gator_hwcnt_names_tbex.h deleted file mode 100644 index 8282a39..0000000 --- a/mali_kbase/mali_kbase_gator_hwcnt_names_tbex.h +++ /dev/null @@ -1,296 +0,0 @@ -/* - * - * (C) COPYRIGHT 2016-2019 ARM Limited. All rights reserved. - * - * This program is free software and is provided to you under the terms of the - * GNU General Public License version 2 as published by the Free Software - * Foundation, and any use by you of this program is subject to the terms - * of such GNU licence. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you can access it online at - * http://www.gnu.org/licenses/gpl-2.0.html. - * - * SPDX-License-Identifier: GPL-2.0 - * - */ - -/* - * This header was autogenerated, it should not be edited. - */ - -#ifndef _KBASE_GATOR_HWCNT_NAMES_TBEX_H_ -#define _KBASE_GATOR_HWCNT_NAMES_TBEX_H_ - -static const char * const hardware_counters_mali_tBEx[] = { - /* Performance counters for the Job Manager */ - "", - "", - "", - "", - "TBEx_MESSAGES_SENT", - "TBEx_MESSAGES_RECEIVED", - "TBEx_GPU_ACTIVE", - "TBEx_IRQ_ACTIVE", - "TBEx_JS0_JOBS", - "TBEx_JS0_TASKS", - "TBEx_JS0_ACTIVE", - "", - "TBEx_JS0_WAIT_READ", - "TBEx_JS0_WAIT_ISSUE", - "TBEx_JS0_WAIT_DEPEND", - "TBEx_JS0_WAIT_FINISH", - "TBEx_JS1_JOBS", - "TBEx_JS1_TASKS", - "TBEx_JS1_ACTIVE", - "", - "TBEx_JS1_WAIT_READ", - "TBEx_JS1_WAIT_ISSUE", - "TBEx_JS1_WAIT_DEPEND", - "TBEx_JS1_WAIT_FINISH", - "TBEx_JS2_JOBS", - "TBEx_JS2_TASKS", - "TBEx_JS2_ACTIVE", - "", - "TBEx_JS2_WAIT_READ", - "TBEx_JS2_WAIT_ISSUE", - "TBEx_JS2_WAIT_DEPEND", - "TBEx_JS2_WAIT_FINISH", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - - /* Performance counters for the Tiler */ - "", - "", - "", - "", - "TBEx_TILER_ACTIVE", - "TBEx_JOBS_PROCESSED", - "TBEx_TRIANGLES", - "TBEx_LINES", - "TBEx_POINTS", - "TBEx_FRONT_FACING", - "TBEx_BACK_FACING", - "TBEx_PRIM_VISIBLE", - "TBEx_PRIM_CULLED", - "TBEx_PRIM_CLIPPED", - "TBEx_PRIM_SAT_CULLED", - "TBEx_BIN_ALLOC_INIT", - "TBEx_BIN_ALLOC_OVERFLOW", - "TBEx_BUS_READ", - "", - "TBEx_BUS_WRITE", - "TBEx_LOADING_DESC", - "TBEx_IDVS_POS_SHAD_REQ", - "TBEx_IDVS_POS_SHAD_WAIT", - "TBEx_IDVS_POS_SHAD_STALL", - "TBEx_IDVS_POS_FIFO_FULL", - "TBEx_PREFETCH_STALL", - "TBEx_VCACHE_HIT", - "TBEx_VCACHE_MISS", - "TBEx_VCACHE_LINE_WAIT", - "TBEx_VFETCH_POS_READ_WAIT", - "TBEx_VFETCH_VERTEX_WAIT", - "TBEx_VFETCH_STALL", - "TBEx_PRIMASSY_STALL", - "TBEx_BBOX_GEN_STALL", - "TBEx_IDVS_VBU_HIT", - "TBEx_IDVS_VBU_MISS", - "TBEx_IDVS_VBU_LINE_DEALLOCATE", - "TBEx_IDVS_VAR_SHAD_REQ", - "TBEx_IDVS_VAR_SHAD_STALL", - "TBEx_BINNER_STALL", - "TBEx_ITER_STALL", - "TBEx_COMPRESS_MISS", - "TBEx_COMPRESS_STALL", - "TBEx_PCACHE_HIT", - "TBEx_PCACHE_MISS", - "TBEx_PCACHE_MISS_STALL", - "TBEx_PCACHE_EVICT_STALL", - "TBEx_PMGR_PTR_WR_STALL", - "TBEx_PMGR_PTR_RD_STALL", - "TBEx_PMGR_CMD_WR_STALL", - "TBEx_WRBUF_ACTIVE", - "TBEx_WRBUF_HIT", - "TBEx_WRBUF_MISS", - "TBEx_WRBUF_NO_FREE_LINE_STALL", - "TBEx_WRBUF_NO_AXI_ID_STALL", - "TBEx_WRBUF_AXI_STALL", - "", - "", - "", - "TBEx_UTLB_TRANS", - "TBEx_UTLB_TRANS_HIT", - "TBEx_UTLB_TRANS_STALL", - "TBEx_UTLB_TRANS_MISS_DELAY", - "TBEx_UTLB_MMU_REQ", - - /* Performance counters for the Shader Core */ - "", - "", - "", - "", - "TBEx_FRAG_ACTIVE", - "TBEx_FRAG_PRIMITIVES_OUT", - "TBEx_FRAG_PRIM_RAST", - "TBEx_FRAG_FPK_ACTIVE", - "TBEx_FRAG_STARVING", - "TBEx_FRAG_WARPS", - "TBEx_FRAG_PARTIAL_QUADS_RAST", - "TBEx_FRAG_QUADS_RAST", - "TBEx_FRAG_QUADS_EZS_TEST", - "TBEx_FRAG_QUADS_EZS_UPDATE", - "TBEx_FRAG_QUADS_EZS_KILL", - "TBEx_FRAG_LZS_TEST", - "TBEx_FRAG_LZS_KILL", - "TBEx_WARP_REG_SIZE_64", - "TBEx_FRAG_PTILES", - "TBEx_FRAG_TRANS_ELIM", - "TBEx_QUAD_FPK_KILLER", - "TBEx_FULL_QUAD_WARPS", - "TBEx_COMPUTE_ACTIVE", - "TBEx_COMPUTE_TASKS", - "TBEx_COMPUTE_WARPS", - "TBEx_COMPUTE_STARVING", - "TBEx_EXEC_CORE_ACTIVE", - "TBEx_EXEC_INSTR_FMA", - "TBEx_EXEC_INSTR_CVT", - "TBEx_EXEC_INSTR_SFU", - "TBEx_EXEC_INSTR_MSG", - "TBEx_EXEC_INSTR_DIVERGED", - "TBEx_EXEC_ICACHE_MISS", - "TBEx_EXEC_STARVE_ARITH", - "TBEx_CALL_BLEND_SHADER", - "TBEx_TEX_MSGI_NUM_FLITS", - "TBEx_TEX_DFCH_CLK_STALLED", - "TBEx_TEX_TFCH_CLK_STALLED", - "TBEx_TEX_TFCH_STARVED_PENDING_DATA_FETCH", - "TBEx_TEX_FILT_NUM_OPERATIONS", - "TBEx_TEX_FILT_NUM_FXR_OPERATIONS", - "TBEx_TEX_FILT_NUM_FST_OPERATIONS", - "TBEx_TEX_MSGO_NUM_MSG", - "TBEx_TEX_MSGO_NUM_FLITS", - "TBEx_LS_MEM_READ_FULL", - "TBEx_LS_MEM_READ_SHORT", - "TBEx_LS_MEM_WRITE_FULL", - "TBEx_LS_MEM_WRITE_SHORT", - "TBEx_LS_MEM_ATOMIC", - "TBEx_VARY_INSTR", - "TBEx_VARY_SLOT_32", - "TBEx_VARY_SLOT_16", - "TBEx_ATTR_INSTR", - "TBEx_ARITH_INSTR_FP_MUL", - "TBEx_BEATS_RD_FTC", - "TBEx_BEATS_RD_FTC_EXT", - "TBEx_BEATS_RD_LSC", - "TBEx_BEATS_RD_LSC_EXT", - "TBEx_BEATS_RD_TEX", - "TBEx_BEATS_RD_TEX_EXT", - "TBEx_BEATS_RD_OTHER", - "TBEx_BEATS_WR_LSC_OTHER", - "TBEx_BEATS_WR_TIB", - "TBEx_BEATS_WR_LSC_WB", - - /* Performance counters for the Memory System */ - "", - "", - "", - "", - "TBEx_MMU_REQUESTS", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "TBEx_L2_RD_MSG_IN", - "TBEx_L2_RD_MSG_IN_STALL", - "TBEx_L2_WR_MSG_IN", - "TBEx_L2_WR_MSG_IN_STALL", - "TBEx_L2_SNP_MSG_IN", - "TBEx_L2_SNP_MSG_IN_STALL", - "TBEx_L2_RD_MSG_OUT", - "TBEx_L2_RD_MSG_OUT_STALL", - "TBEx_L2_WR_MSG_OUT", - "TBEx_L2_ANY_LOOKUP", - "TBEx_L2_READ_LOOKUP", - "TBEx_L2_WRITE_LOOKUP", - "TBEx_L2_EXT_SNOOP_LOOKUP", - "TBEx_L2_EXT_READ", - "TBEx_L2_EXT_READ_NOSNP", - "TBEx_L2_EXT_READ_UNIQUE", - "TBEx_L2_EXT_READ_BEATS", - "TBEx_L2_EXT_AR_STALL", - "TBEx_L2_EXT_AR_CNT_Q1", - "TBEx_L2_EXT_AR_CNT_Q2", - "TBEx_L2_EXT_AR_CNT_Q3", - "TBEx_L2_EXT_RRESP_0_127", - "TBEx_L2_EXT_RRESP_128_191", - "TBEx_L2_EXT_RRESP_192_255", - "TBEx_L2_EXT_RRESP_256_319", - "TBEx_L2_EXT_RRESP_320_383", - "TBEx_L2_EXT_WRITE", - "TBEx_L2_EXT_WRITE_NOSNP_FULL", - "TBEx_L2_EXT_WRITE_NOSNP_PTL", - "TBEx_L2_EXT_WRITE_SNP_FULL", - "TBEx_L2_EXT_WRITE_SNP_PTL", - "TBEx_L2_EXT_WRITE_BEATS", - "TBEx_L2_EXT_W_STALL", - "TBEx_L2_EXT_AW_CNT_Q1", - "TBEx_L2_EXT_AW_CNT_Q2", - "TBEx_L2_EXT_AW_CNT_Q3", - "TBEx_L2_EXT_SNOOP", - "TBEx_L2_EXT_SNOOP_STALL", - "TBEx_L2_EXT_SNOOP_RESP_CLEAN", - "TBEx_L2_EXT_SNOOP_RESP_DATA", - "TBEx_L2_EXT_SNOOP_INTERNAL", - "", - "", - "", - "", - "", - "", - "", -}; - -#endif /* _KBASE_GATOR_HWCNT_NAMES_TBEX_H_ */ diff --git a/mali_kbase/mali_kbase_gator_hwcnt_names_tgox.h b/mali_kbase/mali_kbase_gator_hwcnt_names_tgox.h deleted file mode 100644 index 72b5266..0000000 --- a/mali_kbase/mali_kbase_gator_hwcnt_names_tgox.h +++ /dev/null @@ -1,296 +0,0 @@ -/* - * - * (C) COPYRIGHT 2016-2018 ARM Limited. All rights reserved. - * - * This program is free software and is provided to you under the terms of the - * GNU General Public License version 2 as published by the Free Software - * Foundation, and any use by you of this program is subject to the terms - * of such GNU licence. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you can access it online at - * http://www.gnu.org/licenses/gpl-2.0.html. - * - * SPDX-License-Identifier: GPL-2.0 - * - */ - -/* - * This header was autogenerated, it should not be edited. - */ - -#ifndef _KBASE_GATOR_HWCNT_NAMES_TGOX_H_ -#define _KBASE_GATOR_HWCNT_NAMES_TGOX_H_ - -static const char * const hardware_counters_mali_tGOx[] = { - /* Performance counters for the Job Manager */ - "", - "", - "", - "", - "TGOx_MESSAGES_SENT", - "TGOx_MESSAGES_RECEIVED", - "TGOx_GPU_ACTIVE", - "TGOx_IRQ_ACTIVE", - "TGOx_JS0_JOBS", - "TGOx_JS0_TASKS", - "TGOx_JS0_ACTIVE", - "", - "TGOx_JS0_WAIT_READ", - "TGOx_JS0_WAIT_ISSUE", - "TGOx_JS0_WAIT_DEPEND", - "TGOx_JS0_WAIT_FINISH", - "TGOx_JS1_JOBS", - "TGOx_JS1_TASKS", - "TGOx_JS1_ACTIVE", - "", - "TGOx_JS1_WAIT_READ", - "TGOx_JS1_WAIT_ISSUE", - "TGOx_JS1_WAIT_DEPEND", - "TGOx_JS1_WAIT_FINISH", - "TGOx_JS2_JOBS", - "TGOx_JS2_TASKS", - "TGOx_JS2_ACTIVE", - "", - "TGOx_JS2_WAIT_READ", - "TGOx_JS2_WAIT_ISSUE", - "TGOx_JS2_WAIT_DEPEND", - "TGOx_JS2_WAIT_FINISH", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - - /* Performance counters for the Tiler */ - "", - "", - "", - "", - "TGOx_TILER_ACTIVE", - "TGOx_JOBS_PROCESSED", - "TGOx_TRIANGLES", - "TGOx_LINES", - "TGOx_POINTS", - "TGOx_FRONT_FACING", - "TGOx_BACK_FACING", - "TGOx_PRIM_VISIBLE", - "TGOx_PRIM_CULLED", - "TGOx_PRIM_CLIPPED", - "TGOx_PRIM_SAT_CULLED", - "TGOx_BIN_ALLOC_INIT", - "TGOx_BIN_ALLOC_OVERFLOW", - "TGOx_BUS_READ", - "", - "TGOx_BUS_WRITE", - "TGOx_LOADING_DESC", - "TGOx_IDVS_POS_SHAD_REQ", - "TGOx_IDVS_POS_SHAD_WAIT", - "TGOx_IDVS_POS_SHAD_STALL", - "TGOx_IDVS_POS_FIFO_FULL", - "TGOx_PREFETCH_STALL", - "TGOx_VCACHE_HIT", - "TGOx_VCACHE_MISS", - "TGOx_VCACHE_LINE_WAIT", - "TGOx_VFETCH_POS_READ_WAIT", - "TGOx_VFETCH_VERTEX_WAIT", - "TGOx_VFETCH_STALL", - "TGOx_PRIMASSY_STALL", - "TGOx_BBOX_GEN_STALL", - "TGOx_IDVS_VBU_HIT", - "TGOx_IDVS_VBU_MISS", - "TGOx_IDVS_VBU_LINE_DEALLOCATE", - "TGOx_IDVS_VAR_SHAD_REQ", - "TGOx_IDVS_VAR_SHAD_STALL", - "TGOx_BINNER_STALL", - "TGOx_ITER_STALL", - "TGOx_COMPRESS_MISS", - "TGOx_COMPRESS_STALL", - "TGOx_PCACHE_HIT", - "TGOx_PCACHE_MISS", - "TGOx_PCACHE_MISS_STALL", - "TGOx_PCACHE_EVICT_STALL", - "TGOx_PMGR_PTR_WR_STALL", - "TGOx_PMGR_PTR_RD_STALL", - "TGOx_PMGR_CMD_WR_STALL", - "TGOx_WRBUF_ACTIVE", - "TGOx_WRBUF_HIT", - "TGOx_WRBUF_MISS", - "TGOx_WRBUF_NO_FREE_LINE_STALL", - "TGOx_WRBUF_NO_AXI_ID_STALL", - "TGOx_WRBUF_AXI_STALL", - "", - "", - "", - "TGOx_UTLB_TRANS", - "TGOx_UTLB_TRANS_HIT", - "TGOx_UTLB_TRANS_STALL", - "TGOx_UTLB_TRANS_MISS_DELAY", - "TGOx_UTLB_MMU_REQ", - - /* Performance counters for the Shader Core */ - "", - "", - "", - "", - "TGOx_FRAG_ACTIVE", - "TGOx_FRAG_PRIMITIVES", - "TGOx_FRAG_PRIM_RAST", - "TGOx_FRAG_FPK_ACTIVE", - "TGOx_FRAG_STARVING", - "TGOx_FRAG_WARPS", - "TGOx_FRAG_PARTIAL_WARPS", - "TGOx_FRAG_QUADS_RAST", - "TGOx_FRAG_QUADS_EZS_TEST", - "TGOx_FRAG_QUADS_EZS_UPDATE", - "TGOx_FRAG_QUADS_EZS_KILL", - "TGOx_FRAG_LZS_TEST", - "TGOx_FRAG_LZS_KILL", - "TGOx_WARP_REG_SIZE_64", - "TGOx_FRAG_PTILES", - "TGOx_FRAG_TRANS_ELIM", - "TGOx_QUAD_FPK_KILLER", - "TGOx_FULL_QUAD_WARPS", - "TGOx_COMPUTE_ACTIVE", - "TGOx_COMPUTE_TASKS", - "TGOx_COMPUTE_WARPS", - "TGOx_COMPUTE_STARVING", - "TGOx_EXEC_CORE_ACTIVE", - "TGOx_EXEC_ACTIVE", - "TGOx_EXEC_INSTR_COUNT", - "TGOx_EXEC_INSTR_DIVERGED", - "TGOx_EXEC_INSTR_STARVING", - "TGOx_ARITH_INSTR_SINGLE_FMA", - "TGOx_ARITH_INSTR_DOUBLE", - "TGOx_ARITH_INSTR_MSG", - "TGOx_ARITH_INSTR_MSG_ONLY", - "TGOx_TEX_MSGI_NUM_QUADS", - "TGOx_TEX_DFCH_NUM_PASSES", - "TGOx_TEX_DFCH_NUM_PASSES_MISS", - "TGOx_TEX_DFCH_NUM_PASSES_MIP_MAP", - "TGOx_TEX_TIDX_NUM_SPLIT_MIP_MAP", - "TGOx_TEX_TFCH_NUM_LINES_FETCHED", - "TGOx_TEX_TFCH_NUM_LINES_FETCHED_BLOCK", - "TGOx_TEX_TFCH_NUM_OPERATIONS", - "TGOx_TEX_FILT_NUM_OPERATIONS", - "TGOx_LS_MEM_READ_FULL", - "TGOx_LS_MEM_READ_SHORT", - "TGOx_LS_MEM_WRITE_FULL", - "TGOx_LS_MEM_WRITE_SHORT", - "TGOx_LS_MEM_ATOMIC", - "TGOx_VARY_INSTR", - "TGOx_VARY_SLOT_32", - "TGOx_VARY_SLOT_16", - "TGOx_ATTR_INSTR", - "TGOx_ARITH_INSTR_FP_MUL", - "TGOx_BEATS_RD_FTC", - "TGOx_BEATS_RD_FTC_EXT", - "TGOx_BEATS_RD_LSC", - "TGOx_BEATS_RD_LSC_EXT", - "TGOx_BEATS_RD_TEX", - "TGOx_BEATS_RD_TEX_EXT", - "TGOx_BEATS_RD_OTHER", - "TGOx_BEATS_WR_LSC_WB", - "TGOx_BEATS_WR_TIB", - "TGOx_BEATS_WR_LSC_OTHER", - - /* Performance counters for the Memory System */ - "", - "", - "", - "", - "TGOx_MMU_REQUESTS", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "TGOx_L2_RD_MSG_IN", - "TGOx_L2_RD_MSG_IN_STALL", - "TGOx_L2_WR_MSG_IN", - "TGOx_L2_WR_MSG_IN_STALL", - "TGOx_L2_SNP_MSG_IN", - "TGOx_L2_SNP_MSG_IN_STALL", - "TGOx_L2_RD_MSG_OUT", - "TGOx_L2_RD_MSG_OUT_STALL", - "TGOx_L2_WR_MSG_OUT", - "TGOx_L2_ANY_LOOKUP", - "TGOx_L2_READ_LOOKUP", - "TGOx_L2_WRITE_LOOKUP", - "TGOx_L2_EXT_SNOOP_LOOKUP", - "TGOx_L2_EXT_READ", - "TGOx_L2_EXT_READ_NOSNP", - "TGOx_L2_EXT_READ_UNIQUE", - "TGOx_L2_EXT_READ_BEATS", - "TGOx_L2_EXT_AR_STALL", - "TGOx_L2_EXT_AR_CNT_Q1", - "TGOx_L2_EXT_AR_CNT_Q2", - "TGOx_L2_EXT_AR_CNT_Q3", - "TGOx_L2_EXT_RRESP_0_127", - "TGOx_L2_EXT_RRESP_128_191", - "TGOx_L2_EXT_RRESP_192_255", - "TGOx_L2_EXT_RRESP_256_319", - "TGOx_L2_EXT_RRESP_320_383", - "TGOx_L2_EXT_WRITE", - "TGOx_L2_EXT_WRITE_NOSNP_FULL", - "TGOx_L2_EXT_WRITE_NOSNP_PTL", - "TGOx_L2_EXT_WRITE_SNP_FULL", - "TGOx_L2_EXT_WRITE_SNP_PTL", - "TGOx_L2_EXT_WRITE_BEATS", - "TGOx_L2_EXT_W_STALL", - "TGOx_L2_EXT_AW_CNT_Q1", - "TGOx_L2_EXT_AW_CNT_Q2", - "TGOx_L2_EXT_AW_CNT_Q3", - "TGOx_L2_EXT_SNOOP", - "TGOx_L2_EXT_SNOOP_STALL", - "TGOx_L2_EXT_SNOOP_RESP_CLEAN", - "TGOx_L2_EXT_SNOOP_RESP_DATA", - "TGOx_L2_EXT_SNOOP_INTERNAL", - "", - "", - "", - "", - "", - "", - "", -}; - -#endif /* _KBASE_GATOR_HWCNT_NAMES_TGOX_H_ */ diff --git a/mali_kbase/mali_kbase_gator_hwcnt_names_thex.h b/mali_kbase/mali_kbase_gator_hwcnt_names_thex.h deleted file mode 100644 index e24e91a..0000000 --- a/mali_kbase/mali_kbase_gator_hwcnt_names_thex.h +++ /dev/null @@ -1,296 +0,0 @@ -/* - * - * (C) COPYRIGHT 2016-2018 ARM Limited. All rights reserved. - * - * This program is free software and is provided to you under the terms of the - * GNU General Public License version 2 as published by the Free Software - * Foundation, and any use by you of this program is subject to the terms - * of such GNU licence. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you can access it online at - * http://www.gnu.org/licenses/gpl-2.0.html. - * - * SPDX-License-Identifier: GPL-2.0 - * - */ - -/* - * This header was autogenerated, it should not be edited. - */ - -#ifndef _KBASE_GATOR_HWCNT_NAMES_THEX_H_ -#define _KBASE_GATOR_HWCNT_NAMES_THEX_H_ - -static const char * const hardware_counters_mali_tHEx[] = { - /* Performance counters for the Job Manager */ - "", - "", - "", - "", - "THEx_MESSAGES_SENT", - "THEx_MESSAGES_RECEIVED", - "THEx_GPU_ACTIVE", - "THEx_IRQ_ACTIVE", - "THEx_JS0_JOBS", - "THEx_JS0_TASKS", - "THEx_JS0_ACTIVE", - "", - "THEx_JS0_WAIT_READ", - "THEx_JS0_WAIT_ISSUE", - "THEx_JS0_WAIT_DEPEND", - "THEx_JS0_WAIT_FINISH", - "THEx_JS1_JOBS", - "THEx_JS1_TASKS", - "THEx_JS1_ACTIVE", - "", - "THEx_JS1_WAIT_READ", - "THEx_JS1_WAIT_ISSUE", - "THEx_JS1_WAIT_DEPEND", - "THEx_JS1_WAIT_FINISH", - "THEx_JS2_JOBS", - "THEx_JS2_TASKS", - "THEx_JS2_ACTIVE", - "", - "THEx_JS2_WAIT_READ", - "THEx_JS2_WAIT_ISSUE", - "THEx_JS2_WAIT_DEPEND", - "THEx_JS2_WAIT_FINISH", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - - /* Performance counters for the Tiler */ - "", - "", - "", - "", - "THEx_TILER_ACTIVE", - "THEx_JOBS_PROCESSED", - "THEx_TRIANGLES", - "THEx_LINES", - "THEx_POINTS", - "THEx_FRONT_FACING", - "THEx_BACK_FACING", - "THEx_PRIM_VISIBLE", - "THEx_PRIM_CULLED", - "THEx_PRIM_CLIPPED", - "THEx_PRIM_SAT_CULLED", - "THEx_BIN_ALLOC_INIT", - "THEx_BIN_ALLOC_OVERFLOW", - "THEx_BUS_READ", - "", - "THEx_BUS_WRITE", - "THEx_LOADING_DESC", - "THEx_IDVS_POS_SHAD_REQ", - "THEx_IDVS_POS_SHAD_WAIT", - "THEx_IDVS_POS_SHAD_STALL", - "THEx_IDVS_POS_FIFO_FULL", - "THEx_PREFETCH_STALL", - "THEx_VCACHE_HIT", - "THEx_VCACHE_MISS", - "THEx_VCACHE_LINE_WAIT", - "THEx_VFETCH_POS_READ_WAIT", - "THEx_VFETCH_VERTEX_WAIT", - "THEx_VFETCH_STALL", - "THEx_PRIMASSY_STALL", - "THEx_BBOX_GEN_STALL", - "THEx_IDVS_VBU_HIT", - "THEx_IDVS_VBU_MISS", - "THEx_IDVS_VBU_LINE_DEALLOCATE", - "THEx_IDVS_VAR_SHAD_REQ", - "THEx_IDVS_VAR_SHAD_STALL", - "THEx_BINNER_STALL", - "THEx_ITER_STALL", - "THEx_COMPRESS_MISS", - "THEx_COMPRESS_STALL", - "THEx_PCACHE_HIT", - "THEx_PCACHE_MISS", - "THEx_PCACHE_MISS_STALL", - "THEx_PCACHE_EVICT_STALL", - "THEx_PMGR_PTR_WR_STALL", - "THEx_PMGR_PTR_RD_STALL", - "THEx_PMGR_CMD_WR_STALL", - "THEx_WRBUF_ACTIVE", - "THEx_WRBUF_HIT", - "THEx_WRBUF_MISS", - "THEx_WRBUF_NO_FREE_LINE_STALL", - "THEx_WRBUF_NO_AXI_ID_STALL", - "THEx_WRBUF_AXI_STALL", - "", - "", - "", - "THEx_UTLB_TRANS", - "THEx_UTLB_TRANS_HIT", - "THEx_UTLB_TRANS_STALL", - "THEx_UTLB_TRANS_MISS_DELAY", - "THEx_UTLB_MMU_REQ", - - /* Performance counters for the Shader Core */ - "", - "", - "", - "", - "THEx_FRAG_ACTIVE", - "THEx_FRAG_PRIMITIVES", - "THEx_FRAG_PRIM_RAST", - "THEx_FRAG_FPK_ACTIVE", - "THEx_FRAG_STARVING", - "THEx_FRAG_WARPS", - "THEx_FRAG_PARTIAL_WARPS", - "THEx_FRAG_QUADS_RAST", - "THEx_FRAG_QUADS_EZS_TEST", - "THEx_FRAG_QUADS_EZS_UPDATE", - "THEx_FRAG_QUADS_EZS_KILL", - "THEx_FRAG_LZS_TEST", - "THEx_FRAG_LZS_KILL", - "", - "THEx_FRAG_PTILES", - "THEx_FRAG_TRANS_ELIM", - "THEx_QUAD_FPK_KILLER", - "", - "THEx_COMPUTE_ACTIVE", - "THEx_COMPUTE_TASKS", - "THEx_COMPUTE_WARPS", - "THEx_COMPUTE_STARVING", - "THEx_EXEC_CORE_ACTIVE", - "THEx_EXEC_ACTIVE", - "THEx_EXEC_INSTR_COUNT", - "THEx_EXEC_INSTR_DIVERGED", - "THEx_EXEC_INSTR_STARVING", - "THEx_ARITH_INSTR_SINGLE_FMA", - "THEx_ARITH_INSTR_DOUBLE", - "THEx_ARITH_INSTR_MSG", - "THEx_ARITH_INSTR_MSG_ONLY", - "THEx_TEX_INSTR", - "THEx_TEX_INSTR_MIPMAP", - "THEx_TEX_INSTR_COMPRESSED", - "THEx_TEX_INSTR_3D", - "THEx_TEX_INSTR_TRILINEAR", - "THEx_TEX_COORD_ISSUE", - "THEx_TEX_COORD_STALL", - "THEx_TEX_STARVE_CACHE", - "THEx_TEX_STARVE_FILTER", - "THEx_LS_MEM_READ_FULL", - "THEx_LS_MEM_READ_SHORT", - "THEx_LS_MEM_WRITE_FULL", - "THEx_LS_MEM_WRITE_SHORT", - "THEx_LS_MEM_ATOMIC", - "THEx_VARY_INSTR", - "THEx_VARY_SLOT_32", - "THEx_VARY_SLOT_16", - "THEx_ATTR_INSTR", - "THEx_ARITH_INSTR_FP_MUL", - "THEx_BEATS_RD_FTC", - "THEx_BEATS_RD_FTC_EXT", - "THEx_BEATS_RD_LSC", - "THEx_BEATS_RD_LSC_EXT", - "THEx_BEATS_RD_TEX", - "THEx_BEATS_RD_TEX_EXT", - "THEx_BEATS_RD_OTHER", - "THEx_BEATS_WR_LSC", - "THEx_BEATS_WR_TIB", - "", - - /* Performance counters for the Memory System */ - "", - "", - "", - "", - "THEx_MMU_REQUESTS", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "THEx_L2_RD_MSG_IN", - "THEx_L2_RD_MSG_IN_STALL", - "THEx_L2_WR_MSG_IN", - "THEx_L2_WR_MSG_IN_STALL", - "THEx_L2_SNP_MSG_IN", - "THEx_L2_SNP_MSG_IN_STALL", - "THEx_L2_RD_MSG_OUT", - "THEx_L2_RD_MSG_OUT_STALL", - "THEx_L2_WR_MSG_OUT", - "THEx_L2_ANY_LOOKUP", - "THEx_L2_READ_LOOKUP", - "THEx_L2_WRITE_LOOKUP", - "THEx_L2_EXT_SNOOP_LOOKUP", - "THEx_L2_EXT_READ", - "THEx_L2_EXT_READ_NOSNP", - "THEx_L2_EXT_READ_UNIQUE", - "THEx_L2_EXT_READ_BEATS", - "THEx_L2_EXT_AR_STALL", - "THEx_L2_EXT_AR_CNT_Q1", - "THEx_L2_EXT_AR_CNT_Q2", - "THEx_L2_EXT_AR_CNT_Q3", - "THEx_L2_EXT_RRESP_0_127", - "THEx_L2_EXT_RRESP_128_191", - "THEx_L2_EXT_RRESP_192_255", - "THEx_L2_EXT_RRESP_256_319", - "THEx_L2_EXT_RRESP_320_383", - "THEx_L2_EXT_WRITE", - "THEx_L2_EXT_WRITE_NOSNP_FULL", - "THEx_L2_EXT_WRITE_NOSNP_PTL", - "THEx_L2_EXT_WRITE_SNP_FULL", - "THEx_L2_EXT_WRITE_SNP_PTL", - "THEx_L2_EXT_WRITE_BEATS", - "THEx_L2_EXT_W_STALL", - "THEx_L2_EXT_AW_CNT_Q1", - "THEx_L2_EXT_AW_CNT_Q2", - "THEx_L2_EXT_AW_CNT_Q3", - "THEx_L2_EXT_SNOOP", - "THEx_L2_EXT_SNOOP_STALL", - "THEx_L2_EXT_SNOOP_RESP_CLEAN", - "THEx_L2_EXT_SNOOP_RESP_DATA", - "THEx_L2_EXT_SNOOP_INTERNAL", - "", - "", - "", - "", - "", - "", - "", -}; - -#endif /* _KBASE_GATOR_HWCNT_NAMES_THEX_H_ */ diff --git a/mali_kbase/mali_kbase_gator_hwcnt_names_tmix.h b/mali_kbase/mali_kbase_gator_hwcnt_names_tmix.h deleted file mode 100644 index 63eac50..0000000 --- a/mali_kbase/mali_kbase_gator_hwcnt_names_tmix.h +++ /dev/null @@ -1,296 +0,0 @@ -/* - * - * (C) COPYRIGHT 2016-2018 ARM Limited. All rights reserved. - * - * This program is free software and is provided to you under the terms of the - * GNU General Public License version 2 as published by the Free Software - * Foundation, and any use by you of this program is subject to the terms - * of such GNU licence. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you can access it online at - * http://www.gnu.org/licenses/gpl-2.0.html. - * - * SPDX-License-Identifier: GPL-2.0 - * - */ - -/* - * This header was autogenerated, it should not be edited. - */ - -#ifndef _KBASE_GATOR_HWCNT_NAMES_TMIX_H_ -#define _KBASE_GATOR_HWCNT_NAMES_TMIX_H_ - -static const char * const hardware_counters_mali_tMIx[] = { - /* Performance counters for the Job Manager */ - "", - "", - "", - "", - "TMIx_MESSAGES_SENT", - "TMIx_MESSAGES_RECEIVED", - "TMIx_GPU_ACTIVE", - "TMIx_IRQ_ACTIVE", - "TMIx_JS0_JOBS", - "TMIx_JS0_TASKS", - "TMIx_JS0_ACTIVE", - "", - "TMIx_JS0_WAIT_READ", - "TMIx_JS0_WAIT_ISSUE", - "TMIx_JS0_WAIT_DEPEND", - "TMIx_JS0_WAIT_FINISH", - "TMIx_JS1_JOBS", - "TMIx_JS1_TASKS", - "TMIx_JS1_ACTIVE", - "", - "TMIx_JS1_WAIT_READ", - "TMIx_JS1_WAIT_ISSUE", - "TMIx_JS1_WAIT_DEPEND", - "TMIx_JS1_WAIT_FINISH", - "TMIx_JS2_JOBS", - "TMIx_JS2_TASKS", - "TMIx_JS2_ACTIVE", - "", - "TMIx_JS2_WAIT_READ", - "TMIx_JS2_WAIT_ISSUE", - "TMIx_JS2_WAIT_DEPEND", - "TMIx_JS2_WAIT_FINISH", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - - /* Performance counters for the Tiler */ - "", - "", - "", - "", - "TMIx_TILER_ACTIVE", - "TMIx_JOBS_PROCESSED", - "TMIx_TRIANGLES", - "TMIx_LINES", - "TMIx_POINTS", - "TMIx_FRONT_FACING", - "TMIx_BACK_FACING", - "TMIx_PRIM_VISIBLE", - "TMIx_PRIM_CULLED", - "TMIx_PRIM_CLIPPED", - "TMIx_PRIM_SAT_CULLED", - "TMIx_BIN_ALLOC_INIT", - "TMIx_BIN_ALLOC_OVERFLOW", - "TMIx_BUS_READ", - "", - "TMIx_BUS_WRITE", - "TMIx_LOADING_DESC", - "TMIx_IDVS_POS_SHAD_REQ", - "TMIx_IDVS_POS_SHAD_WAIT", - "TMIx_IDVS_POS_SHAD_STALL", - "TMIx_IDVS_POS_FIFO_FULL", - "TMIx_PREFETCH_STALL", - "TMIx_VCACHE_HIT", - "TMIx_VCACHE_MISS", - "TMIx_VCACHE_LINE_WAIT", - "TMIx_VFETCH_POS_READ_WAIT", - "TMIx_VFETCH_VERTEX_WAIT", - "TMIx_VFETCH_STALL", - "TMIx_PRIMASSY_STALL", - "TMIx_BBOX_GEN_STALL", - "TMIx_IDVS_VBU_HIT", - "TMIx_IDVS_VBU_MISS", - "TMIx_IDVS_VBU_LINE_DEALLOCATE", - "TMIx_IDVS_VAR_SHAD_REQ", - "TMIx_IDVS_VAR_SHAD_STALL", - "TMIx_BINNER_STALL", - "TMIx_ITER_STALL", - "TMIx_COMPRESS_MISS", - "TMIx_COMPRESS_STALL", - "TMIx_PCACHE_HIT", - "TMIx_PCACHE_MISS", - "TMIx_PCACHE_MISS_STALL", - "TMIx_PCACHE_EVICT_STALL", - "TMIx_PMGR_PTR_WR_STALL", - "TMIx_PMGR_PTR_RD_STALL", - "TMIx_PMGR_CMD_WR_STALL", - "TMIx_WRBUF_ACTIVE", - "TMIx_WRBUF_HIT", - "TMIx_WRBUF_MISS", - "TMIx_WRBUF_NO_FREE_LINE_STALL", - "TMIx_WRBUF_NO_AXI_ID_STALL", - "TMIx_WRBUF_AXI_STALL", - "", - "", - "", - "TMIx_UTLB_TRANS", - "TMIx_UTLB_TRANS_HIT", - "TMIx_UTLB_TRANS_STALL", - "TMIx_UTLB_TRANS_MISS_DELAY", - "TMIx_UTLB_MMU_REQ", - - /* Performance counters for the Shader Core */ - "", - "", - "", - "", - "TMIx_FRAG_ACTIVE", - "TMIx_FRAG_PRIMITIVES", - "TMIx_FRAG_PRIM_RAST", - "TMIx_FRAG_FPK_ACTIVE", - "TMIx_FRAG_STARVING", - "TMIx_FRAG_WARPS", - "TMIx_FRAG_PARTIAL_WARPS", - "TMIx_FRAG_QUADS_RAST", - "TMIx_FRAG_QUADS_EZS_TEST", - "TMIx_FRAG_QUADS_EZS_UPDATE", - "TMIx_FRAG_QUADS_EZS_KILL", - "TMIx_FRAG_LZS_TEST", - "TMIx_FRAG_LZS_KILL", - "", - "TMIx_FRAG_PTILES", - "TMIx_FRAG_TRANS_ELIM", - "TMIx_QUAD_FPK_KILLER", - "", - "TMIx_COMPUTE_ACTIVE", - "TMIx_COMPUTE_TASKS", - "TMIx_COMPUTE_WARPS", - "TMIx_COMPUTE_STARVING", - "TMIx_EXEC_CORE_ACTIVE", - "TMIx_EXEC_ACTIVE", - "TMIx_EXEC_INSTR_COUNT", - "TMIx_EXEC_INSTR_DIVERGED", - "TMIx_EXEC_INSTR_STARVING", - "TMIx_ARITH_INSTR_SINGLE_FMA", - "TMIx_ARITH_INSTR_DOUBLE", - "TMIx_ARITH_INSTR_MSG", - "TMIx_ARITH_INSTR_MSG_ONLY", - "TMIx_TEX_INSTR", - "TMIx_TEX_INSTR_MIPMAP", - "TMIx_TEX_INSTR_COMPRESSED", - "TMIx_TEX_INSTR_3D", - "TMIx_TEX_INSTR_TRILINEAR", - "TMIx_TEX_COORD_ISSUE", - "TMIx_TEX_COORD_STALL", - "TMIx_TEX_STARVE_CACHE", - "TMIx_TEX_STARVE_FILTER", - "TMIx_LS_MEM_READ_FULL", - "TMIx_LS_MEM_READ_SHORT", - "TMIx_LS_MEM_WRITE_FULL", - "TMIx_LS_MEM_WRITE_SHORT", - "TMIx_LS_MEM_ATOMIC", - "TMIx_VARY_INSTR", - "TMIx_VARY_SLOT_32", - "TMIx_VARY_SLOT_16", - "TMIx_ATTR_INSTR", - "TMIx_ARITH_INSTR_FP_MUL", - "TMIx_BEATS_RD_FTC", - "TMIx_BEATS_RD_FTC_EXT", - "TMIx_BEATS_RD_LSC", - "TMIx_BEATS_RD_LSC_EXT", - "TMIx_BEATS_RD_TEX", - "TMIx_BEATS_RD_TEX_EXT", - "TMIx_BEATS_RD_OTHER", - "TMIx_BEATS_WR_LSC", - "TMIx_BEATS_WR_TIB", - "", - - /* Performance counters for the Memory System */ - "", - "", - "", - "", - "TMIx_MMU_REQUESTS", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "TMIx_L2_RD_MSG_IN", - "TMIx_L2_RD_MSG_IN_STALL", - "TMIx_L2_WR_MSG_IN", - "TMIx_L2_WR_MSG_IN_STALL", - "TMIx_L2_SNP_MSG_IN", - "TMIx_L2_SNP_MSG_IN_STALL", - "TMIx_L2_RD_MSG_OUT", - "TMIx_L2_RD_MSG_OUT_STALL", - "TMIx_L2_WR_MSG_OUT", - "TMIx_L2_ANY_LOOKUP", - "TMIx_L2_READ_LOOKUP", - "TMIx_L2_WRITE_LOOKUP", - "TMIx_L2_EXT_SNOOP_LOOKUP", - "TMIx_L2_EXT_READ", - "TMIx_L2_EXT_READ_NOSNP", - "TMIx_L2_EXT_READ_UNIQUE", - "TMIx_L2_EXT_READ_BEATS", - "TMIx_L2_EXT_AR_STALL", - "TMIx_L2_EXT_AR_CNT_Q1", - "TMIx_L2_EXT_AR_CNT_Q2", - "TMIx_L2_EXT_AR_CNT_Q3", - "TMIx_L2_EXT_RRESP_0_127", - "TMIx_L2_EXT_RRESP_128_191", - "TMIx_L2_EXT_RRESP_192_255", - "TMIx_L2_EXT_RRESP_256_319", - "TMIx_L2_EXT_RRESP_320_383", - "TMIx_L2_EXT_WRITE", - "TMIx_L2_EXT_WRITE_NOSNP_FULL", - "TMIx_L2_EXT_WRITE_NOSNP_PTL", - "TMIx_L2_EXT_WRITE_SNP_FULL", - "TMIx_L2_EXT_WRITE_SNP_PTL", - "TMIx_L2_EXT_WRITE_BEATS", - "TMIx_L2_EXT_W_STALL", - "TMIx_L2_EXT_AW_CNT_Q1", - "TMIx_L2_EXT_AW_CNT_Q2", - "TMIx_L2_EXT_AW_CNT_Q3", - "TMIx_L2_EXT_SNOOP", - "TMIx_L2_EXT_SNOOP_STALL", - "TMIx_L2_EXT_SNOOP_RESP_CLEAN", - "TMIx_L2_EXT_SNOOP_RESP_DATA", - "TMIx_L2_EXT_SNOOP_INTERNAL", - "", - "", - "", - "", - "", - "", - "", -}; - -#endif /* _KBASE_GATOR_HWCNT_NAMES_TMIX_H_ */ diff --git a/mali_kbase/mali_kbase_gator_hwcnt_names_tnax.h b/mali_kbase/mali_kbase_gator_hwcnt_names_tnax.h deleted file mode 100644 index 579f57b..0000000 --- a/mali_kbase/mali_kbase_gator_hwcnt_names_tnax.h +++ /dev/null @@ -1,296 +0,0 @@ -/* - * - * (C) COPYRIGHT 2016-2019 ARM Limited. All rights reserved. - * - * This program is free software and is provided to you under the terms of the - * GNU General Public License version 2 as published by the Free Software - * Foundation, and any use by you of this program is subject to the terms - * of such GNU licence. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you can access it online at - * http://www.gnu.org/licenses/gpl-2.0.html. - * - * SPDX-License-Identifier: GPL-2.0 - * - */ - -/* - * This header was autogenerated, it should not be edited. - */ - -#ifndef _KBASE_GATOR_HWCNT_NAMES_TNAX_H_ -#define _KBASE_GATOR_HWCNT_NAMES_TNAX_H_ - -static const char * const hardware_counters_mali_tNAx[] = { - /* Performance counters for the Job Manager */ - "", - "", - "", - "", - "TNAx_MESSAGES_SENT", - "TNAx_MESSAGES_RECEIVED", - "TNAx_GPU_ACTIVE", - "TNAx_IRQ_ACTIVE", - "TNAx_JS0_JOBS", - "TNAx_JS0_TASKS", - "TNAx_JS0_ACTIVE", - "", - "TNAx_JS0_WAIT_READ", - "TNAx_JS0_WAIT_ISSUE", - "TNAx_JS0_WAIT_DEPEND", - "TNAx_JS0_WAIT_FINISH", - "TNAx_JS1_JOBS", - "TNAx_JS1_TASKS", - "TNAx_JS1_ACTIVE", - "", - "TNAx_JS1_WAIT_READ", - "TNAx_JS1_WAIT_ISSUE", - "TNAx_JS1_WAIT_DEPEND", - "TNAx_JS1_WAIT_FINISH", - "TNAx_JS2_JOBS", - "TNAx_JS2_TASKS", - "TNAx_JS2_ACTIVE", - "", - "TNAx_JS2_WAIT_READ", - "TNAx_JS2_WAIT_ISSUE", - "TNAx_JS2_WAIT_DEPEND", - "TNAx_JS2_WAIT_FINISH", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - - /* Performance counters for the Tiler */ - "", - "", - "", - "", - "TNAx_TILER_ACTIVE", - "TNAx_JOBS_PROCESSED", - "TNAx_TRIANGLES", - "TNAx_LINES", - "TNAx_POINTS", - "TNAx_FRONT_FACING", - "TNAx_BACK_FACING", - "TNAx_PRIM_VISIBLE", - "TNAx_PRIM_CULLED", - "TNAx_PRIM_CLIPPED", - "TNAx_PRIM_SAT_CULLED", - "TNAx_BIN_ALLOC_INIT", - "TNAx_BIN_ALLOC_OVERFLOW", - "TNAx_BUS_READ", - "", - "TNAx_BUS_WRITE", - "TNAx_LOADING_DESC", - "TNAx_IDVS_POS_SHAD_REQ", - "TNAx_IDVS_POS_SHAD_WAIT", - "TNAx_IDVS_POS_SHAD_STALL", - "TNAx_IDVS_POS_FIFO_FULL", - "TNAx_PREFETCH_STALL", - "TNAx_VCACHE_HIT", - "TNAx_VCACHE_MISS", - "TNAx_VCACHE_LINE_WAIT", - "TNAx_VFETCH_POS_READ_WAIT", - "TNAx_VFETCH_VERTEX_WAIT", - "TNAx_VFETCH_STALL", - "TNAx_PRIMASSY_STALL", - "TNAx_BBOX_GEN_STALL", - "TNAx_IDVS_VBU_HIT", - "TNAx_IDVS_VBU_MISS", - "TNAx_IDVS_VBU_LINE_DEALLOCATE", - "TNAx_IDVS_VAR_SHAD_REQ", - "TNAx_IDVS_VAR_SHAD_STALL", - "TNAx_BINNER_STALL", - "TNAx_ITER_STALL", - "TNAx_COMPRESS_MISS", - "TNAx_COMPRESS_STALL", - "TNAx_PCACHE_HIT", - "TNAx_PCACHE_MISS", - "TNAx_PCACHE_MISS_STALL", - "TNAx_PCACHE_EVICT_STALL", - "TNAx_PMGR_PTR_WR_STALL", - "TNAx_PMGR_PTR_RD_STALL", - "TNAx_PMGR_CMD_WR_STALL", - "TNAx_WRBUF_ACTIVE", - "TNAx_WRBUF_HIT", - "TNAx_WRBUF_MISS", - "TNAx_WRBUF_NO_FREE_LINE_STALL", - "TNAx_WRBUF_NO_AXI_ID_STALL", - "TNAx_WRBUF_AXI_STALL", - "", - "", - "", - "TNAx_UTLB_TRANS", - "TNAx_UTLB_TRANS_HIT", - "TNAx_UTLB_TRANS_STALL", - "TNAx_UTLB_TRANS_MISS_DELAY", - "TNAx_UTLB_MMU_REQ", - - /* Performance counters for the Shader Core */ - "", - "", - "", - "", - "TNAx_FRAG_ACTIVE", - "TNAx_FRAG_PRIMITIVES_OUT", - "TNAx_FRAG_PRIM_RAST", - "TNAx_FRAG_FPK_ACTIVE", - "TNAx_FRAG_STARVING", - "TNAx_FRAG_WARPS", - "TNAx_FRAG_PARTIAL_QUADS_RAST", - "TNAx_FRAG_QUADS_RAST", - "TNAx_FRAG_QUADS_EZS_TEST", - "TNAx_FRAG_QUADS_EZS_UPDATE", - "TNAx_FRAG_QUADS_EZS_KILL", - "TNAx_FRAG_LZS_TEST", - "TNAx_FRAG_LZS_KILL", - "TNAx_WARP_REG_SIZE_64", - "TNAx_FRAG_PTILES", - "TNAx_FRAG_TRANS_ELIM", - "TNAx_QUAD_FPK_KILLER", - "TNAx_FULL_QUAD_WARPS", - "TNAx_COMPUTE_ACTIVE", - "TNAx_COMPUTE_TASKS", - "TNAx_COMPUTE_WARPS", - "TNAx_COMPUTE_STARVING", - "TNAx_EXEC_CORE_ACTIVE", - "TNAx_EXEC_INSTR_FMA", - "TNAx_EXEC_INSTR_CVT", - "TNAx_EXEC_INSTR_SFU", - "TNAx_EXEC_INSTR_MSG", - "TNAx_EXEC_INSTR_DIVERGED", - "TNAx_EXEC_ICACHE_MISS", - "TNAx_EXEC_STARVE_ARITH", - "TNAx_CALL_BLEND_SHADER", - "TNAx_TEX_MSGI_NUM_FLITS", - "TNAx_TEX_DFCH_CLK_STALLED", - "TNAx_TEX_TFCH_CLK_STALLED", - "TNAx_TEX_TFCH_STARVED_PENDING_DATA_FETCH", - "TNAx_TEX_FILT_NUM_OPERATIONS", - "TNAx_TEX_FILT_NUM_FXR_OPERATIONS", - "TNAx_TEX_FILT_NUM_FST_OPERATIONS", - "TNAx_TEX_MSGO_NUM_MSG", - "TNAx_TEX_MSGO_NUM_FLITS", - "TNAx_LS_MEM_READ_FULL", - "TNAx_LS_MEM_READ_SHORT", - "TNAx_LS_MEM_WRITE_FULL", - "TNAx_LS_MEM_WRITE_SHORT", - "TNAx_LS_MEM_ATOMIC", - "TNAx_VARY_INSTR", - "TNAx_VARY_SLOT_32", - "TNAx_VARY_SLOT_16", - "TNAx_ATTR_INSTR", - "TNAx_ARITH_INSTR_FP_MUL", - "TNAx_BEATS_RD_FTC", - "TNAx_BEATS_RD_FTC_EXT", - "TNAx_BEATS_RD_LSC", - "TNAx_BEATS_RD_LSC_EXT", - "TNAx_BEATS_RD_TEX", - "TNAx_BEATS_RD_TEX_EXT", - "TNAx_BEATS_RD_OTHER", - "TNAx_BEATS_WR_LSC_OTHER", - "TNAx_BEATS_WR_TIB", - "TNAx_BEATS_WR_LSC_WB", - - /* Performance counters for the Memory System */ - "", - "", - "", - "", - "TNAx_MMU_REQUESTS", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "TNAx_L2_RD_MSG_IN", - "TNAx_L2_RD_MSG_IN_STALL", - "TNAx_L2_WR_MSG_IN", - "TNAx_L2_WR_MSG_IN_STALL", - "TNAx_L2_SNP_MSG_IN", - "TNAx_L2_SNP_MSG_IN_STALL", - "TNAx_L2_RD_MSG_OUT", - "TNAx_L2_RD_MSG_OUT_STALL", - "TNAx_L2_WR_MSG_OUT", - "TNAx_L2_ANY_LOOKUP", - "TNAx_L2_READ_LOOKUP", - "TNAx_L2_WRITE_LOOKUP", - "TNAx_L2_EXT_SNOOP_LOOKUP", - "TNAx_L2_EXT_READ", - "TNAx_L2_EXT_READ_NOSNP", - "TNAx_L2_EXT_READ_UNIQUE", - "TNAx_L2_EXT_READ_BEATS", - "TNAx_L2_EXT_AR_STALL", - "TNAx_L2_EXT_AR_CNT_Q1", - "TNAx_L2_EXT_AR_CNT_Q2", - "TNAx_L2_EXT_AR_CNT_Q3", - "TNAx_L2_EXT_RRESP_0_127", - "TNAx_L2_EXT_RRESP_128_191", - "TNAx_L2_EXT_RRESP_192_255", - "TNAx_L2_EXT_RRESP_256_319", - "TNAx_L2_EXT_RRESP_320_383", - "TNAx_L2_EXT_WRITE", - "TNAx_L2_EXT_WRITE_NOSNP_FULL", - "TNAx_L2_EXT_WRITE_NOSNP_PTL", - "TNAx_L2_EXT_WRITE_SNP_FULL", - "TNAx_L2_EXT_WRITE_SNP_PTL", - "TNAx_L2_EXT_WRITE_BEATS", - "TNAx_L2_EXT_W_STALL", - "TNAx_L2_EXT_AW_CNT_Q1", - "TNAx_L2_EXT_AW_CNT_Q2", - "TNAx_L2_EXT_AW_CNT_Q3", - "TNAx_L2_EXT_SNOOP", - "TNAx_L2_EXT_SNOOP_STALL", - "TNAx_L2_EXT_SNOOP_RESP_CLEAN", - "TNAx_L2_EXT_SNOOP_RESP_DATA", - "TNAx_L2_EXT_SNOOP_INTERNAL", - "", - "", - "", - "", - "", - "", - "", -}; - -#endif /* _KBASE_GATOR_HWCNT_NAMES_TNAX_H_ */ diff --git a/mali_kbase/mali_kbase_gator_hwcnt_names_tnox.h b/mali_kbase/mali_kbase_gator_hwcnt_names_tnox.h deleted file mode 100644 index 932663c..0000000 --- a/mali_kbase/mali_kbase_gator_hwcnt_names_tnox.h +++ /dev/null @@ -1,296 +0,0 @@ -/* - * - * (C) COPYRIGHT 2016-2018 ARM Limited. All rights reserved. - * - * This program is free software and is provided to you under the terms of the - * GNU General Public License version 2 as published by the Free Software - * Foundation, and any use by you of this program is subject to the terms - * of such GNU licence. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you can access it online at - * http://www.gnu.org/licenses/gpl-2.0.html. - * - * SPDX-License-Identifier: GPL-2.0 - * - */ - -/* - * This header was autogenerated, it should not be edited. - */ - -#ifndef _KBASE_GATOR_HWCNT_NAMES_TNOX_H_ -#define _KBASE_GATOR_HWCNT_NAMES_TNOX_H_ - -static const char * const hardware_counters_mali_tNOx[] = { - /* Performance counters for the Job Manager */ - "", - "", - "", - "", - "TNOx_MESSAGES_SENT", - "TNOx_MESSAGES_RECEIVED", - "TNOx_GPU_ACTIVE", - "TNOx_IRQ_ACTIVE", - "TNOx_JS0_JOBS", - "TNOx_JS0_TASKS", - "TNOx_JS0_ACTIVE", - "", - "TNOx_JS0_WAIT_READ", - "TNOx_JS0_WAIT_ISSUE", - "TNOx_JS0_WAIT_DEPEND", - "TNOx_JS0_WAIT_FINISH", - "TNOx_JS1_JOBS", - "TNOx_JS1_TASKS", - "TNOx_JS1_ACTIVE", - "", - "TNOx_JS1_WAIT_READ", - "TNOx_JS1_WAIT_ISSUE", - "TNOx_JS1_WAIT_DEPEND", - "TNOx_JS1_WAIT_FINISH", - "TNOx_JS2_JOBS", - "TNOx_JS2_TASKS", - "TNOx_JS2_ACTIVE", - "", - "TNOx_JS2_WAIT_READ", - "TNOx_JS2_WAIT_ISSUE", - "TNOx_JS2_WAIT_DEPEND", - "TNOx_JS2_WAIT_FINISH", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - - /* Performance counters for the Tiler */ - "", - "", - "", - "", - "TNOx_TILER_ACTIVE", - "TNOx_JOBS_PROCESSED", - "TNOx_TRIANGLES", - "TNOx_LINES", - "TNOx_POINTS", - "TNOx_FRONT_FACING", - "TNOx_BACK_FACING", - "TNOx_PRIM_VISIBLE", - "TNOx_PRIM_CULLED", - "TNOx_PRIM_CLIPPED", - "TNOx_PRIM_SAT_CULLED", - "TNOx_BIN_ALLOC_INIT", - "TNOx_BIN_ALLOC_OVERFLOW", - "TNOx_BUS_READ", - "", - "TNOx_BUS_WRITE", - "TNOx_LOADING_DESC", - "TNOx_IDVS_POS_SHAD_REQ", - "TNOx_IDVS_POS_SHAD_WAIT", - "TNOx_IDVS_POS_SHAD_STALL", - "TNOx_IDVS_POS_FIFO_FULL", - "TNOx_PREFETCH_STALL", - "TNOx_VCACHE_HIT", - "TNOx_VCACHE_MISS", - "TNOx_VCACHE_LINE_WAIT", - "TNOx_VFETCH_POS_READ_WAIT", - "TNOx_VFETCH_VERTEX_WAIT", - "TNOx_VFETCH_STALL", - "TNOx_PRIMASSY_STALL", - "TNOx_BBOX_GEN_STALL", - "TNOx_IDVS_VBU_HIT", - "TNOx_IDVS_VBU_MISS", - "TNOx_IDVS_VBU_LINE_DEALLOCATE", - "TNOx_IDVS_VAR_SHAD_REQ", - "TNOx_IDVS_VAR_SHAD_STALL", - "TNOx_BINNER_STALL", - "TNOx_ITER_STALL", - "TNOx_COMPRESS_MISS", - "TNOx_COMPRESS_STALL", - "TNOx_PCACHE_HIT", - "TNOx_PCACHE_MISS", - "TNOx_PCACHE_MISS_STALL", - "TNOx_PCACHE_EVICT_STALL", - "TNOx_PMGR_PTR_WR_STALL", - "TNOx_PMGR_PTR_RD_STALL", - "TNOx_PMGR_CMD_WR_STALL", - "TNOx_WRBUF_ACTIVE", - "TNOx_WRBUF_HIT", - "TNOx_WRBUF_MISS", - "TNOx_WRBUF_NO_FREE_LINE_STALL", - "TNOx_WRBUF_NO_AXI_ID_STALL", - "TNOx_WRBUF_AXI_STALL", - "", - "", - "", - "TNOx_UTLB_TRANS", - "TNOx_UTLB_TRANS_HIT", - "TNOx_UTLB_TRANS_STALL", - "TNOx_UTLB_TRANS_MISS_DELAY", - "TNOx_UTLB_MMU_REQ", - - /* Performance counters for the Shader Core */ - "", - "", - "", - "", - "TNOx_FRAG_ACTIVE", - "TNOx_FRAG_PRIMITIVES", - "TNOx_FRAG_PRIM_RAST", - "TNOx_FRAG_FPK_ACTIVE", - "TNOx_FRAG_STARVING", - "TNOx_FRAG_WARPS", - "TNOx_FRAG_PARTIAL_WARPS", - "TNOx_FRAG_QUADS_RAST", - "TNOx_FRAG_QUADS_EZS_TEST", - "TNOx_FRAG_QUADS_EZS_UPDATE", - "TNOx_FRAG_QUADS_EZS_KILL", - "TNOx_FRAG_LZS_TEST", - "TNOx_FRAG_LZS_KILL", - "TNOx_WARP_REG_SIZE_64", - "TNOx_FRAG_PTILES", - "TNOx_FRAG_TRANS_ELIM", - "TNOx_QUAD_FPK_KILLER", - "TNOx_FULL_QUAD_WARPS", - "TNOx_COMPUTE_ACTIVE", - "TNOx_COMPUTE_TASKS", - "TNOx_COMPUTE_WARPS", - "TNOx_COMPUTE_STARVING", - "TNOx_EXEC_CORE_ACTIVE", - "TNOx_EXEC_ACTIVE", - "TNOx_EXEC_INSTR_COUNT", - "TNOx_EXEC_INSTR_DIVERGED", - "TNOx_EXEC_INSTR_STARVING", - "TNOx_ARITH_INSTR_SINGLE_FMA", - "TNOx_ARITH_INSTR_DOUBLE", - "TNOx_ARITH_INSTR_MSG", - "TNOx_ARITH_INSTR_MSG_ONLY", - "TNOx_TEX_MSGI_NUM_QUADS", - "TNOx_TEX_DFCH_NUM_PASSES", - "TNOx_TEX_DFCH_NUM_PASSES_MISS", - "TNOx_TEX_DFCH_NUM_PASSES_MIP_MAP", - "TNOx_TEX_TIDX_NUM_SPLIT_MIP_MAP", - "TNOx_TEX_TFCH_NUM_LINES_FETCHED", - "TNOx_TEX_TFCH_NUM_LINES_FETCHED_BLOCK", - "TNOx_TEX_TFCH_NUM_OPERATIONS", - "TNOx_TEX_FILT_NUM_OPERATIONS", - "TNOx_LS_MEM_READ_FULL", - "TNOx_LS_MEM_READ_SHORT", - "TNOx_LS_MEM_WRITE_FULL", - "TNOx_LS_MEM_WRITE_SHORT", - "TNOx_LS_MEM_ATOMIC", - "TNOx_VARY_INSTR", - "TNOx_VARY_SLOT_32", - "TNOx_VARY_SLOT_16", - "TNOx_ATTR_INSTR", - "TNOx_ARITH_INSTR_FP_MUL", - "TNOx_BEATS_RD_FTC", - "TNOx_BEATS_RD_FTC_EXT", - "TNOx_BEATS_RD_LSC", - "TNOx_BEATS_RD_LSC_EXT", - "TNOx_BEATS_RD_TEX", - "TNOx_BEATS_RD_TEX_EXT", - "TNOx_BEATS_RD_OTHER", - "TNOx_BEATS_WR_LSC_OTHER", - "TNOx_BEATS_WR_TIB", - "TNOx_BEATS_WR_LSC_WB", - - /* Performance counters for the Memory System */ - "", - "", - "", - "", - "TNOx_MMU_REQUESTS", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "TNOx_L2_RD_MSG_IN", - "TNOx_L2_RD_MSG_IN_STALL", - "TNOx_L2_WR_MSG_IN", - "TNOx_L2_WR_MSG_IN_STALL", - "TNOx_L2_SNP_MSG_IN", - "TNOx_L2_SNP_MSG_IN_STALL", - "TNOx_L2_RD_MSG_OUT", - "TNOx_L2_RD_MSG_OUT_STALL", - "TNOx_L2_WR_MSG_OUT", - "TNOx_L2_ANY_LOOKUP", - "TNOx_L2_READ_LOOKUP", - "TNOx_L2_WRITE_LOOKUP", - "TNOx_L2_EXT_SNOOP_LOOKUP", - "TNOx_L2_EXT_READ", - "TNOx_L2_EXT_READ_NOSNP", - "TNOx_L2_EXT_READ_UNIQUE", - "TNOx_L2_EXT_READ_BEATS", - "TNOx_L2_EXT_AR_STALL", - "TNOx_L2_EXT_AR_CNT_Q1", - "TNOx_L2_EXT_AR_CNT_Q2", - "TNOx_L2_EXT_AR_CNT_Q3", - "TNOx_L2_EXT_RRESP_0_127", - "TNOx_L2_EXT_RRESP_128_191", - "TNOx_L2_EXT_RRESP_192_255", - "TNOx_L2_EXT_RRESP_256_319", - "TNOx_L2_EXT_RRESP_320_383", - "TNOx_L2_EXT_WRITE", - "TNOx_L2_EXT_WRITE_NOSNP_FULL", - "TNOx_L2_EXT_WRITE_NOSNP_PTL", - "TNOx_L2_EXT_WRITE_SNP_FULL", - "TNOx_L2_EXT_WRITE_SNP_PTL", - "TNOx_L2_EXT_WRITE_BEATS", - "TNOx_L2_EXT_W_STALL", - "TNOx_L2_EXT_AW_CNT_Q1", - "TNOx_L2_EXT_AW_CNT_Q2", - "TNOx_L2_EXT_AW_CNT_Q3", - "TNOx_L2_EXT_SNOOP", - "TNOx_L2_EXT_SNOOP_STALL", - "TNOx_L2_EXT_SNOOP_RESP_CLEAN", - "TNOx_L2_EXT_SNOOP_RESP_DATA", - "TNOx_L2_EXT_SNOOP_INTERNAL", - "", - "", - "", - "", - "", - "", - "", -}; - -#endif /* _KBASE_GATOR_HWCNT_NAMES_TNOX_H_ */ diff --git a/mali_kbase/mali_kbase_gator_hwcnt_names_tsix.h b/mali_kbase/mali_kbase_gator_hwcnt_names_tsix.h deleted file mode 100644 index b8dde32..0000000 --- a/mali_kbase/mali_kbase_gator_hwcnt_names_tsix.h +++ /dev/null @@ -1,296 +0,0 @@ -/* - * - * (C) COPYRIGHT 2016-2018 ARM Limited. All rights reserved. - * - * This program is free software and is provided to you under the terms of the - * GNU General Public License version 2 as published by the Free Software - * Foundation, and any use by you of this program is subject to the terms - * of such GNU licence. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you can access it online at - * http://www.gnu.org/licenses/gpl-2.0.html. - * - * SPDX-License-Identifier: GPL-2.0 - * - */ - -/* - * This header was autogenerated, it should not be edited. - */ - -#ifndef _KBASE_GATOR_HWCNT_NAMES_TSIX_H_ -#define _KBASE_GATOR_HWCNT_NAMES_TSIX_H_ - -static const char * const hardware_counters_mali_tSIx[] = { - /* Performance counters for the Job Manager */ - "", - "", - "", - "", - "TSIx_MESSAGES_SENT", - "TSIx_MESSAGES_RECEIVED", - "TSIx_GPU_ACTIVE", - "TSIx_IRQ_ACTIVE", - "TSIx_JS0_JOBS", - "TSIx_JS0_TASKS", - "TSIx_JS0_ACTIVE", - "", - "TSIx_JS0_WAIT_READ", - "TSIx_JS0_WAIT_ISSUE", - "TSIx_JS0_WAIT_DEPEND", - "TSIx_JS0_WAIT_FINISH", - "TSIx_JS1_JOBS", - "TSIx_JS1_TASKS", - "TSIx_JS1_ACTIVE", - "", - "TSIx_JS1_WAIT_READ", - "TSIx_JS1_WAIT_ISSUE", - "TSIx_JS1_WAIT_DEPEND", - "TSIx_JS1_WAIT_FINISH", - "TSIx_JS2_JOBS", - "TSIx_JS2_TASKS", - "TSIx_JS2_ACTIVE", - "", - "TSIx_JS2_WAIT_READ", - "TSIx_JS2_WAIT_ISSUE", - "TSIx_JS2_WAIT_DEPEND", - "TSIx_JS2_WAIT_FINISH", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - - /* Performance counters for the Tiler */ - "", - "", - "", - "", - "TSIx_TILER_ACTIVE", - "TSIx_JOBS_PROCESSED", - "TSIx_TRIANGLES", - "TSIx_LINES", - "TSIx_POINTS", - "TSIx_FRONT_FACING", - "TSIx_BACK_FACING", - "TSIx_PRIM_VISIBLE", - "TSIx_PRIM_CULLED", - "TSIx_PRIM_CLIPPED", - "TSIx_PRIM_SAT_CULLED", - "TSIx_BIN_ALLOC_INIT", - "TSIx_BIN_ALLOC_OVERFLOW", - "TSIx_BUS_READ", - "", - "TSIx_BUS_WRITE", - "TSIx_LOADING_DESC", - "TSIx_IDVS_POS_SHAD_REQ", - "TSIx_IDVS_POS_SHAD_WAIT", - "TSIx_IDVS_POS_SHAD_STALL", - "TSIx_IDVS_POS_FIFO_FULL", - "TSIx_PREFETCH_STALL", - "TSIx_VCACHE_HIT", - "TSIx_VCACHE_MISS", - "TSIx_VCACHE_LINE_WAIT", - "TSIx_VFETCH_POS_READ_WAIT", - "TSIx_VFETCH_VERTEX_WAIT", - "TSIx_VFETCH_STALL", - "TSIx_PRIMASSY_STALL", - "TSIx_BBOX_GEN_STALL", - "TSIx_IDVS_VBU_HIT", - "TSIx_IDVS_VBU_MISS", - "TSIx_IDVS_VBU_LINE_DEALLOCATE", - "TSIx_IDVS_VAR_SHAD_REQ", - "TSIx_IDVS_VAR_SHAD_STALL", - "TSIx_BINNER_STALL", - "TSIx_ITER_STALL", - "TSIx_COMPRESS_MISS", - "TSIx_COMPRESS_STALL", - "TSIx_PCACHE_HIT", - "TSIx_PCACHE_MISS", - "TSIx_PCACHE_MISS_STALL", - "TSIx_PCACHE_EVICT_STALL", - "TSIx_PMGR_PTR_WR_STALL", - "TSIx_PMGR_PTR_RD_STALL", - "TSIx_PMGR_CMD_WR_STALL", - "TSIx_WRBUF_ACTIVE", - "TSIx_WRBUF_HIT", - "TSIx_WRBUF_MISS", - "TSIx_WRBUF_NO_FREE_LINE_STALL", - "TSIx_WRBUF_NO_AXI_ID_STALL", - "TSIx_WRBUF_AXI_STALL", - "", - "", - "", - "TSIx_UTLB_TRANS", - "TSIx_UTLB_TRANS_HIT", - "TSIx_UTLB_TRANS_STALL", - "TSIx_UTLB_TRANS_MISS_DELAY", - "TSIx_UTLB_MMU_REQ", - - /* Performance counters for the Shader Core */ - "", - "", - "", - "", - "TSIx_FRAG_ACTIVE", - "TSIx_FRAG_PRIMITIVES", - "TSIx_FRAG_PRIM_RAST", - "TSIx_FRAG_FPK_ACTIVE", - "TSIx_FRAG_STARVING", - "TSIx_FRAG_WARPS", - "TSIx_FRAG_PARTIAL_WARPS", - "TSIx_FRAG_QUADS_RAST", - "TSIx_FRAG_QUADS_EZS_TEST", - "TSIx_FRAG_QUADS_EZS_UPDATE", - "TSIx_FRAG_QUADS_EZS_KILL", - "TSIx_FRAG_LZS_TEST", - "TSIx_FRAG_LZS_KILL", - "", - "TSIx_FRAG_PTILES", - "TSIx_FRAG_TRANS_ELIM", - "TSIx_QUAD_FPK_KILLER", - "", - "TSIx_COMPUTE_ACTIVE", - "TSIx_COMPUTE_TASKS", - "TSIx_COMPUTE_WARPS", - "TSIx_COMPUTE_STARVING", - "TSIx_EXEC_CORE_ACTIVE", - "TSIx_EXEC_ACTIVE", - "TSIx_EXEC_INSTR_COUNT", - "TSIx_EXEC_INSTR_DIVERGED", - "TSIx_EXEC_INSTR_STARVING", - "TSIx_ARITH_INSTR_SINGLE_FMA", - "TSIx_ARITH_INSTR_DOUBLE", - "TSIx_ARITH_INSTR_MSG", - "TSIx_ARITH_INSTR_MSG_ONLY", - "TSIx_TEX_MSGI_NUM_QUADS", - "TSIx_TEX_DFCH_NUM_PASSES", - "TSIx_TEX_DFCH_NUM_PASSES_MISS", - "TSIx_TEX_DFCH_NUM_PASSES_MIP_MAP", - "TSIx_TEX_TIDX_NUM_SPLIT_MIP_MAP", - "TSIx_TEX_TFCH_NUM_LINES_FETCHED", - "TSIx_TEX_TFCH_NUM_LINES_FETCHED_BLOCK", - "TSIx_TEX_TFCH_NUM_OPERATIONS", - "TSIx_TEX_FILT_NUM_OPERATIONS", - "TSIx_LS_MEM_READ_FULL", - "TSIx_LS_MEM_READ_SHORT", - "TSIx_LS_MEM_WRITE_FULL", - "TSIx_LS_MEM_WRITE_SHORT", - "TSIx_LS_MEM_ATOMIC", - "TSIx_VARY_INSTR", - "TSIx_VARY_SLOT_32", - "TSIx_VARY_SLOT_16", - "TSIx_ATTR_INSTR", - "TSIx_ARITH_INSTR_FP_MUL", - "TSIx_BEATS_RD_FTC", - "TSIx_BEATS_RD_FTC_EXT", - "TSIx_BEATS_RD_LSC", - "TSIx_BEATS_RD_LSC_EXT", - "TSIx_BEATS_RD_TEX", - "TSIx_BEATS_RD_TEX_EXT", - "TSIx_BEATS_RD_OTHER", - "TSIx_BEATS_WR_LSC_OTHER", - "TSIx_BEATS_WR_TIB", - "TSIx_BEATS_WR_LSC_WB", - - /* Performance counters for the Memory System */ - "", - "", - "", - "", - "TSIx_MMU_REQUESTS", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "TSIx_L2_RD_MSG_IN", - "TSIx_L2_RD_MSG_IN_STALL", - "TSIx_L2_WR_MSG_IN", - "TSIx_L2_WR_MSG_IN_STALL", - "TSIx_L2_SNP_MSG_IN", - "TSIx_L2_SNP_MSG_IN_STALL", - "TSIx_L2_RD_MSG_OUT", - "TSIx_L2_RD_MSG_OUT_STALL", - "TSIx_L2_WR_MSG_OUT", - "TSIx_L2_ANY_LOOKUP", - "TSIx_L2_READ_LOOKUP", - "TSIx_L2_WRITE_LOOKUP", - "TSIx_L2_EXT_SNOOP_LOOKUP", - "TSIx_L2_EXT_READ", - "TSIx_L2_EXT_READ_NOSNP", - "TSIx_L2_EXT_READ_UNIQUE", - "TSIx_L2_EXT_READ_BEATS", - "TSIx_L2_EXT_AR_STALL", - "TSIx_L2_EXT_AR_CNT_Q1", - "TSIx_L2_EXT_AR_CNT_Q2", - "TSIx_L2_EXT_AR_CNT_Q3", - "TSIx_L2_EXT_RRESP_0_127", - "TSIx_L2_EXT_RRESP_128_191", - "TSIx_L2_EXT_RRESP_192_255", - "TSIx_L2_EXT_RRESP_256_319", - "TSIx_L2_EXT_RRESP_320_383", - "TSIx_L2_EXT_WRITE", - "TSIx_L2_EXT_WRITE_NOSNP_FULL", - "TSIx_L2_EXT_WRITE_NOSNP_PTL", - "TSIx_L2_EXT_WRITE_SNP_FULL", - "TSIx_L2_EXT_WRITE_SNP_PTL", - "TSIx_L2_EXT_WRITE_BEATS", - "TSIx_L2_EXT_W_STALL", - "TSIx_L2_EXT_AW_CNT_Q1", - "TSIx_L2_EXT_AW_CNT_Q2", - "TSIx_L2_EXT_AW_CNT_Q3", - "TSIx_L2_EXT_SNOOP", - "TSIx_L2_EXT_SNOOP_STALL", - "TSIx_L2_EXT_SNOOP_RESP_CLEAN", - "TSIx_L2_EXT_SNOOP_RESP_DATA", - "TSIx_L2_EXT_SNOOP_INTERNAL", - "", - "", - "", - "", - "", - "", - "", -}; - -#endif /* _KBASE_GATOR_HWCNT_NAMES_TSIX_H_ */ diff --git a/mali_kbase/mali_kbase_gator_hwcnt_names_ttrx.h b/mali_kbase/mali_kbase_gator_hwcnt_names_ttrx.h deleted file mode 100644 index 4226a9f..0000000 --- a/mali_kbase/mali_kbase_gator_hwcnt_names_ttrx.h +++ /dev/null @@ -1,296 +0,0 @@ -/* - * - * (C) COPYRIGHT 2016-2019 ARM Limited. All rights reserved. - * - * This program is free software and is provided to you under the terms of the - * GNU General Public License version 2 as published by the Free Software - * Foundation, and any use by you of this program is subject to the terms - * of such GNU licence. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you can access it online at - * http://www.gnu.org/licenses/gpl-2.0.html. - * - * SPDX-License-Identifier: GPL-2.0 - * - */ - -/* - * This header was autogenerated, it should not be edited. - */ - -#ifndef _KBASE_GATOR_HWCNT_NAMES_TTRX_H_ -#define _KBASE_GATOR_HWCNT_NAMES_TTRX_H_ - -static const char * const hardware_counters_mali_tTRx[] = { - /* Performance counters for the Job Manager */ - "", - "", - "", - "", - "TTRx_MESSAGES_SENT", - "TTRx_MESSAGES_RECEIVED", - "TTRx_GPU_ACTIVE", - "TTRx_IRQ_ACTIVE", - "TTRx_JS0_JOBS", - "TTRx_JS0_TASKS", - "TTRx_JS0_ACTIVE", - "", - "TTRx_JS0_WAIT_READ", - "TTRx_JS0_WAIT_ISSUE", - "TTRx_JS0_WAIT_DEPEND", - "TTRx_JS0_WAIT_FINISH", - "TTRx_JS1_JOBS", - "TTRx_JS1_TASKS", - "TTRx_JS1_ACTIVE", - "", - "TTRx_JS1_WAIT_READ", - "TTRx_JS1_WAIT_ISSUE", - "TTRx_JS1_WAIT_DEPEND", - "TTRx_JS1_WAIT_FINISH", - "TTRx_JS2_JOBS", - "TTRx_JS2_TASKS", - "TTRx_JS2_ACTIVE", - "", - "TTRx_JS2_WAIT_READ", - "TTRx_JS2_WAIT_ISSUE", - "TTRx_JS2_WAIT_DEPEND", - "TTRx_JS2_WAIT_FINISH", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - - /* Performance counters for the Tiler */ - "", - "", - "", - "", - "TTRx_TILER_ACTIVE", - "TTRx_JOBS_PROCESSED", - "TTRx_TRIANGLES", - "TTRx_LINES", - "TTRx_POINTS", - "TTRx_FRONT_FACING", - "TTRx_BACK_FACING", - "TTRx_PRIM_VISIBLE", - "TTRx_PRIM_CULLED", - "TTRx_PRIM_CLIPPED", - "TTRx_PRIM_SAT_CULLED", - "TTRx_BIN_ALLOC_INIT", - "TTRx_BIN_ALLOC_OVERFLOW", - "TTRx_BUS_READ", - "", - "TTRx_BUS_WRITE", - "TTRx_LOADING_DESC", - "TTRx_IDVS_POS_SHAD_REQ", - "TTRx_IDVS_POS_SHAD_WAIT", - "TTRx_IDVS_POS_SHAD_STALL", - "TTRx_IDVS_POS_FIFO_FULL", - "TTRx_PREFETCH_STALL", - "TTRx_VCACHE_HIT", - "TTRx_VCACHE_MISS", - "TTRx_VCACHE_LINE_WAIT", - "TTRx_VFETCH_POS_READ_WAIT", - "TTRx_VFETCH_VERTEX_WAIT", - "TTRx_VFETCH_STALL", - "TTRx_PRIMASSY_STALL", - "TTRx_BBOX_GEN_STALL", - "TTRx_IDVS_VBU_HIT", - "TTRx_IDVS_VBU_MISS", - "TTRx_IDVS_VBU_LINE_DEALLOCATE", - "TTRx_IDVS_VAR_SHAD_REQ", - "TTRx_IDVS_VAR_SHAD_STALL", - "TTRx_BINNER_STALL", - "TTRx_ITER_STALL", - "TTRx_COMPRESS_MISS", - "TTRx_COMPRESS_STALL", - "TTRx_PCACHE_HIT", - "TTRx_PCACHE_MISS", - "TTRx_PCACHE_MISS_STALL", - "TTRx_PCACHE_EVICT_STALL", - "TTRx_PMGR_PTR_WR_STALL", - "TTRx_PMGR_PTR_RD_STALL", - "TTRx_PMGR_CMD_WR_STALL", - "TTRx_WRBUF_ACTIVE", - "TTRx_WRBUF_HIT", - "TTRx_WRBUF_MISS", - "TTRx_WRBUF_NO_FREE_LINE_STALL", - "TTRx_WRBUF_NO_AXI_ID_STALL", - "TTRx_WRBUF_AXI_STALL", - "", - "", - "", - "TTRx_UTLB_TRANS", - "TTRx_UTLB_TRANS_HIT", - "TTRx_UTLB_TRANS_STALL", - "TTRx_UTLB_TRANS_MISS_DELAY", - "TTRx_UTLB_MMU_REQ", - - /* Performance counters for the Shader Core */ - "", - "", - "", - "", - "TTRx_FRAG_ACTIVE", - "TTRx_FRAG_PRIMITIVES_OUT", - "TTRx_FRAG_PRIM_RAST", - "TTRx_FRAG_FPK_ACTIVE", - "TTRx_FRAG_STARVING", - "TTRx_FRAG_WARPS", - "TTRx_FRAG_PARTIAL_QUADS_RAST", - "TTRx_FRAG_QUADS_RAST", - "TTRx_FRAG_QUADS_EZS_TEST", - "TTRx_FRAG_QUADS_EZS_UPDATE", - "TTRx_FRAG_QUADS_EZS_KILL", - "TTRx_FRAG_LZS_TEST", - "TTRx_FRAG_LZS_KILL", - "TTRx_WARP_REG_SIZE_64", - "TTRx_FRAG_PTILES", - "TTRx_FRAG_TRANS_ELIM", - "TTRx_QUAD_FPK_KILLER", - "TTRx_FULL_QUAD_WARPS", - "TTRx_COMPUTE_ACTIVE", - "TTRx_COMPUTE_TASKS", - "TTRx_COMPUTE_WARPS", - "TTRx_COMPUTE_STARVING", - "TTRx_EXEC_CORE_ACTIVE", - "TTRx_EXEC_INSTR_FMA", - "TTRx_EXEC_INSTR_CVT", - "TTRx_EXEC_INSTR_SFU", - "TTRx_EXEC_INSTR_MSG", - "TTRx_EXEC_INSTR_DIVERGED", - "TTRx_EXEC_ICACHE_MISS", - "TTRx_EXEC_STARVE_ARITH", - "TTRx_CALL_BLEND_SHADER", - "TTRx_TEX_MSGI_NUM_FLITS", - "TTRx_TEX_DFCH_CLK_STALLED", - "TTRx_TEX_TFCH_CLK_STALLED", - "TTRx_TEX_TFCH_STARVED_PENDING_DATA_FETCH", - "TTRx_TEX_FILT_NUM_OPERATIONS", - "TTRx_TEX_FILT_NUM_FXR_OPERATIONS", - "TTRx_TEX_FILT_NUM_FST_OPERATIONS", - "TTRx_TEX_MSGO_NUM_MSG", - "TTRx_TEX_MSGO_NUM_FLITS", - "TTRx_LS_MEM_READ_FULL", - "TTRx_LS_MEM_READ_SHORT", - "TTRx_LS_MEM_WRITE_FULL", - "TTRx_LS_MEM_WRITE_SHORT", - "TTRx_LS_MEM_ATOMIC", - "TTRx_VARY_INSTR", - "TTRx_VARY_SLOT_32", - "TTRx_VARY_SLOT_16", - "TTRx_ATTR_INSTR", - "TTRx_ARITH_INSTR_FP_MUL", - "TTRx_BEATS_RD_FTC", - "TTRx_BEATS_RD_FTC_EXT", - "TTRx_BEATS_RD_LSC", - "TTRx_BEATS_RD_LSC_EXT", - "TTRx_BEATS_RD_TEX", - "TTRx_BEATS_RD_TEX_EXT", - "TTRx_BEATS_RD_OTHER", - "TTRx_BEATS_WR_LSC_OTHER", - "TTRx_BEATS_WR_TIB", - "TTRx_BEATS_WR_LSC_WB", - - /* Performance counters for the Memory System */ - "", - "", - "", - "", - "TTRx_MMU_REQUESTS", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "TTRx_L2_RD_MSG_IN", - "TTRx_L2_RD_MSG_IN_STALL", - "TTRx_L2_WR_MSG_IN", - "TTRx_L2_WR_MSG_IN_STALL", - "TTRx_L2_SNP_MSG_IN", - "TTRx_L2_SNP_MSG_IN_STALL", - "TTRx_L2_RD_MSG_OUT", - "TTRx_L2_RD_MSG_OUT_STALL", - "TTRx_L2_WR_MSG_OUT", - "TTRx_L2_ANY_LOOKUP", - "TTRx_L2_READ_LOOKUP", - "TTRx_L2_WRITE_LOOKUP", - "TTRx_L2_EXT_SNOOP_LOOKUP", - "TTRx_L2_EXT_READ", - "TTRx_L2_EXT_READ_NOSNP", - "TTRx_L2_EXT_READ_UNIQUE", - "TTRx_L2_EXT_READ_BEATS", - "TTRx_L2_EXT_AR_STALL", - "TTRx_L2_EXT_AR_CNT_Q1", - "TTRx_L2_EXT_AR_CNT_Q2", - "TTRx_L2_EXT_AR_CNT_Q3", - "TTRx_L2_EXT_RRESP_0_127", - "TTRx_L2_EXT_RRESP_128_191", - "TTRx_L2_EXT_RRESP_192_255", - "TTRx_L2_EXT_RRESP_256_319", - "TTRx_L2_EXT_RRESP_320_383", - "TTRx_L2_EXT_WRITE", - "TTRx_L2_EXT_WRITE_NOSNP_FULL", - "TTRx_L2_EXT_WRITE_NOSNP_PTL", - "TTRx_L2_EXT_WRITE_SNP_FULL", - "TTRx_L2_EXT_WRITE_SNP_PTL", - "TTRx_L2_EXT_WRITE_BEATS", - "TTRx_L2_EXT_W_STALL", - "TTRx_L2_EXT_AW_CNT_Q1", - "TTRx_L2_EXT_AW_CNT_Q2", - "TTRx_L2_EXT_AW_CNT_Q3", - "TTRx_L2_EXT_SNOOP", - "TTRx_L2_EXT_SNOOP_STALL", - "TTRx_L2_EXT_SNOOP_RESP_CLEAN", - "TTRx_L2_EXT_SNOOP_RESP_DATA", - "TTRx_L2_EXT_SNOOP_INTERNAL", - "", - "", - "", - "", - "", - "", - "", -}; - -#endif /* _KBASE_GATOR_HWCNT_NAMES_TTRX_H_ */ diff --git a/mali_kbase/mali_kbase_gpu_id.h b/mali_kbase/mali_kbase_gpu_id.h index f9f6703..24b99f2 100644 --- a/mali_kbase/mali_kbase_gpu_id.h +++ b/mali_kbase/mali_kbase_gpu_id.h @@ -1,6 +1,6 @@ /* * - * (C) COPYRIGHT 2015-2018 ARM Limited. All rights reserved. + * (C) COPYRIGHT 2015-2019 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the * GNU General Public License version 2 as published by the Free Software @@ -109,8 +109,6 @@ #define GPU_ID2_PRODUCT_TDVX GPU_ID2_MODEL_MAKE(7, 3) #define GPU_ID2_PRODUCT_TNOX GPU_ID2_MODEL_MAKE(7, 1) #define GPU_ID2_PRODUCT_TGOX GPU_ID2_MODEL_MAKE(7, 2) -#define GPU_ID2_PRODUCT_TKAX GPU_ID2_MODEL_MAKE(8, 0) -#define GPU_ID2_PRODUCT_TBOX GPU_ID2_MODEL_MAKE(8, 2) #define GPU_ID2_PRODUCT_TEGX GPU_ID2_MODEL_MAKE(8, 3) #define GPU_ID2_PRODUCT_TTRX GPU_ID2_MODEL_MAKE(9, 0) #define GPU_ID2_PRODUCT_TNAX GPU_ID2_MODEL_MAKE(9, 1) @@ -119,6 +117,7 @@ #define GPU_ID2_PRODUCT_TDUX GPU_ID2_MODEL_MAKE(10, 1) #define GPU_ID2_PRODUCT_TIDX GPU_ID2_MODEL_MAKE(10, 3) #define GPU_ID2_PRODUCT_TVAX GPU_ID2_MODEL_MAKE(10, 4) +#define GPU_ID2_PRODUCT_TODX GPU_ID2_MODEL_MAKE(10, 8) /* Values for GPU_ID_VERSION_STATUS field for PRODUCT_ID GPU_ID_PI_T60X */ #define GPU_ID_S_15DEV0 0x1 @@ -132,4 +131,8 @@ (((u32)minor) << GPU_ID_VERSION_MINOR_SHIFT) | \ (((u32)status) << GPU_ID_VERSION_STATUS_SHIFT)) +/* Statically set to 0 because the HW revision cannot be seen at compile time + * by the build system */ +#define GPU_HAS_CSF_VERSION_10_REVISION_2 (0) + #endif /* _KBASE_GPU_ID_H_ */ diff --git a/mali_kbase/mali_kbase_gpu_memory_debugfs.c b/mali_kbase/mali_kbase_gpu_memory_debugfs.c index 616505c..2c42f5c 100644 --- a/mali_kbase/mali_kbase_gpu_memory_debugfs.c +++ b/mali_kbase/mali_kbase_gpu_memory_debugfs.c @@ -74,6 +74,7 @@ static int kbasep_gpu_memory_debugfs_open(struct inode *in, struct file *file) } static const struct file_operations kbasep_gpu_memory_debugfs_fops = { + .owner = THIS_MODULE, .open = kbasep_gpu_memory_debugfs_open, .read = seq_read, .llseek = seq_lseek, diff --git a/mali_kbase/mali_kbase_gpuprops.c b/mali_kbase/mali_kbase_gpuprops.c index ee3617c..302d383 100644 --- a/mali_kbase/mali_kbase_gpuprops.c +++ b/mali_kbase/mali_kbase_gpuprops.c @@ -245,10 +245,17 @@ static void kbase_gpuprops_calculate_props(base_gpu_props * const gpu_props, str gpu_props->thread_props.tls_alloc = gpu_props->raw_props.thread_tls_alloc; +#if GPU_HAS_CSF_VERSION_10_REVISION_2 + gpu_props->thread_props.max_registers = KBASE_UBFX32(gpu_props->raw_props.thread_features, 0U, 22); + gpu_props->thread_props.impl_tech = KBASE_UBFX32(gpu_props->raw_props.thread_features, 22U, 2); + gpu_props->thread_props.max_task_queue = KBASE_UBFX32(gpu_props->raw_props.thread_features, 24U, 8); + gpu_props->thread_props.max_thread_group_split = 0; +#else gpu_props->thread_props.max_registers = KBASE_UBFX32(gpu_props->raw_props.thread_features, 0U, 16); gpu_props->thread_props.max_task_queue = KBASE_UBFX32(gpu_props->raw_props.thread_features, 16U, 8); gpu_props->thread_props.max_thread_group_split = KBASE_UBFX32(gpu_props->raw_props.thread_features, 24U, 6); gpu_props->thread_props.impl_tech = KBASE_UBFX32(gpu_props->raw_props.thread_features, 30U, 2); +#endif /* If values are not specified, then use defaults */ if (gpu_props->thread_props.max_registers == 0) { diff --git a/mali_kbase/mali_kbase_gwt.c b/mali_kbase/mali_kbase_gwt.c index 2d1263d..75a0820 100644 --- a/mali_kbase/mali_kbase_gwt.c +++ b/mali_kbase/mali_kbase_gwt.c @@ -1,6 +1,6 @@ /* * - * (C) COPYRIGHT 2010-2018 ARM Limited. All rights reserved. + * (C) COPYRIGHT 2010-2019 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the * GNU General Public License version 2 as published by the Free Software @@ -40,7 +40,8 @@ static inline void kbase_gpu_gwt_setup_page_permission( err = kbase_mmu_update_pages(kctx, reg->start_pfn, kbase_get_gpu_phy_pages(reg), reg->gpu_alloc->nents, - reg->flags & flag); + reg->flags & flag, + reg->gpu_alloc->group_id); if (err) dev_warn(kctx->kbdev->dev, "kbase_mmu_update_pages failure\n"); } diff --git a/mali_kbase/mali_kbase_hw.c b/mali_kbase/mali_kbase_hw.c index 65d6c09..8330698 100644 --- a/mali_kbase/mali_kbase_hw.c +++ b/mali_kbase/mali_kbase_hw.c @@ -62,9 +62,6 @@ void kbase_hw_set_features_mask(struct kbase_device *kbdev) case GPU_ID2_PRODUCT_TGOX: features = base_hw_features_tGOx; break; - case GPU_ID2_PRODUCT_TKAX: - features = base_hw_features_tKAx; - break; case GPU_ID2_PRODUCT_TEGX: features = base_hw_features_tEGx; break; @@ -83,8 +80,8 @@ void kbase_hw_set_features_mask(struct kbase_device *kbdev) case GPU_ID2_PRODUCT_TDUX: features = base_hw_features_tDUx; break; - case GPU_ID2_PRODUCT_TBOX: - features = base_hw_features_tBOx; + case GPU_ID2_PRODUCT_TODX: + features = base_hw_features_tODx; break; case GPU_ID2_PRODUCT_TIDX: features = base_hw_features_tIDx; @@ -213,10 +210,6 @@ static const enum base_hw_issue *kbase_hw_get_issues_for_new_id( {GPU_ID2_VERSION_MAKE(1, 0, 0), base_hw_issues_tGOx_r1p0}, {U32_MAX, NULL} } }, - {GPU_ID2_PRODUCT_TKAX, - {{GPU_ID2_VERSION_MAKE(0, 0, 0), base_hw_issues_tKAx_r0p0}, - {U32_MAX, NULL} } }, - {GPU_ID2_PRODUCT_TEGX, {{GPU_ID2_VERSION_MAKE(0, 0, 0), base_hw_issues_tEGx_r0p0}, {U32_MAX, NULL} } }, @@ -249,8 +242,8 @@ static const enum base_hw_issue *kbase_hw_get_issues_for_new_id( {{GPU_ID2_VERSION_MAKE(0, 0, 0), base_hw_issues_tDUx_r0p0}, {U32_MAX, NULL} } }, - {GPU_ID2_PRODUCT_TBOX, - {{GPU_ID2_VERSION_MAKE(0, 0, 0), base_hw_issues_tBOx_r0p0}, + {GPU_ID2_PRODUCT_TODX, + {{GPU_ID2_VERSION_MAKE(0, 0, 0), base_hw_issues_tODx_r0p0}, {U32_MAX, NULL} } }, {GPU_ID2_PRODUCT_TIDX, @@ -489,9 +482,6 @@ int kbase_hw_set_issues_mask(struct kbase_device *kbdev) case GPU_ID2_PRODUCT_TGOX: issues = base_hw_issues_model_tGOx; break; - case GPU_ID2_PRODUCT_TKAX: - issues = base_hw_issues_model_tKAx; - break; case GPU_ID2_PRODUCT_TEGX: issues = base_hw_issues_model_tEGx; break; @@ -510,8 +500,8 @@ int kbase_hw_set_issues_mask(struct kbase_device *kbdev) case GPU_ID2_PRODUCT_TDUX: issues = base_hw_issues_model_tDUx; break; - case GPU_ID2_PRODUCT_TBOX: - issues = base_hw_issues_model_tBOx; + case GPU_ID2_PRODUCT_TODX: + issues = base_hw_issues_model_tODx; break; case GPU_ID2_PRODUCT_TIDX: issues = base_hw_issues_model_tIDx; diff --git a/mali_kbase/mali_kbase_hwaccess_jm.h b/mali_kbase/mali_kbase_hwaccess_jm.h index e2798eb..c040753 100644 --- a/mali_kbase/mali_kbase_hwaccess_jm.h +++ b/mali_kbase/mali_kbase_hwaccess_jm.h @@ -1,6 +1,6 @@ /* * - * (C) COPYRIGHT 2014-2018 ARM Limited. All rights reserved. + * (C) COPYRIGHT 2014-2019 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the * GNU General Public License version 2 as published by the Free Software @@ -276,87 +276,6 @@ void kbase_jm_wait_for_zero_jobs(struct kbase_context *kctx); u32 kbase_backend_get_current_flush_id(struct kbase_device *kbdev); /** - * kbase_prepare_to_reset_gpu - Prepare for resetting the GPU. - * @kbdev: Device pointer - * - * This function just soft-stops all the slots to ensure that as many jobs as - * possible are saved. - * - * Return: a boolean which should be interpreted as follows: - * - true - Prepared for reset, kbase_reset_gpu should be called. - * - false - Another thread is performing a reset, kbase_reset_gpu should - * not be called. - */ -bool kbase_prepare_to_reset_gpu(struct kbase_device *kbdev); - -/** - * kbase_reset_gpu - Reset the GPU - * @kbdev: Device pointer - * - * This function should be called after kbase_prepare_to_reset_gpu if it returns - * true. It should never be called without a corresponding call to - * kbase_prepare_to_reset_gpu. - * - * After this function is called (or not called if kbase_prepare_to_reset_gpu - * returned false), the caller should wait for kbdev->reset_waitq to be - * signalled to know when the reset has completed. - */ -void kbase_reset_gpu(struct kbase_device *kbdev); - -/** - * kbase_prepare_to_reset_gpu_locked - Prepare for resetting the GPU. - * @kbdev: Device pointer - * - * This function just soft-stops all the slots to ensure that as many jobs as - * possible are saved. - * - * Return: a boolean which should be interpreted as follows: - * - true - Prepared for reset, kbase_reset_gpu should be called. - * - false - Another thread is performing a reset, kbase_reset_gpu should - * not be called. - */ -bool kbase_prepare_to_reset_gpu_locked(struct kbase_device *kbdev); - -/** - * kbase_reset_gpu_locked - Reset the GPU - * @kbdev: Device pointer - * - * This function should be called after kbase_prepare_to_reset_gpu if it - * returns true. It should never be called without a corresponding call to - * kbase_prepare_to_reset_gpu. - * - * After this function is called (or not called if kbase_prepare_to_reset_gpu - * returned false), the caller should wait for kbdev->reset_waitq to be - * signalled to know when the reset has completed. - */ -void kbase_reset_gpu_locked(struct kbase_device *kbdev); - -/** - * kbase_reset_gpu_silent - Reset the GPU silently - * @kbdev: Device pointer - * - * Reset the GPU without trying to cancel jobs and don't emit messages into - * the kernel log while doing the reset. - * - * This function should be used in cases where we are doing a controlled reset - * of the GPU as part of normal processing (e.g. exiting protected mode) where - * the driver will have ensured the scheduler has been idled and all other - * users of the GPU (e.g. instrumentation) have been suspended. - * - * Return: 0 if the reset was started successfully - * -EAGAIN if another reset is currently in progress - */ -int kbase_reset_gpu_silent(struct kbase_device *kbdev); - -/** - * kbase_reset_gpu_active - Reports if the GPU is being reset - * @kbdev: Device pointer - * - * Return: True if the GPU is in the process of being reset. - */ -bool kbase_reset_gpu_active(struct kbase_device *kbdev); - -/** * kbase_job_slot_hardstop - Hard-stop the specified job slot * @kctx: The kbase context that contains the job(s) that should * be hard-stopped diff --git a/mali_kbase/mali_kbase_hwcnt_backend_gpu.c b/mali_kbase/mali_kbase_hwcnt_backend_gpu.c index a3cc287..1e9c25a 100644 --- a/mali_kbase/mali_kbase_hwcnt_backend_gpu.c +++ b/mali_kbase/mali_kbase_hwcnt_backend_gpu.c @@ -24,10 +24,8 @@ #include "mali_kbase_hwcnt_gpu.h" #include "mali_kbase_hwcnt_types.h" #include "mali_kbase.h" -#include "mali_kbase_pm_policy.h" #include "mali_kbase_pm_ca.h" #include "mali_kbase_hwaccess_instr.h" -#include "mali_kbase_tracepoints.h" #ifdef CONFIG_MALI_NO_MALI #include "backend/gpu/mali_kbase_model_dummy.h" #endif diff --git a/mali_kbase/mali_kbase_ioctl.h b/mali_kbase/mali_kbase_ioctl.h index 4181e72..525bfb6 100644 --- a/mali_kbase/mali_kbase_ioctl.h +++ b/mali_kbase/mali_kbase_ioctl.h @@ -80,8 +80,8 @@ extern "C" { * requiring external resource or sticky resource tracking. UNLESS, * CONFIG_MALI_DMA_BUF_MAP_ON_DEMAND is enabled. */ -#define BASE_UK_VERSION_MAJOR ((__u16)11) -#define BASE_UK_VERSION_MINOR ((__u16)16) +#define BASE_UK_VERSION_MAJOR 11 +#define BASE_UK_VERSION_MINOR 16 /** * struct kbase_ioctl_version_check - Check version compatibility with kernel diff --git a/mali_kbase/mali_kbase_jd.c b/mali_kbase/mali_kbase_jd.c index 749ca7f..c984a82 100644 --- a/mali_kbase/mali_kbase_jd.c +++ b/mali_kbase/mali_kbase_jd.c @@ -95,11 +95,7 @@ static int jd_run_atom(struct kbase_jd_atom *katom) katom->status = KBASE_JD_ATOM_STATE_COMPLETED; return 0; } - if ((katom->core_req & BASE_JD_REQ_SOFT_JOB_TYPE) - == BASE_JD_REQ_SOFT_REPLAY) { - if (!kbase_replay_process(katom)) - katom->status = KBASE_JD_ATOM_STATE_COMPLETED; - } else if (kbase_process_soft_job(katom) == 0) { + if (kbase_process_soft_job(katom) == 0) { kbase_finish_soft_job(katom); katom->status = KBASE_JD_ATOM_STATE_COMPLETED; } @@ -270,14 +266,14 @@ static int kbase_jd_pre_external_resources(struct kbase_jd_atom *katom, const st /* need to keep the GPU VM locked while we set up UMM buffers */ kbase_gpu_vm_lock(katom->kctx); for (res_no = 0; res_no < katom->nr_extres; res_no++) { - struct base_external_resource *res; + struct base_external_resource *res = &input_extres[res_no]; struct kbase_va_region *reg; struct kbase_mem_phy_alloc *alloc; +#ifdef CONFIG_MALI_DMA_FENCE bool exclusive; - - res = &input_extres[res_no]; exclusive = (res->ext_resource & BASE_EXT_RES_ACCESS_EXCLUSIVE) ? true : false; +#endif reg = kbase_region_tracker_find_region_enclosing_address( katom->kctx, res->ext_resource & ~BASE_EXT_RES_ACCESS_EXCLUSIVE); @@ -408,14 +404,7 @@ static inline void jd_resolve_dep(struct list_head *out_list, KBASE_DEBUG_ASSERT(dep_atom->status != KBASE_JD_ATOM_STATE_UNUSED); - if ((dep_atom->core_req & BASE_JD_REQ_SOFT_JOB_TYPE) - != BASE_JD_REQ_SOFT_REPLAY) { - dep_atom->will_fail_event_code = - dep_atom->event_code; - } else { - dep_atom->status = - KBASE_JD_ATOM_STATE_COMPLETED; - } + dep_atom->will_fail_event_code = dep_atom->event_code; } other_dep_atom = (struct kbase_jd_atom *) kbase_jd_katom_dep_atom(&dep_atom->dep[other_d]); @@ -459,54 +448,6 @@ static inline void jd_resolve_dep(struct list_head *out_list, KBASE_EXPORT_TEST_API(jd_resolve_dep); -#if MALI_CUSTOMER_RELEASE == 0 -static void jd_force_failure(struct kbase_device *kbdev, struct kbase_jd_atom *katom) -{ - kbdev->force_replay_count++; - - if (kbdev->force_replay_count >= kbdev->force_replay_limit) { - kbdev->force_replay_count = 0; - katom->event_code = BASE_JD_EVENT_FORCE_REPLAY; - - if (kbdev->force_replay_random) - kbdev->force_replay_limit = - (prandom_u32() % KBASEP_FORCE_REPLAY_RANDOM_LIMIT) + 1; - - dev_info(kbdev->dev, "force_replay : promoting to error\n"); - } -} - -/** Test to see if atom should be forced to fail. - * - * This function will check if an atom has a replay job as a dependent. If so - * then it will be considered for forced failure. */ -static void jd_check_force_failure(struct kbase_jd_atom *katom) -{ - struct kbase_context *kctx = katom->kctx; - struct kbase_device *kbdev = kctx->kbdev; - int i; - - if ((kbdev->force_replay_limit == KBASEP_FORCE_REPLAY_DISABLED) || - (katom->core_req & BASEP_JD_REQ_EVENT_NEVER)) - return; - - for (i = 1; i < BASE_JD_ATOM_COUNT; i++) { - if (kbase_jd_katom_dep_atom(&kctx->jctx.atoms[i].dep[0]) == katom || - kbase_jd_katom_dep_atom(&kctx->jctx.atoms[i].dep[1]) == katom) { - struct kbase_jd_atom *dep_atom = &kctx->jctx.atoms[i]; - - if ((dep_atom->core_req & BASE_JD_REQ_SOFT_JOB_TYPE) == - BASE_JD_REQ_SOFT_REPLAY && - (dep_atom->core_req & kbdev->force_replay_core_req) - == kbdev->force_replay_core_req) { - jd_force_failure(kbdev, katom); - return; - } - } - } -} -#endif - /** * is_dep_valid - Validate that a dependency is valid for early dependency * submission @@ -618,10 +559,6 @@ bool jd_done_nolock(struct kbase_jd_atom *katom, KBASE_DEBUG_ASSERT(katom->status != KBASE_JD_ATOM_STATE_UNUSED); -#if MALI_CUSTOMER_RELEASE == 0 - jd_check_force_failure(katom); -#endif - /* This is needed in case an atom is failed due to being invalid, this * can happen *before* the jobs that the atom depends on have completed */ for (i = 0; i < 2; i++) { @@ -678,13 +615,7 @@ bool jd_done_nolock(struct kbase_jd_atom *katom, } else { node->event_code = katom->event_code; - if ((node->core_req & - BASE_JD_REQ_SOFT_JOB_TYPE) == - BASE_JD_REQ_SOFT_REPLAY) { - if (kbase_replay_process(node)) - /* Don't complete this atom */ - continue; - } else if (node->core_req & + if (node->core_req & BASE_JD_REQ_SOFT_JOB) { WARN_ON(!list_empty(&node->queue)); kbase_finish_soft_job(node); @@ -704,7 +635,7 @@ bool jd_done_nolock(struct kbase_jd_atom *katom, } /* Register a completed job as a disjoint event when the GPU - * is in a disjoint state (ie. being reset or replaying jobs). + * is in a disjoint state (ie. being reset). */ kbase_disjoint_event_potential(kctx->kbdev); if (completed_jobs_ctx) @@ -893,9 +824,9 @@ bool jd_submit_atom(struct kbase_context *kctx, const struct base_jd_atom_v2 *us katom->event_code = dep_atom->event_code; katom->status = KBASE_JD_ATOM_STATE_QUEUED; - /* This atom is going through soft replay or - * will be sent back to user space. Do not record any - * dependencies. */ + /* This atom will be sent back to user space. + * Do not record any dependencies. + */ KBASE_TLSTREAM_TL_NEW_ATOM( kbdev, katom, @@ -904,13 +835,6 @@ bool jd_submit_atom(struct kbase_context *kctx, const struct base_jd_atom_v2 *us KBASE_TLSTREAM_TL_ATTRIB_ATOM_STATE(kbdev, katom, TL_ATOM_STATE_IDLE); - if ((katom->core_req & BASE_JD_REQ_SOFT_JOB_TYPE) - == BASE_JD_REQ_SOFT_REPLAY) { - if (kbase_replay_process(katom)) { - ret = false; - goto out; - } - } will_fail = true; } else { @@ -1072,15 +996,7 @@ bool jd_submit_atom(struct kbase_context *kctx, const struct base_jd_atom_v2 *us } #endif /* CONFIG_MALI_DMA_FENCE */ - if ((katom->core_req & BASE_JD_REQ_SOFT_JOB_TYPE) - == BASE_JD_REQ_SOFT_REPLAY) { - if (kbase_replay_process(katom)) - ret = false; - else - ret = jd_done_nolock(katom, NULL); - - goto out; - } else if (katom->core_req & BASE_JD_REQ_SOFT_JOB) { + if (katom->core_req & BASE_JD_REQ_SOFT_JOB) { if (kbase_process_soft_job(katom) == 0) { kbase_finish_soft_job(katom); ret = jd_done_nolock(katom, NULL); @@ -1198,7 +1114,7 @@ while (false) jd_submit_atom(kctx, &user_atom, katom); /* Register a completed job as a disjoint event when the GPU is in a disjoint state - * (ie. being reset or replaying jobs). + * (ie. being reset). */ kbase_disjoint_event_potential(kbdev); diff --git a/mali_kbase/mali_kbase_jd_debugfs.c b/mali_kbase/mali_kbase_jd_debugfs.c index a74ba30..2fc21fd 100644 --- a/mali_kbase/mali_kbase_jd_debugfs.c +++ b/mali_kbase/mali_kbase_jd_debugfs.c @@ -221,6 +221,7 @@ static int kbasep_jd_debugfs_atoms_open(struct inode *in, struct file *file) } static const struct file_operations kbasep_jd_debugfs_atoms_fops = { + .owner = THIS_MODULE, .open = kbasep_jd_debugfs_atoms_open, .read = seq_read, .llseek = seq_lseek, diff --git a/mali_kbase/mali_kbase_mem.c b/mali_kbase/mali_kbase_mem.c index 2ccf300..f55d8ea 100644 --- a/mali_kbase/mali_kbase_mem.c +++ b/mali_kbase/mali_kbase_mem.c @@ -769,13 +769,9 @@ static int kbase_region_tracker_init_jit_64(struct kbase_context *kctx, { struct kbase_va_region *same_va; struct kbase_va_region *custom_va_reg; - u64 same_va_bits = kbase_get_same_va_bits(kctx); - u64 total_va_size; lockdep_assert_held(&kctx->reg_lock); - total_va_size = (1ULL << (same_va_bits - PAGE_SHIFT)) - 1; - /* First verify that a JIT_VA zone has not been created already. */ if (kctx->jit_va) return -EINVAL; @@ -971,6 +967,11 @@ int kbase_mem_init(struct kbase_device *kbdev) dev_info(kbdev->dev, "Memory group manager is not ready\n"); err = -EPROBE_DEFER; + } else if (!try_module_get(kbdev->mgm_dev->owner)) { + dev_err(kbdev->dev, + "Failed to get memory group manger module\n"); + err = -ENODEV; + kbdev->mgm_dev = NULL; } } of_node_put(mgm_node); @@ -1009,6 +1010,9 @@ void kbase_mem_term(struct kbase_device *kbdev) dev_warn(kbdev->dev, "%s: %d pages in use!\n", __func__, pages); kbase_mem_pool_group_term(&kbdev->mem_pools); + + if (kbdev->mgm_dev) + module_put(kbdev->mgm_dev->owner); } KBASE_EXPORT_TEST_API(kbase_mem_term); @@ -1174,6 +1178,8 @@ int kbase_gpu_mmap(struct kbase_context *kctx, struct kbase_va_region *reg, u64 unsigned long attr; unsigned long mask = ~KBASE_REG_MEMATTR_MASK; unsigned long gwt_mask = ~0; + int group_id; + struct kbase_mem_phy_alloc *alloc; #ifdef CONFIG_MALI_CINSTR_GWT if (kctx->gwt_enabled) @@ -1193,12 +1199,12 @@ int kbase_gpu_mmap(struct kbase_context *kctx, struct kbase_va_region *reg, u64 if (err) return err; + alloc = reg->gpu_alloc; + group_id = alloc->group_id; + if (reg->gpu_alloc->type == KBASE_MEM_TYPE_ALIAS) { - u64 stride; - struct kbase_mem_phy_alloc *alloc; + u64 const stride = alloc->imported.alias.stride; - alloc = reg->gpu_alloc; - stride = alloc->imported.alias.stride; KBASE_DEBUG_ASSERT(alloc->imported.alias.aliased); for (i = 0; i < alloc->imported.alias.nents; i++) { if (alloc->imported.alias.aliased[i].alloc) { @@ -1208,7 +1214,8 @@ int kbase_gpu_mmap(struct kbase_context *kctx, struct kbase_va_region *reg, u64 alloc->imported.alias.aliased[i].alloc->pages + alloc->imported.alias.aliased[i].offset, alloc->imported.alias.aliased[i].length, reg->flags & gwt_mask, - kctx->as_nr); + kctx->as_nr, + group_id); if (err) goto bad_insert; @@ -1218,7 +1225,8 @@ int kbase_gpu_mmap(struct kbase_context *kctx, struct kbase_va_region *reg, u64 reg->start_pfn + i * stride, kctx->aliasing_sink_page, alloc->imported.alias.aliased[i].length, - (reg->flags & mask & gwt_mask) | attr); + (reg->flags & mask & gwt_mask) | attr, + group_id); if (err) goto bad_insert; @@ -1231,10 +1239,11 @@ int kbase_gpu_mmap(struct kbase_context *kctx, struct kbase_va_region *reg, u64 kbase_get_gpu_phy_pages(reg), kbase_reg_current_backed_size(reg), reg->flags & gwt_mask, - kctx->as_nr); + kctx->as_nr, + group_id); if (err) goto bad_insert; - kbase_mem_phy_alloc_gpu_mapped(reg->gpu_alloc); + kbase_mem_phy_alloc_gpu_mapped(alloc); } if (reg->flags & KBASE_REG_IMPORT_PAD && @@ -1256,7 +1265,8 @@ int kbase_gpu_mmap(struct kbase_context *kctx, struct kbase_va_region *reg, u64 kctx->aliasing_sink_page, reg->nr_pages - reg->gpu_alloc->nents, (reg->flags | KBASE_REG_GPU_RD) & - ~KBASE_REG_GPU_WR); + ~KBASE_REG_GPU_WR, + KBASE_MEM_GROUP_SINK); if (err) goto bad_insert; } @@ -1268,11 +1278,11 @@ bad_insert: reg->start_pfn, reg->nr_pages, kctx->as_nr); - if (reg->gpu_alloc->type == KBASE_MEM_TYPE_ALIAS) { - KBASE_DEBUG_ASSERT(reg->gpu_alloc->imported.alias.aliased); + if (alloc->type == KBASE_MEM_TYPE_ALIAS) { + KBASE_DEBUG_ASSERT(alloc->imported.alias.aliased); while (i--) - if (reg->gpu_alloc->imported.alias.aliased[i].alloc) - kbase_mem_phy_alloc_gpu_unmapped(reg->gpu_alloc->imported.alias.aliased[i].alloc); + if (alloc->imported.alias.aliased[i].alloc) + kbase_mem_phy_alloc_gpu_unmapped(alloc->imported.alias.aliased[i].alloc); } kbase_remove_va_region(reg); @@ -2444,11 +2454,6 @@ void kbase_free_phy_pages_helper_locked(struct kbase_mem_phy_alloc *alloc, } } -/** - * kbase_jd_user_buf_unpin_pages - Release the pinned pages of a user buffer. - * @alloc: The allocation for the imported user buffer. - */ -static void kbase_jd_user_buf_unpin_pages(struct kbase_mem_phy_alloc *alloc); void kbase_mem_kref_free(struct kref *kref) { @@ -2516,7 +2521,6 @@ void kbase_mem_kref_free(struct kref *kref) break; #endif case KBASE_MEM_TYPE_IMPORTED_USER_BUF: - kbase_jd_user_buf_unpin_pages(alloc); if (alloc->imported.user_buf.mm) mmdrop(alloc->imported.user_buf.mm); if (alloc->properties & KBASE_MEM_PHY_ALLOC_LARGE) @@ -3530,24 +3534,6 @@ bool kbase_has_exec_va_zone(struct kbase_context *kctx) return has_exec_va_zone; } -static void kbase_jd_user_buf_unpin_pages(struct kbase_mem_phy_alloc *alloc) -{ - if (alloc->nents) { - struct page **pages = alloc->imported.user_buf.pages; - long i; - - WARN_ON(alloc->nents != alloc->imported.user_buf.nr_pages); - - for (i = 0; i < alloc->nents; i++) { - /* Shall come to this point only if the userbuf pages - * were pinned but weren't mapped on the GPU side. If - * they were mapped then pages would have got unpinned - * before kbase_mem_kref_free() was called. - */ - put_page(pages[i]); - } - } -} int kbase_jd_user_buf_pin_pages(struct kbase_context *kctx, struct kbase_va_region *reg) @@ -3626,14 +3612,13 @@ static int kbase_jd_user_buf_map(struct kbase_context *kctx, struct page **pages; struct tagged_addr *pa; long i; - int err = -ENOMEM; unsigned long address; struct device *dev; unsigned long offset; unsigned long local_size; unsigned long gwt_mask = ~0; + int err = kbase_jd_user_buf_pin_pages(kctx, reg); - err = kbase_jd_user_buf_pin_pages(kctx, reg); if (err) return err; @@ -3671,7 +3656,8 @@ static int kbase_jd_user_buf_map(struct kbase_context *kctx, err = kbase_mmu_insert_pages(kctx->kbdev, &kctx->mmu, reg->start_pfn, pa, kbase_reg_current_backed_size(reg), - reg->flags & gwt_mask, kctx->as_nr); + reg->flags & gwt_mask, kctx->as_nr, + alloc->group_id); if (err == 0) return 0; @@ -3692,9 +3678,9 @@ unwind: return err; } -/* This function also performs the work of kbase_jd_user_buf_unpin_pages() - * which implies that a call to kbase_jd_user_buf_pin_pages() may NOT - * necessarily have a corresponding call to kbase_jd_user_buf_unpin_pages(). +/* This function would also perform the work of unpinning pages on Job Manager + * GPUs, which implies that a call to kbase_jd_user_buf_pin_pages() will NOT + * have a corresponding call to kbase_jd_user_buf_unpin_pages(). */ static void kbase_jd_user_buf_unmap(struct kbase_context *kctx, struct kbase_mem_phy_alloc *alloc, bool writeable) diff --git a/mali_kbase/mali_kbase_mem.h b/mali_kbase/mali_kbase_mem.h index 672bcac..ca5bbee 100644 --- a/mali_kbase/mali_kbase_mem.h +++ b/mali_kbase/mali_kbase_mem.h @@ -1036,25 +1036,45 @@ int kbase_mmu_init(struct kbase_device *kbdev, struct kbase_mmu_table *mmut, */ void kbase_mmu_term(struct kbase_device *kbdev, struct kbase_mmu_table *mmut); +/** + * kbase_mmu_create_ate - Create an address translation entry + * + * @kbdev: Instance of GPU platform device, allocated from the probe method. + * @phy: Physical address of the page to be mapped for GPU access. + * @flags: Bitmask of attributes of the GPU memory region being mapped. + * @level: Page table level for which to build an address translation entry. + * @group_id: The physical memory group in which the page was allocated. + * Valid range is 0..(MEMORY_GROUP_MANAGER_NR_GROUPS-1). + * + * This function creates an address translation entry to encode the physical + * address of a page to be mapped for access by the GPU, along with any extra + * attributes required for the GPU memory region. + * + * Return: An address translation entry, either in LPAE or AArch64 format + * (depending on the driver's configuration). + */ +u64 kbase_mmu_create_ate(struct kbase_device *kbdev, + struct tagged_addr phy, unsigned long flags, int level, int group_id); + int kbase_mmu_insert_pages_no_flush(struct kbase_device *kbdev, struct kbase_mmu_table *mmut, const u64 start_vpfn, struct tagged_addr *phys, size_t nr, - unsigned long flags); + unsigned long flags, int group_id); int kbase_mmu_insert_pages(struct kbase_device *kbdev, struct kbase_mmu_table *mmut, u64 vpfn, struct tagged_addr *phys, size_t nr, - unsigned long flags, int as_nr); + unsigned long flags, int as_nr, int group_id); int kbase_mmu_insert_single_page(struct kbase_context *kctx, u64 vpfn, struct tagged_addr phys, size_t nr, - unsigned long flags); + unsigned long flags, int group_id); int kbase_mmu_teardown_pages(struct kbase_device *kbdev, struct kbase_mmu_table *mmut, u64 vpfn, size_t nr, int as_nr); int kbase_mmu_update_pages(struct kbase_context *kctx, u64 vpfn, struct tagged_addr *phys, size_t nr, - unsigned long flags); + unsigned long flags, int const group_id); /** * @brief Register region and map it on the GPU. @@ -1387,6 +1407,7 @@ void kbase_mmu_interrupt_process(struct kbase_device *kbdev, struct kbase_context *kctx, struct kbase_as *as, struct kbase_fault *fault); + /** * @brief Process a page fault. * diff --git a/mali_kbase/mali_kbase_mem_linux.c b/mali_kbase/mali_kbase_mem_linux.c index d62940c..9e121f0 100644 --- a/mali_kbase/mali_kbase_mem_linux.c +++ b/mali_kbase/mali_kbase_mem_linux.c @@ -44,6 +44,7 @@ #endif /* defined(CONFIG_DMA_SHARED_BUFFER) */ #include <linux/shrinker.h> #include <linux/cache.h> +#include <linux/memory_group_manager.h> #include <mali_kbase.h> #include <mali_kbase_mem_linux.h> @@ -51,33 +52,22 @@ #include <mali_kbase_ioctl.h> #if KERNEL_VERSION(4, 17, 2) > LINUX_VERSION_CODE -/* Enable workaround for ion in v4.17.2 and earlier to avoid the potentially +/* Enable workaround for ion for versions prior to v4.17.2 to avoid the potentially * disruptive warnings which can come if begin_cpu_access and end_cpu_access * methods are not called in pairs. + * * dma_sync_sg_for_* calls will be made directly as a workaround. + * + * Note that some long term maintenance kernel versions (e.g. 4.9.x, 4.14.x) only require this + * workaround on their earlier releases. However it is still safe to use it on such releases, and + * it simplifies the version check. + * * This will also address the case on kernels prior to 4.12, where ion lacks * the cache maintenance in begin_cpu_access and end_cpu_access methods. */ #define KBASE_MEM_ION_SYNC_WORKAROUND #endif -#if (KERNEL_VERSION(4, 17, 0) > LINUX_VERSION_CODE) -#define vm_fault_t int - -static inline vm_fault_t vmf_insert_pfn(struct vm_area_struct *vma, - unsigned long addr, unsigned long pfn) -{ - int err = vm_insert_pfn(vma, addr, pfn); - - if (unlikely(err == -ENOMEM)) - return VM_FAULT_OOM; - if (unlikely(err < 0 && err != -EBUSY)) - return VM_FAULT_SIGBUS; - - return VM_FAULT_NOPAGE; -} -#endif - static int kbase_vmap_phy_pages(struct kbase_context *kctx, struct kbase_va_region *reg, u64 offset_bytes, size_t size, @@ -957,7 +947,8 @@ int kbase_mem_flags_change(struct kbase_context *kctx, u64 gpu_addr, unsigned in ret = kbase_mmu_update_pages(kctx, reg->start_pfn, kbase_get_gpu_phy_pages(reg), kbase_reg_current_backed_size(reg), - new_flags); + new_flags, + reg->gpu_alloc->group_id); if (ret) dev_warn(kctx->kbdev->dev, "Failed to update GPU page tables on flag change: %d\n", @@ -990,23 +981,28 @@ int kbase_mem_do_sync_imported(struct kbase_context *kctx, struct dma_buf *dma_buf; enum dma_data_direction dir = DMA_BIDIRECTIONAL; + lockdep_assert_held(&kctx->reg_lock); + /* We assume that the same physical allocation object is used for both * GPU and CPU for imported buffers. */ WARN_ON(reg->cpu_alloc != reg->gpu_alloc); - /* Currently only handle dma-bufs - * - * Also, attempting to sync with CONFIG_MALI_DMA_BUF_MAP_ON_DEMAND + /* Currently only handle dma-bufs */ + if (reg->gpu_alloc->type != KBASE_MEM_TYPE_IMPORTED_UMM) + return ret; + /* + * Attempting to sync with CONFIG_MALI_DMA_BUF_MAP_ON_DEMAND * enabled can expose us to a Linux Kernel issue between v4.6 and * v4.19. We will not attempt to support cache syncs on dma-bufs that * are mapped on demand (i.e. not on import), even on pre-4.6, neither * on 4.20 or newer kernels, because this makes it difficult for * userspace to know when they can rely on the cache sync. - * Instead, only support syncing when we've mapped dma-bufs on import. + * Instead, only support syncing when we always map dma-bufs on import, + * or if the particular buffer is mapped right now. */ - if (reg->gpu_alloc->type != KBASE_MEM_TYPE_IMPORTED_UMM || - IS_ENABLED(CONFIG_MALI_DMA_BUF_MAP_ON_DEMAND)) + if (IS_ENABLED(CONFIG_MALI_DMA_BUF_MAP_ON_DEMAND) && + !reg->gpu_alloc->imported.umm.current_mapping_usage_count) return ret; dma_buf = reg->gpu_alloc->imported.umm.dma_buf; @@ -1026,6 +1022,10 @@ int kbase_mem_do_sync_imported(struct kbase_context *kctx, ret = 0; } #else + /* Though the below version check could be superfluous depending upon the version condition + * used for enabling KBASE_MEM_ION_SYNC_WORKAROUND, we still keep this check here to allow + * ease of modification for non-ION systems or systems where ION has been patched. + */ #if KERNEL_VERSION(4, 6, 0) > LINUX_VERSION_CODE && !defined(CONFIG_CHROMEOS) dma_buf_end_cpu_access(dma_buf, 0, dma_buf->size, @@ -1172,12 +1172,15 @@ int kbase_mem_umm_map(struct kbase_context *kctx, struct kbase_va_region *reg) { int err; + struct kbase_mem_phy_alloc *alloc; unsigned long gwt_mask = ~0; lockdep_assert_held(&kctx->reg_lock); - reg->gpu_alloc->imported.umm.current_mapping_usage_count++; - if (reg->gpu_alloc->imported.umm.current_mapping_usage_count != 1) { + alloc = reg->gpu_alloc; + + alloc->imported.umm.current_mapping_usage_count++; + if (alloc->imported.umm.current_mapping_usage_count != 1) { if (IS_ENABLED(CONFIG_MALI_DMA_BUF_LEGACY_COMPAT)) { if (!kbase_is_region_invalid_or_free(reg)) { err = kbase_mem_do_sync_imported(kctx, reg, @@ -1203,25 +1206,27 @@ int kbase_mem_umm_map(struct kbase_context *kctx, kbase_get_gpu_phy_pages(reg), kbase_reg_current_backed_size(reg), reg->flags & gwt_mask, - kctx->as_nr); + kctx->as_nr, + alloc->group_id); if (err) goto bad_insert; if (reg->flags & KBASE_REG_IMPORT_PAD && - !WARN_ON(reg->nr_pages < reg->gpu_alloc->nents)) { + !WARN_ON(reg->nr_pages < alloc->nents)) { /* For padded imported dma-buf memory, map the dummy aliasing * page from the end of the dma-buf pages, to the end of the * region using a read only mapping. * - * Assume reg->gpu_alloc->nents is the number of actual pages - * in the dma-buf memory. + * Assume alloc->nents is the number of actual pages in the + * dma-buf memory. */ err = kbase_mmu_insert_single_page(kctx, - reg->start_pfn + reg->gpu_alloc->nents, + reg->start_pfn + alloc->nents, kctx->aliasing_sink_page, - reg->nr_pages - reg->gpu_alloc->nents, + reg->nr_pages - alloc->nents, (reg->flags | KBASE_REG_GPU_RD) & - ~KBASE_REG_GPU_WR); + ~KBASE_REG_GPU_WR, + KBASE_MEM_GROUP_SINK); if (err) goto bad_pad_insert; } @@ -1232,12 +1237,12 @@ bad_pad_insert: kbase_mmu_teardown_pages(kctx->kbdev, &kctx->mmu, reg->start_pfn, - reg->gpu_alloc->nents, + alloc->nents, kctx->as_nr); bad_insert: - kbase_mem_umm_unmap_attachment(kctx, reg->gpu_alloc); + kbase_mem_umm_unmap_attachment(kctx, alloc); bad_map_attachment: - reg->gpu_alloc->imported.umm.current_mapping_usage_count--; + alloc->imported.umm.current_mapping_usage_count--; return err; } @@ -1271,6 +1276,25 @@ void kbase_mem_umm_unmap(struct kbase_context *kctx, kbase_mem_umm_unmap_attachment(kctx, alloc); } +static int get_umm_memory_group_id(struct kbase_context *kctx, + struct dma_buf *dma_buf) +{ + int group_id = BASE_MEM_GROUP_DEFAULT; + + if (kctx->kbdev->mgm_dev->ops.mgm_get_import_memory_id) { + struct memory_group_manager_import_data mgm_import_data; + + mgm_import_data.type = + MEMORY_GROUP_MANAGER_IMPORT_TYPE_DMA_BUF; + mgm_import_data.u.dma_buf = dma_buf; + + group_id = kctx->kbdev->mgm_dev->ops.mgm_get_import_memory_id( + kctx->kbdev->mgm_dev, &mgm_import_data); + } + + return group_id; +} + /** * kbase_mem_from_umm - Import dma-buf memory into kctx * @kctx: Pointer to kbase context to import memory into @@ -1293,6 +1317,7 @@ static struct kbase_va_region *kbase_mem_from_umm(struct kbase_context *kctx, struct dma_buf *dma_buf; struct dma_buf_attachment *dma_attachment; bool shared_zone = false; + int group_id; /* 64-bit address range is the max */ if (*va_pages > (U64_MAX / PAGE_SIZE)) @@ -1357,8 +1382,10 @@ static struct kbase_va_region *kbase_mem_from_umm(struct kbase_context *kctx, return NULL; } + group_id = get_umm_memory_group_id(kctx, dma_buf); + reg->gpu_alloc = kbase_alloc_create(kctx, *va_pages, - KBASE_MEM_TYPE_IMPORTED_UMM, BASE_MEM_GROUP_DEFAULT); + KBASE_MEM_TYPE_IMPORTED_UMM, group_id); if (IS_ERR_OR_NULL(reg->gpu_alloc)) goto no_alloc; @@ -1974,8 +2001,9 @@ int kbase_mem_grow_gpu_mapping(struct kbase_context *kctx, /* Map the new pages into the GPU */ phy_pages = kbase_get_gpu_phy_pages(reg); - ret = kbase_mmu_insert_pages(kctx->kbdev, &kctx->mmu, reg->start_pfn + old_pages, - phy_pages + old_pages, delta, reg->flags, kctx->as_nr); + ret = kbase_mmu_insert_pages(kctx->kbdev, &kctx->mmu, + reg->start_pfn + old_pages, phy_pages + old_pages, delta, + reg->flags, kctx->as_nr, reg->gpu_alloc->group_id); return ret; } @@ -2230,6 +2258,7 @@ static vm_fault_t kbase_cpu_vm_fault(struct vm_fault *vmf) size_t nents; struct tagged_addr *pages; vm_fault_t ret = VM_FAULT_SIGBUS; + struct memory_group_manager_device *mgm_dev; KBASE_DEBUG_ASSERT(map); KBASE_DEBUG_ASSERT(map->count > 0); @@ -2258,15 +2287,9 @@ static vm_fault_t kbase_cpu_vm_fault(struct vm_fault *vmf) if (fault_pgoff >= nents) goto exit; - /* Apparently when job dumping is enabled, there are accesses to the GPU - * memory (JIT) that has been marked as reclaimable. Disallowing that - * causes job dumping to fail. - */ -#if !defined(CONFIG_MALI_JOB_DUMP) && !defined(CONFIG_MALI_VECTOR_DUMP) /* Fault on access to DONT_NEED regions */ if (map->alloc->reg && (map->alloc->reg->flags & KBASE_REG_DONT_NEED)) goto exit; -#endif /* We are inserting all valid pages from the start of CPU mapping and * not from the fault location (the mmap handler was previously doing @@ -2274,9 +2297,13 @@ static vm_fault_t kbase_cpu_vm_fault(struct vm_fault *vmf) */ i = map_start_pgoff; addr = (pgoff_t)(vma->vm_start >> PAGE_SHIFT); + mgm_dev = map->kctx->kbdev->mgm_dev; while (i < nents && (addr < vma->vm_end >> PAGE_SHIFT)) { - ret = vmf_insert_pfn(vma, addr << PAGE_SHIFT, - PFN_DOWN(as_phys_addr_t(pages[i]))); + + ret = mgm_dev->ops.mgm_vmf_insert_pfn_prot(mgm_dev, + map->alloc->group_id, vma, addr << PAGE_SHIFT, + PFN_DOWN(as_phys_addr_t(pages[i])), vma->vm_page_prot); + if (ret != VM_FAULT_NOPAGE) goto exit; @@ -2343,6 +2370,7 @@ static int kbase_cpu_mmap(struct kbase_context *kctx, if (!aliased) { err = -EINVAL; + kfree(map); goto out; } } @@ -2389,7 +2417,28 @@ static int kbase_cpu_mmap(struct kbase_context *kctx, return err; } -static int kbase_mmu_dump_mmap(struct kbase_context *kctx, struct vm_area_struct *vma, struct kbase_va_region **const reg, void **const kmap_addr) +#ifdef CONFIG_MALI_VECTOR_DUMP +static void kbase_free_unused_jit_allocations(struct kbase_context *kctx) +{ + /* Free all cached/unused JIT allocations as their contents are not + * really needed for the replay. The GPU writes to them would already + * have been captured through the GWT mechanism. + * This considerably reduces the size of mmu-snapshot-file and it also + * helps avoid segmentation fault issue during vector dumping of + * complex contents when the unused JIT allocations are accessed to + * dump their contents (as they appear in the page tables snapshot) + * but they got freed by the shrinker under low memory scenarios + * (which do occur with complex contents). + */ + while (kbase_jit_evict(kctx)) + ; +} +#endif + +static int kbase_mmu_dump_mmap(struct kbase_context *kctx, + struct vm_area_struct *vma, + struct kbase_va_region **const reg, + void **const kmap_addr) { struct kbase_va_region *new_reg; void *kaddr; @@ -2401,6 +2450,10 @@ static int kbase_mmu_dump_mmap(struct kbase_context *kctx, struct vm_area_struct size = (vma->vm_end - vma->vm_start); nr_pages = size >> PAGE_SHIFT; +#ifdef CONFIG_MALI_VECTOR_DUMP + kbase_free_unused_jit_allocations(kctx); +#endif + kaddr = kbase_mmu_dump(kctx, nr_pages); if (!kaddr) { diff --git a/mali_kbase/mali_kbase_mem_profile_debugfs.c b/mali_kbase/mali_kbase_mem_profile_debugfs.c index a59f572..5d38ed2 100644 --- a/mali_kbase/mali_kbase_mem_profile_debugfs.c +++ b/mali_kbase/mali_kbase_mem_profile_debugfs.c @@ -58,6 +58,7 @@ static int kbasep_mem_profile_debugfs_open(struct inode *in, struct file *file) } static const struct file_operations kbasep_mem_profile_debugfs_fops = { + .owner = THIS_MODULE, .open = kbasep_mem_profile_debugfs_open, .read = seq_read, .llseek = seq_lseek, diff --git a/mali_kbase/mali_kbase_mem_profile_debugfs_buf_size.h b/mali_kbase/mali_kbase_mem_profile_debugfs_buf_size.h index 3c76071..81e2886 100644 --- a/mali_kbase/mali_kbase_mem_profile_debugfs_buf_size.h +++ b/mali_kbase/mali_kbase_mem_profile_debugfs_buf_size.h @@ -1,6 +1,6 @@ /* * - * (C) COPYRIGHT 2014, 2018 ARM Limited. All rights reserved. + * (C) COPYRIGHT 2014, 2018-2019 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the * GNU General Public License version 2 as published by the Free Software @@ -33,7 +33,7 @@ * @see @ref CCTXP_HIST_BUF_SIZE_MAX_LENGTH_REPORT */ #define KBASE_MEM_PROFILE_MAX_BUF_SIZE \ - ((size_t) (64 + ((80 + (56 * 64)) * 35) + 56)) + ((size_t) (64 + ((80 + (56 * 64)) * 50) + 56)) #endif /*_KBASE_MEM_PROFILE_DEBUGFS_BUF_SIZE_H_*/ diff --git a/mali_kbase/mali_kbase_mmu.c b/mali_kbase/mali_kbase_mmu.c index b1bd5c4..a8cd5ac 100644 --- a/mali_kbase/mali_kbase_mmu.c +++ b/mali_kbase/mali_kbase_mmu.c @@ -44,6 +44,7 @@ #include <mali_kbase_hwaccess_jm.h> #include <mali_kbase_hwaccess_time.h> #include <mali_kbase_mem.h> +#include <mali_kbase_reset_gpu.h> #define KBASE_MMU_PAGE_ENTRIES 512 @@ -116,7 +117,7 @@ static void kbase_mmu_report_fault_and_kill(struct kbase_context *kctx, static int kbase_mmu_update_pages_no_flush(struct kbase_context *kctx, u64 vpfn, struct tagged_addr *phys, size_t nr, - unsigned long flags); + unsigned long flags, int group_id); /** * reg_grow_calc_extra_pages() - Calculate the number of backed pages to add to @@ -274,7 +275,7 @@ static void kbase_gpu_mmu_handle_write_fault(struct kbase_context *kctx, /* Now make this faulting page writable to GPU. */ ret = kbase_mmu_update_pages_no_flush(kctx, fault_pfn, &kbase_get_gpu_phy_pages(region)[pfn_offset], - 1, region->flags); + 1, region->flags, region->gpu_alloc->group_id); /* flush L2 and unlock the VA (resumes the MMU) */ if (kbase_hw_has_issue(kbdev, BASE_HW_ISSUE_6367)) @@ -760,9 +761,9 @@ page_fault_retry: * us to unlock the MMU as we see fit. */ err = kbase_mmu_insert_pages_no_flush(kbdev, &kctx->mmu, - region->start_pfn + pfn_offset, - &kbase_get_gpu_phy_pages(region)[pfn_offset], - new_pages, region->flags); + region->start_pfn + pfn_offset, + &kbase_get_gpu_phy_pages(region)[pfn_offset], + new_pages, region->flags, region->gpu_alloc->group_id); if (err) { kbase_free_phy_pages_helper(region->gpu_alloc, new_pages); if (region->gpu_alloc != region->cpu_alloc) @@ -989,7 +990,7 @@ static int mmu_get_next_pgd(struct kbase_device *kbdev, static int mmu_get_pgd_at_level(struct kbase_device *kbdev, struct kbase_mmu_table *mmut, u64 vpfn, - unsigned int level, + int level, phys_addr_t *out_pgd) { phys_addr_t pgd; @@ -1045,7 +1046,7 @@ static void mmu_insert_pages_failure_recovery(struct kbase_device *kbdev, unsigned int count = KBASE_MMU_PAGE_ENTRIES - idx; unsigned int pcount = 0; unsigned int left = to_vpfn - vpfn; - unsigned int level; + int level; u64 *page; if (count > left) @@ -1098,7 +1099,7 @@ next: */ int kbase_mmu_insert_single_page(struct kbase_context *kctx, u64 vpfn, struct tagged_addr phys, size_t nr, - unsigned long flags) + unsigned long flags, int const group_id) { phys_addr_t pgd; u64 *pgd_page; @@ -1109,13 +1110,13 @@ int kbase_mmu_insert_single_page(struct kbase_context *kctx, u64 vpfn, size_t recover_count = 0; size_t remain = nr; int err; - struct kbase_mmu_mode const *mmu_mode; + struct kbase_device *kbdev; KBASE_DEBUG_ASSERT(NULL != kctx); /* 64-bit address range is the max */ KBASE_DEBUG_ASSERT(vpfn <= (U64_MAX / PAGE_SIZE)); - mmu_mode = kctx->kbdev->mmu_mode; + kbdev = kctx->kbdev; /* Early out if there is nothing to do */ if (nr == 0) @@ -1140,7 +1141,7 @@ int kbase_mmu_insert_single_page(struct kbase_context *kctx, u64 vpfn, * 256 pages at once (on average). Do we really care? */ do { - err = mmu_get_bottom_pgd(kctx->kbdev, &kctx->mmu, + err = mmu_get_bottom_pgd(kbdev, &kctx->mmu, vpfn, &pgd); if (err != -ENOMEM) break; @@ -1149,17 +1150,17 @@ int kbase_mmu_insert_single_page(struct kbase_context *kctx, u64 vpfn, */ mutex_unlock(&kctx->mmu.mmu_lock); err = kbase_mem_pool_grow( - &kctx->kbdev->mem_pools.small[ + &kbdev->mem_pools.small[ kctx->mmu.group_id], MIDGARD_MMU_BOTTOMLEVEL); mutex_lock(&kctx->mmu.mmu_lock); } while (!err); if (err) { - dev_warn(kctx->kbdev->dev, "kbase_mmu_insert_pages: mmu_get_bottom_pgd failure\n"); + dev_warn(kbdev->dev, "kbase_mmu_insert_pages: mmu_get_bottom_pgd failure\n"); if (recover_required) { /* Invalidate the pages we have partially * completed */ - mmu_insert_pages_failure_recovery(kctx->kbdev, + mmu_insert_pages_failure_recovery(kbdev, &kctx->mmu, recover_vpfn, recover_vpfn + recover_count); @@ -1170,11 +1171,11 @@ int kbase_mmu_insert_single_page(struct kbase_context *kctx, u64 vpfn, p = pfn_to_page(PFN_DOWN(pgd)); pgd_page = kmap(p); if (!pgd_page) { - dev_warn(kctx->kbdev->dev, "kbase_mmu_insert_pages: kmap failure\n"); + dev_warn(kbdev->dev, "kbase_mmu_insert_pages: kmap failure\n"); if (recover_required) { /* Invalidate the pages we have partially * completed */ - mmu_insert_pages_failure_recovery(kctx->kbdev, + mmu_insert_pages_failure_recovery(kbdev, &kctx->mmu, recover_vpfn, recover_vpfn + recover_count); @@ -1189,15 +1190,14 @@ int kbase_mmu_insert_single_page(struct kbase_context *kctx, u64 vpfn, /* Fail if the current page is a valid ATE entry */ KBASE_DEBUG_ASSERT(0 == (pgd_page[ofs] & 1UL)); - mmu_mode->entry_set_ate(&pgd_page[ofs], - phys, flags, - MIDGARD_MMU_BOTTOMLEVEL); + pgd_page[ofs] = kbase_mmu_create_ate(kbdev, + phys, flags, MIDGARD_MMU_BOTTOMLEVEL, group_id); } vpfn += count; remain -= count; - kbase_mmu_sync_pgd(kctx->kbdev, + kbase_mmu_sync_pgd(kbdev, kbase_dma_addr(p) + (index * sizeof(u64)), count * sizeof(u64)); @@ -1239,11 +1239,23 @@ static inline void cleanup_empty_pte(struct kbase_device *kbdev, atomic_sub(1, &kbdev->memdev.used_pages); } +u64 kbase_mmu_create_ate(struct kbase_device *const kbdev, + struct tagged_addr const phy, unsigned long const flags, + int const level, int const group_id) +{ + u64 entry; + + kbdev->mmu_mode->entry_set_ate(&entry, phy, flags, level); + return kbdev->mgm_dev->ops.mgm_update_gpu_pte(kbdev->mgm_dev, + group_id, level, entry); +} + int kbase_mmu_insert_pages_no_flush(struct kbase_device *kbdev, struct kbase_mmu_table *mmut, const u64 start_vpfn, struct tagged_addr *phys, size_t nr, - unsigned long flags) + unsigned long flags, + int const group_id) { phys_addr_t pgd; u64 *pgd_page; @@ -1269,7 +1281,7 @@ int kbase_mmu_insert_pages_no_flush(struct kbase_device *kbdev, unsigned int vindex = insert_vpfn & 0x1FF; unsigned int count = KBASE_MMU_PAGE_ENTRIES - vindex; struct page *p; - unsigned int cur_level; + int cur_level; if (count > remain) count = remain; @@ -1329,13 +1341,13 @@ int kbase_mmu_insert_pages_no_flush(struct kbase_device *kbdev, } if (cur_level == MIDGARD_MMU_LEVEL(2)) { - unsigned int level_index = (insert_vpfn >> 9) & 0x1FF; + int level_index = (insert_vpfn >> 9) & 0x1FF; u64 *target = &pgd_page[level_index]; if (mmu_mode->pte_is_valid(*target, cur_level)) cleanup_empty_pte(kbdev, mmut, target); - mmu_mode->entry_set_ate(target, *phys, flags, - cur_level); + *target = kbase_mmu_create_ate(kbdev, *phys, flags, + cur_level, group_id); } else { for (i = 0; i < count; i++) { unsigned int ofs = vindex + i; @@ -1350,8 +1362,8 @@ int kbase_mmu_insert_pages_no_flush(struct kbase_device *kbdev, */ WARN_ON((*target & 1UL) != 0); - kbdev->mmu_mode->entry_set_ate(target, - phys[i], flags, cur_level); + *target = kbase_mmu_create_ate(kbdev, + phys[i], flags, cur_level, group_id); } } @@ -1380,12 +1392,12 @@ fail_unlock: int kbase_mmu_insert_pages(struct kbase_device *kbdev, struct kbase_mmu_table *mmut, u64 vpfn, struct tagged_addr *phys, size_t nr, - unsigned long flags, int as_nr) + unsigned long flags, int as_nr, int const group_id) { int err; err = kbase_mmu_insert_pages_no_flush(kbdev, mmut, vpfn, - phys, nr, flags); + phys, nr, flags, group_id); if (mmut->kctx) kbase_mmu_flush_invalidate(mmut->kctx, vpfn, nr, false); @@ -1444,7 +1456,7 @@ static void kbase_mmu_flush_invalidate_noretain(struct kbase_context *kctx, * request will pick it up. */ if ((!err) && sync && - kbase_hw_has_issue(kctx->kbdev, BASE_HW_ISSUE_6367)) + kbase_hw_has_issue(kbdev, BASE_HW_ISSUE_6367)) atomic_set(&kctx->drain_pending, 1); #endif /* !CONFIG_MALI_NO_MALI */ } @@ -1624,7 +1636,7 @@ int kbase_mmu_teardown_pages(struct kbase_device *kbdev, unsigned int index = vpfn & 0x1FF; unsigned int count = KBASE_MMU_PAGE_ENTRIES - index; unsigned int pcount; - unsigned int level; + int level; u64 *page; if (count > nr) @@ -1740,15 +1752,17 @@ KBASE_EXPORT_TEST_API(kbase_mmu_teardown_pages); * current mappings * @nr: Number of pages to update * @flags: Flags + * @group_id: The physical memory group in which the page was allocated. + * Valid range is 0..(MEMORY_GROUP_MANAGER_NR_GROUPS-1). */ static int kbase_mmu_update_pages_no_flush(struct kbase_context *kctx, u64 vpfn, struct tagged_addr *phys, size_t nr, - unsigned long flags) + unsigned long flags, int const group_id) { phys_addr_t pgd; u64 *pgd_page; - struct kbase_mmu_mode const *mmu_mode; int err; + struct kbase_device *kbdev; KBASE_DEBUG_ASSERT(NULL != kctx); KBASE_DEBUG_ASSERT(vpfn <= (U64_MAX / PAGE_SIZE)); @@ -1759,7 +1773,7 @@ static int kbase_mmu_update_pages_no_flush(struct kbase_context *kctx, u64 vpfn, mutex_lock(&kctx->mmu.mmu_lock); - mmu_mode = kctx->kbdev->mmu_mode; + kbdev = kctx->kbdev; while (nr) { unsigned int i; @@ -1771,7 +1785,7 @@ static int kbase_mmu_update_pages_no_flush(struct kbase_context *kctx, u64 vpfn, count = nr; do { - err = mmu_get_bottom_pgd(kctx->kbdev, &kctx->mmu, + err = mmu_get_bottom_pgd(kbdev, &kctx->mmu, vpfn, &pgd); if (err != -ENOMEM) break; @@ -1780,13 +1794,13 @@ static int kbase_mmu_update_pages_no_flush(struct kbase_context *kctx, u64 vpfn, */ mutex_unlock(&kctx->mmu.mmu_lock); err = kbase_mem_pool_grow( - &kctx->kbdev->mem_pools.small[ + &kbdev->mem_pools.small[ kctx->mmu.group_id], MIDGARD_MMU_BOTTOMLEVEL); mutex_lock(&kctx->mmu.mmu_lock); } while (!err); if (err) { - dev_warn(kctx->kbdev->dev, + dev_warn(kbdev->dev, "mmu_get_bottom_pgd failure\n"); goto fail_unlock; } @@ -1794,20 +1808,21 @@ static int kbase_mmu_update_pages_no_flush(struct kbase_context *kctx, u64 vpfn, p = pfn_to_page(PFN_DOWN(pgd)); pgd_page = kmap(p); if (!pgd_page) { - dev_warn(kctx->kbdev->dev, "kmap failure\n"); + dev_warn(kbdev->dev, "kmap failure\n"); err = -ENOMEM; goto fail_unlock; } for (i = 0; i < count; i++) - mmu_mode->entry_set_ate(&pgd_page[index + i], phys[i], - flags, MIDGARD_MMU_BOTTOMLEVEL); + pgd_page[index + i] = kbase_mmu_create_ate(kbdev, + phys[i], flags, MIDGARD_MMU_BOTTOMLEVEL, + group_id); phys += count; vpfn += count; nr -= count; - kbase_mmu_sync_pgd(kctx->kbdev, + kbase_mmu_sync_pgd(kbdev, kbase_dma_addr(p) + (index * sizeof(u64)), count * sizeof(u64)); @@ -1824,11 +1839,12 @@ fail_unlock: int kbase_mmu_update_pages(struct kbase_context *kctx, u64 vpfn, struct tagged_addr *phys, size_t nr, - unsigned long flags) + unsigned long flags, int const group_id) { int err; - err = kbase_mmu_update_pages_no_flush(kctx, vpfn, phys, nr, flags); + err = kbase_mmu_update_pages_no_flush(kctx, vpfn, phys, nr, flags, + group_id); kbase_mmu_flush_invalidate(kctx, vpfn, nr, true); return err; } @@ -1951,16 +1967,18 @@ static size_t kbasep_mmu_dump_level(struct kbase_context *kctx, phys_addr_t pgd, int i; size_t size = KBASE_MMU_PAGE_ENTRIES * sizeof(u64) + sizeof(u64); size_t dump_size; + struct kbase_device *kbdev; struct kbase_mmu_mode const *mmu_mode; KBASE_DEBUG_ASSERT(NULL != kctx); lockdep_assert_held(&kctx->mmu.mmu_lock); - mmu_mode = kctx->kbdev->mmu_mode; + kbdev = kctx->kbdev; + mmu_mode = kbdev->mmu_mode; pgd_page = kmap(pfn_to_page(PFN_DOWN(pgd))); if (!pgd_page) { - dev_warn(kctx->kbdev->dev, "kbasep_mmu_dump_level: kmap failure\n"); + dev_warn(kbdev->dev, "%s: kmap failure\n", __func__); return 0; } @@ -2346,6 +2364,7 @@ static const char *access_type_name(struct kbase_device *kbdev, } } + /** * The caller must ensure it's retained the ctx to prevent it from being scheduled out whilst it's being worked on. */ @@ -2413,6 +2432,7 @@ static void kbase_mmu_report_fault_and_kill(struct kbase_context *kctx, /* Kill any running jobs from the context. Submit is disallowed, so no more jobs from this * context can appear in the job slots from this point on */ kbase_backend_jm_kill_jobs_from_kctx(kctx); + /* AS transaction begin */ mutex_lock(&kbdev->mmu_hw_mutex); if (kbase_hw_has_issue(kbdev, BASE_HW_ISSUE_8245)) { @@ -2429,6 +2449,8 @@ static void kbase_mmu_report_fault_and_kill(struct kbase_context *kctx, spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags); mutex_unlock(&kbdev->mmu_hw_mutex); + + /* AS transaction end */ /* Clear down the fault */ kbase_mmu_hw_clear_fault(kbdev, as, diff --git a/mali_kbase/mali_kbase_mmu_mode_aarch64.c b/mali_kbase/mali_kbase_mmu_mode_aarch64.c index 38ca456..7b9cc0c 100644 --- a/mali_kbase/mali_kbase_mmu_mode_aarch64.c +++ b/mali_kbase/mali_kbase_mmu_mode_aarch64.c @@ -1,6 +1,6 @@ /* * - * (C) COPYRIGHT 2010-2014, 2016-2018 ARM Limited. All rights reserved. + * (C) COPYRIGHT 2010-2014, 2016-2019 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the * GNU General Public License version 2 as published by the Free Software @@ -130,7 +130,7 @@ static phys_addr_t pte_to_phy_addr(u64 entry) return entry & ~0xFFF; } -static int ate_is_valid(u64 ate, unsigned int level) +static int ate_is_valid(u64 ate, int const level) { if (level == MIDGARD_MMU_BOTTOMLEVEL) return ((ate & ENTRY_TYPE_MASK) == ENTRY_IS_ATE_L3); @@ -138,7 +138,7 @@ static int ate_is_valid(u64 ate, unsigned int level) return ((ate & ENTRY_TYPE_MASK) == ENTRY_IS_ATE_L02); } -static int pte_is_valid(u64 pte, unsigned int level) +static int pte_is_valid(u64 pte, int const level) { /* PTEs cannot exist at the bottom level */ if (level == MIDGARD_MMU_BOTTOMLEVEL) @@ -181,7 +181,7 @@ static u64 get_mmu_flags(unsigned long flags) static void entry_set_ate(u64 *entry, struct tagged_addr phy, unsigned long flags, - unsigned int level) + int const level) { if (level == MIDGARD_MMU_BOTTOMLEVEL) page_table_entry_set(entry, as_phys_addr_t(phy) | diff --git a/mali_kbase/mali_kbase_mmu_mode_lpae.c b/mali_kbase/mali_kbase_mmu_mode_lpae.c index f6bdf91..7ec90cf 100644 --- a/mali_kbase/mali_kbase_mmu_mode_lpae.c +++ b/mali_kbase/mali_kbase_mmu_mode_lpae.c @@ -1,6 +1,6 @@ /* * - * (C) COPYRIGHT 2010-2018 ARM Limited. All rights reserved. + * (C) COPYRIGHT 2010-2019 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the * GNU General Public License version 2 as published by the Free Software @@ -130,12 +130,12 @@ static phys_addr_t pte_to_phy_addr(u64 entry) return entry & ~0xFFF; } -static int ate_is_valid(u64 ate, unsigned int level) +static int ate_is_valid(u64 ate, int const level) { return ((ate & ENTRY_TYPE_MASK) == ENTRY_IS_ATE); } -static int pte_is_valid(u64 pte, unsigned int level) +static int pte_is_valid(u64 pte, int const level) { return ((pte & ENTRY_TYPE_MASK) == ENTRY_IS_PTE); } @@ -179,7 +179,7 @@ static u64 get_mmu_flags(unsigned long flags) static void entry_set_ate(u64 *entry, struct tagged_addr phy, unsigned long flags, - unsigned int level) + int const level) { page_table_entry_set(entry, as_phys_addr_t(phy) | get_mmu_flags(flags) | ENTRY_IS_ATE); diff --git a/mali_kbase/mali_kbase_native_mgm.c b/mali_kbase/mali_kbase_native_mgm.c index 8c4a7fd..022c056 100644 --- a/mali_kbase/mali_kbase_native_mgm.c +++ b/mali_kbase/mali_kbase_native_mgm.c @@ -21,17 +21,41 @@ */ #include <linux/gfp.h> +#include <linux/mm.h> #include <linux/memory_group_manager.h> #include <mali_kbase.h> #include <mali_kbase_native_mgm.h> +#if (KERNEL_VERSION(4, 17, 0) > LINUX_VERSION_CODE) +static inline vm_fault_t vmf_insert_pfn(struct vm_area_struct *vma, + unsigned long addr, unsigned long pfn) +{ + int err = vm_insert_pfn(vma, addr, pfn); + + if (unlikely(err == -ENOMEM)) + return VM_FAULT_OOM; + if (unlikely(err < 0 && err != -EBUSY)) + return VM_FAULT_SIGBUS; + + return VM_FAULT_NOPAGE; +} +#endif + +#if (KERNEL_VERSION(4, 20, 0) > LINUX_VERSION_CODE) +static inline vm_fault_t vmf_insert_pfn_prot(struct vm_area_struct *vma, + unsigned long addr, unsigned long pfn, pgprot_t pgprot) +{ + if (pgprot_val(pgprot) != pgprot_val(vma->vm_page_prot)) + return VM_FAULT_SIGBUS; + + return vmf_insert_pfn(vma, addr, pfn); +} +#endif + /** * kbase_native_mgm_alloc - Native physical memory allocation method * - * Delegates all memory allocation requests to the kernel's alloc_pages - * function. - * * @mgm_dev: The memory group manager the request is being made through. * @group_id: A physical memory group ID, which must be valid but is not used. * Its valid range is 0 .. MEMORY_GROUP_MANAGER_NR_GROUPS-1. @@ -39,15 +63,30 @@ * @order: Page order for physical page size (order=0 means 4 KiB, * order=9 means 2 MiB). * + * Delegates all memory allocation requests to the kernel's alloc_pages + * function. + * * Return: Pointer to allocated page, or NULL if allocation failed. */ static struct page *kbase_native_mgm_alloc( struct memory_group_manager_device *mgm_dev, int group_id, gfp_t gfp_mask, unsigned int order) { + /* + * Check that the base and the mgm defines, from separate header files, + * for the max number of memory groups are compatible. + */ + BUILD_BUG_ON(BASE_MEM_GROUP_COUNT != MEMORY_GROUP_MANAGER_NR_GROUPS); + /* + * Check that the mask used for storing the memory group ID is big + * enough for the largest possible memory group ID. + */ + BUILD_BUG_ON((BASEP_CONTEXT_MMU_GROUP_ID_MASK + >> BASEP_CONTEXT_MMU_GROUP_ID_SHIFT) + < (BASE_MEM_GROUP_COUNT - 1)); + CSTD_UNUSED(mgm_dev); - WARN_ON(group_id < 0); - WARN_ON(group_id >= MEMORY_GROUP_MANAGER_NR_GROUPS); + CSTD_UNUSED(group_id); return alloc_pages(gfp_mask, order); } @@ -55,31 +94,86 @@ static struct page *kbase_native_mgm_alloc( /** * kbase_native_mgm_free - Native physical memory freeing method * - * Delegates all memory freeing requests to the kernel's __free_pages function. - * * @mgm_dev: The memory group manager the request is being made through. * @group_id: A physical memory group ID, which must be valid but is not used. * Its valid range is 0 .. MEMORY_GROUP_MANAGER_NR_GROUPS-1. * @page: Address of the struct associated with a page of physical - * memory that was allocated by calling the alloc method of - * the same memory pool with the same argument values. + * memory that was allocated by calling kbase_native_mgm_alloc + * with the same argument values. * @order: Page order for physical page size (order=0 means 4 KiB, * order=9 means 2 MiB). + * + * Delegates all memory freeing requests to the kernel's __free_pages function. */ static void kbase_native_mgm_free(struct memory_group_manager_device *mgm_dev, int group_id, struct page *page, unsigned int order) { CSTD_UNUSED(mgm_dev); - WARN_ON(group_id < 0); - WARN_ON(group_id >= MEMORY_GROUP_MANAGER_NR_GROUPS); + CSTD_UNUSED(group_id); __free_pages(page, order); } +/** + * kbase_native_mgm_vmf_insert_pfn_prot - Native method to map a page on the CPU + * + * @mgm_dev: The memory group manager the request is being made through. + * @group_id: A physical memory group ID, which must be valid but is not used. + * Its valid range is 0 .. MEMORY_GROUP_MANAGER_NR_GROUPS-1. + * @vma: The virtual memory area to insert the page into. + * @addr: An address contained in @vma to assign to the inserted page. + * @pfn: The kernel Page Frame Number to insert at @addr in @vma. + * @pgprot: Protection flags for the inserted page. + * + * Called from a CPU virtual memory page fault handler. Delegates all memory + * mapping requests to the kernel's vmf_insert_pfn_prot function. + * + * Return: Type of fault that occurred or VM_FAULT_NOPAGE if the page table + * entry was successfully installed. + */ +static vm_fault_t kbase_native_mgm_vmf_insert_pfn_prot( + struct memory_group_manager_device *mgm_dev, int group_id, + struct vm_area_struct *vma, unsigned long addr, + unsigned long pfn, pgprot_t pgprot) +{ + CSTD_UNUSED(mgm_dev); + CSTD_UNUSED(group_id); + + return vmf_insert_pfn_prot(vma, addr, pfn, pgprot); +} + +/** + * kbase_native_mgm_update_gpu_pte - Native method to modify a GPU page table + * entry + * + * @mgm_dev: The memory group manager the request is being made through. + * @group_id: A physical memory group ID, which must be valid but is not used. + * Its valid range is 0 .. MEMORY_GROUP_MANAGER_NR_GROUPS-1. + * @mmu_level: The level of the MMU page table where the page is getting mapped. + * @pte: The prepared page table entry. + * + * This function simply returns the @pte without modification. + * + * Return: A GPU page table entry to be stored in a page table. + */ +static u64 +kbase_native_mgm_update_gpu_pte(struct memory_group_manager_device *mgm_dev, + int group_id, int mmu_level, u64 pte) +{ + CSTD_UNUSED(mgm_dev); + CSTD_UNUSED(group_id); + CSTD_UNUSED(mmu_level); + + return pte; +} + struct memory_group_manager_device kbase_native_mgm_dev = { .ops = { .mgm_alloc_page = kbase_native_mgm_alloc, - .mgm_free_page = kbase_native_mgm_free + .mgm_free_page = kbase_native_mgm_free, + .mgm_get_import_memory_id = NULL, + .mgm_vmf_insert_pfn_prot = kbase_native_mgm_vmf_insert_pfn_prot, + .mgm_update_gpu_pte = kbase_native_mgm_update_gpu_pte, }, .data = NULL }; diff --git a/mali_kbase/mali_kbase_regs_history_debugfs.c b/mali_kbase/mali_kbase_regs_history_debugfs.c index 763740e..53d9427 100644 --- a/mali_kbase/mali_kbase_regs_history_debugfs.c +++ b/mali_kbase/mali_kbase_regs_history_debugfs.c @@ -1,6 +1,6 @@ /* * - * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. + * (C) COPYRIGHT 2016, 2019 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the * GNU General Public License version 2 as published by the Free Software @@ -111,6 +111,7 @@ static int regs_history_open(struct inode *in, struct file *file) static const struct file_operations regs_history_fops = { + .owner = THIS_MODULE, .open = ®s_history_open, .read = seq_read, .llseek = seq_lseek, diff --git a/mali_kbase/mali_kbase_replay.c b/mali_kbase/mali_kbase_replay.c deleted file mode 100644 index 92101fe..0000000 --- a/mali_kbase/mali_kbase_replay.c +++ /dev/null @@ -1,1156 +0,0 @@ -/* - * - * (C) COPYRIGHT 2014-2017 ARM Limited. All rights reserved. - * - * This program is free software and is provided to you under the terms of the - * GNU General Public License version 2 as published by the Free Software - * Foundation, and any use by you of this program is subject to the terms - * of such GNU licence. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you can access it online at - * http://www.gnu.org/licenses/gpl-2.0.html. - * - * SPDX-License-Identifier: GPL-2.0 - * - */ - -/** - * @file mali_kbase_replay.c - * Replay soft job handlers - */ - -#include <linux/dma-mapping.h> -#include <mali_kbase_config.h> -#include <mali_kbase.h> -#include <mali_kbase_mem.h> -#include <mali_kbase_mem_linux.h> - -#define JOB_NOT_STARTED 0 -#define JOB_TYPE_NULL (1) -#define JOB_TYPE_VERTEX (5) -#define JOB_TYPE_TILER (7) -#define JOB_TYPE_FUSED (8) -#define JOB_TYPE_FRAGMENT (9) - -#define JOB_HEADER_32_FBD_OFFSET (31*4) -#define JOB_HEADER_64_FBD_OFFSET (44*4) - -#define FBD_POINTER_MASK (~0x3f) - -#define SFBD_TILER_OFFSET (48*4) - -#define MFBD_TILER_OFFSET (14*4) - -#define FBD_HIERARCHY_WEIGHTS 8 -#define FBD_HIERARCHY_MASK_MASK 0x1fff - -#define FBD_TYPE 1 - -#define HIERARCHY_WEIGHTS 13 - -#define JOB_HEADER_ID_MAX 0xffff - -#define JOB_SOURCE_ID(status) (((status) >> 16) & 0xFFFF) -#define JOB_POLYGON_LIST (0x03) - -struct fragment_job { - struct job_descriptor_header header; - - u32 x[2]; - union { - u64 _64; - u32 _32; - } fragment_fbd; -}; - -static void dump_job_head(struct kbase_context *kctx, char *head_str, - struct job_descriptor_header *job) -{ -#ifdef CONFIG_MALI_DEBUG - dev_dbg(kctx->kbdev->dev, "%s\n", head_str); - dev_dbg(kctx->kbdev->dev, - "addr = %p\n" - "exception_status = %x (Source ID: 0x%x Access: 0x%x Exception: 0x%x)\n" - "first_incomplete_task = %x\n" - "fault_pointer = %llx\n" - "job_descriptor_size = %x\n" - "job_type = %x\n" - "job_barrier = %x\n" - "_reserved_01 = %x\n" - "_reserved_02 = %x\n" - "_reserved_03 = %x\n" - "_reserved_04/05 = %x,%x\n" - "job_index = %x\n" - "dependencies = %x,%x\n", - job, job->exception_status, - JOB_SOURCE_ID(job->exception_status), - (job->exception_status >> 8) & 0x3, - job->exception_status & 0xFF, - job->first_incomplete_task, - job->fault_pointer, job->job_descriptor_size, - job->job_type, job->job_barrier, job->_reserved_01, - job->_reserved_02, job->_reserved_03, - job->_reserved_04, job->_reserved_05, - job->job_index, - job->job_dependency_index_1, - job->job_dependency_index_2); - - if (job->job_descriptor_size) - dev_dbg(kctx->kbdev->dev, "next = %llx\n", - job->next_job._64); - else - dev_dbg(kctx->kbdev->dev, "next = %x\n", - job->next_job._32); -#endif -} - -static int kbasep_replay_reset_sfbd(struct kbase_context *kctx, - u64 fbd_address, u64 tiler_heap_free, - u16 hierarchy_mask, u32 default_weight) -{ - struct { - u32 padding_1[1]; - u32 flags; - u64 padding_2[2]; - u64 heap_free_address; - u32 padding[8]; - u32 weights[FBD_HIERARCHY_WEIGHTS]; - } *fbd_tiler; - struct kbase_vmap_struct map; - - dev_dbg(kctx->kbdev->dev, "fbd_address: %llx\n", fbd_address); - - fbd_tiler = kbase_vmap(kctx, fbd_address + SFBD_TILER_OFFSET, - sizeof(*fbd_tiler), &map); - if (!fbd_tiler) { - dev_err(kctx->kbdev->dev, "kbasep_replay_reset_fbd: failed to map fbd\n"); - return -EINVAL; - } - -#ifdef CONFIG_MALI_DEBUG - dev_dbg(kctx->kbdev->dev, - "FBD tiler:\n" - "flags = %x\n" - "heap_free_address = %llx\n", - fbd_tiler->flags, fbd_tiler->heap_free_address); -#endif - if (hierarchy_mask) { - u32 weights[HIERARCHY_WEIGHTS]; - u16 old_hierarchy_mask = fbd_tiler->flags & - FBD_HIERARCHY_MASK_MASK; - int i, j = 0; - - for (i = 0; i < HIERARCHY_WEIGHTS; i++) { - if (old_hierarchy_mask & (1 << i)) { - KBASE_DEBUG_ASSERT(j < FBD_HIERARCHY_WEIGHTS); - weights[i] = fbd_tiler->weights[j++]; - } else { - weights[i] = default_weight; - } - } - - - dev_dbg(kctx->kbdev->dev, "Old hierarchy mask=%x New hierarchy mask=%x\n", - old_hierarchy_mask, hierarchy_mask); - - for (i = 0; i < HIERARCHY_WEIGHTS; i++) - dev_dbg(kctx->kbdev->dev, " Hierarchy weight %02d: %08x\n", - i, weights[i]); - - j = 0; - - for (i = 0; i < HIERARCHY_WEIGHTS; i++) { - if (hierarchy_mask & (1 << i)) { - KBASE_DEBUG_ASSERT(j < FBD_HIERARCHY_WEIGHTS); - - dev_dbg(kctx->kbdev->dev, " Writing hierarchy level %02d (%08x) to %d\n", - i, weights[i], j); - - fbd_tiler->weights[j++] = weights[i]; - } - } - - for (; j < FBD_HIERARCHY_WEIGHTS; j++) - fbd_tiler->weights[j] = 0; - - fbd_tiler->flags = hierarchy_mask | (1 << 16); - } - - fbd_tiler->heap_free_address = tiler_heap_free; - - dev_dbg(kctx->kbdev->dev, "heap_free_address=%llx flags=%x\n", - fbd_tiler->heap_free_address, fbd_tiler->flags); - - kbase_vunmap(kctx, &map); - - return 0; -} - -static int kbasep_replay_reset_mfbd(struct kbase_context *kctx, - u64 fbd_address, u64 tiler_heap_free, - u16 hierarchy_mask, u32 default_weight) -{ - struct kbase_vmap_struct map; - struct { - u32 padding_0; - u32 flags; - u64 padding_1[2]; - u64 heap_free_address; - u64 padding_2; - u32 weights[FBD_HIERARCHY_WEIGHTS]; - } *fbd_tiler; - - dev_dbg(kctx->kbdev->dev, "fbd_address: %llx\n", fbd_address); - - fbd_tiler = kbase_vmap(kctx, fbd_address + MFBD_TILER_OFFSET, - sizeof(*fbd_tiler), &map); - if (!fbd_tiler) { - dev_err(kctx->kbdev->dev, - "kbasep_replay_reset_fbd: failed to map fbd\n"); - return -EINVAL; - } - -#ifdef CONFIG_MALI_DEBUG - dev_dbg(kctx->kbdev->dev, "FBD tiler:\n" - "flags = %x\n" - "heap_free_address = %llx\n", - fbd_tiler->flags, - fbd_tiler->heap_free_address); -#endif - if (hierarchy_mask) { - u32 weights[HIERARCHY_WEIGHTS]; - u16 old_hierarchy_mask = (fbd_tiler->flags) & - FBD_HIERARCHY_MASK_MASK; - int i, j = 0; - - for (i = 0; i < HIERARCHY_WEIGHTS; i++) { - if (old_hierarchy_mask & (1 << i)) { - KBASE_DEBUG_ASSERT(j < FBD_HIERARCHY_WEIGHTS); - weights[i] = fbd_tiler->weights[j++]; - } else { - weights[i] = default_weight; - } - } - - - dev_dbg(kctx->kbdev->dev, "Old hierarchy mask=%x New hierarchy mask=%x\n", - old_hierarchy_mask, hierarchy_mask); - - for (i = 0; i < HIERARCHY_WEIGHTS; i++) - dev_dbg(kctx->kbdev->dev, " Hierarchy weight %02d: %08x\n", - i, weights[i]); - - j = 0; - - for (i = 0; i < HIERARCHY_WEIGHTS; i++) { - if (hierarchy_mask & (1 << i)) { - KBASE_DEBUG_ASSERT(j < FBD_HIERARCHY_WEIGHTS); - - dev_dbg(kctx->kbdev->dev, - " Writing hierarchy level %02d (%08x) to %d\n", - i, weights[i], j); - - fbd_tiler->weights[j++] = weights[i]; - } - } - - for (; j < FBD_HIERARCHY_WEIGHTS; j++) - fbd_tiler->weights[j] = 0; - - fbd_tiler->flags = hierarchy_mask | (1 << 16); - } - - fbd_tiler->heap_free_address = tiler_heap_free; - - kbase_vunmap(kctx, &map); - - return 0; -} - -/** - * @brief Reset the status of an FBD pointed to by a tiler job - * - * This performs two functions : - * - Set the hierarchy mask - * - Reset the tiler free heap address - * - * @param[in] kctx Context pointer - * @param[in] job_header Address of job header to reset. - * @param[in] tiler_heap_free The value to reset Tiler Heap Free to - * @param[in] hierarchy_mask The hierarchy mask to use - * @param[in] default_weight Default hierarchy weight to write when no other - * weight is given in the FBD - * @param[in] job_64 true if this job is using 64-bit - * descriptors - * - * @return 0 on success, error code on failure - */ -static int kbasep_replay_reset_tiler_job(struct kbase_context *kctx, - u64 job_header, u64 tiler_heap_free, - u16 hierarchy_mask, u32 default_weight, bool job_64) -{ - struct kbase_vmap_struct map; - u64 fbd_address; - - if (job_64) { - u64 *job_ext; - - job_ext = kbase_vmap(kctx, - job_header + JOB_HEADER_64_FBD_OFFSET, - sizeof(*job_ext), &map); - - if (!job_ext) { - dev_err(kctx->kbdev->dev, "kbasep_replay_reset_tiler_job: failed to map jc\n"); - return -EINVAL; - } - - fbd_address = *job_ext; - - kbase_vunmap(kctx, &map); - } else { - u32 *job_ext; - - job_ext = kbase_vmap(kctx, - job_header + JOB_HEADER_32_FBD_OFFSET, - sizeof(*job_ext), &map); - - if (!job_ext) { - dev_err(kctx->kbdev->dev, "kbasep_replay_reset_tiler_job: failed to map jc\n"); - return -EINVAL; - } - - fbd_address = *job_ext; - - kbase_vunmap(kctx, &map); - } - - if (fbd_address & FBD_TYPE) { - return kbasep_replay_reset_mfbd(kctx, - fbd_address & FBD_POINTER_MASK, - tiler_heap_free, - hierarchy_mask, - default_weight); - } else { - return kbasep_replay_reset_sfbd(kctx, - fbd_address & FBD_POINTER_MASK, - tiler_heap_free, - hierarchy_mask, - default_weight); - } -} - -/** - * @brief Reset the status of a job - * - * This performs the following functions : - * - * - Reset the Job Status field of each job to NOT_STARTED. - * - Set the Job Type field of any Vertex Jobs to Null Job. - * - For any jobs using an FBD, set the Tiler Heap Free field to the value of - * the tiler_heap_free parameter, and set the hierarchy level mask to the - * hier_mask parameter. - * - Offset HW dependencies by the hw_job_id_offset parameter - * - Set the Perform Job Barrier flag if this job is the first in the chain - * - Read the address of the next job header - * - * @param[in] kctx Context pointer - * @param[in,out] job_header Address of job header to reset. Set to address - * of next job header on exit. - * @param[in] prev_jc Previous job chain to link to, if this job is - * the last in the chain. - * @param[in] hw_job_id_offset Offset for HW job IDs - * @param[in] tiler_heap_free The value to reset Tiler Heap Free to - * @param[in] hierarchy_mask The hierarchy mask to use - * @param[in] default_weight Default hierarchy weight to write when no other - * weight is given in the FBD - * @param[in] first_in_chain true if this job is the first in the chain - * @param[in] fragment_chain true if this job is in the fragment chain - * - * @return 0 on success, error code on failure - */ -static int kbasep_replay_reset_job(struct kbase_context *kctx, - u64 *job_header, u64 prev_jc, - u64 tiler_heap_free, u16 hierarchy_mask, - u32 default_weight, u16 hw_job_id_offset, - bool first_in_chain, bool fragment_chain) -{ - struct fragment_job *frag_job; - struct job_descriptor_header *job; - u64 new_job_header; - struct kbase_vmap_struct map; - - frag_job = kbase_vmap(kctx, *job_header, sizeof(*frag_job), &map); - if (!frag_job) { - dev_err(kctx->kbdev->dev, - "kbasep_replay_parse_jc: failed to map jc\n"); - return -EINVAL; - } - job = &frag_job->header; - - dump_job_head(kctx, "Job header:", job); - - if (job->exception_status == JOB_NOT_STARTED && !fragment_chain) { - dev_err(kctx->kbdev->dev, "Job already not started\n"); - goto out_unmap; - } - job->exception_status = JOB_NOT_STARTED; - - if (job->job_type == JOB_TYPE_VERTEX) - job->job_type = JOB_TYPE_NULL; - - if (job->job_type == JOB_TYPE_FUSED) { - dev_err(kctx->kbdev->dev, "Fused jobs can not be replayed\n"); - goto out_unmap; - } - - if (first_in_chain) - job->job_barrier = 1; - - if ((job->job_dependency_index_1 + hw_job_id_offset) > - JOB_HEADER_ID_MAX || - (job->job_dependency_index_2 + hw_job_id_offset) > - JOB_HEADER_ID_MAX || - (job->job_index + hw_job_id_offset) > JOB_HEADER_ID_MAX) { - dev_err(kctx->kbdev->dev, - "Job indicies/dependencies out of valid range\n"); - goto out_unmap; - } - - if (job->job_dependency_index_1) - job->job_dependency_index_1 += hw_job_id_offset; - if (job->job_dependency_index_2) - job->job_dependency_index_2 += hw_job_id_offset; - - job->job_index += hw_job_id_offset; - - if (job->job_descriptor_size) { - new_job_header = job->next_job._64; - if (!job->next_job._64) - job->next_job._64 = prev_jc; - } else { - new_job_header = job->next_job._32; - if (!job->next_job._32) - job->next_job._32 = prev_jc; - } - dump_job_head(kctx, "Updated to:", job); - - if (job->job_type == JOB_TYPE_TILER) { - bool job_64 = job->job_descriptor_size != 0; - - if (kbasep_replay_reset_tiler_job(kctx, *job_header, - tiler_heap_free, hierarchy_mask, - default_weight, job_64) != 0) - goto out_unmap; - - } else if (job->job_type == JOB_TYPE_FRAGMENT) { - u64 fbd_address; - - if (job->job_descriptor_size) - fbd_address = frag_job->fragment_fbd._64; - else - fbd_address = (u64)frag_job->fragment_fbd._32; - - if (fbd_address & FBD_TYPE) { - if (kbasep_replay_reset_mfbd(kctx, - fbd_address & FBD_POINTER_MASK, - tiler_heap_free, - hierarchy_mask, - default_weight) != 0) - goto out_unmap; - } else { - if (kbasep_replay_reset_sfbd(kctx, - fbd_address & FBD_POINTER_MASK, - tiler_heap_free, - hierarchy_mask, - default_weight) != 0) - goto out_unmap; - } - } - - kbase_vunmap(kctx, &map); - - *job_header = new_job_header; - - return 0; - -out_unmap: - kbase_vunmap(kctx, &map); - return -EINVAL; -} - -/** - * @brief Find the highest job ID in a job chain - * - * @param[in] kctx Context pointer - * @param[in] jc Job chain start address - * @param[out] hw_job_id Highest job ID in chain - * - * @return 0 on success, error code on failure - */ -static int kbasep_replay_find_hw_job_id(struct kbase_context *kctx, - u64 jc, u16 *hw_job_id) -{ - while (jc) { - struct job_descriptor_header *job; - struct kbase_vmap_struct map; - - dev_dbg(kctx->kbdev->dev, - "kbasep_replay_find_hw_job_id: parsing jc=%llx\n", jc); - - job = kbase_vmap(kctx, jc, sizeof(*job), &map); - if (!job) { - dev_err(kctx->kbdev->dev, "failed to map jc\n"); - - return -EINVAL; - } - - if (job->job_index > *hw_job_id) - *hw_job_id = job->job_index; - - if (job->job_descriptor_size) - jc = job->next_job._64; - else - jc = job->next_job._32; - - kbase_vunmap(kctx, &map); - } - - return 0; -} - -/** - * @brief Reset the status of a number of jobs - * - * This function walks the provided job chain, and calls - * kbasep_replay_reset_job for each job. It also links the job chain to the - * provided previous job chain. - * - * The function will fail if any of the jobs passed already have status of - * NOT_STARTED. - * - * @param[in] kctx Context pointer - * @param[in] jc Job chain to be processed - * @param[in] prev_jc Job chain to be added to. May be NULL - * @param[in] tiler_heap_free The value to reset Tiler Heap Free to - * @param[in] hierarchy_mask The hierarchy mask to use - * @param[in] default_weight Default hierarchy weight to write when no other - * weight is given in the FBD - * @param[in] hw_job_id_offset Offset for HW job IDs - * @param[in] fragment_chain true if this chain is the fragment chain - * - * @return 0 on success, error code otherwise - */ -static int kbasep_replay_parse_jc(struct kbase_context *kctx, - u64 jc, u64 prev_jc, - u64 tiler_heap_free, u16 hierarchy_mask, - u32 default_weight, u16 hw_job_id_offset, - bool fragment_chain) -{ - bool first_in_chain = true; - int nr_jobs = 0; - - dev_dbg(kctx->kbdev->dev, "kbasep_replay_parse_jc: jc=%llx hw_job_id=%x\n", - jc, hw_job_id_offset); - - while (jc) { - dev_dbg(kctx->kbdev->dev, "kbasep_replay_parse_jc: parsing jc=%llx\n", jc); - - if (kbasep_replay_reset_job(kctx, &jc, prev_jc, - tiler_heap_free, hierarchy_mask, - default_weight, hw_job_id_offset, - first_in_chain, fragment_chain) != 0) - return -EINVAL; - - first_in_chain = false; - - nr_jobs++; - if (fragment_chain && - nr_jobs >= BASE_JD_REPLAY_F_CHAIN_JOB_LIMIT) { - dev_err(kctx->kbdev->dev, - "Exceeded maximum number of jobs in fragment chain\n"); - return -EINVAL; - } - } - - return 0; -} - -/** - * @brief Reset the status of a replay job, and set up dependencies - * - * This performs the actions to allow the replay job to be re-run following - * completion of the passed dependency. - * - * @param[in] katom The atom to be reset - * @param[in] dep_atom The dependency to be attached to the atom - */ -static void kbasep_replay_reset_softjob(struct kbase_jd_atom *katom, - struct kbase_jd_atom *dep_atom) -{ - katom->status = KBASE_JD_ATOM_STATE_QUEUED; - kbase_jd_katom_dep_set(&katom->dep[0], dep_atom, BASE_JD_DEP_TYPE_DATA); - list_add_tail(&katom->dep_item[0], &dep_atom->dep_head[0]); -} - -/** - * @brief Allocate an unused katom - * - * This will search the provided context for an unused katom, and will mark it - * as KBASE_JD_ATOM_STATE_QUEUED. - * - * If no atoms are available then the function will fail. - * - * @param[in] kctx Context pointer - * @return An atom ID, or -1 on failure - */ -static int kbasep_allocate_katom(struct kbase_context *kctx) -{ - struct kbase_jd_context *jctx = &kctx->jctx; - int i; - - for (i = BASE_JD_ATOM_COUNT-1; i > 0; i--) { - if (jctx->atoms[i].status == KBASE_JD_ATOM_STATE_UNUSED) { - jctx->atoms[i].status = KBASE_JD_ATOM_STATE_QUEUED; - dev_dbg(kctx->kbdev->dev, - "kbasep_allocate_katom: Allocated atom %d\n", - i); - return i; - } - } - - return -1; -} - -/** - * @brief Release a katom - * - * This will mark the provided atom as available, and remove any dependencies. - * - * For use on error path. - * - * @param[in] kctx Context pointer - * @param[in] atom_id ID of atom to release - */ -static void kbasep_release_katom(struct kbase_context *kctx, int atom_id) -{ - struct kbase_jd_context *jctx = &kctx->jctx; - - dev_dbg(kctx->kbdev->dev, "kbasep_release_katom: Released atom %d\n", - atom_id); - - while (!list_empty(&jctx->atoms[atom_id].dep_head[0])) - list_del(jctx->atoms[atom_id].dep_head[0].next); - - while (!list_empty(&jctx->atoms[atom_id].dep_head[1])) - list_del(jctx->atoms[atom_id].dep_head[1].next); - - jctx->atoms[atom_id].status = KBASE_JD_ATOM_STATE_UNUSED; -} - -static void kbasep_replay_create_atom(struct kbase_context *kctx, - struct base_jd_atom_v2 *atom, - int atom_nr, - base_jd_prio prio) -{ - atom->nr_extres = 0; - atom->extres_list = 0; - atom->device_nr = 0; - atom->prio = prio; - atom->atom_number = atom_nr; - - base_jd_atom_dep_set(&atom->pre_dep[0], 0, BASE_JD_DEP_TYPE_INVALID); - base_jd_atom_dep_set(&atom->pre_dep[1], 0, BASE_JD_DEP_TYPE_INVALID); - - atom->udata.blob[0] = 0; - atom->udata.blob[1] = 0; -} - -/** - * @brief Create two atoms for the purpose of replaying jobs - * - * Two atoms are allocated and created. The jc pointer is not set at this - * stage. The second atom has a dependency on the first. The remaining fields - * are set up as follows : - * - * - No external resources. Any required external resources will be held by the - * replay atom. - * - device_nr is set to 0. This is not relevant as - * BASE_JD_REQ_SPECIFIC_COHERENT_GROUP should not be set. - * - Priority is inherited from the replay job. - * - * @param[out] t_atom Atom to use for tiler jobs - * @param[out] f_atom Atom to use for fragment jobs - * @param[in] prio Priority of new atom (inherited from replay soft - * job) - * @return 0 on success, error code on failure - */ -static int kbasep_replay_create_atoms(struct kbase_context *kctx, - struct base_jd_atom_v2 *t_atom, - struct base_jd_atom_v2 *f_atom, - base_jd_prio prio) -{ - int t_atom_nr, f_atom_nr; - - t_atom_nr = kbasep_allocate_katom(kctx); - if (t_atom_nr < 0) { - dev_err(kctx->kbdev->dev, "Failed to allocate katom\n"); - return -EINVAL; - } - - f_atom_nr = kbasep_allocate_katom(kctx); - if (f_atom_nr < 0) { - dev_err(kctx->kbdev->dev, "Failed to allocate katom\n"); - kbasep_release_katom(kctx, t_atom_nr); - return -EINVAL; - } - - kbasep_replay_create_atom(kctx, t_atom, t_atom_nr, prio); - kbasep_replay_create_atom(kctx, f_atom, f_atom_nr, prio); - - base_jd_atom_dep_set(&f_atom->pre_dep[0], t_atom_nr, - BASE_JD_DEP_TYPE_DATA); - - return 0; -} - -#ifdef CONFIG_MALI_DEBUG -static void payload_dump(struct kbase_context *kctx, base_jd_replay_payload *payload) -{ - u64 next; - - dev_dbg(kctx->kbdev->dev, "Tiler jc list :\n"); - next = payload->tiler_jc_list; - - while (next) { - struct kbase_vmap_struct map; - base_jd_replay_jc *jc_struct; - - jc_struct = kbase_vmap(kctx, next, sizeof(*jc_struct), &map); - - if (!jc_struct) - return; - - dev_dbg(kctx->kbdev->dev, "* jc_struct=%p jc=%llx next=%llx\n", - jc_struct, jc_struct->jc, jc_struct->next); - - next = jc_struct->next; - - kbase_vunmap(kctx, &map); - } -} -#endif - -/** - * @brief Parse a base_jd_replay_payload provided by userspace - * - * This will read the payload from userspace, and parse the job chains. - * - * @param[in] kctx Context pointer - * @param[in] replay_atom Replay soft job atom - * @param[in] t_atom Atom to use for tiler jobs - * @param[in] f_atom Atom to use for fragment jobs - * @return 0 on success, error code on failure - */ -static int kbasep_replay_parse_payload(struct kbase_context *kctx, - struct kbase_jd_atom *replay_atom, - struct base_jd_atom_v2 *t_atom, - struct base_jd_atom_v2 *f_atom) -{ - base_jd_replay_payload *payload = NULL; - u64 next; - u64 prev_jc = 0; - u16 hw_job_id_offset = 0; - int ret = -EINVAL; - struct kbase_vmap_struct map; - - dev_dbg(kctx->kbdev->dev, "kbasep_replay_parse_payload: replay_atom->jc = %llx sizeof(payload) = %zu\n", - replay_atom->jc, sizeof(payload)); - - payload = kbase_vmap(kctx, replay_atom->jc, sizeof(*payload), &map); - if (!payload) { - dev_err(kctx->kbdev->dev, "kbasep_replay_parse_payload: failed to map payload into kernel space\n"); - return -EINVAL; - } - -#ifdef CONFIG_MALI_DEBUG - dev_dbg(kctx->kbdev->dev, "kbasep_replay_parse_payload: payload=%p\n", payload); - dev_dbg(kctx->kbdev->dev, "Payload structure:\n" - "tiler_jc_list = %llx\n" - "fragment_jc = %llx\n" - "tiler_heap_free = %llx\n" - "fragment_hierarchy_mask = %x\n" - "tiler_hierarchy_mask = %x\n" - "hierarchy_default_weight = %x\n" - "tiler_core_req = %x\n" - "fragment_core_req = %x\n", - payload->tiler_jc_list, - payload->fragment_jc, - payload->tiler_heap_free, - payload->fragment_hierarchy_mask, - payload->tiler_hierarchy_mask, - payload->hierarchy_default_weight, - payload->tiler_core_req, - payload->fragment_core_req); - payload_dump(kctx, payload); -#endif - t_atom->core_req = payload->tiler_core_req | BASEP_JD_REQ_EVENT_NEVER; - f_atom->core_req = payload->fragment_core_req | BASEP_JD_REQ_EVENT_NEVER; - - /* Sanity check core requirements*/ - if ((t_atom->core_req & BASE_JD_REQ_ATOM_TYPE) != BASE_JD_REQ_T || - (f_atom->core_req & BASE_JD_REQ_ATOM_TYPE) != BASE_JD_REQ_FS || - t_atom->core_req & BASE_JD_REQ_EXTERNAL_RESOURCES || - f_atom->core_req & BASE_JD_REQ_EXTERNAL_RESOURCES) { - - int t_atom_type = t_atom->core_req & BASE_JD_REQ_ATOM_TYPE & ~BASE_JD_REQ_COHERENT_GROUP; - int f_atom_type = f_atom->core_req & BASE_JD_REQ_ATOM_TYPE & ~BASE_JD_REQ_COHERENT_GROUP & ~BASE_JD_REQ_FS_AFBC; - int t_has_ex_res = t_atom->core_req & BASE_JD_REQ_EXTERNAL_RESOURCES; - int f_has_ex_res = f_atom->core_req & BASE_JD_REQ_EXTERNAL_RESOURCES; - - if (t_atom_type != BASE_JD_REQ_T) { - dev_err(kctx->kbdev->dev, "Invalid core requirement: Tiler atom not a tiler job. Was: 0x%x\n Expected: 0x%x", - t_atom_type, BASE_JD_REQ_T); - } - if (f_atom_type != BASE_JD_REQ_FS) { - dev_err(kctx->kbdev->dev, "Invalid core requirement: Fragment shader atom not a fragment shader. Was 0x%x Expected: 0x%x\n", - f_atom_type, BASE_JD_REQ_FS); - } - if (t_has_ex_res) { - dev_err(kctx->kbdev->dev, "Invalid core requirement: Tiler atom has external resources.\n"); - } - if (f_has_ex_res) { - dev_err(kctx->kbdev->dev, "Invalid core requirement: Fragment shader atom has external resources.\n"); - } - - goto out; - } - - /* Process tiler job chains */ - next = payload->tiler_jc_list; - if (!next) { - dev_err(kctx->kbdev->dev, "Invalid tiler JC list\n"); - goto out; - } - - while (next) { - base_jd_replay_jc *jc_struct; - struct kbase_vmap_struct jc_map; - u64 jc; - - jc_struct = kbase_vmap(kctx, next, sizeof(*jc_struct), &jc_map); - - if (!jc_struct) { - dev_err(kctx->kbdev->dev, "Failed to map jc struct\n"); - goto out; - } - - jc = jc_struct->jc; - next = jc_struct->next; - if (next) - jc_struct->jc = 0; - - kbase_vunmap(kctx, &jc_map); - - if (jc) { - u16 max_hw_job_id = 0; - - if (kbasep_replay_find_hw_job_id(kctx, jc, - &max_hw_job_id) != 0) - goto out; - - if (kbasep_replay_parse_jc(kctx, jc, prev_jc, - payload->tiler_heap_free, - payload->tiler_hierarchy_mask, - payload->hierarchy_default_weight, - hw_job_id_offset, false) != 0) { - goto out; - } - - hw_job_id_offset += max_hw_job_id; - - prev_jc = jc; - } - } - t_atom->jc = prev_jc; - - /* Process fragment job chain */ - f_atom->jc = payload->fragment_jc; - if (kbasep_replay_parse_jc(kctx, payload->fragment_jc, 0, - payload->tiler_heap_free, - payload->fragment_hierarchy_mask, - payload->hierarchy_default_weight, 0, - true) != 0) { - goto out; - } - - if (!t_atom->jc || !f_atom->jc) { - dev_err(kctx->kbdev->dev, "Invalid payload\n"); - goto out; - } - - dev_dbg(kctx->kbdev->dev, "t_atom->jc=%llx f_atom->jc=%llx\n", - t_atom->jc, f_atom->jc); - ret = 0; - -out: - kbase_vunmap(kctx, &map); - - return ret; -} - -static void kbase_replay_process_worker(struct work_struct *data) -{ - struct kbase_jd_atom *katom; - struct kbase_context *kctx; - struct kbase_jd_context *jctx; - bool need_to_try_schedule_context = false; - - struct base_jd_atom_v2 t_atom, f_atom; - struct kbase_jd_atom *t_katom, *f_katom; - base_jd_prio atom_prio; - - katom = container_of(data, struct kbase_jd_atom, work); - kctx = katom->kctx; - jctx = &kctx->jctx; - - mutex_lock(&jctx->lock); - - atom_prio = kbasep_js_sched_prio_to_atom_prio(katom->sched_priority); - - if (kbasep_replay_create_atoms( - kctx, &t_atom, &f_atom, atom_prio) != 0) { - katom->event_code = BASE_JD_EVENT_JOB_CANCELLED; - goto out; - } - - t_katom = &jctx->atoms[t_atom.atom_number]; - f_katom = &jctx->atoms[f_atom.atom_number]; - - if (kbasep_replay_parse_payload(kctx, katom, &t_atom, &f_atom) != 0) { - kbasep_release_katom(kctx, t_atom.atom_number); - kbasep_release_katom(kctx, f_atom.atom_number); - katom->event_code = BASE_JD_EVENT_JOB_CANCELLED; - goto out; - } - - kbasep_replay_reset_softjob(katom, f_katom); - - need_to_try_schedule_context |= jd_submit_atom(kctx, &t_atom, t_katom); - if (t_katom->event_code == BASE_JD_EVENT_JOB_INVALID) { - dev_err(kctx->kbdev->dev, "Replay failed to submit atom\n"); - kbasep_release_katom(kctx, f_atom.atom_number); - katom->event_code = BASE_JD_EVENT_JOB_CANCELLED; - goto out; - } - need_to_try_schedule_context |= jd_submit_atom(kctx, &f_atom, f_katom); - if (f_katom->event_code == BASE_JD_EVENT_JOB_INVALID) { - dev_err(kctx->kbdev->dev, "Replay failed to submit atom\n"); - katom->event_code = BASE_JD_EVENT_JOB_CANCELLED; - goto out; - } - - katom->event_code = BASE_JD_EVENT_DONE; - -out: - if (katom->event_code != BASE_JD_EVENT_DONE) { - kbase_disjoint_state_down(kctx->kbdev); - - need_to_try_schedule_context |= jd_done_nolock(katom, NULL); - } - - if (need_to_try_schedule_context) - kbase_js_sched_all(kctx->kbdev); - - mutex_unlock(&jctx->lock); -} - -/** - * @brief Check job replay fault - * - * This will read the job payload, checks fault type and source, then decides - * whether replay is required. - * - * @param[in] katom The atom to be processed - * @return true (success) if replay required or false on failure. - */ -static bool kbase_replay_fault_check(struct kbase_jd_atom *katom) -{ - struct kbase_context *kctx = katom->kctx; - struct device *dev = kctx->kbdev->dev; - base_jd_replay_payload *payload; - u64 job_header; - u64 job_loop_detect; - struct job_descriptor_header *job; - struct kbase_vmap_struct job_map; - struct kbase_vmap_struct map; - bool err = false; - - /* Replay job if fault is of type BASE_JD_EVENT_JOB_WRITE_FAULT or - * if force_replay is enabled. - */ - if (BASE_JD_EVENT_TERMINATED == katom->event_code) { - return false; - } else if (BASE_JD_EVENT_JOB_WRITE_FAULT == katom->event_code) { - return true; - } else if (BASE_JD_EVENT_FORCE_REPLAY == katom->event_code) { - katom->event_code = BASE_JD_EVENT_DATA_INVALID_FAULT; - return true; - } else if (BASE_JD_EVENT_DATA_INVALID_FAULT != katom->event_code) { - /* No replay for faults of type other than - * BASE_JD_EVENT_DATA_INVALID_FAULT. - */ - return false; - } - - /* Job fault is BASE_JD_EVENT_DATA_INVALID_FAULT, now scan fragment jc - * to find out whether the source of exception is POLYGON_LIST. Replay - * is required if the source of fault is POLYGON_LIST. - */ - payload = kbase_vmap(kctx, katom->jc, sizeof(*payload), &map); - if (!payload) { - dev_err(dev, "kbase_replay_fault_check: failed to map payload.\n"); - return false; - } - -#ifdef CONFIG_MALI_DEBUG - dev_dbg(dev, "kbase_replay_fault_check: payload=%p\n", payload); - dev_dbg(dev, "\nPayload structure:\n" - "fragment_jc = 0x%llx\n" - "fragment_hierarchy_mask = 0x%x\n" - "fragment_core_req = 0x%x\n", - payload->fragment_jc, - payload->fragment_hierarchy_mask, - payload->fragment_core_req); -#endif - /* Process fragment job chain */ - job_header = (u64) payload->fragment_jc; - job_loop_detect = job_header; - while (job_header) { - job = kbase_vmap(kctx, job_header, sizeof(*job), &job_map); - if (!job) { - dev_err(dev, "failed to map jc\n"); - /* unmap payload*/ - kbase_vunmap(kctx, &map); - return false; - } - - - dump_job_head(kctx, "\njob_head structure:\n", job); - - /* Replay only when the polygon list reader caused the - * DATA_INVALID_FAULT */ - if ((BASE_JD_EVENT_DATA_INVALID_FAULT == katom->event_code) && - (JOB_POLYGON_LIST == JOB_SOURCE_ID(job->exception_status))) { - err = true; - kbase_vunmap(kctx, &job_map); - break; - } - - /* Move on to next fragment job in the list */ - if (job->job_descriptor_size) - job_header = job->next_job._64; - else - job_header = job->next_job._32; - - kbase_vunmap(kctx, &job_map); - - /* Job chain loop detected */ - if (job_header == job_loop_detect) - break; - } - - /* unmap payload*/ - kbase_vunmap(kctx, &map); - - return err; -} - - -/** - * @brief Process a replay job - * - * Called from kbase_process_soft_job. - * - * On exit, if the job has completed, katom->event_code will have been updated. - * If the job has not completed, and is replaying jobs, then the atom status - * will have been reset to KBASE_JD_ATOM_STATE_QUEUED. - * - * @param[in] katom The atom to be processed - * @return false if the atom has completed - * true if the atom is replaying jobs - */ -bool kbase_replay_process(struct kbase_jd_atom *katom) -{ - struct kbase_context *kctx = katom->kctx; - struct kbase_device *kbdev = kctx->kbdev; - - /* Don't replay this atom if these issues are not present in the - * hardware */ - if (!kbase_hw_has_issue(kbdev, BASE_HW_ISSUE_11020) && - !kbase_hw_has_issue(kbdev, BASE_HW_ISSUE_11024)) { - dev_dbg(kbdev->dev, "Hardware does not need replay workaround"); - - /* Signal failure to userspace */ - katom->event_code = BASE_JD_EVENT_JOB_INVALID; - - return false; - } - - if (katom->event_code == BASE_JD_EVENT_DONE) { - dev_dbg(kbdev->dev, "Previous job succeeded - not replaying\n"); - - if (katom->retry_count) - kbase_disjoint_state_down(kbdev); - - return false; - } - - if (kbase_ctx_flag(kctx, KCTX_DYING)) { - dev_dbg(kbdev->dev, "Not replaying; context is dying\n"); - - if (katom->retry_count) - kbase_disjoint_state_down(kbdev); - - return false; - } - - /* Check job exception type and source before replaying. */ - if (!kbase_replay_fault_check(katom)) { - dev_dbg(kbdev->dev, - "Replay cancelled on event %x\n", katom->event_code); - /* katom->event_code is already set to the failure code of the - * previous job. - */ - return false; - } - - dev_warn(kbdev->dev, "Replaying jobs retry=%d\n", - katom->retry_count); - - katom->retry_count++; - - if (katom->retry_count > BASEP_JD_REPLAY_LIMIT) { - dev_err(kbdev->dev, "Replay exceeded limit - failing jobs\n"); - - kbase_disjoint_state_down(kbdev); - - /* katom->event_code is already set to the failure code of the - previous job */ - return false; - } - - /* only enter the disjoint state once for the whole time while the replay is ongoing */ - if (katom->retry_count == 1) - kbase_disjoint_state_up(kbdev); - - INIT_WORK(&katom->work, kbase_replay_process_worker); - queue_work(kctx->event_workq, &katom->work); - - return true; -} diff --git a/mali_kbase/mali_kbase_reset_gpu.h b/mali_kbase/mali_kbase_reset_gpu.h new file mode 100644 index 0000000..df72eec --- /dev/null +++ b/mali_kbase/mali_kbase_reset_gpu.h @@ -0,0 +1,139 @@ +/* + * + * (C) COPYRIGHT 2019 ARM Limited. All rights reserved. + * + * This program is free software and is provided to you under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation, and any use by you of this program is subject to the terms + * of such GNU licence. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, you can access it online at + * http://www.gnu.org/licenses/gpl-2.0.html. + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +#ifndef _KBASE_RESET_GPU_H_ +#define _KBASE_RESET_GPU_H_ + +/** + * kbase_prepare_to_reset_gpu_locked - Prepare for resetting the GPU. + * @kbdev: Device pointer + * + * Caller is expected to hold the kbdev->hwaccess_lock. + * + * Return: a boolean which should be interpreted as follows: + * - true - Prepared for reset, kbase_reset_gpu should be called. + * - false - Another thread is performing a reset, kbase_reset_gpu should + * not be called. + */ +bool kbase_prepare_to_reset_gpu_locked(struct kbase_device *kbdev); + +/** + * kbase_prepare_to_reset_gpu - Prepare for resetting the GPU. + * @kbdev: Device pointer + * + * Return: a boolean which should be interpreted as follows: + * - true - Prepared for reset, kbase_reset_gpu should be called. + * - false - Another thread is performing a reset, kbase_reset_gpu should + * not be called. + */ +bool kbase_prepare_to_reset_gpu(struct kbase_device *kbdev); + +/** + * kbase_reset_gpu - Reset the GPU + * @kbdev: Device pointer + * + * This function should be called after kbase_prepare_to_reset_gpu if it returns + * true. It should never be called without a corresponding call to + * kbase_prepare_to_reset_gpu (only on Job Manager GPUs). + * + * After this function is called the caller should call kbase_reset_gpu_wait() + * to know when the reset has completed. + */ +void kbase_reset_gpu(struct kbase_device *kbdev); + +/** + * kbase_reset_gpu_locked - Reset the GPU + * @kbdev: Device pointer + * + * This function should be called after kbase_prepare_to_reset_gpu_locked if it + * returns true. It should never be called without a corresponding call to + * kbase_prepare_to_reset_gpu (only on Job Manager GPUs). + * Caller is expected to hold the kbdev->hwaccess_lock. + * + * After this function is called, the caller should call kbase_reset_gpu_wait() + * to know when the reset has completed. + */ +void kbase_reset_gpu_locked(struct kbase_device *kbdev); + +/** + * kbase_reset_gpu_silent - Reset the GPU silently + * @kbdev: Device pointer + * + * Reset the GPU without trying to cancel jobs (applicable to Job Manager GPUs) + * and don't emit messages into the kernel log while doing the reset. + * + * This function should be used in cases where we are doing a controlled reset + * of the GPU as part of normal processing (e.g. exiting protected mode) where + * the driver will have ensured the scheduler has been idled and all other + * users of the GPU (e.g. instrumentation) have been suspended. + * + * Return: 0 if the reset was started successfully + * -EAGAIN if another reset is currently in progress + */ +int kbase_reset_gpu_silent(struct kbase_device *kbdev); + +/** + * kbase_reset_gpu_is_active - Reports if the GPU is being reset + * @kbdev: Device pointer + * + * Return: True if the GPU is in the process of being reset (or if the reset of + * GPU failed, not applicable to Job Manager GPUs). + */ +bool kbase_reset_gpu_is_active(struct kbase_device *kbdev); + +/** + * kbase_reset_gpu_wait - Wait for a GPU reset to complete + * @kbdev: Device pointer + * + * This function may wait indefinitely. + * + * Return: 0 if successful or a negative error code on failure. + */ +int kbase_reset_gpu_wait(struct kbase_device *kbdev); + +/** + * kbase_reset_gpu_init - Initialize the GPU reset handling mechanism. + * + * @kbdev: Device pointer + * + * Return: 0 if successful or a negative error code on failure. + */ +int kbase_reset_gpu_init(struct kbase_device *kbdev); + +/** + * kbase_reset_gpu_term - Terminate the GPU reset handling mechanism. + * + * @kbdev: Device pointer + */ +void kbase_reset_gpu_term(struct kbase_device *kbdev); + +/** + * kbase_reset_gpu_register_complete_cb - Register the callback function to be + * invoked on completion of GPU reset. + * + * @kbdev: Device pointer + * @complete_callback: Pointer to the callback function + */ +void kbase_reset_gpu_register_complete_cb(struct kbase_device *kbdev, + int (*complete_callback)(struct kbase_device *kbdev)); + +#endif diff --git a/mali_kbase/mali_kbase_softjobs.c b/mali_kbase/mali_kbase_softjobs.c index 6d0a268..868e1ea 100644 --- a/mali_kbase/mali_kbase_softjobs.c +++ b/mali_kbase/mali_kbase_softjobs.c @@ -1160,15 +1160,15 @@ static int kbase_jit_allocate_process(struct kbase_jd_atom *katom) * Retrieve the mmu flags for JIT allocation * only if dumping is enabled */ - kctx->kbdev->mmu_mode->entry_set_ate(&entry_mmu_flags, - (struct tagged_addr){ 0 }, - reg->flags, - MIDGARD_MMU_BOTTOMLEVEL); + entry_mmu_flags = kbase_mmu_create_ate(kbdev, + (struct tagged_addr){ 0 }, reg->flags, + MIDGARD_MMU_BOTTOMLEVEL, kctx->jit_group_id); #endif KBASE_TLSTREAM_TL_ATTRIB_ATOM_JIT(kbdev, katom, - info->gpu_alloc_addr, - new_addr, entry_mmu_flags, info->id); + info->gpu_alloc_addr, new_addr, info->flags, + entry_mmu_flags, info->id, info->commit_pages, + info->extent, info->va_pages); kbase_vunmap(kctx, &mapping); } @@ -1503,10 +1503,6 @@ int kbase_process_soft_job(struct kbase_jd_atom *katom) break; } #endif - - case BASE_JD_REQ_SOFT_REPLAY: - ret = kbase_replay_process(katom); - break; case BASE_JD_REQ_SOFT_EVENT_WAIT: ret = kbasep_soft_event_wait(katom); break; @@ -1621,8 +1617,6 @@ int kbase_prepare_soft_job(struct kbase_jd_atom *katom) #endif /* CONFIG_SYNC || CONFIG_SYNC_FILE */ case BASE_JD_REQ_SOFT_JIT_ALLOC: return kbase_jit_allocate_prepare(katom); - case BASE_JD_REQ_SOFT_REPLAY: - break; case BASE_JD_REQ_SOFT_JIT_FREE: return kbase_jit_free_prepare(katom); case BASE_JD_REQ_SOFT_EVENT_WAIT: @@ -1715,12 +1709,7 @@ void kbase_resume_suspended_soft_jobs(struct kbase_device *kbdev) if (kbase_process_soft_job(katom_iter) == 0) { kbase_finish_soft_job(katom_iter); resched |= jd_done_nolock(katom_iter, NULL); - } else { - KBASE_DEBUG_ASSERT((katom_iter->core_req & - BASE_JD_REQ_SOFT_JOB_TYPE) - != BASE_JD_REQ_SOFT_REPLAY); } - mutex_unlock(&kctx->jctx.lock); } diff --git a/mali_kbase/mali_kbase_sync.h b/mali_kbase/mali_kbase_sync.h index 70557dd..785b9ff 100644 --- a/mali_kbase/mali_kbase_sync.h +++ b/mali_kbase/mali_kbase_sync.h @@ -1,6 +1,6 @@ /* * - * (C) COPYRIGHT 2012-2018 ARM Limited. All rights reserved. + * (C) COPYRIGHT 2012-2019 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the * GNU General Public License version 2 as published by the Free Software @@ -188,6 +188,16 @@ int kbase_sync_fence_in_info_get(struct kbase_jd_atom *katom, int kbase_sync_fence_out_info_get(struct kbase_jd_atom *katom, struct kbase_sync_fence_info *info); +#if defined(CONFIG_SYNC_FILE) +#if (KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE) +void kbase_sync_fence_info_get(struct fence *fence, + struct kbase_sync_fence_info *info); +#else +void kbase_sync_fence_info_get(struct dma_fence *fence, + struct kbase_sync_fence_info *info); +#endif +#endif + /** * kbase_sync_status_string() - Get string matching @status * @status: Value of fence status. diff --git a/mali_kbase/mali_kbase_sync_common.c b/mali_kbase/mali_kbase_sync_common.c index 5239dae..03c0df5 100644 --- a/mali_kbase/mali_kbase_sync_common.c +++ b/mali_kbase/mali_kbase_sync_common.c @@ -1,6 +1,6 @@ /* * - * (C) COPYRIGHT 2012-2018 ARM Limited. All rights reserved. + * (C) COPYRIGHT 2012-2019 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the * GNU General Public License version 2 as published by the Free Software @@ -41,9 +41,9 @@ void kbase_sync_fence_wait_worker(struct work_struct *data) const char *kbase_sync_status_string(int status) { if (status == 0) - return "signaled"; - else if (status > 0) return "active"; + else if (status > 0) + return "signaled"; else return "error"; } diff --git a/mali_kbase/mali_kbase_sync_file.c b/mali_kbase/mali_kbase_sync_file.c index bb94aee..0679c48 100644 --- a/mali_kbase/mali_kbase_sync_file.c +++ b/mali_kbase/mali_kbase_sync_file.c @@ -1,6 +1,6 @@ /* * - * (C) COPYRIGHT 2012-2018 ARM Limited. All rights reserved. + * (C) COPYRIGHT 2012-2019 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the * GNU General Public License version 2 as published by the Free Software @@ -85,7 +85,9 @@ int kbase_sync_fence_out_create(struct kbase_jd_atom *katom, int stream_fd) /* create a sync_file fd representing the fence */ sync_file = sync_file_create(fence); if (!sync_file) { +#if (KERNEL_VERSION(4, 9, 67) >= LINUX_VERSION_CODE) dma_fence_put(fence); +#endif kbase_fence_out_remove(katom); return -ENOMEM; } @@ -272,12 +274,12 @@ void kbase_sync_fence_in_remove(struct kbase_jd_atom *katom) kbase_fence_in_remove(katom); } -#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 10, 0)) -static void kbase_sync_fence_info_get(struct fence *fence, - struct kbase_sync_fence_info *info) +#if (KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE) +void kbase_sync_fence_info_get(struct fence *fence, + struct kbase_sync_fence_info *info) #else -static void kbase_sync_fence_info_get(struct dma_fence *fence, - struct kbase_sync_fence_info *info) +void kbase_sync_fence_info_get(struct dma_fence *fence, + struct kbase_sync_fence_info *info) #endif { info->fence = fence; @@ -303,12 +305,15 @@ static void kbase_sync_fence_info_get(struct dma_fence *fence, info->status = 0; /* still active (unsignaled) */ } -#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0)) +#if (KERNEL_VERSION(4, 8, 0) > LINUX_VERSION_CODE) scnprintf(info->name, sizeof(info->name), "%u#%u", fence->context, fence->seqno); -#else +#elif (KERNEL_VERSION(5, 1, 0) > LINUX_VERSION_CODE) scnprintf(info->name, sizeof(info->name), "%llu#%u", fence->context, fence->seqno); +#else + scnprintf(info->name, sizeof(info->name), "%llu#%llu", + fence->context, fence->seqno); #endif } diff --git a/mali_kbase/mali_kbase_timeline.c b/mali_kbase/mali_kbase_timeline.c index d527bb3..17470fc 100644 --- a/mali_kbase/mali_kbase_timeline.c +++ b/mali_kbase/mali_kbase_timeline.c @@ -31,7 +31,6 @@ #include <linux/atomic.h> #include <linux/file.h> #include <linux/mutex.h> -#include <linux/poll.h> #include <linux/spinlock.h> #include <linux/string.h> #include <linux/stringify.h> @@ -71,7 +70,8 @@ static void kbasep_timeline_autoflush_timer_callback(struct timer_list *timer) CSTD_UNUSED(timer); - for (stype = 0; stype < TL_STREAM_TYPE_COUNT; stype++) { + for (stype = (enum tl_stream_type)0; stype < TL_STREAM_TYPE_COUNT; + stype++) { struct kbase_tlstream *stream = &timeline->streams[stype]; int af_cnt = atomic_read(&stream->autoflush_counter); @@ -142,7 +142,7 @@ void kbase_timeline_term(struct kbase_timeline *timeline) if (!timeline) return; - for (i = 0; i < TL_STREAM_TYPE_COUNT; i++) + for (i = (enum tl_stream_type)0; i < TL_STREAM_TYPE_COUNT; i++) kbase_tlstream_term(&timeline->streams[i]); kfree(timeline); @@ -332,7 +332,8 @@ void kbase_timeline_stats(struct kbase_timeline *timeline, /* Accumulate bytes generated per stream */ *bytes_generated = 0; - for (stype = 0; stype < TL_STREAM_TYPE_COUNT; stype++) + for (stype = (enum tl_stream_type)0; stype < TL_STREAM_TYPE_COUNT; + stype++) *bytes_generated += atomic_read( &timeline->streams[stype].bytes_generated); diff --git a/mali_kbase/mali_kbase_timeline_io.c b/mali_kbase/mali_kbase_timeline_io.c index f01bf57..ffcf84a 100644 --- a/mali_kbase/mali_kbase_timeline_io.c +++ b/mali_kbase/mali_kbase_timeline_io.c @@ -37,6 +37,7 @@ static int kbasep_timeline_io_release(struct inode *inode, struct file *filp); /* The timeline stream file operations structure. */ const struct file_operations kbasep_tlstream_fops = { + .owner = THIS_MODULE, .release = kbasep_timeline_io_release, .read = kbasep_timeline_io_read, .poll = kbasep_timeline_io_poll, @@ -60,12 +61,12 @@ static int kbasep_timeline_io_packet_pending( struct kbase_tlstream **ready_stream, unsigned int *rb_idx_raw) { - enum tl_stream_type i = 0; + enum tl_stream_type i; KBASE_DEBUG_ASSERT(ready_stream); KBASE_DEBUG_ASSERT(rb_idx_raw); - for (i = 0; i < TL_STREAM_TYPE_COUNT; ++i) { + for (i = (enum tl_stream_type)0; i < TL_STREAM_TYPE_COUNT; ++i) { struct kbase_tlstream *stream = &timeline->streams[i]; *rb_idx_raw = atomic_read(&stream->rbi); /* Read buffer index may be updated by writer in case of diff --git a/mali_kbase/mali_kbase_tlstream.h b/mali_kbase/mali_kbase_tlstream.h index ed6dca4..5797738 100644 --- a/mali_kbase/mali_kbase_tlstream.h +++ b/mali_kbase/mali_kbase_tlstream.h @@ -93,7 +93,8 @@ struct kbase_tlstream { /* Types of streams generated by timeline. */ enum tl_stream_type { - TL_STREAM_TYPE_OBJ_SUMMARY, + TL_STREAM_TYPE_FIRST, + TL_STREAM_TYPE_OBJ_SUMMARY = TL_STREAM_TYPE_FIRST, TL_STREAM_TYPE_OBJ, TL_STREAM_TYPE_AUX, diff --git a/mali_kbase/mali_kbase_tracepoints.c b/mali_kbase/mali_kbase_tracepoints.c index 2f7784f..2c55127 100644 --- a/mali_kbase/mali_kbase_tracepoints.c +++ b/mali_kbase/mali_kbase_tracepoints.c @@ -109,7 +109,9 @@ enum tl_msg_id_obj { KBASE_TL_EVENT_ARRAY_ITEM_KCPUQUEUE_EXECUTE_JIT_ALLOC_END, KBASE_TL_EVENT_ARRAY_END_KCPUQUEUE_EXECUTE_JIT_ALLOC_END, KBASE_TL_EVENT_KCPUQUEUE_EXECUTE_JIT_FREE_START, - KBASE_TL_EVENT_KCPUQUEUE_EXECUTE_JIT_FREE_END, + KBASE_TL_EVENT_ARRAY_BEGIN_KCPUQUEUE_EXECUTE_JIT_FREE_END, + KBASE_TL_EVENT_ARRAY_ITEM_KCPUQUEUE_EXECUTE_JIT_FREE_END, + KBASE_TL_EVENT_ARRAY_END_KCPUQUEUE_EXECUTE_JIT_FREE_END, KBASE_TL_EVENT_KCPUQUEUE_EXECUTE_ERRORBARRIER, KBASE_OBJ_MSG_COUNT, }; @@ -224,8 +226,8 @@ enum tl_msg_id_aux { "atom") \ TP_DESC(KBASE_TL_ATTRIB_ATOM_JIT, \ "jit done for atom", \ - "@pLLLI", \ - "atom,edit_addr,new_addr,jit_flags,j_id") \ + "@pLLILILLL", \ + "atom,edit_addr,new_addr,jit_flags,mem_flags,j_id,com_pgs,extent,va_pgs") \ TP_DESC(KBASE_TL_JIT_USEDPAGES, \ "used pages for jit", \ "@LI", \ @@ -233,7 +235,7 @@ enum tl_msg_id_aux { TP_DESC(KBASE_TL_ATTRIB_ATOM_JITALLOCINFO, \ "Information about JIT allocations", \ "@pLLLIIIII", \ - "atom,va_pgs,com_pgs,extent,j_id,bin_id,max_allocs,flags,usg_id") \ + "atom,va_pgs,com_pgs,extent,j_id,bin_id,max_allocs,jit_flags,usg_id") \ TP_DESC(KBASE_TL_ATTRIB_ATOM_JITFREEINFO, \ "Information about JIT frees", \ "@pI", \ @@ -424,8 +426,8 @@ enum tl_msg_id_aux { "kcpu_queue") \ TP_DESC(KBASE_TL_EVENT_ARRAY_ITEM_KCPUQUEUE_EXECUTE_JIT_ALLOC_END, \ "Array item of KCPU Queue ends an array of JIT Allocs", \ - "@pLLL", \ - "kcpu_queue,jit_alloc_gpu_alloc_addr,jit_alloc_mmu_flags,jit_alloc_pages_allocated") \ + "@pLL", \ + "kcpu_queue,jit_alloc_gpu_alloc_addr,jit_alloc_mmu_flags") \ TP_DESC(KBASE_TL_EVENT_ARRAY_END_KCPUQUEUE_EXECUTE_JIT_ALLOC_END, \ "End array of KCPU Queue ends an array of JIT Allocs", \ "@p", \ @@ -434,8 +436,16 @@ enum tl_msg_id_aux { "KCPU Queue starts an array of JIT Frees", \ "@p", \ "kcpu_queue") \ - TP_DESC(KBASE_TL_EVENT_KCPUQUEUE_EXECUTE_JIT_FREE_END, \ - "KCPU Queue ends an array of JIT Frees", \ + TP_DESC(KBASE_TL_EVENT_ARRAY_BEGIN_KCPUQUEUE_EXECUTE_JIT_FREE_END, \ + "Begin array of KCPU Queue ends an array of JIT Frees", \ + "@p", \ + "kcpu_queue") \ + TP_DESC(KBASE_TL_EVENT_ARRAY_ITEM_KCPUQUEUE_EXECUTE_JIT_FREE_END, \ + "Array item of KCPU Queue ends an array of JIT Frees", \ + "@pL", \ + "kcpu_queue,jit_free_pages_used") \ + TP_DESC(KBASE_TL_EVENT_ARRAY_END_KCPUQUEUE_EXECUTE_JIT_FREE_END, \ + "End array of KCPU Queue ends an array of JIT Frees", \ "@p", \ "kcpu_queue") \ TP_DESC(KBASE_TL_EVENT_KCPUQUEUE_EXECUTE_ERRORBARRIER, \ @@ -1122,8 +1132,12 @@ void __kbase_tlstream_tl_attrib_atom_jit( const void *atom, u64 edit_addr, u64 new_addr, - u64 jit_flags, - u32 j_id) + u32 jit_flags, + u64 mem_flags, + u32 j_id, + u64 com_pgs, + u64 extent, + u64 va_pgs) { const u32 msg_id = KBASE_TL_ATTRIB_ATOM_JIT; const size_t msg_size = sizeof(msg_id) + sizeof(u64) @@ -1131,7 +1145,11 @@ void __kbase_tlstream_tl_attrib_atom_jit( + sizeof(edit_addr) + sizeof(new_addr) + sizeof(jit_flags) + + sizeof(mem_flags) + sizeof(j_id) + + sizeof(com_pgs) + + sizeof(extent) + + sizeof(va_pgs) ; char *buffer; unsigned long acq_flags; @@ -1150,7 +1168,15 @@ void __kbase_tlstream_tl_attrib_atom_jit( pos = kbasep_serialize_bytes(buffer, pos, &jit_flags, sizeof(jit_flags)); pos = kbasep_serialize_bytes(buffer, + pos, &mem_flags, sizeof(mem_flags)); + pos = kbasep_serialize_bytes(buffer, pos, &j_id, sizeof(j_id)); + pos = kbasep_serialize_bytes(buffer, + pos, &com_pgs, sizeof(com_pgs)); + pos = kbasep_serialize_bytes(buffer, + pos, &extent, sizeof(extent)); + pos = kbasep_serialize_bytes(buffer, + pos, &va_pgs, sizeof(va_pgs)); kbase_tlstream_msgbuf_release(stream, acq_flags); } @@ -1190,7 +1216,7 @@ void __kbase_tlstream_tl_attrib_atom_jitallocinfo( u32 j_id, u32 bin_id, u32 max_allocs, - u32 flags, + u32 jit_flags, u32 usg_id) { const u32 msg_id = KBASE_TL_ATTRIB_ATOM_JITALLOCINFO; @@ -1202,7 +1228,7 @@ void __kbase_tlstream_tl_attrib_atom_jitallocinfo( + sizeof(j_id) + sizeof(bin_id) + sizeof(max_allocs) - + sizeof(flags) + + sizeof(jit_flags) + sizeof(usg_id) ; char *buffer; @@ -1228,7 +1254,7 @@ void __kbase_tlstream_tl_attrib_atom_jitallocinfo( pos = kbasep_serialize_bytes(buffer, pos, &max_allocs, sizeof(max_allocs)); pos = kbasep_serialize_bytes(buffer, - pos, &flags, sizeof(flags)); + pos, &jit_flags, sizeof(jit_flags)); pos = kbasep_serialize_bytes(buffer, pos, &usg_id, sizeof(usg_id)); @@ -2645,15 +2671,13 @@ void __kbase_tlstream_tl_event_array_item_kcpuqueue_execute_jit_alloc_end( struct kbase_tlstream *stream, const void *kcpu_queue, u64 jit_alloc_gpu_alloc_addr, - u64 jit_alloc_mmu_flags, - u64 jit_alloc_pages_allocated) + u64 jit_alloc_mmu_flags) { const u32 msg_id = KBASE_TL_EVENT_ARRAY_ITEM_KCPUQUEUE_EXECUTE_JIT_ALLOC_END; const size_t msg_size = sizeof(msg_id) + sizeof(u64) + sizeof(kcpu_queue) + sizeof(jit_alloc_gpu_alloc_addr) + sizeof(jit_alloc_mmu_flags) - + sizeof(jit_alloc_pages_allocated) ; char *buffer; unsigned long acq_flags; @@ -2669,8 +2693,6 @@ void __kbase_tlstream_tl_event_array_item_kcpuqueue_execute_jit_alloc_end( pos, &jit_alloc_gpu_alloc_addr, sizeof(jit_alloc_gpu_alloc_addr)); pos = kbasep_serialize_bytes(buffer, pos, &jit_alloc_mmu_flags, sizeof(jit_alloc_mmu_flags)); - pos = kbasep_serialize_bytes(buffer, - pos, &jit_alloc_pages_allocated, sizeof(jit_alloc_pages_allocated)); kbase_tlstream_msgbuf_release(stream, acq_flags); } @@ -2719,11 +2741,59 @@ void __kbase_tlstream_tl_event_kcpuqueue_execute_jit_free_start( kbase_tlstream_msgbuf_release(stream, acq_flags); } -void __kbase_tlstream_tl_event_kcpuqueue_execute_jit_free_end( +void __kbase_tlstream_tl_event_array_begin_kcpuqueue_execute_jit_free_end( + struct kbase_tlstream *stream, + const void *kcpu_queue) +{ + const u32 msg_id = KBASE_TL_EVENT_ARRAY_BEGIN_KCPUQUEUE_EXECUTE_JIT_FREE_END; + const size_t msg_size = sizeof(msg_id) + sizeof(u64) + + sizeof(kcpu_queue) + ; + char *buffer; + unsigned long acq_flags; + size_t pos = 0; + + buffer = kbase_tlstream_msgbuf_acquire(stream, msg_size, &acq_flags); + + pos = kbasep_serialize_bytes(buffer, pos, &msg_id, sizeof(msg_id)); + pos = kbasep_serialize_timestamp(buffer, pos); + pos = kbasep_serialize_bytes(buffer, + pos, &kcpu_queue, sizeof(kcpu_queue)); + + kbase_tlstream_msgbuf_release(stream, acq_flags); +} + +void __kbase_tlstream_tl_event_array_item_kcpuqueue_execute_jit_free_end( + struct kbase_tlstream *stream, + const void *kcpu_queue, + u64 jit_free_pages_used) +{ + const u32 msg_id = KBASE_TL_EVENT_ARRAY_ITEM_KCPUQUEUE_EXECUTE_JIT_FREE_END; + const size_t msg_size = sizeof(msg_id) + sizeof(u64) + + sizeof(kcpu_queue) + + sizeof(jit_free_pages_used) + ; + char *buffer; + unsigned long acq_flags; + size_t pos = 0; + + buffer = kbase_tlstream_msgbuf_acquire(stream, msg_size, &acq_flags); + + pos = kbasep_serialize_bytes(buffer, pos, &msg_id, sizeof(msg_id)); + pos = kbasep_serialize_timestamp(buffer, pos); + pos = kbasep_serialize_bytes(buffer, + pos, &kcpu_queue, sizeof(kcpu_queue)); + pos = kbasep_serialize_bytes(buffer, + pos, &jit_free_pages_used, sizeof(jit_free_pages_used)); + + kbase_tlstream_msgbuf_release(stream, acq_flags); +} + +void __kbase_tlstream_tl_event_array_end_kcpuqueue_execute_jit_free_end( struct kbase_tlstream *stream, const void *kcpu_queue) { - const u32 msg_id = KBASE_TL_EVENT_KCPUQUEUE_EXECUTE_JIT_FREE_END; + const u32 msg_id = KBASE_TL_EVENT_ARRAY_END_KCPUQUEUE_EXECUTE_JIT_FREE_END; const size_t msg_size = sizeof(msg_id) + sizeof(u64) + sizeof(kcpu_queue) ; diff --git a/mali_kbase/mali_kbase_tracepoints.h b/mali_kbase/mali_kbase_tracepoints.h index 6447bad..7346493 100644 --- a/mali_kbase/mali_kbase_tracepoints.h +++ b/mali_kbase/mali_kbase_tracepoints.h @@ -180,8 +180,12 @@ void __kbase_tlstream_tl_attrib_atom_jit( const void *atom, u64 edit_addr, u64 new_addr, - u64 jit_flags, - u32 j_id); + u32 jit_flags, + u64 mem_flags, + u32 j_id, + u64 com_pgs, + u64 extent, + u64 va_pgs); void __kbase_tlstream_tl_jit_usedpages( struct kbase_tlstream *stream, u64 used_pages, @@ -195,7 +199,7 @@ void __kbase_tlstream_tl_attrib_atom_jitallocinfo( u32 j_id, u32 bin_id, u32 max_allocs, - u32 flags, + u32 jit_flags, u32 usg_id); void __kbase_tlstream_tl_attrib_atom_jitfreeinfo( struct kbase_tlstream *stream, @@ -410,15 +414,21 @@ void __kbase_tlstream_tl_event_array_item_kcpuqueue_execute_jit_alloc_end( struct kbase_tlstream *stream, const void *kcpu_queue, u64 jit_alloc_gpu_alloc_addr, - u64 jit_alloc_mmu_flags, - u64 jit_alloc_pages_allocated); + u64 jit_alloc_mmu_flags); void __kbase_tlstream_tl_event_array_end_kcpuqueue_execute_jit_alloc_end( struct kbase_tlstream *stream, const void *kcpu_queue); void __kbase_tlstream_tl_event_kcpuqueue_execute_jit_free_start( struct kbase_tlstream *stream, const void *kcpu_queue); -void __kbase_tlstream_tl_event_kcpuqueue_execute_jit_free_end( +void __kbase_tlstream_tl_event_array_begin_kcpuqueue_execute_jit_free_end( + struct kbase_tlstream *stream, + const void *kcpu_queue); +void __kbase_tlstream_tl_event_array_item_kcpuqueue_execute_jit_free_end( + struct kbase_tlstream *stream, + const void *kcpu_queue, + u64 jit_free_pages_used); +void __kbase_tlstream_tl_event_array_end_kcpuqueue_execute_jit_free_end( struct kbase_tlstream *stream, const void *kcpu_queue); void __kbase_tlstream_tl_event_kcpuqueue_execute_errorbarrier( @@ -924,9 +934,16 @@ struct kbase_tlstream; * @atom: Atom identifier * @edit_addr: Address edited by jit * @new_addr: Address placed into the edited location - * @jit_flags: Flags defining the properties of the memory region + * @jit_flags: Flags specifying the special requirements for + * the JIT allocation. + * @mem_flags: Flags defining the properties of a memory region * @j_id: Unique ID provided by the caller, this is used * to pair allocation and free requests. + * @com_pgs: The minimum number of physical pages which + * should back the allocation. + * @extent: Granularity of physical pages to grow the + * allocation by during a fault. + * @va_pgs: The minimum number of virtual pages required */ #define KBASE_TLSTREAM_TL_ATTRIB_ATOM_JIT( \ kbdev, \ @@ -934,14 +951,18 @@ struct kbase_tlstream; edit_addr, \ new_addr, \ jit_flags, \ - j_id \ + mem_flags, \ + j_id, \ + com_pgs, \ + extent, \ + va_pgs \ ) \ do { \ int enabled = atomic_read(&kbdev->timeline_is_enabled); \ if (enabled & BASE_TLSTREAM_JOB_DUMPING_ENABLED) \ __kbase_tlstream_tl_attrib_atom_jit( \ __TL_DISPATCH_STREAM(kbdev, obj), \ - atom, edit_addr, new_addr, jit_flags, j_id); \ + atom, edit_addr, new_addr, jit_flags, mem_flags, j_id, com_pgs, extent, va_pgs); \ } while (0) /** @@ -983,7 +1004,7 @@ struct kbase_tlstream; * max_allocations to limit the number of each * type of JIT allocation. * @max_allocs: Maximum allocations allowed in this bin. - * @flags: Flags specifying the special requirements for + * @jit_flags: Flags specifying the special requirements for * the JIT allocation. * @usg_id: A hint about which allocation should be reused. */ @@ -996,7 +1017,7 @@ struct kbase_tlstream; j_id, \ bin_id, \ max_allocs, \ - flags, \ + jit_flags, \ usg_id \ ) \ do { \ @@ -1004,7 +1025,7 @@ struct kbase_tlstream; if (enabled & TLSTREAM_ENABLED) \ __kbase_tlstream_tl_attrib_atom_jitallocinfo( \ __TL_DISPATCH_STREAM(kbdev, obj), \ - atom, va_pgs, com_pgs, extent, j_id, bin_id, max_allocs, flags, usg_id); \ + atom, va_pgs, com_pgs, extent, j_id, bin_id, max_allocs, jit_flags, usg_id); \ } while (0) /** @@ -1536,7 +1557,7 @@ struct kbase_tlstream; * @kbdev: Kbase device * @kcpu_queue: KCPU queue * @cqs_obj_gpu_addr: CQS Object GPU ptr - * @cqs_obj_compare_value: Semaphore value that should be met or exceeded + * @cqs_obj_compare_value: Semaphore value that should be exceeded * for the WAIT to pass */ #define KBASE_TLSTREAM_TL_EVENT_ARRAY_ITEM_KCPUQUEUE_ENQUEUE_CQS_WAIT( \ @@ -2189,22 +2210,19 @@ struct kbase_tlstream; * @kcpu_queue: KCPU queue * @jit_alloc_gpu_alloc_addr: The JIT allocated GPU virtual address * @jit_alloc_mmu_flags: The MMU flags for the JIT allocation - * @jit_alloc_pages_allocated: The number of pages allocated by the JIT - * allocation */ #define KBASE_TLSTREAM_TL_EVENT_ARRAY_ITEM_KCPUQUEUE_EXECUTE_JIT_ALLOC_END( \ kbdev, \ kcpu_queue, \ jit_alloc_gpu_alloc_addr, \ - jit_alloc_mmu_flags, \ - jit_alloc_pages_allocated \ + jit_alloc_mmu_flags \ ) \ do { \ int enabled = atomic_read(&kbdev->timeline_is_enabled); \ if (enabled & TLSTREAM_ENABLED) \ __kbase_tlstream_tl_event_array_item_kcpuqueue_execute_jit_alloc_end( \ __TL_DISPATCH_STREAM(kbdev, obj), \ - kcpu_queue, jit_alloc_gpu_alloc_addr, jit_alloc_mmu_flags, jit_alloc_pages_allocated); \ + kcpu_queue, jit_alloc_gpu_alloc_addr, jit_alloc_mmu_flags); \ } while (0) /** @@ -2246,20 +2264,61 @@ struct kbase_tlstream; } while (0) /** - * KBASE_TLSTREAM_TL_EVENT_KCPUQUEUE_EXECUTE_JIT_FREE_END - - * KCPU Queue ends an array of JIT Frees + * KBASE_TLSTREAM_TL_EVENT_ARRAY_BEGIN_KCPUQUEUE_EXECUTE_JIT_FREE_END - + * Begin array of KCPU Queue ends an array of JIT Frees + * + * @kbdev: Kbase device + * @kcpu_queue: KCPU queue + */ +#define KBASE_TLSTREAM_TL_EVENT_ARRAY_BEGIN_KCPUQUEUE_EXECUTE_JIT_FREE_END( \ + kbdev, \ + kcpu_queue \ + ) \ + do { \ + int enabled = atomic_read(&kbdev->timeline_is_enabled); \ + if (enabled & TLSTREAM_ENABLED) \ + __kbase_tlstream_tl_event_array_begin_kcpuqueue_execute_jit_free_end( \ + __TL_DISPATCH_STREAM(kbdev, obj), \ + kcpu_queue); \ + } while (0) + +/** + * KBASE_TLSTREAM_TL_EVENT_ARRAY_ITEM_KCPUQUEUE_EXECUTE_JIT_FREE_END - + * Array item of KCPU Queue ends an array of JIT Frees + * + * @kbdev: Kbase device + * @kcpu_queue: KCPU queue + * @jit_free_pages_used: The actual number of pages used by the JIT + * allocation + */ +#define KBASE_TLSTREAM_TL_EVENT_ARRAY_ITEM_KCPUQUEUE_EXECUTE_JIT_FREE_END( \ + kbdev, \ + kcpu_queue, \ + jit_free_pages_used \ + ) \ + do { \ + int enabled = atomic_read(&kbdev->timeline_is_enabled); \ + if (enabled & TLSTREAM_ENABLED) \ + __kbase_tlstream_tl_event_array_item_kcpuqueue_execute_jit_free_end( \ + __TL_DISPATCH_STREAM(kbdev, obj), \ + kcpu_queue, jit_free_pages_used); \ + } while (0) + +/** + * KBASE_TLSTREAM_TL_EVENT_ARRAY_END_KCPUQUEUE_EXECUTE_JIT_FREE_END - + * End array of KCPU Queue ends an array of JIT Frees * * @kbdev: Kbase device * @kcpu_queue: KCPU queue */ -#define KBASE_TLSTREAM_TL_EVENT_KCPUQUEUE_EXECUTE_JIT_FREE_END( \ +#define KBASE_TLSTREAM_TL_EVENT_ARRAY_END_KCPUQUEUE_EXECUTE_JIT_FREE_END( \ kbdev, \ kcpu_queue \ ) \ do { \ int enabled = atomic_read(&kbdev->timeline_is_enabled); \ if (enabled & TLSTREAM_ENABLED) \ - __kbase_tlstream_tl_event_kcpuqueue_execute_jit_free_end( \ + __kbase_tlstream_tl_event_array_end_kcpuqueue_execute_jit_free_end( \ __TL_DISPATCH_STREAM(kbdev, obj), \ kcpu_queue); \ } while (0) diff --git a/mali_kbase/mali_kbase_vinstr.c b/mali_kbase/mali_kbase_vinstr.c index 51cb365..377642d 100644 --- a/mali_kbase/mali_kbase_vinstr.c +++ b/mali_kbase/mali_kbase_vinstr.c @@ -1,6 +1,6 @@ /* * - * (C) COPYRIGHT 2011-2018 ARM Limited. All rights reserved. + * (C) COPYRIGHT 2011-2019 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the * GNU General Public License version 2 as published by the Free Software @@ -124,6 +124,7 @@ static int kbasep_vinstr_hwcnt_reader_release( /* Vinstr client file operations */ static const struct file_operations vinstr_client_fops = { + .owner = THIS_MODULE, .poll = kbasep_vinstr_hwcnt_reader_poll, .unlocked_ioctl = kbasep_vinstr_hwcnt_reader_ioctl, .compat_ioctl = kbasep_vinstr_hwcnt_reader_ioctl, diff --git a/mali_kbase/mali_midg_regmap.h b/mali_kbase/mali_midg_regmap.h index 45f7c14..a4aba19 100644 --- a/mali_kbase/mali_midg_regmap.h +++ b/mali_kbase/mali_midg_regmap.h @@ -325,6 +325,96 @@ #define AS_COMMAND_FLUSH_MEM 0x05 /* Wait for memory accesses to complete, flush all the L1s cache then flush all L2 caches then issue a flush region command to all MMUs */ +#if GPU_HAS_CSF_VERSION_10_REVISION_2 +/* GPU_COMMAND codes */ +#define GPU_COMMAND_CODE_NOP 0x00 /* No operation, nothing happens */ +#define GPU_COMMAND_CODE_RESET 0x01 /* Reset the GPU */ +#define GPU_COMMAND_CODE_PRFCNT 0x02 /* Clear or sample performance counters */ +#define GPU_COMMAND_CODE_TIME 0x03 /* Configure time sources */ +#define GPU_COMMAND_CODE_FLUSH_CACHES 0x04 /* Flush caches */ +#define GPU_COMMAND_CODE_SET_PROTECTED_MODE 0x05 /* Places the GPU in protected mode */ +#define GPU_COMMAND_CODE_FINISH_HALT 0x06 /* Halt CSF */ + +/* GPU_COMMAND_RESET payloads */ + +/* This will leave the state of active jobs UNDEFINED, but will leave the external bus in a defined and idle state. + * Power domains will remain powered on. + */ +#define GPU_COMMAND_RESET_PAYLOAD_FAST_RESET 0x00 + +/* This will leave the state of active command streams UNDEFINED, but will leave the external bus in a defined and + * idle state. + */ +#define GPU_COMMAND_RESET_PAYLOAD_SOFT_RESET 0x01 + +/* This reset will leave the state of currently active streams UNDEFINED, will likely lose data, and may leave + * the system bus in an inconsistent state. Use only as a last resort when nothing else works. + */ +#define GPU_COMMAND_RESET_PAYLOAD_HARD_RESET 0x02 + +/* GPU_COMMAND_PRFCNT payloads */ +#define GPU_COMMAND_PRFCNT_PAYLOAD_SAMPLE 0x01 /* Sample performance counters */ +#define GPU_COMMAND_PRFCNT_PAYLOAD_CLEAR 0x02 /* Clear performance counters */ + +/* GPU_COMMAND_TIME payloads */ +#define GPU_COMMAND_TIME_DISABLE 0x00 /* Disable cycle counter */ +#define GPU_COMMAND_TIME_ENABLE 0x01 /* Enable cycle counter */ + +/* GPU_COMMAND_FLUSH_CACHES payloads */ +#define GPU_COMMAND_FLUSH_PAYLOAD_NONE 0x00 /* No flush */ +#define GPU_COMMAND_FLUSH_PAYLOAD_CLEAN 0x01 /* Clean the caches */ +#define GPU_COMMAND_FLUSH_PAYLOAD_INVALIDATE 0x02 /* Invalidate the caches */ +#define GPU_COMMAND_FLUSH_PAYLOAD_CLEAN_INVALIDATE 0x03 /* Clean and invalidate the caches */ + +/* GPU_COMMAND command + payload */ +#define GPU_COMMAND_CODE_PAYLOAD(opcode, payload) \ + ((u32)opcode || ((u32)payload << 8)) + +/* Final GPU_COMMAND form */ +/* No operation, nothing happens */ +#define GPU_COMMAND_NOP \ + GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_NOP, 0) + +/* Stop all external bus interfaces, and then reset the entire GPU. */ +#define GPU_COMMAND_SOFT_RESET \ + GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_RESET, GPU_COMMAND_RESET_PAYLOAD_SOFT_RESET) + +/* Immediately reset the entire GPU. */ +#define GPU_COMMAND_HARD_RESET \ + GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_RESET, GPU_COMMAND_RESET_PAYLOAD_HARD_RESET) + +/* Clear all performance counters, setting them all to zero. */ +#define GPU_COMMAND_PRFCNT_CLEAR \ + GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_PRFCNT, GPU_COMMAND_PRFCNT_PAYLOAD_CLEAR) + +/* Sample all performance counters, writing them out to memory */ +#define GPU_COMMAND_PRFCNT_SAMPLE \ + GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_PRFCNT, GPU_COMMAND_PRFCNT_PAYLOAD_SAMPLE) + +/* Starts the cycle counter, and system timestamp propagation */ +#define GPU_COMMAND_CYCLE_COUNT_START \ + GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_TIME, GPU_COMMAND_TIME_ENABLE) + +/* Stops the cycle counter, and system timestamp propagation */ +#define GPU_COMMAND_CYCLE_COUNT_STOP \ + GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_TIME, GPU_COMMAND_TIME_DISABLE) + +/* Clean all caches */ +#define GPU_COMMAND_CLEAN_CACHES \ + GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_FLUSH_CACHES, GPU_COMMAND_FLUSH_PAYLOAD_CLEAN) + +/* Clean and invalidate all caches */ +#define GPU_COMMAND_CLEAN_INV_CACHES \ + GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_FLUSH_CACHES, GPU_COMMAND_FLUSH_PAYLOAD_CLEAN_INVALIDATE) + +/* Places the GPU in protected mode */ +#define GPU_COMMAND_SET_PROTECTED_MODE \ + GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_SET_PROTECTED_MODE, 0) + +/* Halt CSF */ +#define GPU_COMMAND_FINISH_HALT \ + GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_FINISH_HALT, 0) +#else /* GPU_COMMAND values */ #define GPU_COMMAND_NOP 0x00 /* No operation, nothing happens */ #define GPU_COMMAND_SOFT_RESET 0x01 /* Stop all external bus interfaces, and then reset the entire GPU. */ @@ -336,6 +426,8 @@ #define GPU_COMMAND_CLEAN_CACHES 0x07 /* Clean all caches */ #define GPU_COMMAND_CLEAN_INV_CACHES 0x08 /* Clean and invalidate all caches */ #define GPU_COMMAND_SET_PROTECTED_MODE 0x09 /* Places the GPU in protected mode */ +#endif + /* End Command Values */ diff --git a/mali_kbase/platform/devicetree/mali_kbase_runtime_pm.c b/mali_kbase/platform/devicetree/mali_kbase_runtime_pm.c index c5f3ad7..8772edb 100644 --- a/mali_kbase/platform/devicetree/mali_kbase_runtime_pm.c +++ b/mali_kbase/platform/devicetree/mali_kbase_runtime_pm.c @@ -1,6 +1,6 @@ /* * - * (C) COPYRIGHT 2015, 2017 ARM Limited. All rights reserved. + * (C) COPYRIGHT 2015, 2017-2019 ARM Limited. All rights reserved. * * This program is free software and is provided to you under the terms of the * GNU General Public License version 2 as published by the Free Software @@ -23,8 +23,56 @@ #include <mali_kbase.h> #include <mali_kbase_defs.h> #include <linux/pm_runtime.h> +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/regulator/consumer.h> #include "mali_kbase_config_platform.h" +static void enable_gpu_power_control(struct kbase_device *kbdev) +{ + unsigned int i; + +#if defined(CONFIG_REGULATOR) + for (i = 0; i < kbdev->nr_regulators; i++) { + if (WARN_ON(kbdev->regulators[i] == NULL)) + ; + else if (!regulator_is_enabled(kbdev->regulators[i])) + WARN_ON(regulator_enable(kbdev->regulators[i])); + } +#endif + + for (i = 0; i < kbdev->nr_clocks; i++) { + if (WARN_ON(kbdev->clocks[i] == NULL)) + ; + else if (!__clk_is_enabled(kbdev->clocks[i])) + WARN_ON(clk_prepare_enable(kbdev->clocks[i])); + } +} + +static void disable_gpu_power_control(struct kbase_device *kbdev) +{ + unsigned int i; + + for (i = 0; i < kbdev->nr_clocks; i++) { + if (WARN_ON(kbdev->clocks[i] == NULL)) + ; + else if (__clk_is_enabled(kbdev->clocks[i])) { + clk_disable_unprepare(kbdev->clocks[i]); + WARN_ON(__clk_is_enabled(kbdev->clocks[i])); + } + + } + +#if defined(CONFIG_REGULATOR) + for (i = 0; i < kbdev->nr_regulators; i++) { + if (WARN_ON(kbdev->regulators[i] == NULL)) + ; + else if (regulator_is_enabled(kbdev->regulators[i])) + WARN_ON(regulator_disable(kbdev->regulators[i])); + } +#endif +} + static int pm_callback_power_on(struct kbase_device *kbdev) { int ret = 1; /* Assume GPU has been powered off */ @@ -33,6 +81,8 @@ static int pm_callback_power_on(struct kbase_device *kbdev) dev_dbg(kbdev->dev, "pm_callback_power_on %p\n", (void *)kbdev->dev->pm_domain); + enable_gpu_power_control(kbdev); + error = pm_runtime_get_sync(kbdev->dev); if (error == 1) { /* @@ -53,6 +103,10 @@ static void pm_callback_power_off(struct kbase_device *kbdev) pm_runtime_mark_last_busy(kbdev->dev); pm_runtime_put_autosuspend(kbdev->dev); + +#ifndef KBASE_PM_RUNTIME + disable_gpu_power_control(kbdev); +#endif } #ifdef KBASE_PM_RUNTIME @@ -87,12 +141,15 @@ static int pm_callback_runtime_on(struct kbase_device *kbdev) { dev_dbg(kbdev->dev, "pm_callback_runtime_on\n"); + enable_gpu_power_control(kbdev); return 0; } static void pm_callback_runtime_off(struct kbase_device *kbdev) { dev_dbg(kbdev->dev, "pm_callback_runtime_off\n"); + + disable_gpu_power_control(kbdev); } static void pm_callback_resume(struct kbase_device *kbdev) diff --git a/mali_kbase/tests/build.bp b/mali_kbase/tests/build.bp deleted file mode 100644 index a0823c7..0000000 --- a/mali_kbase/tests/build.bp +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright: - * ---------------------------------------------------------------------------- - * This confidential and proprietary software may be used only as authorized - * by a licensing agreement from ARM Limited. - * (C) COPYRIGHT 2018 ARM Limited, ALL RIGHTS RESERVED - * The entire notice above must be reproduced on all authorized copies and - * copies may only be made to the extent permitted by a licensing agreement - * from ARM Limited. - * ---------------------------------------------------------------------------- - */ - -bob_defaults { - name: "kernel_test_module_defaults", - defaults: ["mali_kbase_shared_config_defaults"], - include_dirs: [ - "kernel/drivers/gpu/arm", - "kernel/drivers/gpu/arm/midgard", - "kernel/drivers/gpu/arm/midgard/backend/gpu", - "kernel/drivers/gpu/arm/midgard/tests/include", - ], -} diff --git a/mali_kbase/tests/kutf/build.bp b/mali_kbase/tests/kutf/build.bp index 960c8fa..f0c7a0c 100644 --- a/mali_kbase/tests/kutf/build.bp +++ b/mali_kbase/tests/kutf/build.bp @@ -3,7 +3,7 @@ * ---------------------------------------------------------------------------- * This confidential and proprietary software may be used only as authorized * by a licensing agreement from ARM Limited. - * (C) COPYRIGHT 2018 ARM Limited, ALL RIGHTS RESERVED + * (C) COPYRIGHT 2018-2019 ARM Limited, ALL RIGHTS RESERVED * The entire notice above must be reproduced on all authorized copies and * copies may only be made to the extent permitted by a licensing agreement * from ARM Limited. @@ -12,7 +12,10 @@ bob_kernel_module { name: "kutf", - defaults: ["kernel_defaults"], + defaults: [ + "kernel_defaults", + "kutf_includes", + ], srcs: [ "Kbuild", "kutf_helpers.c", @@ -23,7 +26,6 @@ bob_kernel_module { "kutf_utils.c", ], kbuild_options: ["CONFIG_MALI_KUTF=m"], - include_dirs: ["kernel/drivers/gpu/arm/midgard/tests/include"], enabled: false, base_build_kutf: { enabled: true, diff --git a/mali_kbase/tests/mali_kutf_irq_test/build.bp b/mali_kbase/tests/mali_kutf_irq_test/build.bp index 66f4eb3..971f092 100644 --- a/mali_kbase/tests/mali_kutf_irq_test/build.bp +++ b/mali_kbase/tests/mali_kutf_irq_test/build.bp @@ -3,7 +3,7 @@ * ---------------------------------------------------------------------------- * This confidential and proprietary software may be used only as authorized * by a licensing agreement from ARM Limited. - * (C) COPYRIGHT 2018 ARM Limited, ALL RIGHTS RESERVED + * (C) COPYRIGHT 2018-2019 ARM Limited, ALL RIGHTS RESERVED * The entire notice above must be reproduced on all authorized copies and * copies may only be made to the extent permitted by a licensing agreement * from ARM Limited. @@ -12,7 +12,10 @@ bob_kernel_module { name: "mali_kutf_irq_test", - defaults: ["kernel_test_module_defaults"], + defaults: [ + "mali_kbase_shared_config_defaults", + "kernel_test_includes", + ], srcs: [ "Kbuild", "mali_kutf_irq_test_main.c", diff --git a/mali_mgm/memory_group_manager.c b/mali_mgm/memory_group_manager.c index 7b208d5..5e0ff3a 100644 --- a/mali_mgm/memory_group_manager.c +++ b/mali_mgm/memory_group_manager.c @@ -29,14 +29,45 @@ #ifdef CONFIG_DEBUG_FS #include <linux/debugfs.h> #endif +#include <linux/mm.h> #include <linux/memory_group_manager.h> +#if (KERNEL_VERSION(4, 17, 0) > LINUX_VERSION_CODE) +static inline vm_fault_t vmf_insert_pfn(struct vm_area_struct *vma, + unsigned long addr, unsigned long pfn) +{ + int err = vm_insert_pfn(vma, addr, pfn); + + if (unlikely(err == -ENOMEM)) + return VM_FAULT_OOM; + if (unlikely(err < 0 && err != -EBUSY)) + return VM_FAULT_SIGBUS; + + return VM_FAULT_NOPAGE; +} +#endif + +#if (KERNEL_VERSION(4, 20, 0) > LINUX_VERSION_CODE) +static inline vm_fault_t vmf_insert_pfn_prot(struct vm_area_struct *vma, + unsigned long addr, unsigned long pfn, pgprot_t pgprot) +{ + if (pgprot_val(pgprot) != pgprot_val(vma->vm_page_prot)) + return VM_FAULT_SIGBUS; + + return vmf_insert_pfn(vma, addr, pfn); +} +#endif + +#define IMPORTED_MEMORY_ID (MEMORY_GROUP_MANAGER_NR_GROUPS - 1) + /** * struct mgm_group - Structure to keep track of the number of allocated * pages per group * * @size: The number of allocated small(4KB) pages * @lp_size: The number of allocated large(2MB) pages + * @insert_pfn: The number of calls to map pages for CPU access. + * @update_gpu_pte: The number of calls to update GPU page table entries. * * This structure allows page allocation information to be displayed via * debugfs. Display is organized per group with small and large sized pages. @@ -44,6 +75,8 @@ struct mgm_group { size_t size; size_t lp_size; + size_t insert_pfn; + size_t update_gpu_pte; }; /** @@ -84,9 +117,33 @@ static int mgm_lp_size_get(void *data, u64 *val) return 0; } +static int mgm_insert_pfn_get(void *data, u64 *val) +{ + struct mgm_group *group = data; + + *val = group->insert_pfn; + + return 0; +} + +static int mgm_update_gpu_pte_get(void *data, u64 *val) +{ + struct mgm_group *group = data; + + *val = group->update_gpu_pte; + + return 0; +} + DEFINE_SIMPLE_ATTRIBUTE(fops_mgm_size, mgm_size_get, NULL, "%llu\n"); DEFINE_SIMPLE_ATTRIBUTE(fops_mgm_lp_size, mgm_lp_size_get, NULL, "%llu\n"); +DEFINE_SIMPLE_ATTRIBUTE(fops_mgm_insert_pfn, mgm_insert_pfn_get, NULL, + "%llu\n"); + +DEFINE_SIMPLE_ATTRIBUTE(fops_mgm_update_gpu_pte, mgm_update_gpu_pte_get, NULL, + "%llu\n"); + static void mgm_term_debugfs(struct mgm_groups *data) { debugfs_remove_recursive(data->mgm_debugfs_root); @@ -136,6 +193,22 @@ static int mgm_initialize_debugfs(struct mgm_groups *mgm_data) "fail to create lp_size[%d]\n", i); goto remove_debugfs; } + + e = debugfs_create_file("insert_pfn", 0444, g, + &mgm_data->groups[i], &fops_mgm_insert_pfn); + if (IS_ERR(e)) { + dev_err(mgm_data->dev, + "fail to create insert_pfn[%d]\n", i); + goto remove_debugfs; + } + + e = debugfs_create_file("update_gpu_pte", 0444, g, + &mgm_data->groups[i], &fops_mgm_update_gpu_pte); + if (IS_ERR(e)) { + dev_err(mgm_data->dev, + "fail to create update_gpu_pte[%d]\n", i); + goto remove_debugfs; + } } return 0; @@ -194,10 +267,15 @@ static struct page *example_mgm_alloc_page( struct memory_group_manager_device *mgm_dev, int group_id, gfp_t gfp_mask, unsigned int order) { + struct mgm_groups *const data = mgm_dev->data; struct page *p; - WARN_ON(group_id < 0); - WARN_ON(group_id >= MEMORY_GROUP_MANAGER_NR_GROUPS); + dev_dbg(data->dev, "%s(mgm_dev=%p, group_id=%d gfp_mask=0x%x order=%u\n", + __func__, (void *)mgm_dev, group_id, gfp_mask, order); + + if (WARN_ON(group_id < 0) || + WARN_ON(group_id >= MEMORY_GROUP_MANAGER_NR_GROUPS)) + return NULL; p = alloc_pages(gfp_mask, order); @@ -216,14 +294,90 @@ static void example_mgm_free_page( struct memory_group_manager_device *mgm_dev, int group_id, struct page *page, unsigned int order) { - WARN_ON(group_id < 0); - WARN_ON(group_id >= MEMORY_GROUP_MANAGER_NR_GROUPS); + struct mgm_groups *const data = mgm_dev->data; + + dev_dbg(data->dev, "%s(mgm_dev=%p, group_id=%d page=%p order=%u\n", + __func__, (void *)mgm_dev, group_id, (void *)page, order); + + if (WARN_ON(group_id < 0) || + WARN_ON(group_id >= MEMORY_GROUP_MANAGER_NR_GROUPS)) + return; __free_pages(page, order); update_size(mgm_dev, group_id, order, false); } +static int example_mgm_get_import_memory_id( + struct memory_group_manager_device *mgm_dev, + struct memory_group_manager_import_data *import_data) +{ + struct mgm_groups *const data = mgm_dev->data; + + dev_dbg(data->dev, "%s(mgm_dev=%p, import_data=%p (type=%d)\n", + __func__, (void *)mgm_dev, (void *)import_data, + (int)import_data->type); + + if (!WARN_ON(!import_data)) { + WARN_ON(!import_data->u.dma_buf); + + WARN_ON(import_data->type != + MEMORY_GROUP_MANAGER_IMPORT_TYPE_DMA_BUF); + } + + return IMPORTED_MEMORY_ID; +} + +static u64 example_mgm_update_gpu_pte( + struct memory_group_manager_device *const mgm_dev, int const group_id, + int const mmu_level, u64 pte) +{ + struct mgm_groups *const data = mgm_dev->data; + const u32 pbha_bit_pos = 59; /* bits 62:59 */ + const u32 pbha_bit_mask = 0xf; /* 4-bit */ + + dev_dbg(data->dev, + "%s(mgm_dev=%p, group_id=%d, mmu_level=%d, pte=0x%llx)\n", + __func__, (void *)mgm_dev, group_id, mmu_level, pte); + + if (WARN_ON(group_id < 0) || + WARN_ON(group_id >= MEMORY_GROUP_MANAGER_NR_GROUPS)) + return pte; + + pte |= ((u64)group_id & pbha_bit_mask) << pbha_bit_pos; + + data->groups[group_id].update_gpu_pte++; + + return pte; +} + +static vm_fault_t example_mgm_vmf_insert_pfn_prot( + struct memory_group_manager_device *const mgm_dev, int const group_id, + struct vm_area_struct *const vma, unsigned long const addr, + unsigned long const pfn, pgprot_t const prot) +{ + struct mgm_groups *const data = mgm_dev->data; + vm_fault_t fault; + + dev_dbg(data->dev, + "%s(mgm_dev=%p, group_id=%d, vma=%p, addr=0x%lx, pfn=0x%lx, prot=0x%llx)\n", + __func__, (void *)mgm_dev, group_id, (void *)vma, addr, pfn, + pgprot_val(prot)); + + if (WARN_ON(group_id < 0) || + WARN_ON(group_id >= MEMORY_GROUP_MANAGER_NR_GROUPS)) + return VM_FAULT_SIGBUS; + + fault = vmf_insert_pfn_prot(vma, addr, pfn, prot); + + if (fault == VM_FAULT_NOPAGE) + data->groups[group_id].insert_pfn++; + else + dev_err(data->dev, "vmf_insert_pfn_prot failed\n"); + + return fault; +} + static int mgm_initialize_data(struct mgm_groups *mgm_data) { int i; @@ -231,6 +385,8 @@ static int mgm_initialize_data(struct mgm_groups *mgm_data) for (i = 0; i < MEMORY_GROUP_MANAGER_NR_GROUPS; i++) { mgm_data->groups[i].size = 0; mgm_data->groups[i].lp_size = 0; + mgm_data->groups[i].insert_pfn = 0; + mgm_data->groups[i].update_gpu_pte = 0; } return mgm_initialize_debugfs(mgm_data); @@ -263,8 +419,13 @@ static int memory_group_manager_probe(struct platform_device *pdev) if (!mgm_dev) return -ENOMEM; + mgm_dev->owner = THIS_MODULE; mgm_dev->ops.mgm_alloc_page = example_mgm_alloc_page; mgm_dev->ops.mgm_free_page = example_mgm_free_page; + mgm_dev->ops.mgm_get_import_memory_id = + example_mgm_get_import_memory_id; + mgm_dev->ops.mgm_vmf_insert_pfn_prot = example_mgm_vmf_insert_pfn_prot; + mgm_dev->ops.mgm_update_gpu_pte = example_mgm_update_gpu_pte; mgm_data = kzalloc(sizeof(*mgm_data), GFP_KERNEL); if (!mgm_data) { @@ -316,6 +477,12 @@ static struct platform_driver memory_group_manager_driver = { .name = "physical-memory-group-manager", .owner = THIS_MODULE, .of_match_table = of_match_ptr(memory_group_manager_dt_ids), + /* + * Prevent the mgm_dev from being unbound and freed, as other's + * may have pointers to it and would get confused, or crash, if + * it suddenly disappear. + */ + .suppress_bind_attrs = true, } }; |