diff options
Diffstat (limited to 'common/include/uapi/gpu/arm/midgard/csf/mali_gpu_csf_registers.h')
| -rw-r--r-- | common/include/uapi/gpu/arm/midgard/csf/mali_gpu_csf_registers.h | 50 |
1 files changed, 35 insertions, 15 deletions
diff --git a/common/include/uapi/gpu/arm/midgard/csf/mali_gpu_csf_registers.h b/common/include/uapi/gpu/arm/midgard/csf/mali_gpu_csf_registers.h index 06cc4c2..a5dc745 100644 --- a/common/include/uapi/gpu/arm/midgard/csf/mali_gpu_csf_registers.h +++ b/common/include/uapi/gpu/arm/midgard/csf/mali_gpu_csf_registers.h @@ -20,7 +20,8 @@ */ /* - * This header was autogenerated, it should not be edited. + * This header was originally autogenerated, but it is now ok (and + * expected) to have to add to it. */ #ifndef _UAPI_GPU_CSF_REGISTERS_H_ @@ -212,7 +213,6 @@ #define GLB_PWROFF_TIMER 0x0014 /* () Global shader core power off timer */ #define GLB_ALLOC_EN_LO 0x0018 /* () Global shader core allocation enable mask, low word */ #define GLB_ALLOC_EN_HI 0x001C /* () Global shader core allocation enable mask, high word */ -#define GLB_PROTM_COHERENCY 0x0020 /* () Configure COHERENCY_ENABLE register value to use in protected mode execution */ #define GLB_PRFCNT_JASID 0x0024 /* () Performance counter address space */ #define GLB_PRFCNT_BASE_LO 0x0028 /* () Performance counter buffer address, low word */ @@ -653,7 +653,9 @@ (((reg_val) & ~CS_FAULT_EXCEPTION_TYPE_MASK) | \ (((value) << CS_FAULT_EXCEPTION_TYPE_SHIFT) & CS_FAULT_EXCEPTION_TYPE_MASK)) /* CS_FAULT_EXCEPTION_TYPE values */ +#define CS_FAULT_EXCEPTION_TYPE_KABOOM 0x05 #define CS_FAULT_EXCEPTION_TYPE_CS_RESOURCE_TERMINATED 0x0F +#define CS_FAULT_EXCEPTION_TYPE_CS_BUS_FAULT 0x48 #define CS_FAULT_EXCEPTION_TYPE_CS_INHERIT_FAULT 0x4B #define CS_FAULT_EXCEPTION_TYPE_INSTR_INVALID_PC 0x50 #define CS_FAULT_EXCEPTION_TYPE_INSTR_INVALID_ENC 0x51 @@ -1164,6 +1166,13 @@ (((reg_val) & ~GLB_REQ_FIRMWARE_CONFIG_UPDATE_MASK) | \ (((value) << GLB_REQ_FIRMWARE_CONFIG_UPDATE_SHIFT) & \ GLB_REQ_FIRMWARE_CONFIG_UPDATE_MASK)) +#define GLB_REQ_SLEEP_SHIFT 12 +#define GLB_REQ_SLEEP_MASK (0x1 << GLB_REQ_SLEEP_SHIFT) +#define GLB_REQ_SLEEP_GET(reg_val) \ + (((reg_val) & GLB_REQ_SLEEP_MASK) >> GLB_REQ_SLEEP_SHIFT) +#define GLB_REQ_SLEEP_SET(reg_val, value) \ + (((reg_val) & ~GLB_REQ_SLEEP_MASK) | \ + (((value) << GLB_REQ_SLEEP_SHIFT) & GLB_REQ_SLEEP_MASK)) #define GLB_REQ_INACTIVE_COMPUTE_SHIFT 20 #define GLB_REQ_INACTIVE_COMPUTE_MASK (0x1 << GLB_REQ_INACTIVE_COMPUTE_SHIFT) #define GLB_REQ_INACTIVE_COMPUTE_GET(reg_val) \ @@ -1391,19 +1400,6 @@ #define GLB_ALLOC_EN_MASK_SET(reg_val, value) \ (((reg_val) & ~GLB_ALLOC_EN_MASK_MASK) | (((value) << GLB_ALLOC_EN_MASK_SHIFT) & GLB_ALLOC_EN_MASK_MASK)) -/* GLB_PROTM_COHERENCY register */ -#define GLB_PROTM_COHERENCY_L2_CACHE_PROTOCOL_SELECT_SHIFT 0 -#define GLB_PROTM_COHERENCY_L2_CACHE_PROTOCOL_SELECT_MASK \ - (0xFFFFFFFF << GLB_PROTM_COHERENCY_L2_CACHE_PROTOCOL_SELECT_SHIFT) -#define GLB_PROTM_COHERENCY_L2_CACHE_PROTOCOL_SELECT_GET(reg_val) \ - (((reg_val)&GLB_PROTM_COHERENCY_L2_CACHE_PROTOCOL_SELECT_MASK) >> \ - GLB_PROTM_COHERENCY_L2_CACHE_PROTOCOL_SELECT_SHIFT) -#define GLB_PROTM_COHERENCY_L2_CACHE_PROTOCOL_SELECT_SET(reg_val, value) \ - (((reg_val) & ~GLB_PROTM_COHERENCY_L2_CACHE_PROTOCOL_SELECT_MASK) | \ - (((value) << GLB_PROTM_COHERENCY_L2_CACHE_PROTOCOL_SELECT_SHIFT) & \ - GLB_PROTM_COHERENCY_L2_CACHE_PROTOCOL_SELECT_MASK)) -/* End of GLB_INPUT_BLOCK register set definitions */ - /* GLB_OUTPUT_BLOCK register set definitions */ /* GLB_ACK register */ @@ -1485,4 +1481,28 @@ (((reg_val) & ~CSG_STATUS_STATE_IDLE_MASK) | \ (((value) << CSG_STATUS_STATE_IDLE_SHIFT) & CSG_STATUS_STATE_IDLE_MASK)) +/* GLB_FEATURES_ITER_TRACE_SUPPORTED register */ +#define GLB_FEATURES_ITER_TRACE_SUPPORTED_SHIFT GPU_U(4) +#define GLB_FEATURES_ITER_TRACE_SUPPORTED_MASK \ + (GPU_U(0x1) << GLB_FEATURES_ITER_TRACE_SUPPORTED_SHIFT) +#define GLB_FEATURES_ITER_TRACE_SUPPORTED_GET(reg_val) \ + (((reg_val)&GLB_FEATURES_ITER_TRACE_SUPPORTED_MASK) >> \ + GLB_FEATURES_ITER_TRACE_SUPPORTED_SHIFT) +#define GLB_FEATURES_ITER_TRACE_SUPPORTED_SET(reg_val, value) \ + (((reg_val) & ~GLB_FEATURES_ITER_TRACE_SUPPORTED_MASK) | \ + (((value) << GLB_FEATURES_ITER_TRACE_SUPPORTED_SHIFT) & \ + GLB_FEATURES_ITER_TRACE_SUPPORTED_MASK)) + +/* GLB_REQ_ITER_TRACE_ENABLE register */ +#define GLB_REQ_ITER_TRACE_ENABLE_SHIFT GPU_U(11) +#define GLB_REQ_ITER_TRACE_ENABLE_MASK \ + (GPU_U(0x1) << GLB_REQ_ITER_TRACE_ENABLE_SHIFT) +#define GLB_REQ_ITER_TRACE_ENABLE_GET(reg_val) \ + (((reg_val)&GLB_REQ_ITER_TRACE_ENABLE_MASK) >> \ + GLB_REQ_ITER_TRACE_ENABLE_SHIFT) +#define GLB_REQ_ITER_TRACE_ENABLE_SET(reg_val, value) \ + (((reg_val) & ~GLB_REQ_ITER_TRACE_ENABLE_MASK) | \ + (((value) << GLB_REQ_ITER_TRACE_ENABLE_SHIFT) & \ + GLB_REQ_ITER_TRACE_ENABLE_MASK)) + #endif /* _UAPI_GPU_CSF_REGISTERS_H_ */ |