From 2bfaaa5f53c45ab7b4f6daba20e92ef6d16ab53b Mon Sep 17 00:00:00 2001 From: Sidath Senanayake Date: Thu, 17 Jun 2021 17:58:22 +0100 Subject: Mali Valhall DDK r32p1 BETA KMD Provenance: 59f633569 (collaborate/google/android/v_r32p1-00bet0) VX504X08X-BU-00000-r32p1-00bet0 - Valhall Android DDK VX504X08X-BU-60000-r32p1-00bet0 - Valhall Android Document Bundle VX504X08X-DC-11001-r32p1-00bet0 - Valhall Android DDK Software Errata VX504X08X-SW-99006-r32p1-00bet0 - Valhall Android Renderscript AOSP parts Signed-off-by: Sidath Senanayake Change-Id: I6c9fc6e1e9f2e58bc804eb79582ad7afaafdef1b --- .../midgard/backend/gpu/mali_kbase_model_dummy.h | 53 --------------- .../gpu/arm/midgard/csf/mali_gpu_csf_registers.h | 76 +++++++++++++++++++++- .../gpu/arm/midgard/csf/mali_kbase_csf_ioctl.h | 47 ++++++++++++- .../uapi/gpu/arm/midgard/gpu/mali_kbase_gpu_id.h | 2 + .../gpu/arm/midgard/gpu/mali_kbase_gpu_regmap.h | 10 +++ 5 files changed, 132 insertions(+), 56 deletions(-) delete mode 100644 common/include/uapi/gpu/arm/midgard/backend/gpu/mali_kbase_model_dummy.h (limited to 'common/include/uapi/gpu/arm') diff --git a/common/include/uapi/gpu/arm/midgard/backend/gpu/mali_kbase_model_dummy.h b/common/include/uapi/gpu/arm/midgard/backend/gpu/mali_kbase_model_dummy.h deleted file mode 100644 index 61da071..0000000 --- a/common/include/uapi/gpu/arm/midgard/backend/gpu/mali_kbase_model_dummy.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * - * (C) COPYRIGHT 2021 ARM Limited. All rights reserved. - * - * This program is free software and is provided to you under the terms of the - * GNU General Public License version 2 as published by the Free Software - * Foundation, and any use by you of this program is subject to the terms - * of such GNU license. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, you can access it online at - * http://www.gnu.org/licenses/gpl-2.0.html. - * - */ - -/* - * Dummy Model interface - */ - -#ifndef _UAPI_KBASE_MODEL_DUMMY_H_ -#define _UAPI_KBASE_MODEL_DUMMY_H_ - -#include - -#define KBASE_DUMMY_MODEL_COUNTER_HEADER_DWORDS (4) -#define KBASE_DUMMY_MODEL_COUNTER_PER_CORE (60) -#define KBASE_DUMMY_MODEL_COUNTER_PER_CORE_TYPE \ - (64*KBASE_DUMMY_MODEL_COUNTER_PER_CORE) -#define KBASE_DUMMY_MODEL_COUNTERS_PER_BIT (4) -#define KBASE_DUMMY_MODEL_COUNTER_ENABLED(enable_mask, ctr_idx) \ - (enable_mask & (1 << (ctr_idx / KBASE_DUMMY_MODEL_COUNTERS_PER_BIT))) - -#define KBASE_DUMMY_MODEL_HEADERS_PER_BLOCK 4 -#define KBASE_DUMMY_MODEL_COUNTERS_PER_BLOCK 60 -#define KBASE_DUMMY_MODEL_VALUES_PER_BLOCK \ - (KBASE_DUMMY_MODEL_COUNTERS_PER_BLOCK + \ - KBASE_DUMMY_MODEL_HEADERS_PER_BLOCK) -#define KBASE_DUMMY_MODEL_BLOCK_SIZE \ - (KBASE_DUMMY_MODEL_VALUES_PER_BLOCK * sizeof(__u32)) -#define KBASE_DUMMY_MODEL_MAX_MEMSYS_BLOCKS 8 -#define KBASE_DUMMY_MODEL_MAX_SHADER_CORES 32 -#define KBASE_DUMMY_MODEL_MAX_NUM_PERF_BLOCKS \ - (1 + 1 + KBASE_DUMMY_MODEL_MAX_MEMSYS_BLOCKS + KBASE_DUMMY_MODEL_MAX_SHADER_CORES) -#define KBASE_DUMMY_MODEL_COUNTER_TOTAL \ - (KBASE_DUMMY_MODEL_MAX_NUM_PERF_BLOCKS * KBASE_DUMMY_MODEL_COUNTER_PER_CORE_TYPE) - -#endif /* _UAPI_KBASE_MODEL_DUMMY_H_ */ diff --git a/common/include/uapi/gpu/arm/midgard/csf/mali_gpu_csf_registers.h b/common/include/uapi/gpu/arm/midgard/csf/mali_gpu_csf_registers.h index f233a0d..bed336c 100644 --- a/common/include/uapi/gpu/arm/midgard/csf/mali_gpu_csf_registers.h +++ b/common/include/uapi/gpu/arm/midgard/csf/mali_gpu_csf_registers.h @@ -104,6 +104,12 @@ #define CS_USER_INPUT_HI 0x0034 /* () CS user mode input page address, high word */ #define CS_USER_OUTPUT_LO 0x0038 /* () CS user mode input page address, low word */ #define CS_USER_OUTPUT_HI 0x003C /* () CS user mode input page address, high word */ +#define CS_INSTR_CONFIG 0x0040 /* () Instrumentation buffer configuration */ +#define CS_INSTR_BUFFER_SIZE 0x0044 /* () Instrumentation buffer size */ +#define CS_INSTR_BUFFER_BASE_LO 0x0048 /* () Instrumentation buffer base pointer, low word */ +#define CS_INSTR_BUFFER_BASE_HI 0x004C /* () Instrumentation buffer base pointer, high word */ +#define CS_INSTR_BUFFER_OFFSET_POINTER_LO 0x0050 /* () Instrumentation buffer pointer to insert offset, low word */ +#define CS_INSTR_BUFFER_OFFSET_POINTER_HI 0x0054 /* () Instrumentation buffer pointer to insert offset, high word */ /* CS_KERNEL_OUTPUT_BLOCK register offsets */ #define CS_ACK 0x0000 /* () CS acknowledge flags */ @@ -173,7 +179,8 @@ #define GLB_GROUP_NUM 0x0010 /* () Number of CSG interfaces */ #define GLB_GROUP_STRIDE 0x0014 /* () Stride between CSG interfaces */ #define GLB_PRFCNT_SIZE 0x0018 /* () Size of CSF performance counters */ -#define GLB_INSTR_FEATURES 0x001C /* () TRACE_POINT instrumentation features */ +#define GLB_INSTR_FEATURES \ + 0x001C /* () TRACE_POINT instrumentation. (csf >= 1.1.0) */ #define GROUP_CONTROL_0 0x1000 /* () CSG control and capabilities */ #define GROUP_CONTROL(n) (GROUP_CONTROL_0 + (n)*256) #define GROUP_CONTROL_REG(n, r) (GROUP_CONTROL(n) + GROUP_CONTROL_BLOCK_REG(r)) @@ -417,6 +424,57 @@ #define CS_USER_OUTPUT_POINTER_SET(reg_val, value) \ (((reg_val) & ~CS_USER_OUTPUT_POINTER_MASK) | \ (((value) << CS_USER_OUTPUT_POINTER_SHIFT) & CS_USER_OUTPUT_POINTER_MASK)) + +/* CS_INSTR_CONFIG register */ +#define CS_INSTR_CONFIG_JASID_SHIFT (0) +#define CS_INSTR_CONFIG_JASID_MASK ((u32)0xF << CS_INSTR_CONFIG_JASID_SHIFT) +#define CS_INSTR_CONFIG_JASID_GET(reg_val) (((reg_val)&CS_INSTR_CONFIG_JASID_MASK) >> CS_INSTR_CONFIG_JASID_SHIFT) +#define CS_INSTR_CONFIG_JASID_SET(reg_val, value) \ + (((reg_val) & ~CS_INSTR_CONFIG_JASID_MASK) | \ + (((value) << CS_INSTR_CONFIG_JASID_SHIFT) & CS_INSTR_CONFIG_JASID_MASK)) +#define CS_INSTR_CONFIG_EVENT_SIZE_SHIFT (4) +#define CS_INSTR_CONFIG_EVENT_SIZE_MASK ((u32)0xF << CS_INSTR_CONFIG_EVENT_SIZE_SHIFT) +#define CS_INSTR_CONFIG_EVENT_SIZE_GET(reg_val) \ + (((reg_val)&CS_INSTR_CONFIG_EVENT_SIZE_MASK) >> CS_INSTR_CONFIG_EVENT_SIZE_SHIFT) +#define CS_INSTR_CONFIG_EVENT_SIZE_SET(reg_val, value) \ + (((reg_val) & ~CS_INSTR_CONFIG_EVENT_SIZE_MASK) | \ + (((value) << CS_INSTR_CONFIG_EVENT_SIZE_SHIFT) & CS_INSTR_CONFIG_EVENT_SIZE_MASK)) +#define CS_INSTR_CONFIG_EVENT_STATE_SHIFT (16) +#define CS_INSTR_CONFIG_EVENT_STATE_MASK ((u32)0xFF << CS_INSTR_CONFIG_EVENT_STATE_SHIFT) +#define CS_INSTR_CONFIG_EVENT_STATE_GET(reg_val) \ + (((reg_val)&CS_INSTR_CONFIG_EVENT_STATE_MASK) >> CS_INSTR_CONFIG_EVENT_STATE_SHIFT) +#define CS_INSTR_CONFIG_EVENT_STATE_SET(reg_val, value) \ + (((reg_val) & ~CS_INSTR_CONFIG_EVENT_STATE_MASK) | \ + (((value) << CS_INSTR_CONFIG_EVENT_STATE_SHIFT) & CS_INSTR_CONFIG_EVENT_STATE_MASK)) + +/* CS_INSTR_BUFFER_SIZE register */ +#define CS_INSTR_BUFFER_SIZE_SIZE_SHIFT (0) +#define CS_INSTR_BUFFER_SIZE_SIZE_MASK ((u32)0xFFFFFFFF << CS_INSTR_BUFFER_SIZE_SIZE_SHIFT) +#define CS_INSTR_BUFFER_SIZE_SIZE_GET(reg_val) \ + (((reg_val)&CS_INSTR_BUFFER_SIZE_SIZE_MASK) >> CS_INSTR_BUFFER_SIZE_SIZE_SHIFT) +#define CS_INSTR_BUFFER_SIZE_SIZE_SET(reg_val, value) \ + (((reg_val) & ~CS_INSTR_BUFFER_SIZE_SIZE_MASK) | \ + (((value) << CS_INSTR_BUFFER_SIZE_SIZE_SHIFT) & CS_INSTR_BUFFER_SIZE_SIZE_MASK)) + +/* CS_INSTR_BUFFER_BASE register */ +#define CS_INSTR_BUFFER_BASE_POINTER_SHIFT (0) +#define CS_INSTR_BUFFER_BASE_POINTER_MASK ((u64)0xFFFFFFFFFFFFFFFF << CS_INSTR_BUFFER_BASE_POINTER_SHIFT) +#define CS_INSTR_BUFFER_BASE_POINTER_GET(reg_val) \ + (((reg_val)&CS_INSTR_BUFFER_BASE_POINTER_MASK) >> CS_INSTR_BUFFER_BASE_POINTER_SHIFT) +#define CS_INSTR_BUFFER_BASE_POINTER_SET(reg_val, value) \ + (((reg_val) & ~CS_INSTR_BUFFER_BASE_POINTER_MASK) | \ + (((value) << CS_INSTR_BUFFER_BASE_POINTER_SHIFT) & CS_INSTR_BUFFER_BASE_POINTER_MASK)) + +/* CS_INSTR_BUFFER_OFFSET_POINTER register */ +#define CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_SHIFT (0) +#define CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_MASK \ + ((u64)0xFFFFFFFFFFFFFFFF) << CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_SHIFT) +#define CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_GET(reg_val) \ + (((reg_val)&CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_MASK) >> CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_SHIFT) +#define CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_SET(reg_val, value) \ + (((reg_val) & ~CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_MASK) | \ + (((value) << CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_SHIFT) & CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_MASK)) + /* End of CS_KERNEL_INPUT_BLOCK register set definitions */ /* CS_KERNEL_OUTPUT_BLOCK register set definitions */ @@ -1401,6 +1459,22 @@ #define GLB_IDLE_TIMER_TIMER_SOURCE_GPU_COUNTER 0x1 /* End of GLB_IDLE_TIMER_TIMER_SOURCE values */ +/* GLB_INSTR_FEATURES register */ +#define GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_SHIFT (0) +#define GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_MASK ((u32)0xF << GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_SHIFT) +#define GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_GET(reg_val) \ + (((reg_val)&GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_MASK) >> GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_SHIFT) +#define GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_SET(reg_val, value) \ + (((reg_val) & ~GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_MASK) | \ + (((value) << GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_SHIFT) & GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_MASK)) +#define GLB_INSTR_FEATURES_EVENT_SIZE_MAX_SHIFT (4) +#define GLB_INSTR_FEATURES_EVENT_SIZE_MAX_MASK ((u32)0xF << GLB_INSTR_FEATURES_EVENT_SIZE_MAX_SHIFT) +#define GLB_INSTR_FEATURES_EVENT_SIZE_MAX_GET(reg_val) \ + (((reg_val)&GLB_INSTR_FEATURES_EVENT_SIZE_MAX_MASK) >> GLB_INSTR_FEATURES_EVENT_SIZE_MAX_SHIFT) +#define GLB_INSTR_FEATURES_EVENT_SIZE_MAX_SET(reg_val, value) \ + (((reg_val) & ~GLB_INSTR_FEATURES_EVENT_SIZE_MAX_MASK) | \ + (((value) << GLB_INSTR_FEATURES_EVENT_SIZE_MAX_SHIFT) & GLB_INSTR_FEATURES_EVENT_SIZE_MAX_MASK)) + #define CSG_STATUS_STATE (0x0018) /* CSG state status register */ /* CSG_STATUS_STATE register */ #define CSG_STATUS_STATE_IDLE_SHIFT (0) diff --git a/common/include/uapi/gpu/arm/midgard/csf/mali_kbase_csf_ioctl.h b/common/include/uapi/gpu/arm/midgard/csf/mali_kbase_csf_ioctl.h index 237cc2e..337195a 100644 --- a/common/include/uapi/gpu/arm/midgard/csf/mali_kbase_csf_ioctl.h +++ b/common/include/uapi/gpu/arm/midgard/csf/mali_kbase_csf_ioctl.h @@ -40,10 +40,14 @@ * 1.4: * - Replace padding in kbase_ioctl_cs_get_glb_iface with * instr_features member of same size + * 1.5: + * - Add ioctl 40: kbase_ioctl_cs_queue_register_ex, this is a new + * queue registration call with extended format for supporting CS + * trace configurations with CSF trace_command. */ #define BASE_UK_VERSION_MAJOR 1 -#define BASE_UK_VERSION_MINOR 4 +#define BASE_UK_VERSION_MINOR 5 /** * struct kbase_ioctl_version_check - Check version compatibility between @@ -69,6 +73,9 @@ struct kbase_ioctl_version_check { * @buffer_size: Size of the buffer in bytes * @priority: Priority of the queue within a group when run within a process * @padding: Currently unused, must be zero + * + * @Note: There is an identical sub-section in kbase_ioctl_cs_queue_register_ex. + * Any change of this struct should also be mirrored to the latter. */ struct kbase_ioctl_cs_queue_register { __u64 buffer_gpu_addr; @@ -120,7 +127,42 @@ union kbase_ioctl_cs_queue_bind { #define KBASE_IOCTL_CS_QUEUE_BIND \ _IOWR(KBASE_IOCTL_TYPE, 39, union kbase_ioctl_cs_queue_bind) -/* ioctl 40 is free to use */ +/** + * struct kbase_ioctl_cs_queue_register_ex - Register a GPU command queue with the + * base back-end in extended format, + * involving trace buffer configuration + * + * @buffer_gpu_addr: GPU address of the buffer backing the queue + * @buffer_size: Size of the buffer in bytes + * @priority: Priority of the queue within a group when run within a process + * @padding: Currently unused, must be zero + * @ex_offset_var_addr: GPU address of the trace buffer write offset variable + * @ex_buffer_base: Trace buffer GPU base address for the queue + * @ex_buffer_size: Size of the trace buffer in bytes + * @ex_event_size: Trace event write size, in log2 designation + * @ex_event_state: Trace event states configuration + * @ex_padding: Currently unused, must be zero + * + * @Note: There is an identical sub-section at the start of this struct to that + * of @ref kbase_ioctl_cs_queue_register. Any change of this sub-section + * must also be mirrored to the latter. Following the said sub-section, + * the remaining fields forms the extension, marked with ex_*. + */ +struct kbase_ioctl_cs_queue_register_ex { + __u64 buffer_gpu_addr; + __u32 buffer_size; + __u8 priority; + __u8 padding[3]; + __u64 ex_offset_var_addr; + __u64 ex_buffer_base; + __u32 ex_buffer_size; + __u8 ex_event_size; + __u8 ex_event_state; + __u8 ex_padding[2]; +}; + +#define KBASE_IOCTL_CS_QUEUE_REGISTER_EX \ + _IOW(KBASE_IOCTL_TYPE, 40, struct kbase_ioctl_cs_queue_register_ex) /** * struct kbase_ioctl_cs_queue_terminate - Terminate a GPU command queue @@ -314,6 +356,7 @@ struct kbase_ioctl_cs_tiler_heap_term { * @out.total_stream_num: Total number of CSs, summed across all groups. * @out.instr_features: Instrumentation features. Bits 7:4 hold the maximum * size of events. Bits 3:0 hold the offset update rate. + * (csf >= 1.1.0) * */ union kbase_ioctl_cs_get_glb_iface { diff --git a/common/include/uapi/gpu/arm/midgard/gpu/mali_kbase_gpu_id.h b/common/include/uapi/gpu/arm/midgard/gpu/mali_kbase_gpu_id.h index 0145920..74a95c1 100644 --- a/common/include/uapi/gpu/arm/midgard/gpu/mali_kbase_gpu_id.h +++ b/common/include/uapi/gpu/arm/midgard/gpu/mali_kbase_gpu_id.h @@ -106,6 +106,8 @@ #define GPU_ID2_PRODUCT_TBAX GPU_ID2_MODEL_MAKE(9, 5) #define GPU_ID2_PRODUCT_TDUX GPU_ID2_MODEL_MAKE(10, 1) #define GPU_ID2_PRODUCT_TODX GPU_ID2_MODEL_MAKE(10, 2) +#define GPU_ID2_PRODUCT_TGRX GPU_ID2_MODEL_MAKE(10, 3) +#define GPU_ID2_PRODUCT_TVAX GPU_ID2_MODEL_MAKE(10, 4) #define GPU_ID2_PRODUCT_LODX GPU_ID2_MODEL_MAKE(10, 7) /* Helper macro to create a GPU_ID assuming valid values for id, major, diff --git a/common/include/uapi/gpu/arm/midgard/gpu/mali_kbase_gpu_regmap.h b/common/include/uapi/gpu/arm/midgard/gpu/mali_kbase_gpu_regmap.h index 9977212..9c738ee 100644 --- a/common/include/uapi/gpu/arm/midgard/gpu/mali_kbase_gpu_regmap.h +++ b/common/include/uapi/gpu/arm/midgard/gpu/mali_kbase_gpu_regmap.h @@ -67,6 +67,9 @@ #define PWR_OVERRIDE1 0x058 /* (RW) Power manager override settings */ #define GPU_FEATURES_LO 0x060 /* (RO) GPU features, low word */ #define GPU_FEATURES_HI 0x064 /* (RO) GPU features, high word */ +#define PRFCNT_FEATURES 0x068 /* (RO) Performance counter features */ +#define TIMESTAMP_OFFSET_LO 0x088 /* (RW) Global time stamp offset, low word */ +#define TIMESTAMP_OFFSET_HI 0x08C /* (RW) Global time stamp offset, high word */ #define CYCLE_COUNT_LO 0x090 /* (RO) Cycle counter, low word */ #define CYCLE_COUNT_HI 0x094 /* (RO) Cycle counter, high word */ #define TIMESTAMP_LO 0x098 /* (RO) Global time stamp counter, low word */ @@ -285,6 +288,13 @@ #define AS_FAULTSTATUS_SOURCE_ID_GET(reg_val) \ (((reg_val)&AS_FAULTSTATUS_SOURCE_ID_MASK) >> AS_FAULTSTATUS_SOURCE_ID_SHIFT) +#define PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_SHIFT (0) +#define PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_MASK \ + ((0xFF) << PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_SHIFT) +#define PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_GET(reg_val) \ + (((reg_val)&PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_MASK) >> \ + PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_SHIFT) + /* * Begin MMU TRANSCFG register values */ -- cgit v1.2.3