diff options
Diffstat (limited to 'amalthea/csrs.h')
| -rw-r--r-- | amalthea/csrs.h | 73 |
1 files changed, 14 insertions, 59 deletions
diff --git a/amalthea/csrs.h b/amalthea/csrs.h index a8b8d07..5b9dac4 100644 --- a/amalthea/csrs.h +++ b/amalthea/csrs.h @@ -16,11 +16,6 @@ enum gxp_csrs { GXP_REG_LPM_VERSION = 0x40000, - GXP_REG_LPM_PSM_0 = 0x41000, - GXP_REG_LPM_PSM_1 = 0x42000, - GXP_REG_LPM_PSM_2 = 0x43000, - GXP_REG_LPM_PSM_3 = 0x44000, - GXP_REG_LPM_PSM_4 = 0x45000, GXP_REG_AURORA_REVISION = 0x80000, GXP_REG_COMMON_INT_POL_0 = 0x81000, GXP_REG_COMMON_INT_POL_1 = 0x81004, @@ -49,14 +44,20 @@ enum gxp_csrs { #define GXP_REG_COMMON_INT_MASK_0_DOORBELLS_MASK 0xFFFFFFFF #define GXP_REG_ETM_PWRCTL_CORE_RESET_SHIFT 16 -enum gxp_core_csrs { - GXP_REG_INST_BPM = 0x0000, - GXP_REG_PROFILING_CONDITION = 0x4000, - GXP_REG_PROCESSOR_ID = 0x4004, - GXP_REG_ALT_RESET_VECTOR = 0x4008, - GXP_REG_COMMON_INT_MASK_0 = 0x4010, - GXP_REG_ETM_PWRCTL = 0xB020, -}; +/* helpers for calculating core CSRs offsets */ +#define GXP_CORE_0_BASE GXP_REG_CORE_0_INST_BPM +#define GXP_CORE_SIZE (GXP_REG_CORE_1_INST_BPM - GXP_REG_CORE_0_INST_BPM) +#define GXP_CORE_REG(core, off) (GXP_CORE_0_BASE + GXP_CORE_SIZE * core + off) + +/* Per core CSRs. @core should be in region 0 ~ GXP_NUM_CORES-1 */ +#define GXP_CORE_REG_INST_BPM(core) GXP_CORE_REG(core, 0x0) +#define GXP_CORE_REG_PROFILING_CONDITION(core) GXP_CORE_REG(core, 0x4000) +#define GXP_CORE_REG_PROCESSOR_ID(core) GXP_CORE_REG(core, 0x4004) +#define GXP_CORE_REG_ALT_RESET_VECTOR(core) GXP_CORE_REG(core, 0x4008) +#define GXP_CORE_REG_COMMON_INT_MASK_0(core) GXP_CORE_REG(core, 0x4010) +#define GXP_CORE_REG_COMMON_INT_MASK_1(core) GXP_CORE_REG(core, 0x4014) +#define GXP_CORE_REG_DEDICATED_INT_MASK(core) GXP_CORE_REG(core, 0x401C) +#define GXP_CORE_REG_ETM_PWRCTL(core) GXP_CORE_REG(core, 0xB020) #define SYNC_BARRIER_SHADOW_OFFSET 0x800 @@ -73,50 +74,4 @@ enum gxp_core_csrs { #define PLL_CON0_PLL_AUR 0x100 #define PLL_CON0_NOC_USER 0x610 -/* LPM Registers */ -#define LPM_VERSION_OFFSET 0x0 -#define TRIGGER_CSR_START_OFFSET 0x4 -#define IMEM_START_OFFSET 0x8 -#define LPM_CONFIG_OFFSET 0xC -#define PSM_DESCRIPTOR_OFFSET 0x10 -#define EVENTS_EN_OFFSET 0x100 -#define EVENTS_INV_OFFSET 0x140 -#define FUNCTION_SELECT_OFFSET 0x180 -#define TRIGGER_STATUS_OFFSET 0x184 -#define EVENT_STATUS_OFFSET 0x188 -#define OPS_OFFSET 0x800 -#define PSM_DESCRIPTOR_BASE(_x_) ((_x_) << 2) -#define PSM_DESCRIPTOR_COUNT 5 -#define EVENTS_EN_BASE(_x_) ((_x_) << 2) -#define EVENTS_EN_COUNT 16 -#define EVENTS_INV_BASE(_x_) ((_x_) << 2) -#define EVENTS_INV_COUNT 16 -#define OPS_BASE(_x_) ((_x_) << 2) -#define OPS_COUNT 128 -#define PSM_COUNT 5 -#define PSM_STATE_TABLE_BASE(_x_) ((_x_) << 8) -#define PSM_STATE_TABLE_COUNT 6 -#define PSM_TRANS_BASE(_x_) ((_x_) << 5) -#define PSM_TRANS_COUNT 4 -#define PSM_DMEM_BASE(_x_) ((_x_) << 2) -#define PSM_DATA_COUNT 32 -#define PSM_NEXT_STATE_OFFSET 0x0 -#define PSM_SEQ_ADDR_OFFSET 0x4 -#define PSM_TIMER_VAL_OFFSET 0x8 -#define PSM_TIMER_EN_OFFSET 0xC -#define PSM_TRIGGER_NUM_OFFSET 0x10 -#define PSM_TRIGGER_EN_OFFSET 0x14 -#define PSM_ENABLE_STATE_OFFSET 0x80 -#define PSM_DATA_OFFSET 0x600 -#define PSM_CFG_OFFSET 0x680 -#define PSM_START_OFFSET 0x684 -#define PSM_STATUS_OFFSET 0x688 -#define PSM_DEBUG_CFG_OFFSET 0x68C -#define PSM_BREAK_ADDR_OFFSET 0x694 -#define PSM_GPIN_LO_RD_OFFSET 0x6A0 -#define PSM_GPIN_HI_RD_OFFSET 0x6A4 -#define PSM_GPOUT_LO_RD_OFFSET 0x6B0 -#define PSM_GPOUT_HI_RD_OFFSET 0x6B4 -#define PSM_DEBUG_STATUS_OFFSET 0x6B8 - #endif /* __AMALTHEA_CSRS_H__ */ |