Rel3 Drop for bcm4389, 2020.09.18 Version : 101.10.384

[Features]
BUG: 152265516 bcmdhd: Enable Packet fates for mgmt frame
BUG: 162003474 DSCP mapping

[BUGs]
BUG: 163302778 Fix for 5.4 Kernel + Android S
BUG: 163302778 Adjust order of sscd register
BUG: 155251670 Add prefix to DHD_PKT_MON and fix log formation
BUG: 151049090 Add timestamp to FW log when it add to FW_VERBOSE ring
BUG: 155491082 ANQP mac randomization
BUG: Removed GSCAN support from Makefile

[Note]
CONFIG_BCMDHD_HTPUT=y is default now. DEFAULT_DMA_COHERENT_POOL_SIZE should be 4M

Bug: 168332407
Test: Running with firmware 20.25.294 (Rel3 Release),
      Device can boot and WiFi can connect.
Note: Individual features will be verified separately
Change-Id: I99be06d068565e9e5a177b0ac1cad9f34269c554
Signed-off-by: Roger Wang <wangroger@google.com>

1 files changed, 75 insertions, 2 deletions

diff --git a/dhd_linux_lb.c b/dhd_linux_lb.c
index 8923fd3..656fec7 100644
--- a/dhd_linux_lb.c
+++ b/dhd_linux_lb.c
@@ -1361,7 +1361,7 @@ dhd_lb_tx_handler(unsigned long data)
 #endif /* DHD_LB_TXP */
 #endif /* DHD_LB */
 
-#if defined(DHD_CONTROL_PCIE_CPUCORE_WIFI_TURNON)
+#if defined(SET_PCIE_IRQ_CPU_CORE) || defined(DHD_CONTROL_PCIE_CPUCORE_WIFI_TURNON)
 void
 dhd_irq_set_affinity(dhd_pub_t *dhdp, const struct cpumask *cpumask)
 {
@@ -1391,4 +1391,77 @@ dhd_irq_set_affinity(dhd_pub_t *dhdp, const struct cpumask *cpumask)
 		DHD_ERROR(("%s : irq set affinity is failed cpu:0x%lx\n",
 				__FUNCTION__, *cpumask_bits(cpumask)));
 }
-#endif /* DHD_CONTROL_PCIE_CPUCORE_WIFI_TURNON */
+#endif /* SET_PCIE_IRQ_CPU_CORE ||  DHD_CONTROL_PCIE_CPUCORE_WIFI_TURNON */
+
+#ifdef SET_PCIE_IRQ_CPU_CORE
+void
+dhd_set_irq_cpucore(dhd_pub_t *dhdp, int affinity_cmd)
+{
+#if defined(DHD_LB) && defined(DHD_LB_HOST_CTRL)
+	struct dhd_info  *dhd = NULL;
+#endif /* DHD_LB && DHD_LB_HOST_CTRL */
+
+	if (!dhdp) {
+		DHD_ERROR(("%s : dhd is NULL\n", __FUNCTION__));
+		return;
+	}
+
+	if (!dhdp->bus) {
+		DHD_ERROR(("%s : dhd->bus is NULL\n", __FUNCTION__));
+		return;
+	}
+
+	if (affinity_cmd < DHD_AFFINITY_OFF || affinity_cmd > DHD_AFFINITY_LAST) {
+		DHD_ERROR(("Wrong Affinity cmds:%d, %s\n", affinity_cmd, __FUNCTION__));
+		return;
+	}
+
+	DHD_ERROR(("Enter %s, PCIe affinity cmd=0x%x\n", __FUNCTION__, affinity_cmd));
+
+#if defined(DHD_LB) && defined(DHD_LB_HOST_CTRL)
+	dhd = dhdp->info;
+
+	if (affinity_cmd == DHD_AFFINITY_OFF) {
+		dhd->permitted_primary_cpu = FALSE;
+	} else if (affinity_cmd == DHD_AFFINITY_TPUT_150MBPS ||
+		affinity_cmd == DHD_AFFINITY_TPUT_300MBPS) {
+		dhd->permitted_primary_cpu = TRUE;
+	}
+	dhd_select_cpu_candidacy(dhd);
+	/*
+	* It needs to NAPI disable -> enable to raise NET_RX napi CPU core
+	* during Rx traffic
+	* NET_RX does not move to NAPI CPU core if continusly calling napi polling
+	* function
+	*/
+	napi_disable(&dhd->rx_napi_struct);
+	napi_enable(&dhd->rx_napi_struct);
+#endif /* DHD_LB && DHD_LB_HOST_CTRL */
+
+	/*
+		irq_set_affinity() assign dedicated CPU core PCIe interrupt
+		If dedicated CPU core is not on-line,
+		PCIe interrupt scheduled on CPU core 0
+	*/
+	switch (affinity_cmd) {
+		case DHD_AFFINITY_OFF:
+#if defined(DHD_LB) && defined(DHD_LB_HOST_CTRL)
+			dhd_irq_set_affinity(dhdp, dhdp->info->cpumask_secondary);
+#endif /* DHD_LB && DHD_LB_HOST_CTRL */
+			break;
+		case DHD_AFFINITY_TPUT_150MBPS:
+			dhd_irq_set_affinity(dhdp, dhdp->info->cpumask_primary);
+			break;
+		case DHD_AFFINITY_TPUT_300MBPS:
+#ifdef CONFIG_ARCH_EXYNOS
+			dhd_irq_set_affinity(dhdp, cpumask_of(PCIE_IRQ_CPU_CORE));
+#else
+			dhd_irq_set_affinity(dhdp, dhdp->info->cpumask_primary);
+#endif /* CONFIG_ARCH_EXYNOS */
+			break;
+		default:
+			DHD_ERROR(("%s, Unknown PCIe affinity cmd=0x%x\n",
+				__FUNCTION__, affinity_cmd));
+	}
+}
+#endif /* SET_PCIE_IRQ_CPU_CORE */