diff options
| author | tinghsin <tinghsin@google.com> | 2023-06-17 10:34:14 +0800 |
|---|---|---|
| committer | Ken Sun <kensun@google.com> | 2023-06-27 11:39:58 +0000 |
| commit | ebbe792e6fafa3eb6a9786a773011f83aac0d79c (patch) | |
| tree | e8b1b170bc09a2ca4b29aee5a461ce9a5f0e1408 | |
| parent | f9092f8183a5a2ef14ef135c24e5a612d57c8196 (diff) | |
| download | bcm4398-ebbe792e6fafa3eb6a9786a773011f83aac0d79c.tar.gz | |
wlan: Change WAR API from pcie driver
Previously we have a WAR on D3 ack timeout issue that calling API from
pcie driver to prevent the following cfg space access. Now pcie driver
have changed the API name to make it more generic and this change
compliance with it.
Bug: 277732484
Change-Id: I42ac5be209caf6611a28336720cba721fdee88d9
Signed-off-by: tinghsin <tinghsin@google.com>
| -rw-r--r-- | dhd_custom_google.c | 7 | ||||
| -rw-r--r-- | dhd_linux_platdev.c | 5 | ||||
| -rw-r--r-- | dhd_msgbuf.c | 4 | ||||
| -rw-r--r-- | dhd_pcie.c | 4 | ||||
| -rw-r--r-- | dhd_plat.h | 1 |
5 files changed, 16 insertions, 5 deletions
diff --git a/dhd_custom_google.c b/dhd_custom_google.c index a35e1f6..4d26c01 100644 --- a/dhd_custom_google.c +++ b/dhd_custom_google.c @@ -1023,6 +1023,13 @@ uint16 dhd_plat_align_rxbuf_size(uint16 rxbufpost_sz) #endif } +extern void exynos_pcie_set_skip_config(int ch_num, bool val); +void dhd_plat_pcie_skip_config_set(bool val) +{ + DHD_PRINT(("%s: set skip config\n", __FUNCTION__)); + exynos_pcie_set_skip_config(pcie_ch_num, val); +} + #ifndef BCMDHD_MODULAR /* Required only for Built-in DHD */ device_initcall(dhd_wlan_init); diff --git a/dhd_linux_platdev.c b/dhd_linux_platdev.c index 4851f4d..71aee02 100644 --- a/dhd_linux_platdev.c +++ b/dhd_linux_platdev.c @@ -1107,6 +1107,11 @@ uint16 __attribute__ ((weak)) dhd_plat_align_rxbuf_size(uint16 rxbufpost_sz) return rxbufpost_sz; } +void __attribute__ ((weak)) dhd_plat_pcie_skip_config_set(bool val) +{ + return; +} + int __attribute__ ((weak)) dhd_get_platform_naming_for_nvram_clmblob_file(download_type_t component, char *file_name) diff --git a/dhd_msgbuf.c b/dhd_msgbuf.c index 9f063da..0bbb52e 100644 --- a/dhd_msgbuf.c +++ b/dhd_msgbuf.c @@ -52,6 +52,7 @@ #include <pcie_core.h> #include <bcmpcie.h> #include <dhd_pcie.h> +#include <dhd_plat.h> #ifdef DHD_TIMESYNC #include <dhd_timesync.h> #endif /* DHD_TIMESYNC */ @@ -1282,7 +1283,6 @@ static void dhd_prot_h2d_sync_init(dhd_pub_t *dhd); void dhd_fill_cso_info(dhd_pub_t *dhd, void *pktbuf, void *txdesc, uint32 item_len); #endif -extern void exynos_pcie_d3_ack_timeout_set(bool val); uint dhd_get_ring_size_from_version_array(uint cursize, uint* size_array, int version) @@ -11712,7 +11712,7 @@ dhd_msgbuf_wait_ioctl_cmplt(dhd_pub_t *dhd, uint32 len, void *buf) #ifdef DHD_TREAT_D3ACKTO_AS_LINKDWN if ((prot->ioctl_received == 0) && (timeleft == 0)) { DHD_ERROR(("%s: Treating IOVAR timeout as PCIe linkdown !\n", __FUNCTION__)); - exynos_pcie_d3_ack_timeout_set(1); + dhd_plat_pcie_skip_config_set(TRUE); dhd->bus->is_linkdown = 1; dhd->bus->iovarto_as_linkdwn_cnt++; dhd->hang_reason = HANG_REASON_PCIE_LINK_DOWN_RC_DETECT; @@ -783,8 +783,6 @@ const bcm_iovar_t dhdpcie_iovars[] = { {NULL, 0, 0, 0, 0, 0 } }; -extern void exynos_pcie_d3_ack_timeout_set(bool val); - #ifdef BCMQT_HW #define MAX_READ_TIMEOUT 200 * 1000 /* 200 ms in dongle time */ #elif defined(NDIS) @@ -11363,9 +11361,9 @@ dhdpcie_bus_suspend(struct dhd_bus *bus, bool state) #ifdef DHD_TREAT_D3ACKTO_AS_LINKDWN if ((bus->wait_for_d3_ack == 0) && (timeleft == 0)) { + dhd_plat_pcie_skip_config_set(TRUE); DHD_ERROR(("%s: Treating D3 ack timeout during" " suspend-resume as PCIe linkdown !\n", __FUNCTION__)); - exynos_pcie_d3_ack_timeout_set(1); bus->is_linkdown = 1; bus->d3ackto_as_linkdwn_cnt++; bus->dhd->hang_reason = HANG_REASON_PCIE_LINK_DOWN_RC_DETECT; @@ -95,5 +95,6 @@ extern uint32 dhd_plat_get_rc_vendor_id(void); extern uint32 dhd_plat_get_rc_device_id(void); extern uint16 dhd_plat_align_rxbuf_size(uint16 rxbufpost_sz); +extern void dhd_plat_pcie_skip_config_set(bool val); #endif /* __linux__ */ #endif /* __DHD_PLAT_H__ */ |