From 846e21e9f4ff37895a01274539511fdc0cd51ed2 Mon Sep 17 00:00:00 2001 From: Hsiu-Chang Chen Date: Tue, 6 Sep 2022 13:32:49 +0800 Subject: wcn6740: Update cnss/mhi/qmi/qrtr drivers Migrate wlan codes to PostCS release Bug: 245009352 Test: Regression Test Change-Id: Icb90ab318ced3f028a19d6e329d509a23c3774a6 --- cnss2/main.c | 9 +++++++- cnss2/main.h | 1 + cnss2/pci.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++++---------- cnss2/qmi.c | 7 ++++-- cnss2/reg.h | 5 ++++ 5 files changed, 81 insertions(+), 15 deletions(-) (limited to 'cnss2') diff --git a/cnss2/main.c b/cnss2/main.c index 5f4a5ab..b3656de 100644 --- a/cnss2/main.c +++ b/cnss2/main.c @@ -676,6 +676,11 @@ static int cnss_fw_ready_hdlr(struct cnss_plat_data *plat_priv) if (!plat_priv) return -ENODEV; + if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) { + cnss_pr_err("Reboot is in progress, ignore FW ready\n"); + return -EINVAL; + } + cnss_pr_dbg("Processing FW Init Done..\n"); del_timer(&plat_priv->fw_boot_timer); set_bit(CNSS_FW_READY, &plat_priv->driver_state); @@ -3445,7 +3450,9 @@ static int cnss_misc_init(struct cnss_plat_data *plat_priv) cnss_pr_err("QMI IPC connection call back register failed, err = %d\n", ret); - plat_priv->sram_dump = kcalloc(SRAM_DUMP_SIZE, 1, GFP_KERNEL); + if (plat_priv->device_id == QCA6490_DEVICE_ID && + cnss_get_host_build_type() == QMI_HOST_BUILD_TYPE_PRIMARY_V01) + plat_priv->sram_dump = kcalloc(SRAM_DUMP_SIZE, 1, GFP_KERNEL); return 0; } diff --git a/cnss2/main.h b/cnss2/main.h index e965f02..0125237 100644 --- a/cnss2/main.h +++ b/cnss2/main.h @@ -554,6 +554,7 @@ struct cnss_plat_data { /* bitmap to detect FEM combination */ u8 hwid_bitmap; enum cnss_driver_mode driver_mode; + u32 num_shadow_regs_v3; }; #if IS_ENABLED(CONFIG_ARCH_QCOM) && !IS_ENABLED(CONFIG_WCN_GOOGLE) diff --git a/cnss2/pci.c b/cnss2/pci.c index 66a19fc..98e6760 100644 --- a/cnss2/pci.c +++ b/cnss2/pci.c @@ -1893,8 +1893,16 @@ static int cnss_pci_get_device_timestamp(struct cnss_pci_data *pci_priv, return -EINVAL; } - cnss_pci_reg_read(pci_priv, WLAON_GLOBAL_COUNTER_CTRL3, &low); - cnss_pci_reg_read(pci_priv, WLAON_GLOBAL_COUNTER_CTRL4, &high); + switch (pci_priv->device_id) { + case KIWI_DEVICE_ID: + cnss_pci_reg_read(pci_priv, PCIE_MHI_TIME_LOW, &low); + cnss_pci_reg_read(pci_priv, PCIE_MHI_TIME_HIGH, &high); + break; + default: + cnss_pci_reg_read(pci_priv, WLAON_GLOBAL_COUNTER_CTRL3, &low); + cnss_pci_reg_read(pci_priv, WLAON_GLOBAL_COUNTER_CTRL4, &high); + break; + } device_ticks = (u64)high << 32 | low; do_div(device_ticks, plat_priv->device_freq_hz / 100000); @@ -1905,16 +1913,60 @@ static int cnss_pci_get_device_timestamp(struct cnss_pci_data *pci_priv, static void cnss_pci_enable_time_sync_counter(struct cnss_pci_data *pci_priv) { + switch (pci_priv->device_id) { + case KIWI_DEVICE_ID: + return; + default: + break; + } + cnss_pci_reg_write(pci_priv, WLAON_GLOBAL_COUNTER_CTRL5, TIME_SYNC_ENABLE); } static void cnss_pci_clear_time_sync_counter(struct cnss_pci_data *pci_priv) { + switch (pci_priv->device_id) { + case KIWI_DEVICE_ID: + return; + default: + break; + } + cnss_pci_reg_write(pci_priv, WLAON_GLOBAL_COUNTER_CTRL5, TIME_SYNC_CLEAR); } +static void cnss_pci_time_sync_reg_update(struct cnss_pci_data *pci_priv, + u32 low, u32 high) +{ + u32 time_reg_low; + u32 time_reg_high; + + switch (pci_priv->device_id) { + case KIWI_DEVICE_ID: + /* Use the next two shadow registers after host's usage */ + time_reg_low = PCIE_SHADOW_REG_VALUE_0 + + (pci_priv->plat_priv->num_shadow_regs_v3 * + SHADOW_REG_LEN_BYTES); + time_reg_high = time_reg_low + SHADOW_REG_LEN_BYTES; + break; + default: + time_reg_low = PCIE_SHADOW_REG_VALUE_34; + time_reg_high = PCIE_SHADOW_REG_VALUE_35; + break; + } + + cnss_pci_reg_write(pci_priv, time_reg_low, low); + cnss_pci_reg_write(pci_priv, time_reg_high, high); + + cnss_pci_reg_read(pci_priv, time_reg_low, &low); + cnss_pci_reg_read(pci_priv, time_reg_high, &high); + + cnss_pr_dbg("Updated time sync regs [0x%x] = 0x%x, [0x%x] = 0x%x\n", + time_reg_low, low, time_reg_high, high); +} + static int cnss_pci_update_timestamp(struct cnss_pci_data *pci_priv) { struct cnss_plat_data *plat_priv = pci_priv->plat_priv; @@ -1956,15 +2008,7 @@ static int cnss_pci_update_timestamp(struct cnss_pci_data *pci_priv) low = offset & 0xFFFFFFFF; high = offset >> 32; - cnss_pci_reg_write(pci_priv, PCIE_SHADOW_REG_VALUE_34, low); - cnss_pci_reg_write(pci_priv, PCIE_SHADOW_REG_VALUE_35, high); - - cnss_pci_reg_read(pci_priv, PCIE_SHADOW_REG_VALUE_34, &low); - cnss_pci_reg_read(pci_priv, PCIE_SHADOW_REG_VALUE_35, &high); - - cnss_pr_dbg("Updated time sync regs [0x%x] = 0x%x, [0x%x] = 0x%x\n", - PCIE_SHADOW_REG_VALUE_34, low, - PCIE_SHADOW_REG_VALUE_35, high); + cnss_pci_time_sync_reg_update(pci_priv, low, high); force_wake_put: cnss_pci_force_wake_put(pci_priv); @@ -2036,6 +2080,7 @@ static void cnss_pci_stop_time_sync_update(struct cnss_pci_data *pci_priv) switch (pci_priv->device_id) { case QCA6390_DEVICE_ID: case QCA6490_DEVICE_ID: + case KIWI_DEVICE_ID: break; default: return; @@ -2072,6 +2117,10 @@ int cnss_pci_call_driver_probe(struct cnss_pci_data *pci_priv) return -ENODEV; plat_priv = pci_priv->plat_priv; + if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) { + cnss_pr_err("Reboot is in progress, skip driver probe\n"); + return -EINVAL; + } if (test_bit(CNSS_DRIVER_DEBUG, &plat_priv->driver_state)) { clear_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state); @@ -4836,7 +4885,6 @@ void cnss_pci_collect_dump_info(struct cnss_pci_data *pci_priv, bool in_panic) cnss_pci_soc_scratch_reg_dump(pci_priv); cnss_pci_dump_misc_reg(pci_priv); cnss_pci_dump_shadow_reg(pci_priv); - cnss_pci_dump_qdss_reg(pci_priv); ret = mhi_download_rddm_image(pci_priv->mhi_ctrl, in_panic); if (ret) { @@ -4852,6 +4900,8 @@ void cnss_pci_collect_dump_info(struct cnss_pci_data *pci_priv, bool in_panic) rddm_image = pci_priv->mhi_ctrl->rddm_image; dump_data->nentries = 0; + if (plat_priv->qdss_mem_seg_len) + cnss_pci_dump_qdss_reg(pci_priv); cnss_mhi_dump_sfr(pci_priv); if (!dump_seg) { diff --git a/cnss2/qmi.c b/cnss2/qmi.c index 311b976..1572c94 100644 --- a/cnss2/qmi.c +++ b/cnss2/qmi.c @@ -1549,8 +1549,6 @@ int cnss_wlfw_wlan_cfg_send_sync(struct cnss_plat_data *plat_priv, sizeof(struct wlfw_shadow_reg_v2_cfg_s_v01) * req->shadow_reg_v2_len); } else { - cnss_pr_dbg("Shadow reg v3 len: %d\n", - config->num_shadow_reg_v3_cfg); req->shadow_reg_v3_valid = 1; if (config->num_shadow_reg_v3_cfg > MAX_NUM_SHADOW_REG_V3) @@ -1558,6 +1556,11 @@ int cnss_wlfw_wlan_cfg_send_sync(struct cnss_plat_data *plat_priv, else req->shadow_reg_v3_len = config->num_shadow_reg_v3_cfg; + plat_priv->num_shadow_regs_v3 = req->shadow_reg_v3_len; + + cnss_pr_dbg("Shadow reg v3 len: %d\n", + plat_priv->num_shadow_regs_v3); + memcpy(req->shadow_reg_v3, config->shadow_reg_v3_cfg, sizeof(struct wlfw_shadow_reg_v3_cfg_s_v01) * req->shadow_reg_v3_len); diff --git a/cnss2/reg.h b/cnss2/reg.h index 9a3729e..7280add 100644 --- a/cnss2/reg.h +++ b/cnss2/reg.h @@ -52,13 +52,18 @@ #define CE_REG_INTERVAL 0x2000 #define SHADOW_REG_COUNT 36 +#define SHADOW_REG_LEN_BYTES 4 #define PCIE_SHADOW_REG_VALUE_0 0x8FC +#define PCIE_SHADOW_REG_VALUE_1 0x900 #define PCIE_SHADOW_REG_VALUE_34 0x984 #define PCIE_SHADOW_REG_VALUE_35 0x988 #define SHADOW_REG_INTER_COUNT 43 #define PCIE_SHADOW_REG_INTER_0 0x1E05000 +#define PCIE_MHI_TIME_LOW 0xA28 +#define PCIE_MHI_TIME_HIGH 0xA2C + #define QDSS_APB_DEC_CSR_BASE 0x1C01000 #define QDSS_APB_DEC_CSR_ETRIRQCTRL_OFFSET 0x6C -- cgit v1.2.3