diff options
| author | Steve Capper <steve.capper@arm.com> | 2012-08-10 17:59:21 +0100 |
|---|---|---|
| committer | Tushar Behera <tushar.behera@linaro.org> | 2013-01-22 11:41:41 +0530 |
| commit | c8606480624c885043687bf77b5f9ad2466e0cb1 (patch) | |
| tree | b0b30f048c0c25224ba9742af5bdfee0e6555dbc | |
| parent | b309415c157965d25f058f1be71d684a17ad0366 (diff) | |
| download | linux-topics-c8606480624c885043687bf77b5f9ad2466e0cb1.tar.gz | |
ARM: mm: correct pte_same behaviour for LPAE.
For 3 levels of paging the PTE_EXT_NG bit will be set for user address ptes
that are written to a page table but not for ptes created with mk_pte.
This can cause some comparison tests made by pte_same to fail spuriously and
lead to other problems.
To correct this behaviour, we mask off PTE_EXT_NG for any pte that is
present before running the comparison.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Steve Capper <steve.capper@arm.com>
| -rw-r--r-- | arch/arm/include/asm/pgtable-2level.h | 5 | ||||
| -rw-r--r-- | arch/arm/include/asm/pgtable-3level.h | 5 | ||||
| -rw-r--r-- | arch/arm/include/asm/pgtable.h | 23 |
3 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h index f97ee02386e..44d1903553a 100644 --- a/arch/arm/include/asm/pgtable-2level.h +++ b/arch/arm/include/asm/pgtable-2level.h @@ -127,6 +127,11 @@ #define L_PTE_NONE (_AT(pteval_t, 1) << 11) /* + * for 2 levels of paging we don't mask off any bits when comparing present ptes + */ +#define L_PTE_CMP_MASKOFF 0 + +/* * These are the memory types, defined to be compatible with * pre-ARMv6 CPUs cacheable and bufferable bits: XXCB */ diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h index 554f6d3260d..5ffcf91de46 100644 --- a/arch/arm/include/asm/pgtable-3level.h +++ b/arch/arm/include/asm/pgtable-3level.h @@ -86,6 +86,11 @@ #define L_PTE_DIRTY_HIGH (1 << (55 - 32)) /* + * we need to mask off PTE_EXT_NG when comparing present ptes. + */ +#define L_PTE_CMP_MASKOFF PTE_EXT_NG + +/* * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). */ #define L_PTE_MT_UNCACHED (_AT(pteval_t, 0) << 2) /* strongly ordered */ diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index 9c82f988c0e..d91748d0ff7 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h @@ -246,6 +246,29 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) } /* + * For 3 levels of paging the PTE_EXT_NG bit will be set for user address ptes + * that are written to a page table but not for ptes created with mk_pte. + * + * This can cause some comparison tests made by pte_same to fail spuriously and + * lead to other problems. + * + * To correct this behaviour, we mask off PTE_EXT_NG for any pte that is + * present before running the comparison. + */ +#define __HAVE_ARCH_PTE_SAME +static inline int pte_same(pte_t pte_a, pte_t pte_b) +{ + pteval_t vala = pte_val(pte_a), valb = pte_val(pte_b); + if (pte_present(pte_a)) + vala &= ~L_PTE_CMP_MASKOFF; + + if (pte_present(pte_b)) + valb &= ~L_PTE_CMP_MASKOFF; + + return vala == valb; +} + +/* * Encode and decode a swap entry. Swap entries are stored in the Linux * page tables as follows: * |