display: Correctly setting up mdss interface offsets

Mdss interface offsets have changed between 8974 V1 and
V2.
Change-Id: I551ffaafd6e8884800e0aaac2caf9f00011f7e8a

2 files changed, 64 insertions, 37 deletions

diff --git a/platform/msm_shared/include/mdp5.h b/platform/msm_shared/include/mdp5.h
index 497b4d08..357663eb 100644
--- a/platform/msm_shared/include/mdp5.h
+++ b/platform/msm_shared/include/mdp5.h
@@ -54,6 +54,11 @@
 #define MDP_VP_0_LAYER_3_BLEND_OP               REG_MDP(0x32B0)
 #define MDP_VP_0_LAYER_3_BLEND0_FG_ALPHA        REG_MDP(0x32B4)
 
+
+#define MDSS_MDP_HW_REV_100                     0x10000000
+#define MDSS_MDP_HW_REV_102                     0x10020000
+
+#define MDP_HW_REV                              REG_MDP(0x0100)
 #define MDP_INTR_EN                             REG_MDP(0x0110)
 #define MDP_INTR_CLEAR                          REG_MDP(0x0118)
 #define MDP_HIST_INTR_EN                        REG_MDP(0x011C)
@@ -63,29 +68,29 @@
 #define MDP_UPPER_NEW_ROI_PRIOR_RO_START        REG_MDP(0x02EC)
 #define MDP_LOWER_NEW_ROI_PRIOR_TO_START        REG_MDP(0x04F8)
 
-#define MDP_INTF_1_TIMING_ENGINE_EN             REG_MDP(0x21300)
+#define MDP_INTF_1_TIMING_ENGINE_EN             REG_MDP(0x12700)
 
 #define MDP_CTL_0_LAYER_0                       REG_MDP(0x600)
 #define MDP_CTL_0_TOP                           REG_MDP(0x614)
 #define MDP_CTL_0_FLUSH                         REG_MDP(0x618)
 
-#define MDP_INTF_1_HSYNC_CTL                    REG_MDP(0x21308)
-#define MDP_INTF_1_VSYNC_PERIOD_F0              REG_MDP(0x2130C)
-#define MDP_INTF_1_VSYNC_PERIOD_F1              REG_MDP(0x21310)
-#define MDP_INTF_1_VSYNC_PULSE_WIDTH_F0         REG_MDP(0x21314)
-#define MDP_INTF_1_VSYNC_PULSE_WIDTH_F1         REG_MDP(0x21318)
-#define MDP_INTF_1_DISPLAY_HCTL                 REG_MDP(0x2133C)
-#define MDP_INTF_1_DISPLAY_V_START_F0           REG_MDP(0x2131C)
-#define MDP_INTF_1_DISPLAY_V_START_F1           REG_MDP(0x21320)
-#define MDP_INTF_1_DISPLAY_V_END_F0             REG_MDP(0x21324)
-#define MDP_INTF_1_DISPLAY_V_END_F1             REG_MDP(0x21328)
-#define MDP_INTF_1_ACTIVE_HCTL                  REG_MDP(0x21340)
-#define MDP_INTF_1_ACTIVE_V_START_F0            REG_MDP(0x2132C)
-#define MDP_INTF_1_ACTIVE_V_START_F1            REG_MDP(0x21330)
-#define MDP_INTF_1_ACTIVE_V_END_F0              REG_MDP(0x21334)
-#define MDP_INTF_1_ACTIVE_V_END_F1              REG_MDP(0x21338)
-#define MDP_INTF_1_UNDERFFLOW_COLOR             REG_MDP(0x21348)
-#define MDP_INTF_1_PANEL_FORMAT                 REG_MDP(0x21390)
+#define MDP_INTF_1_HSYNC_CTL                    REG_MDP(0x12708)
+#define MDP_INTF_1_VSYNC_PERIOD_F0              REG_MDP(0x1270C)
+#define MDP_INTF_1_VSYNC_PERIOD_F1              REG_MDP(0x12710)
+#define MDP_INTF_1_VSYNC_PULSE_WIDTH_F0         REG_MDP(0x12714)
+#define MDP_INTF_1_VSYNC_PULSE_WIDTH_F1         REG_MDP(0x12718)
+#define MDP_INTF_1_DISPLAY_HCTL                 REG_MDP(0x1273C)
+#define MDP_INTF_1_DISPLAY_V_START_F0           REG_MDP(0x1271C)
+#define MDP_INTF_1_DISPLAY_V_START_F1           REG_MDP(0x12720)
+#define MDP_INTF_1_DISPLAY_V_END_F0             REG_MDP(0x12724)
+#define MDP_INTF_1_DISPLAY_V_END_F1             REG_MDP(0x12728)
+#define MDP_INTF_1_ACTIVE_HCTL                  REG_MDP(0x12740)
+#define MDP_INTF_1_ACTIVE_V_START_F0            REG_MDP(0x1272C)
+#define MDP_INTF_1_ACTIVE_V_START_F1            REG_MDP(0x12730)
+#define MDP_INTF_1_ACTIVE_V_END_F0              REG_MDP(0x12734)
+#define MDP_INTF_1_ACTIVE_V_END_F1              REG_MDP(0x12738)
+#define MDP_INTF_1_UNDERFFLOW_COLOR             REG_MDP(0x12748)
+#define MDP_INTF_1_PANEL_FORMAT                 REG_MDP(0x12790)
 
 #define MDP_CLK_CTRL0                           REG_MDP(0x03AC)
 #define MDP_CLK_CTRL1                           REG_MDP(0x03B4)
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index 468969cc..4d6de3a8 100644
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -55,6 +55,19 @@ int mdp_get_revision()
 	return mdp_rev;
 }
 
+uint32_t mdss_mdp_intf_offset()
+{
+	uint32_t mdss_mdp_intf_off;
+	uint32_t mdss_mdp_rev = readl(MDP_HW_REV);
+
+	if (mdss_mdp_rev > MDSS_MDP_HW_REV_100)
+		mdss_mdp_intf_off = 0;
+	else
+		mdss_mdp_intf_off = 0xEC00;
+
+	return mdss_mdp_intf_off;
+}
+
 void mdp_clk_gating_ctrl(void)
 {
 	writel(0x40000000, MDP_CLK_CTRL0);
@@ -77,6 +90,7 @@ int mdp_dsi_video_config(struct msm_panel_info *pinfo,
 	struct lcdc_panel_info *lcdc = NULL;
 	unsigned mdp_rgb_size;
 	int access_secure = 0;
+	uint32_t mdss_mdp_intf_off = 0;
 
 	if (pinfo == NULL)
 		return ERR_INVALID_ARGS;
@@ -108,6 +122,8 @@ int mdp_dsi_video_config(struct msm_panel_info *pinfo,
 	hsync_ctl = (hsync_period << 16) | lcdc->h_pulse_width;
 	display_hctl = (hsync_end_x << 16) | hsync_start_x;
 
+	mdss_mdp_intf_off = mdss_mdp_intf_offset();
+
 	/* write active region size*/
 	mdp_rgb_size = (fb->height << 16) + fb->width;
 
@@ -135,22 +151,27 @@ int mdp_dsi_video_config(struct msm_panel_info *pinfo,
 	writel(0x00101010, MMSS_MDP_SMP_ALLOC_R_0);
 	writel(0x00000010, MMSS_MDP_SMP_ALLOC_R_1);
 
-	writel(hsync_ctl, MDP_INTF_1_HSYNC_CTL);
-	writel(vsync_period*hsync_period, MDP_INTF_1_VSYNC_PERIOD_F0);
-	writel(0x00, MDP_INTF_1_VSYNC_PERIOD_F1);
-	writel(lcdc->v_pulse_width*hsync_period, MDP_INTF_1_VSYNC_PULSE_WIDTH_F0);
-	writel(0x00, MDP_INTF_1_VSYNC_PULSE_WIDTH_F1);
-	writel(display_hctl, MDP_INTF_1_DISPLAY_HCTL);
-	writel(display_vstart, MDP_INTF_1_DISPLAY_V_START_F0);
-	writel(0x00, MDP_INTF_1_DISPLAY_V_START_F1);
-	writel(display_vend, MDP_INTF_1_DISPLAY_V_END_F0);
-	writel(0x00, MDP_INTF_1_DISPLAY_V_END_F1);
-	writel(0x00, MDP_INTF_1_ACTIVE_HCTL);
-	writel(0x00, MDP_INTF_1_ACTIVE_V_START_F0);
-	writel(0x00, MDP_INTF_1_ACTIVE_V_START_F1);
-	writel(0x00, MDP_INTF_1_ACTIVE_V_END_F0);
-	writel(0x00, MDP_INTF_1_ACTIVE_V_END_F1);
-	writel(0xFF, MDP_INTF_1_UNDERFFLOW_COLOR);
+	writel(hsync_ctl, MDP_INTF_1_HSYNC_CTL + mdss_mdp_intf_off);
+	writel(vsync_period*hsync_period, MDP_INTF_1_VSYNC_PERIOD_F0 +
+			mdss_mdp_intf_off);
+	writel(0x00, MDP_INTF_1_VSYNC_PERIOD_F1 + mdss_mdp_intf_off);
+	writel(lcdc->v_pulse_width*hsync_period,
+			MDP_INTF_1_VSYNC_PULSE_WIDTH_F0 +
+			mdss_mdp_intf_off);
+	writel(0x00, MDP_INTF_1_VSYNC_PULSE_WIDTH_F1 + mdss_mdp_intf_off);
+	writel(display_hctl, MDP_INTF_1_DISPLAY_HCTL + mdss_mdp_intf_off);
+	writel(display_vstart, MDP_INTF_1_DISPLAY_V_START_F0 +
+			mdss_mdp_intf_off);
+	writel(0x00, MDP_INTF_1_DISPLAY_V_START_F1 + mdss_mdp_intf_off);
+	writel(display_vend, MDP_INTF_1_DISPLAY_V_END_F0 +
+			mdss_mdp_intf_off);
+	writel(0x00, MDP_INTF_1_DISPLAY_V_END_F1 + mdss_mdp_intf_off);
+	writel(0x00, MDP_INTF_1_ACTIVE_HCTL + mdss_mdp_intf_off);
+	writel(0x00, MDP_INTF_1_ACTIVE_V_START_F0 + mdss_mdp_intf_off);
+	writel(0x00, MDP_INTF_1_ACTIVE_V_START_F1 + mdss_mdp_intf_off);
+	writel(0x00, MDP_INTF_1_ACTIVE_V_END_F0 + mdss_mdp_intf_off);
+	writel(0x00, MDP_INTF_1_ACTIVE_V_END_F1 + mdss_mdp_intf_off);
+	writel(0xFF, MDP_INTF_1_UNDERFFLOW_COLOR + mdss_mdp_intf_off);
 
 	writel(fb->base, MDP_VP_0_RGB_0_SSPP_SRC0_ADDR);
 	writel((fb->stride * fb->bpp/8),MDP_VP_0_RGB_0_SSPP_SRC_YSTRIDE);
@@ -179,7 +200,7 @@ int mdp_dsi_video_config(struct msm_panel_info *pinfo,
 	writel(0x010000200, MDP_CTL_0_LAYER_0);
 
 	writel(0x1F20, MDP_CTL_0_TOP);
-	writel(0x213F, MDP_INTF_1_PANEL_FORMAT);
+	writel(0x213F, MDP_INTF_1_PANEL_FORMAT + mdss_mdp_intf_off);
 
 	writel(0x0100, MDP_DISP_INTF_SEL);
 	writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL);
@@ -201,7 +222,7 @@ int mdp_dsi_video_on(void)
 {
 	int ret = NO_ERROR;
 	writel(0x32048, MDP_CTL_0_FLUSH);
-	writel(0x01, MDP_INTF_1_TIMING_ENGINE_EN);
+	writel(0x01, MDP_INTF_1_TIMING_ENGINE_EN  + mdss_mdp_intf_offset());
 	return ret;
 }
 
@@ -209,7 +230,8 @@ int mdp_dsi_video_off()
 {
 	if(!target_cont_splash_screen())
 	{
-		writel(0x00000000, MDP_INTF_1_TIMING_ENGINE_EN);
+		writel(0x00000000, MDP_INTF_1_TIMING_ENGINE_EN +
+				mdss_mdp_intf_offset());
 		mdelay(60);
 		/* Ping-Pong done Tear Check Read/Write  */
 		/* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable  */