Merge "target: mdm9625: Update the reset config api."

4 files changed, 24 insertions, 2 deletions

diff --git a/dev/pmic/pm8x41/include/pm8x41.h b/dev/pmic/pm8x41/include/pm8x41.h
index 8ed54ba1..03de67d3 100644
--- a/dev/pmic/pm8x41/include/pm8x41.h
+++ b/dev/pmic/pm8x41/include/pm8x41.h
@@ -60,6 +60,7 @@
 #define PM_GPIO_OUTPUT_MASK     0x0F
 
 #define PON_PSHOLD_WARM_RESET   0x1
+#define PON_PSHOLD_SHUTDOWN     0x4
 
 #define PMIC_VERSION_V2         1
 
@@ -89,6 +90,7 @@ void pm8x41_set_boot_done();
 uint32_t pm8x41_resin_status();
 uint32_t pm8x41_resin_bark_workaround_status();
 void pm8x41_reset_configure(uint8_t);
+void pm8x41_v2_reset_configure(uint8_t);
 int pm8x41_ldo_set_voltage(const char *, uint32_t);
 int pm8x41_ldo_control(const char *, uint8_t);
 uint8_t pm8x41_get_pmic_rev();
diff --git a/dev/pmic/pm8x41/include/pm8x41_hw.h b/dev/pmic/pm8x41/include/pm8x41_hw.h
index ff23061b..cfc72fbd 100644
--- a/dev/pmic/pm8x41/include/pm8x41_hw.h
+++ b/dev/pmic/pm8x41/include/pm8x41_hw.h
@@ -69,6 +69,7 @@
 #define PON_RESIN_N_RESET_S2_TIMER            0x845  /* bits 0:2  : S2_TIMER */
 #define PON_RESIN_N_RESET_S2_CTL              0x846  /* bit 7: S2_RESET_EN, bit 0:3 : RESET_TYPE  */
 #define PON_PS_HOLD_RESET_CTL                 0x85A  /* bit 7: S2_RESET_EN, bit 0:3 : RESET_TYPE  */
+#define PON_PS_HOLD_RESET_CTL2                0x85B
 
 /* PON Peripheral register bit values */
 #define RESIN_ON_INT_BIT                      1
diff --git a/dev/pmic/pm8x41/pm8x41.c b/dev/pmic/pm8x41/pm8x41.c
index 64aecae5..ca7d230e 100644
--- a/dev/pmic/pm8x41/pm8x41.c
+++ b/dev/pmic/pm8x41/pm8x41.c
@@ -225,7 +225,7 @@ uint32_t pm8x41_resin_status()
 	return (rt_sts & BIT(RESIN_ON_INT_BIT));
 }
 
-void pm8x41_reset_configure(uint8_t reset_type)
+void pm8x41_v2_reset_configure(uint8_t reset_type)
 {
 	uint8_t val;
 
@@ -245,6 +245,21 @@ void pm8x41_reset_configure(uint8_t reset_type)
 	REG_WRITE(PON_PS_HOLD_RESET_CTL, val);
 }
 
+void pm8x41_reset_configure(uint8_t reset_type)
+{
+	/* disable PS_HOLD_RESET */
+	REG_WRITE(PON_PS_HOLD_RESET_CTL2, 0x0);
+
+	/* Delay needed for disable to kick in. */
+	udelay(300);
+
+	/* configure reset type */
+	REG_WRITE(PON_PS_HOLD_RESET_CTL, reset_type);
+
+	/* enable PS_HOLD_RESET */
+	REG_WRITE(PON_PS_HOLD_RESET_CTL2, BIT(S2_RESET_EN_BIT));
+}
+
 static struct pm8x41_ldo *ldo_get(const char *ldo_name)
 {
 	uint8_t i;
diff --git a/target/mdm9625/init.c b/target/mdm9625/init.c
index 407e3c7f..ab9fd90a 100644
--- a/target/mdm9625/init.c
+++ b/target/mdm9625/init.c
@@ -152,7 +152,11 @@ void reboot_device(unsigned reboot_reason)
 		writel(reboot_reason, RESTART_REASON_ADDR);
 
 	/* Configure PMIC for warm reset */
-	pm8x41_reset_configure(PON_PSHOLD_WARM_RESET);
+	/* PM 8019 v1 aligns with PM8941 v2.
+	 * This call should be based on the pmic version
+	 * when PM8019 v2 is available.
+	 */
+	pm8x41_v2_reset_configure(PON_PSHOLD_WARM_RESET);
 
 	/* Drop PS_HOLD for MSM */
 	writel(0x00, MPM2_MPM_PS_HOLD);