platform: msm8974: Add clock support for command mode panels

Add support for command mode panels for continuous splash enabled
and disabled case.

Change-Id: I64aa2dc27578f33c9ea45cef5a417cee8de2c93a

3 files changed, 73 insertions, 2 deletions

diff --git a/platform/msm8974/acpuclock.c b/platform/msm8974/acpuclock.c
index 9392c691..c3be9523 100644
--- a/platform/msm8974/acpuclock.c
+++ b/platform/msm8974/acpuclock.c
@@ -339,8 +339,11 @@ void mdp_gdsc_ctrl(uint8_t enable)
 		}
 
 		while(readl(MDP_GDSCR) & ((GDSC_POWER_ON_BIT) | (GDSC_POWER_ON_STATUS_BIT)));
-	} else
-		ASSERT(1);
+	} else {
+		reg &= ~BIT(0);
+		writel(reg, MDP_GDSCR);
+		while(!(readl(MDP_GDSCR) & ((GDSC_POWER_ON_BIT))));
+	}
 }
 
 /* Configure MDP clock */
@@ -363,6 +366,13 @@ void mdp_clock_init(void)
 		ASSERT(0);
 	}
 
+	ret = clk_get_set_enable("mdss_vsync_clk", 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set mdss vsync clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
 	ret = clk_get_set_enable("mdss_mdp_clk", 0, 1);
 	if(ret)
 	{
@@ -378,6 +388,18 @@ void mdp_clock_init(void)
 	}
 }
 
+void mdp_clock_disable(void)
+{
+	writel(0x0, DSI_BYTE0_CBCR);
+	writel(0x0, DSI_PIXEL0_CBCR);
+	clk_disable(clk_get("mdss_vsync_clk"));
+	clk_disable(clk_get("mdss_mdp_clk"));
+	clk_disable(clk_get("mdss_mdp_lut_clk"));
+	clk_disable(clk_get("mdss_mdp_clk_src"));
+	clk_disable(clk_get("mdp_ahb_clk"));
+
+}
+
 /* Initialize all clocks needed by Display */
 void mmss_clock_init(void)
 {
@@ -425,3 +447,20 @@ void mmss_clock_init(void)
 	writel(0x1, DSI_PIXEL0_CMD_RCGR);
 	writel(0x1, DSI_PIXEL0_CBCR);
 }
+
+void mmss_clock_disable(void)
+{
+
+	/* Disable ESC clock */
+	clk_disable(clk_get("mdss_esc0_clk"));
+
+	/* Disable MDSS AXI clock */
+	clk_disable(clk_get("mdss_axi_clk"));
+
+	/* Disable MMSSNOC S0AXI clock */
+	clk_disable(clk_get("mmss_s0_axi_clk"));
+
+	/* Disable MMSSNOC AXI clock */
+	clk_disable(clk_get("mmss_mmssnoc_axi_clk"));
+
+}
diff --git a/platform/msm8974/include/platform/clock.h b/platform/msm8974/include/platform/clock.h
index 0e11d4e6..cb96f003 100644
--- a/platform/msm8974/include/platform/clock.h
+++ b/platform/msm8974/include/platform/clock.h
@@ -42,6 +42,9 @@
 #define GDSC_EN_FEW_WAIT_MASK           (0x0F << 16)
 #define GDSC_EN_FEW_WAIT_256_MASK       BIT(19)
 
+#define VSYNC_CMD_RCGR                  REG_MM(0x2080)
+#define VSYNC_CFG_RCGR                  REG_MM(0x2084)
+#define MDSS_VSYNC_CBCR                 REG_MM(0x2328)
 #define MDP_CMD_RCGR                    REG_MM(0x2040)
 #define MDP_CFG_RCGR                    REG_MM(0x2044)
 #define MDP_CBCR                        REG_MM(0x231C)
diff --git a/platform/msm8974/msm8974-clock.c b/platform/msm8974/msm8974-clock.c
index 9f1e590c..ae6db46c 100644
--- a/platform/msm8974/msm8974-clock.c
+++ b/platform/msm8974/msm8974-clock.c
@@ -426,6 +426,23 @@ static struct rcg_clk dsi_esc0_clk_src = {
 	},
 };
 
+static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = {
+	F_MM(19200000,    cxo,   1,   0,   0),
+	F_END
+};
+
+static struct rcg_clk vsync_clk_src = {
+	.cmd_reg  = (uint32_t *) VSYNC_CMD_RCGR,
+	.cfg_reg  = (uint32_t *) VSYNC_CFG_RCGR,
+	.set_rate = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl = ftbl_mdss_vsync_clk,
+
+	.c        = {
+		.dbg_name = "vsync_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
 static struct rcg_clk mdp_axi_clk_src = {
 	.cmd_reg  = (uint32_t *) MDP_AXI_CMD_RCGR,
 	.cfg_reg  = (uint32_t *) MDP_AXI_CFG_RCGR,
@@ -527,6 +544,17 @@ static struct branch_clk mdss_mdp_lut_clk = {
 	},
 };
 
+static struct branch_clk mdss_vsync_clk = {
+	.cbcr_reg    = MDSS_VSYNC_CBCR,
+	.parent      = &vsync_clk_src.c,
+	.has_sibling = 0,
+
+	.c           = {
+		.dbg_name = "mdss_vsync_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
 /* Clock lookup table */
 static struct clk_lookup msm_clocks_8974[] =
 {
@@ -558,6 +586,7 @@ static struct clk_lookup msm_clocks_8974[] =
 	CLK_LOOKUP("mdss_axi_clk",         mdss_axi_clk.c),
 	CLK_LOOKUP("mmss_mmssnoc_axi_clk", mmss_mmssnoc_axi_clk.c),
 	CLK_LOOKUP("mmss_s0_axi_clk",      mmss_s0_axi_clk.c),
+	CLK_LOOKUP("mdss_vsync_clk",       mdss_vsync_clk.c),
 	CLK_LOOKUP("mdss_mdp_clk_src",     mdss_mdp_clk_src.c),
 	CLK_LOOKUP("mdss_mdp_clk",         mdss_mdp_clk.c),
 	CLK_LOOKUP("mdss_mdp_lut_clk",     mdss_mdp_lut_clk.c),