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| author | QuIC Gerrit Code Review <gerrit@quicinc.com> | 2010-01-14 18:46:44 -0800 |
|---|---|---|
| committer | QuIC Gerrit Code Review <gerrit@quicinc.com> | 2010-01-14 18:46:44 -0800 |
| commit | 99b7003e09d09a367a54bafd3af5e731711984c8 (patch) | |
| tree | 75a77da01ae356c0a6190a7496f0ae4ea12249a1 | |
| parent | 26a5690a4eec23b1f4b141517453980fc3b5702b (diff) | |
| parent | 037b2264b2082dc765a560f6335f08ab70049cde (diff) | |
| download | lk-99b7003e09d09a367a54bafd3af5e731711984c8.tar.gz | |
Merge change I5dcc8279
* changes:
[platform/msm7x30]: Fix the Debug timer clock divider value according to hardware version.
| -rw-r--r-- | platform/msm7x30/include/platform/iomap.h | 5 | ||||
| -rw-r--r-- | platform/msm_shared/timer.c | 9 |
2 files changed, 12 insertions, 2 deletions
diff --git a/platform/msm7x30/include/platform/iomap.h b/platform/msm7x30/include/platform/iomap.h index a0bdb438..fd107b35 100644 --- a/platform/msm7x30/include/platform/iomap.h +++ b/platform/msm7x30/include/platform/iomap.h @@ -44,8 +44,9 @@ #define MSM_GCC_BASE 0xC0182000 #if defined(PLATFORM_MSM7X30) -#define MSM_SHARED_BASE 0x00100000 +#define MSM_SHARED_BASE 0x00100000 +#define HW_REVISION_NUMBER 0xABC00270 #else -#define MSM_SHARED_BASE 0x01F00000 +#define MSM_SHARED_BASE 0x01F00000 #endif #endif diff --git a/platform/msm_shared/timer.c b/platform/msm_shared/timer.c index 31cc6fff..b249b233 100644 --- a/platform/msm_shared/timer.c +++ b/platform/msm_shared/timer.c @@ -60,6 +60,7 @@ #define DGT_ENABLE_CLR_ON_MATCH_EN 2 #define DGT_ENABLE_EN 1 #define DGT_CLEAR DGT_REG(0x000C) +#define DGT_CLK_CTL DGT_REG(0x0010) #else #define GPT_REG(off) (MSM_GPT_BASE + (off)) @@ -98,6 +99,14 @@ status_t platform_set_periodic_timer( platform_timer_callback callback, void *arg, time_t interval) { +#ifdef PLATFORM_MSM7X30 + unsigned val = 0; + unsigned mask = (0x1 << 28); + //Check for the hardware revision + val = readl(HW_REVISION_NUMBER); + if(val & mask) + writel(1, DGT_CLK_CTL); +#endif enter_critical_section(); timer_callback = callback; |