From 7dc3aa920cdfff9415f94e3a2255422a0bfbc4cf Mon Sep 17 00:00:00 2001 From: Siddhartha Agrawal Date: Sun, 21 Apr 2013 16:04:26 -0700 Subject: msm_shared: mdp: Add MDP5 support for command mode panels Add MDSS MDP5 related support for command mode enabe panels. Change-Id: Ic68d329ab2cb809a3a518334e337a2447190e920 --- platform/msm_shared/include/mdp5.h | 3 ++ platform/msm_shared/mdp5.c | 84 +++++++++++++++++++++++++++++++++++++- 2 files changed, 86 insertions(+), 1 deletion(-) diff --git a/platform/msm_shared/include/mdp5.h b/platform/msm_shared/include/mdp5.h index 357663eb..430bdae3 100644 --- a/platform/msm_shared/include/mdp5.h +++ b/platform/msm_shared/include/mdp5.h @@ -45,6 +45,7 @@ #define MDP_VP_0_LAYER_0_OUT_SIZE REG_MDP(0x3204) #define MDP_VP_0_LAYER_0_OP_MODE REG_MDP(0x3200) +#define MDP_VP_0_LAYER_0_BORDER_COLOR_0 REG_MDP(0x3208) #define MDP_VP_0_LAYER_0_BLEND_OP REG_MDP(0x3220) #define MDP_VP_0_LAYER_0_BLEND0_FG_ALPHA REG_MDP(0x3224) #define MDP_VP_0_LAYER_1_BLEND_OP REG_MDP(0x3250) @@ -73,6 +74,7 @@ #define MDP_CTL_0_LAYER_0 REG_MDP(0x600) #define MDP_CTL_0_TOP REG_MDP(0x614) #define MDP_CTL_0_FLUSH REG_MDP(0x618) +#define MDP_CTL_0_START REG_MDP(0x61C) #define MDP_INTF_1_HSYNC_CTL REG_MDP(0x12708) #define MDP_INTF_1_VSYNC_PERIOD_F0 REG_MDP(0x1270C) @@ -97,6 +99,7 @@ #define MDP_CLK_CTRL2 REG_MDP(0x03BC) #define MDP_CLK_CTRL3 REG_MDP(0x04A8) #define MDP_CLK_CTRL4 REG_MDP(0x04B0) +#define MDP_CLK_CTRL5 REG_MDP(0x04B8) #define MMSS_MDP_SMP_ALLOC_W_0 REG_MDP(0x0180) #define MMSS_MDP_SMP_ALLOC_W_1 REG_MDP(0x0184) diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c index 66afa825..9e5cf673 100644 --- a/platform/msm_shared/mdp5.c +++ b/platform/msm_shared/mdp5.c @@ -217,8 +217,80 @@ int mdp_dsi_video_config(struct msm_panel_info *pinfo, int mdp_dsi_cmd_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) { + int ret = NO_ERROR; + + struct lcdc_panel_info *lcdc = NULL; + uint32_t mdp_rgb_size; + int access_secure = 0; + uint32_t mdss_mdp_intf_off = 0; + + if (pinfo == NULL) + return ERR_INVALID_ARGS; + + lcdc = &(pinfo->lcdc); + if (lcdc == NULL) + return ERR_INVALID_ARGS; + + mdss_mdp_intf_off = mdss_mdp_intf_offset(); + /* write active region size*/ + mdp_rgb_size = (fb->height << 16) + fb->width; + + access_secure = restore_secure_cfg(SECURE_DEVICE_MDSS); + + mdp_clk_gating_ctrl(); + + writel(0x0100, MDP_DISP_INTF_SEL); + + /* Ignore TZ return value till it's fixed */ + if (!access_secure || 1) { + /* Force VBIF Clocks on */ + writel(0x1, VBIF_VBIF_DDR_FORCE_CLK_ON); + /* Configure DDR burst length */ + writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); + writel(0x00000030, VBIF_VBIF_DDR_ARB_CTRL ); + writel(0x00000001, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); + writel(0x00000FFF, VBIF_VBIF_DDR_OUT_AOOO_AXI_EN); + writel(0x0FFF0FFF, VBIF_VBIF_DDR_OUT_AX_AOOO); + writel(0x22222222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0); + writel(0x00002222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1); + } + + /* Allocate SMP blocks */ + writel(0x00101010, MMSS_MDP_SMP_ALLOC_W_0); + writel(0x00000010, MMSS_MDP_SMP_ALLOC_W_1); + writel(0x00101010, MMSS_MDP_SMP_ALLOC_R_0); + writel(0x00000010, MMSS_MDP_SMP_ALLOC_R_1); + + writel(fb->base, MDP_VP_0_RGB_0_SSPP_SRC0_ADDR); + writel((fb->stride * fb->bpp/8),MDP_VP_0_RGB_0_SSPP_SRC_YSTRIDE); + writel(mdp_rgb_size, MDP_VP_0_RGB_0_SSPP_SRC_IMG_SIZE); + writel(mdp_rgb_size, MDP_VP_0_RGB_0_SSPP_SRC_SIZE); + writel(mdp_rgb_size, MDP_VP_0_RGB_0_SSPP_SRC_OUT_SIZE); + writel(0x00, MDP_VP_0_RGB_0_SSPP_SRC_XY); + writel(0x00, MDP_VP_0_RGB_0_SSPP_OUT_XY); + /* Tight Packing 3bpp 0-Alpha 8-bit R B G */ + writel(0x0002243F, MDP_VP_0_RGB_0_SSPP_SRC_FORMAT); + writel(0x00020001, MDP_VP_0_RGB_0_SSPP_SRC_UNPACK_PATTERN); + writel(0x00, MDP_VP_0_RGB_0_SSPP_SRC_OP_MODE); + + writel(mdp_rgb_size,MDP_VP_0_LAYER_0_OUT_SIZE); + writel(0x00, MDP_VP_0_LAYER_0_OP_MODE); + writel(0x100, MDP_VP_0_LAYER_0_BLEND_OP); + writel(0xFF, MDP_VP_0_LAYER_0_BLEND0_FG_ALPHA); + writel(0x100, MDP_VP_0_LAYER_1_BLEND_OP); + writel(0xFF, MDP_VP_0_LAYER_1_BLEND0_FG_ALPHA); + writel(0x100, MDP_VP_0_LAYER_2_BLEND_OP); + writel(0xFF, MDP_VP_0_LAYER_2_BLEND0_FG_ALPHA); + writel(0x100, MDP_VP_0_LAYER_3_BLEND_OP); + writel(0xFF, MDP_VP_0_LAYER_3_BLEND0_FG_ALPHA); + + /* Baselayer for layer mixer 0 */ + writel(0x00000200, MDP_CTL_0_LAYER_0); + + writel(0x213F, MDP_INTF_1_PANEL_FORMAT + mdss_mdp_intf_off); + + writel(0x20020, MDP_CTL_0_TOP); - int ret = 0; return ret; } @@ -249,11 +321,21 @@ int mdp_dsi_video_off() int mdp_dsi_cmd_off() { + if(!target_cont_splash_screen()) + { + /* Ping-Pong done Tear Check Read/Write */ + /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ + writel(0xFF777713, MDP_INTR_CLEAR); + } + writel(0x00000000, MDP_INTR_EN); + return NO_ERROR; } int mdp_dma_on(void) { + writel(0x32048, MDP_CTL_0_FLUSH); + writel(0x01, MDP_CTL_0_START); return NO_ERROR; } -- cgit v1.2.3