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| author | Meng Wang <mengw@codeaurora.org> | 2020-08-25 17:14:49 +0800 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2020-09-04 23:41:48 -0700 |
| commit | 6bb6f668f80b6855255cd4a74953bd610a753b06 (patch) | |
| tree | d8879409f22b26224e25feaeab221703637852dc | |
| parent | 08747bef396f04f38ea4632444c6e17cb232d69d (diff) | |
| download | msm-extra-6bb6f668f80b6855255cd4a74953bd610a753b06.tar.gz | |
soc: swr-mstr: update component and interrupt enable sequence
Enable component after enabling interrupt to avoid missing
some intterupt during master init.
Change-Id: I0f60c5431a815c58f878d3b9275a046e47939111
Signed-off-by: Meng Wang <mengw@codeaurora.org>
| -rw-r--r-- | soc/swr-mstr-ctrl.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/soc/swr-mstr-ctrl.c b/soc/swr-mstr-ctrl.c index 623f70e6..a489be17 100644 --- a/soc/swr-mstr-ctrl.c +++ b/soc/swr-mstr-ctrl.c @@ -2473,9 +2473,6 @@ static int swrm_master_init(struct swr_mstr_ctrl *swrm) reg[len] = SWRM_COMP_CFG_ADDR; value[len++] = 0x02; - reg[len] = SWRM_COMP_CFG_ADDR; - value[len++] = 0x03; - reg[len] = SWRM_INTERRUPT_CLEAR; value[len++] = 0xFFFFFFFF; @@ -2487,6 +2484,9 @@ static int swrm_master_init(struct swr_mstr_ctrl *swrm) reg[len] = SWR_MSTR_RX_SWRM_CPU_INTERRUPT_EN; value[len++] = swrm->intr_mask; + reg[len] = SWRM_COMP_CFG_ADDR; + value[len++] = 0x03; + swr_master_bulk_write(swrm, reg, value, len); if (!swrm_check_link_status(swrm, 0x1)) { |