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| author | Laxminath Kasam <lkasam@codeaurora.org> | 2019-03-08 14:56:39 +0530 |
|---|---|---|
| committer | Meng Wang <mengw@codeaurora.org> | 2019-04-16 13:15:01 +0800 |
| commit | 260b769735d348e129b1bad955db6e206b603000 (patch) | |
| tree | f3b27a0639e9751ed0217c4a29c36e48f8b96d90 /asoc/codecs/wcd934x | |
| parent | e039f16fa42042615cfdfd3ec6a3a23a09f6e589 (diff) | |
| download | msm-extra-260b769735d348e129b1bad955db6e206b603000.tar.gz | |
asoc: wcd934x: Fix TX HPF setting update
In case TX HPF mixer ctl set to 150Hz, go bit register
is not updated. Always update go bit along with
setting 150Hz at TX enable sequence.
CRs-Fixed: 2407902
Change-Id: I05b8a471cb2505d1ca5b290ea7ba35da5a534170
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
Diffstat (limited to 'asoc/codecs/wcd934x')
| -rw-r--r-- | asoc/codecs/wcd934x/wcd934x.c | 24 |
1 files changed, 11 insertions, 13 deletions
diff --git a/asoc/codecs/wcd934x/wcd934x.c b/asoc/codecs/wcd934x/wcd934x.c index 07bbcb39..f1c35369 100644 --- a/asoc/codecs/wcd934x/wcd934x.c +++ b/asoc/codecs/wcd934x/wcd934x.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. */ #include <linux/module.h> #include <linux/init.h> @@ -4687,20 +4687,18 @@ static int tavil_codec_enable_dec(struct snd_soc_dapm_widget *w, tavil->tx_hpf_work[decimator].hpf_cut_off_freq = hpf_cut_off_freq; - if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) { - snd_soc_component_update_bits(component, dec_cfg_reg, - TX_HPF_CUT_OFF_FREQ_MASK, - CF_MIN_3DB_150HZ << 5); - snd_soc_component_update_bits(component, hpf_gate_reg, + snd_soc_component_update_bits(component, dec_cfg_reg, + TX_HPF_CUT_OFF_FREQ_MASK, + CF_MIN_3DB_150HZ << 5); + snd_soc_component_update_bits(component, hpf_gate_reg, 0x02, 0x02); - /* - * Minimum 1 clk cycle delay is required as per - * HW spec. - */ - usleep_range(1000, 1010); - snd_soc_component_update_bits(component, hpf_gate_reg, + /* + * Minimum 1 clk cycle delay is required as per + * HW spec. + */ + usleep_range(1000, 1010); + snd_soc_component_update_bits(component, hpf_gate_reg, 0x02, 0x00); - } /* schedule work queue to Remove Mute */ schedule_delayed_work(&tavil->tx_mute_dwork[decimator].dwork, msecs_to_jiffies(tx_unmute_delay)); |