diff options
| author | Laxminath Kasam <lkasam@codeaurora.org> | 2020-06-05 20:36:44 +0530 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2020-07-28 05:25:11 -0700 |
| commit | 04170363287912fa23dd6e2d0ff06f1ae588c528 (patch) | |
| tree | c7b11481be6ebfcf8f8f02a289e239f489baae2f /asoc/codecs/wcd938x | |
| parent | ead188cb70dac01923cda368996955fa7a17038d (diff) | |
| download | msm-extra-04170363287912fa23dd6e2d0ff06f1ae588c528.tar.gz | |
asoc: wcd938x: Add WCD ADC Mode mask to control modes
To set correct swr clk rate in concurrency,
use WCD ADC modes as status mask bit to confirm
ADC paths active and control set clock rate.
Change-Id: Id3401d6ed59bd617e0751e7c704268346b36dac4
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
Diffstat (limited to 'asoc/codecs/wcd938x')
| -rw-r--r-- | asoc/codecs/wcd938x/wcd938x.c | 28 |
1 files changed, 24 insertions, 4 deletions
diff --git a/asoc/codecs/wcd938x/wcd938x.c b/asoc/codecs/wcd938x/wcd938x.c index 511fd1f2..9207bbd2 100644 --- a/asoc/codecs/wcd938x/wcd938x.c +++ b/asoc/codecs/wcd938x/wcd938x.c @@ -58,6 +58,10 @@ enum { HPH_PA_DELAY, AMIC2_BCS_ENABLE, WCD_SUPPLIES_LPM_MODE, + WCD_ADC1_MODE, + WCD_ADC2_MODE, + WCD_ADC3_MODE, + WCD_ADC4_MODE, }; enum { @@ -1513,13 +1517,17 @@ static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w, switch (event) { case SND_SOC_DAPM_PRE_PMU: if (strnstr(w->name, "ADC", sizeof("ADC"))) { - if (test_bit(WCD_ADC1, &wcd938x->status_mask)) + if (test_bit(WCD_ADC1, &wcd938x->status_mask) || + test_bit(WCD_ADC1_MODE, &wcd938x->status_mask)) mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]]; - if (test_bit(WCD_ADC2, &wcd938x->status_mask)) + if (test_bit(WCD_ADC2, &wcd938x->status_mask) || + test_bit(WCD_ADC2_MODE, &wcd938x->status_mask)) mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]]; - if (test_bit(WCD_ADC3, &wcd938x->status_mask)) + if (test_bit(WCD_ADC3, &wcd938x->status_mask) || + test_bit(WCD_ADC3_MODE, &wcd938x->status_mask)) mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]]; - if (test_bit(WCD_ADC4, &wcd938x->status_mask)) + if (test_bit(WCD_ADC4, &wcd938x->status_mask) || + test_bit(WCD_ADC4_MODE, &wcd938x->status_mask)) mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]]; if (mode != 0) { @@ -1551,6 +1559,14 @@ static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w, false); if (strnstr(w->name, "ADC", sizeof("ADC"))) wcd938x_set_swr_clk_rate(component, rate, bank); + if (strnstr(w->name, "ADC1", sizeof("ADC1"))) + clear_bit(WCD_ADC1_MODE, &wcd938x->status_mask); + else if (strnstr(w->name, "ADC2", sizeof("ADC2"))) + clear_bit(WCD_ADC2_MODE, &wcd938x->status_mask); + else if (strnstr(w->name, "ADC3", sizeof("ADC3"))) + clear_bit(WCD_ADC3_MODE, &wcd938x->status_mask); + else if (strnstr(w->name, "ADC4", sizeof("ADC4"))) + clear_bit(WCD_ADC4_MODE, &wcd938x->status_mask); break; }; @@ -1999,21 +2015,25 @@ static int wcd938x_event_notify(struct notifier_block *block, if (test_bit(WCD_ADC1, &wcd938x->status_mask)) { snd_soc_component_update_bits(component, WCD938X_ANA_TX_CH2, 0x40, 0x00); + set_bit(WCD_ADC1_MODE, &wcd938x->status_mask); clear_bit(WCD_ADC1, &wcd938x->status_mask); } if (test_bit(WCD_ADC2, &wcd938x->status_mask)) { snd_soc_component_update_bits(component, WCD938X_ANA_TX_CH2, 0x20, 0x00); + set_bit(WCD_ADC2_MODE, &wcd938x->status_mask); clear_bit(WCD_ADC2, &wcd938x->status_mask); } if (test_bit(WCD_ADC3, &wcd938x->status_mask)) { snd_soc_component_update_bits(component, WCD938X_ANA_TX_CH4, 0x40, 0x00); + set_bit(WCD_ADC3_MODE, &wcd938x->status_mask); clear_bit(WCD_ADC3, &wcd938x->status_mask); } if (test_bit(WCD_ADC4, &wcd938x->status_mask)) { snd_soc_component_update_bits(component, WCD938X_ANA_TX_CH4, 0x20, 0x00); + set_bit(WCD_ADC4_MODE, &wcd938x->status_mask); clear_bit(WCD_ADC4, &wcd938x->status_mask); } break; |