diff options
| author | Sudheer Papothi <spapothi@codeaurora.org> | 2020-05-16 11:50:48 +0530 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2020-09-07 01:23:24 -0700 |
| commit | 95712bc373cded8b676210ebb59a4be9c60bbb7b (patch) | |
| tree | 98da0b7e6f3e903f06d63d87ccba47ba3fb55853 /asoc | |
| parent | 908583ff00ed2b342fffc388e0a15693c2801bb4 (diff) | |
| download | msm-extra-95712bc373cded8b676210ebb59a4be9c60bbb7b.tar.gz | |
ASoC: wsa883x: Update register sequence to reduce CnP
Update register sequence of WSA883x codec to reduce CnP
during bringup and teardown of speaker path.
Change-Id: I348a55e1324b5c26a36b8d7c78edf52a66e40381
Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
Diffstat (limited to 'asoc')
| -rw-r--r-- | asoc/codecs/wsa883x/wsa883x.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/asoc/codecs/wsa883x/wsa883x.c b/asoc/codecs/wsa883x/wsa883x.c index 3a319c7e..8a5e99e4 100644 --- a/asoc/codecs/wsa883x/wsa883x.c +++ b/asoc/codecs/wsa883x/wsa883x.c @@ -108,6 +108,7 @@ static const struct wsa_reg_mask_val reg_init[] = { {WSA883X_ADC_7, 0x04, 0x04}, {WSA883X_ADC_7, 0x02, 0x02}, {WSA883X_CKWD_CTL_0, 0x60, 0x00}, + {WSA883X_DRE_CTL_1, 0x3E, 0x20}, {WSA883X_CKWD_CTL_1, 0x1F, 0x1B}, {WSA883X_GMAMP_SUP1, 0x60, 0x60}, }; @@ -986,6 +987,12 @@ static int wsa883x_spkr_event(struct snd_soc_dapm_widget *w, swr_slvdev_datapath_control(wsa883x->swr_slave, wsa883x->swr_slave->dev_num, true); + /* Added delay as per HW sequence */ + usleep_range(250, 300); + snd_soc_component_update_bits(component, WSA883X_DRE_CTL_1, + 0x01, 0x01); + /* Added delay as per HW sequence */ + usleep_range(250, 300); /* Force remove group */ swr_remove_from_group(wsa883x->swr_slave, wsa883x->swr_slave->dev_num); @@ -1393,6 +1400,13 @@ static int wsa883x_event_notify(struct notifier_block *nb, 0x01, 0x01); wcd_enable_irq(&wsa883x->irq_info, WSA883X_IRQ_INT_PDM_WD); + /* Added delay as per HW sequence */ + usleep_range(3000, 3100); + snd_soc_component_update_bits(wsa883x->component, + WSA883X_DRE_CTL_1, + 0x01, 0x00); + /* Added delay as per HW sequence */ + usleep_range(5000, 5050); } break; case BOLERO_WSA_EVT_PA_ON_POST_FSCLK_ADIE_LB: |