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authorJigarkumar Zala <jzala@quicinc.com>2019-06-14 15:21:12 -0700
committerJigarkumar Zala <jzala@quicinc.com>2019-06-14 15:22:07 -0700
commite10e40625ac5bed6d1d5a51a10e9ff840a102172 (patch)
tree4898f4cd080f36e2c499ed2cded1425225abd5d0 /bindings/msm-cam-vfe.txt
parent3bd3ae4fc70d70c2c6ad3aecb199f87c03ba24ce (diff)
downloadcamera-devicetree-e10e40625ac5bed6d1d5a51a10e9ff840a102172.tar.gz
dt-bindings: Move camera devicetree bindins from video
Move camera devicetree bindings from video to camera project. Change-Id: Iacfbd2a1a248ebae54ae3f42d785a454320a5f49
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+* Qualcomm Technologies, Inc. MSM Camera VFE
+
+Camera VFE device provides the definitions for enabling
+the VFE hardware. It also provides the functions for the client
+to control the VFE hardware.
+
+=======================
+Required Node Structure
+=======================
+The VFE device is described in one level of the device node.
+
+======================================
+First Level Node - CAM VFE device
+======================================
+Required properties:
+- compatible
+ Usage: required
+ Value type: <string>
+ Definition: Should specify the compatibility string for matching the
+ driver. e.g. "qcom,vfe480", "qcom,vfe175", "qcom,vfe170", "qcom,vfe175_130",
+ "qcom,vfe-lite480", "qcom,vfe-lite175", "qcom,vfe-lite175_130", "qcom,vfe-lite170".
+
+- cell-index
+ Usage: required
+ Value type: <u32>
+ Definition: Should specify the hardware index id.
+
+- reg-names
+ Usage: required
+ Value type: <string>
+ Definition: Should specify the name of the register block.
+
+- reg
+ Usage: required
+ Value type: <u32>
+ Definition: Register values.
+
+- interrupt-names
+ Usage: Required
+ Value type: <string>
+ Definition: Name of the interrupt.
+
+- interrupts
+ Usage: Required
+ Value type: <u32>
+ Definition: Interrupt associated with VFE HW.
+
+- regulator-names
+ Usage: required
+ Value type: <string>
+ Definition: Name of the regulator resources for VFE HW.
+
+- xxxx-supply
+ Usage: required
+ Value type: <phandle>
+ Definition: Regulator reference corresponding to the names listed in
+ "regulator-names".
+
+- clock-names
+ Usage: required
+ Value type: <string>
+ Definition: List of clock names required for VFE HW.
+
+- clocks
+ Usage: required
+ Value type: <phandle>
+ Definition: List of clocks used for VFE HW.
+
+- clock-rates
+ Usage: required
+ Value type: <u32>
+ Definition: List of clocks rates.
+
+- src-clock-name
+ Usage: required
+ Value type: <string>
+ Definition: Source clock name.
+
+Optional properties:
+- clock-names-option
+ Usage: optional
+ Value type: <string>
+ Definition: Optional clock names.
+
+- clocks-option
+ Usage: required if clock-names-option defined
+ Value type: <phandle>
+ Definition: List of optinal clocks used for VFE HW.
+
+- clock-rates-option
+ Usage: required if clock-names-option defined
+ Value type: <u32>
+ Definition: List of clocks rates for optional clocks.
+
+- clock-control-debugfs
+ Usage: optional
+ Value type: <string>
+ Definition: Enable/Disable clk rate control.
+
+- qcom,cam-cx-ipeak:
+ Usage: optional
+ Value type: <phandle bit>
+ phandle - phandle of CX Ipeak device node
+ bit - Every bit corresponds to a client of CX Ipeak
+ Definition: CX Ipeak is a mitigation scheme which throttles camera frequency
+ if all the clients are running at their respective threshold
+ frequencies to limit CX peak current.
+ driver in the relevant register.
+
+Example:
+ qcom,vfe0@acaf000 {
+ cell-index = <0>;
+ compatible = "qcom,vfe480";
+ reg-names = "ife";
+ reg = <0xacaf000 0x4000>;
+ interrupts = <0 465 0>;
+ interrupt-names = "ife";
+ vdd-names = "camss-vdd", "ife0-vdd";
+ camss-vdd-supply = <&titan_top_gdsc>;
+ ife0-vdd-supply = <&ife_0_gdsc>;
+ clock-names = "soc_ahb_clk",
+ "cpas_ahb_clk",
+ "slow_ahb_clk_src",
+ "ife_clk",
+ "ife_clk_src",
+ "ife_csid_clk",
+ "ife_csid_clk_src",
+ "camnoc_axi_clk",
+ "ife_axi_clk",
+ clocks = <&clock_camcc CAM_CC_SOC_AHB_CLK>,
+ <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
+ <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_0_CLK>,
+ <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
+ <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
+ <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
+ clock-rates = <0 0 80000000 0 320000000 0 384000000 0 0 0>;
+ src-clock-name = "ife_clk_src";
+ clock-names-option = "ife_dsp_clk";
+ clocks-option = <&clock_camcc CAM_CC_IFE_0_DSP_CLK>;
+ clock-rates-option = <600000000>;
+ qcom,cam-cx-ipeak = <&cx_ipeak_lm 2>;
+ status = "ok";
+ };