Commit label r00062.1a - ES5 0.0.062.1a

TRACKING-ID:61c69312-1265-42e7-9bf4-b2978b9c9e60

221 files changed, 20786 insertions, 1707 deletions

diff --git a/bindings/arm/msm/heap-sharing.txt b/bindings/arm/msm/heap-sharing.txt
index 03b1efdd..77ca3498 100755
--- a/bindings/arm/msm/heap-sharing.txt
+++ b/bindings/arm/msm/heap-sharing.txt
@@ -31,6 +31,8 @@ Optional properties for child nodes:
 
 - qcom,allocate-on-request:	Indicates memory allocation happens only upon client request
 
+- qcom,shared:			Indicates memory allocation should be shared by HLOS and peripheral.
+
 Note: qcom,allocate-boot-time and qcom,allocate-on-request are mutually exclusive rite now.
 
 - qcom,guard-band:	Indicates addition of a guard band memory allocation in addition to the client's memory region.
@@ -62,4 +64,4 @@ qcom,memshare {
 		qcom,guard-band;
 		label = "modem";
 	};
-};
\ No newline at end of file
+};
diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt
index bdf8ed7d..5aa5cebd 100755
--- a/bindings/arm/msm/msm.txt
+++ b/bindings/arm/msm/msm.txt
@@ -107,6 +107,9 @@ SoCs:
 - KAKA
   compatible = "qcom,kaka"
 
+- CROW
+  compatible = "qcom,crow"
+
 - CINDER
   compatible = "qcom,cinder"
 
@@ -128,6 +131,9 @@ SoCs:
 - SDXBAAGHA
   compatible = "qcom,sdxbaagha"
 
+- MONACO_AUTO
+  compatible = "qcom,monaco_auto"
+
 Generic board variants:
 
 - CDP device:
@@ -252,6 +258,7 @@ compatible = "qcom,kona-cdp"
 compatible = "qcom,kona-qrd"
 compatible = "qcom,kona-iot"
 compatible = "qcom,kona-iot-qrd"
+compatible = "qcom,kona-hdk"
 compatible = "qcom,lahaina-rumi"
 compatible = "qcom,lahaina-atp"
 compatible = "qcom,lahaina-mtp"
@@ -283,6 +290,7 @@ compatible = "qcom,sm6150-qrd"
 compatible = "qcom,sm6150-idp"
 compatible = "qcom,qcs405-rumi"
 compatible = "qcom,qcs405-iot"
+compatible = "qcom,qcs407-iot"
 compatible = "qcom,qcs403-iot"
 compatible = "qcom,sa8150-adp-star"
 compatible = "qcom,adp-star"
@@ -322,6 +330,7 @@ compatible = "qcom,kalamap-qrd"
 compatible = "qcom,kalamap-hdk"
 compatible = "qcom,kalamap-hhg"
 compatible = "qcom,kaka-rumi"
+compatible = "qcom,crow-rumi"
 compatible = "qcom,cinder-rumi"
 compatible = "qcom,cinder-idp"
 compatible = "qcom,cinder-x100"
@@ -366,3 +375,4 @@ compatible = "qcom,lemans-adas-high-adp-star"
 compatible = "qcom,lemans-adas-high-qam-star"
 compatible = "qcom,lemans-ivi-adas-adp-star"
 compatible = "qcom,lemans-ivi-adas-qam-star"
+compatible = "qcom,monaco_auto-rumi"
diff --git a/bindings/clock/qcom,camcc.txt b/bindings/clock/qcom,camcc.txt
index 9cddfbce..889d8737 100755
--- a/bindings/clock/qcom,camcc.txt
+++ b/bindings/clock/qcom,camcc.txt
@@ -19,6 +19,7 @@ Required properties :
 		"qcom,sc8180x-camcc"
 		"qcom,sm8250-camcc"
 		"qcom,lemans-camcc"
+		"qcom,crow-camcc"
 
 - reg : shall contain base register location and length.
 - #clock-cells : from common clock binding, shall contain 1.
diff --git a/bindings/clock/qcom,debugcc.txt b/bindings/clock/qcom,debugcc.txt
index cced5fab..61e8d7e3 100755
--- a/bindings/clock/qcom,debugcc.txt
+++ b/bindings/clock/qcom,debugcc.txt
@@ -13,6 +13,7 @@ Required properties :
 			"qcom,kalama-debugcc"
 			"qcom,sm8150-debugcc"
 			"qcom,cinder-debugcc"
+			"qcom,cinder-debugcc-v2"
 			"qcom,khaje-debugcc"
 			"qcom,sc8180x-debugcc"
 			"qcom,monaco-debugcc"
diff --git a/bindings/clock/qcom,dispcc.txt b/bindings/clock/qcom,dispcc.txt
index 71a6cc58..70deebda 100755
--- a/bindings/clock/qcom,dispcc.txt
+++ b/bindings/clock/qcom,dispcc.txt
@@ -29,6 +29,7 @@ Required properties :
 			"qcom,lemans-dispcc0"
 			"qcom,lemans-dispcc1"
                         "qcom,sm8250-dispcc"
+			"qcom,crow-dispcc"
 
 - reg : shall contain base register location and length.
 - #clock-cells : from common clock binding, shall contain 1.
diff --git a/bindings/clock/qcom,ecpricc.txt b/bindings/clock/qcom,ecpricc.txt
index 5dc95e3a..386c7509 100755
--- a/bindings/clock/qcom,ecpricc.txt
+++ b/bindings/clock/qcom,ecpricc.txt
@@ -2,7 +2,7 @@ Qualcomm Technologies, Inc. ECPRI Clock Controller Binding
 --------------------------------------------------------------------
 
 Required properties :
-- compatible : shall contain "qcom,cinder-ecpricc"
+- compatible : shall contain "qcom,cinder-ecpricc" or "qcom,cinder-ecpricc-v2"
 
 - reg: shall contain base register offset and size.
 - reg-names: names of registers listed in the same order as in the reg property.
diff --git a/bindings/clock/qcom,gcc.txt b/bindings/clock/qcom,gcc.txt
index 1b13ef77..ac97f4b6 100755
--- a/bindings/clock/qcom,gcc.txt
+++ b/bindings/clock/qcom,gcc.txt
@@ -37,6 +37,7 @@ Required properties :
 			"qcom,kalama-gcc"
 			"qcom,kalama-gcc-v2"
 			"qcom,cinder-gcc"
+			"qcom,cinder-gcc-v2"
 			"qcom,khaje-gcc"
 			"qcom,gcc-sc8180x"
 			"qcom,monaco-gcc"
@@ -46,6 +47,7 @@ Required properties :
 			"qcom,lemans-gcc"
 			"qcom,sa410m-gcc"
 			"qcom,direwolf-gcc"
+			"qcom,crow-gcc"
 
 - reg : shall contain base register location and length
 - vdd_cx-supply: The vdd_cx logic rail supply.
diff --git a/bindings/clock/qcom,gpucc.txt b/bindings/clock/qcom,gpucc.txt
index 57af8042..ec5071ee 100755
--- a/bindings/clock/qcom,gpucc.txt
+++ b/bindings/clock/qcom,gpucc.txt
@@ -18,6 +18,7 @@ Required properties :
 		"qcom,monaco-gpucc",
 		"qcom,scuba-gpucc"
 		"qcom,lemans-gpucc"
+		"qcom,crow-gpucc"
 
 - reg: shall contain base register offset and size.
 - reg-names: names of registers listed in the same order as in the reg property.
diff --git a/bindings/clock/qcom,tcsrcc.txt b/bindings/clock/qcom,tcsrcc.txt
index 72b63cd9..2f84d0a7 100755
--- a/bindings/clock/qcom,tcsrcc.txt
+++ b/bindings/clock/qcom,tcsrcc.txt
@@ -4,7 +4,8 @@ Qualcomm Technologies, Inc. Top-Level CSR Clock & Reset Controller Binding
 Required properties :
 - compatible : shall contain only one of the following:
 
-			"qcom,tcsrcc-kalama"
+			"qcom,kalama-tcsrcc"
+			"qcom,crow-tcsrcc"
 
 - reg : shall contain base register location and length
 - #clock-cells : from common clock binding, shall contain 1.
diff --git a/bindings/clock/qcom,videocc.txt b/bindings/clock/qcom,videocc.txt
index 74772ab8..9a6c93a8 100755
--- a/bindings/clock/qcom,videocc.txt
+++ b/bindings/clock/qcom,videocc.txt
@@ -17,6 +17,7 @@ Required properties :
 			"qcom,sa8155-videocc"
 			"qcom,sa8155-videocc-v2"
 			"qcom,lemans-videocc"
+			"qcom,crow-videocc"
 
 - reg : shall contain base register location and length
 - #clock-cells : from common clock binding, shall contain 1.
diff --git a/bindings/crypto/msm/ice.txt b/bindings/crypto/msm/ice.txt
new file mode 100755
index 00000000..acafaebd
--- /dev/null
+++ b/bindings/crypto/msm/ice.txt
@@ -0,0 +1,51 @@
+* Inline Crypto Engine (ICE)
+
+Required properties:
+  - compatible : should be "qcom,ice"
+  - reg : <register mapping>
+
+Optional properties:
+  - interrupt-names     	: name describing the interrupts for ICE IRQ
+  - interrupts          	: <interrupt mapping for ICE IRQ>
+  - qcom,enable-ice-clk 	: should enable clocks for ICE HW
+  - clocks              	: List of phandle and clock specifier pairs
+  - clock-names         	: List of clock input name strings sorted in the same
+								order as the clocks property.
+  - qocm,op-freq-hz     	: max clock speed sorted in the same order as the clocks
+								property.
+  - qcom,instance-type  	: describe the storage type for which ICE node is defined
+								currently, only "ufs" and "sdcc" are supported storage type
+  - vdd-hba-supply		: regulated supply to be used by ICE HW
+  - qcom,bus-vector-names	: bus vectors mapping
+
+Example:
+        ufs_ice: ufsice@630000 {
+                compatible = "qcom,ice";
+                reg = <0x630000 0x8000>;
+                interrupt-names = "ufs_ice_nonsec_level_irq", "ufs_ice_sec_level_irq";
+                interrupts = <0 258 0>, <0 257 0>;
+                qcom,enable-ice-clk;
+                clock-names = "ice_core_clk_src", "ice_core_clk";
+                clocks = <&clock_gcc clk_ufs_ice_core_clk_src>,
+                         <&clock_gcc clk_gcc_ufs_ice_core_clk>;
+                qcom,op-freq-hz = <300000000>, <0>;
+		qcom,instance-type = "ufs";
+                status = "disabled";
+        };
+
+	ufs_card_ice: ufscardice@1db0000 {
+		compatible = "qcom,ice_card";
+		reg = <0x1db0000 0x8000>;
+		qcom,enable-ice-clk;
+		clock-names = "ufs_core_clk", "bus_clk",
+			      "iface_clk", "ice_core_clk";
+		clocks = <&clock_gcc GCC_UFS_CARD_AXI_CLK>,
+			 <&clock_gcc GCC_UFS_CARD_CLKREF_CLK>,
+			 <&clock_gcc GCC_UFS_CARD_AHB_CLK>,
+			 <&clock_gcc GCC_UFS_CARD_ICE_CORE_CLK>;
+		qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;
+		vdd-hba-supply = <&ufs_card_gdsc>;
+		qcom,bus-vector-names = "MIN",
+					"MAX";
+		qcom,instance-type = "ufs_card";
+	};
diff --git a/bindings/interrupt-controller/qcom,mpm.txt b/bindings/interrupt-controller/qcom,mpm.txt
index f4196db8..71a20d87 100755
--- a/bindings/interrupt-controller/qcom,mpm.txt
+++ b/bindings/interrupt-controller/qcom,mpm.txt
@@ -28,6 +28,7 @@ Properties:
 		"qcom,mpm-monaco"
 		"qcom,mpm-scuba"
 		"qcom,mpm-sa410m"
+		"qcom,mpm-qcs405"
 
 - interrupts:
 	Usage: required
diff --git a/bindings/interrupt-controller/qcom,pdc.txt b/bindings/interrupt-controller/qcom,pdc.txt
index a2030839..a38dd5d8 100755
--- a/bindings/interrupt-controller/qcom,pdc.txt
+++ b/bindings/interrupt-controller/qcom,pdc.txt
@@ -28,6 +28,7 @@ Properties:
 		    - "qcom,lemans-pdc": For lemans
 		    - "qcom,sdxbaagha-pdc": For SDXBAAGHA
 		    - "qcom,kona-pdc": For Kona
+		    - "qcom,crow-pdc": For Crow
 
 - reg:
 	Usage: required
diff --git a/bindings/iommu/virt,smmu-v3.txt b/bindings/iommu/virt,smmu-v3.txt
new file mode 100755
index 00000000..3bb431a4
--- /dev/null
+++ b/bindings/iommu/virt,smmu-v3.txt
@@ -0,0 +1,28 @@
+* Paravirtualized ARM SMMUv3
+
+The Parvirt smmu-v3 driver communicates with the underlying
+hypervisor to provide S1 translation context descriptor and
+other properties which is set by the client. The backend SMMUv3
+driver in hypervisor is supposed to program the SMMUv3 hardware
+with the information from the paravirt SMMUv3 driver.
+
+** Paravirt SMMUv3 required properties:
+
+- compatible        : Should include:
+
+			"arm,virt-smmu-v3"
+
+
+- #iommu-cells      : See the generic IOMMU binding described in
+                      devicetree/bindings/pci/pci-iommu.txt
+                      for details. For Paravirt SMMUv3, must be 1,
+		      with each cell describing a single stream ID.
+		      All possible stream IDs which a device may
+		      emit must be described.
+
+** Example
+
+	virt_smmuv3: qcom,virt-smmuv3 {
+		#iommu-cells = <1>;
+		compatible = "arm,virt-smmu-v3";
+	};
diff --git a/bindings/media/msm-npu-pwrlevels.txt b/bindings/media/msm-npu-pwrlevels.txt
new file mode 100755
index 00000000..9a8a014c
--- /dev/null
+++ b/bindings/media/msm-npu-pwrlevels.txt
@@ -0,0 +1,164 @@
+Qualcomm Technologies, Inc. NPU powerlevels
+
+Powerlevels are defined in sets by qcom,npu-pwrlevels. Each powerlevel defines
+a series of clock frequencies. These frequencies are for the corresponding
+clocks in the clocks property of the msm_npu device.
+
+qcom,npu-pwrlevels bindings:
+
+Required Properties:
+- #address-cells: Should be set to 1
+- #size-cells: Should be set to 0
+- compatible: Must be qcom,npu-pwrlevels
+- initial-pwrlevel: NPU initial wakeup power level, this is the index of the
+	child node.
+
+qcom,npu-pwrlevel: This is a child node defining power levels.
+qcom,npu-pwrlevels must contain at least one power level node. Each child node
+has the following properties:
+
+Required Properties:
+- reg: Index of the powerlevel (0 = lowest performance)
+- clk-freq: List of clock frequencies (in Hz) of each clock for the current
+	powerlevel. List of clocks and order described in:
+	Documentation/devicetree/bindings/media/msm-npu.txt
+
+Example:
+	qcom,npu-pwrlevels {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "qcom,npu-pwrlevels";
+		initial-pwrlevel = <4>;
+		qcom,npu-pwrlevel@0 {
+			reg = <0>;
+			clk-freq = <9600000
+					9600000
+					19200000
+					19200000
+					19200000
+					19200000
+					9600000
+					60000000
+					19200000
+					19200000
+					30000000
+					19200000
+					19200000
+					19200000
+					19200000
+					19200000
+					9600000
+					19200000
+					0>;
+		};
+		qcom,npu-pwrlevel@1 {
+			reg = <1>;
+			clk-freq = <300000000
+					300000000
+					19200000
+					100000000
+					19200000
+					19200000
+					300000000
+					150000000
+					19200000
+					19200000
+					60000000
+					100000000
+					100000000
+					37500000
+					100000000
+					19200000
+					300000000
+					19200000
+					0>;
+		};
+		qcom,npu-pwrlevel@2 {
+			reg = <2>;
+			clk-freq = <350000000
+					350000000
+					19200000
+					150000000
+					19200000
+					19200000
+					350000000
+					200000000
+					37500000
+					19200000
+					120000000
+					150000000
+					150000000
+					75000000
+					150000000
+					19200000
+					350000000
+					19200000
+					0>;
+		};
+		qcom,npu-pwrlevel@3 {
+			reg = <3>;
+			clk-freq = <400000000
+					400000000
+					19200000
+					200000000
+					19200000
+					19200000
+					400000000
+					300000000
+					37500000
+					19200000
+					120000000
+					200000000
+					200000000
+					75000000
+					200000000
+					19200000
+					400000000
+					19200000
+					0>;
+		};
+		qcom,npu-pwrlevel@4 {
+			reg = <4>;
+			clk-freq = <600000000
+					600000000
+					19200000
+					300000000
+					19200000
+					19200000
+					600000000
+					403000000
+					75000000
+					19200000
+					240000000
+					300000000
+					300000000
+					150000000
+					300000000
+					19200000
+					600000000
+					19200000
+					0>;
+		};
+		qcom,npu-pwrlevel@5 {
+			reg = <5>;
+			clk-freq = <715000000
+					715000000
+					19200000
+					350000000
+					19200000
+					19200000
+					715000000
+					533000000
+					75000000
+					19200000
+					240000000
+					350000000
+					350000000
+					150000000
+					350000000
+					19200000
+					715000000
+					19200000
+					0>;
+		};
+	};
diff --git a/bindings/media/msm-npu.txt b/bindings/media/msm-npu.txt
new file mode 100755
index 00000000..f009650f
--- /dev/null
+++ b/bindings/media/msm-npu.txt
@@ -0,0 +1,228 @@
+* Qualcomm Technologies, Inc. MSM NPU
+
+NPU (Neural Network Processing Unit) applies neural network processing
+
+Required properties:
+- compatible: Must be "qcom,msm-npu"
+- reg: Specify offset and length of the device register sets.
+- reg-names: Names corresponding to the defined register sets.
+	- "npu_base": npu base registers
+- interrupts: Specify the npu interrupts.
+- interrupt-names: should specify relevant names to each interrupts
+	property defined.
+- cache-slice-names: A set of names that identify the usecase names of a
+	client that uses cache slice. These strings are used to look up the
+	cache slice entries by name
+- cache-slices: The tuple has phandle to llcc device as the first argument
+	and the second argument is the usecase id of the client
+- clocks: clocks required for the device.
+- clock-names: names of clocks required for the device.
+- vdd-supply: Phandle for vdd regulator device node
+- vdd_'reg'-supply: Reference to the regulator that supplies the corresponding
+	'reg' domain, e.g. vdd_cx-supply.
+- qcom,proxy-reg-names: Names of the regulators that need to be turned on/off
+	during proxy voting/unvoting.
+- qcom,vdd_'reg'-uV-uA: Voltage and current values for the 'reg' regulator,
+	e.g. qcom,vdd_cx-uV-uA.
+- mboxes: Phandle array for mailbox controllers to be used for IPC
+- mbox-names: names of each mailboxes
+- #cooling-cells: Should be set to 2
+- qcom,npubw-dev: a phandle to a device representing bus bandwidth requirements
+	(see devbw.txt)
+- qcom,npu-pwrlevels: Container for NPU power levels
+	(see msm-npu-pwrlevels.txt)
+Example:
+	msm_npu: qcom,msm_npu@9800000 {
+		compatible = "qcom,msm-npu";
+		status = "ok";
+		reg = <0x9800000 0x800000>;
+		reg-names = "npu_base";
+		interrupts = <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>;
+		iommus = <&apps_smmu 0x1461 0x0>, <&apps_smmu 0x2061 0x0>;
+		cache-slice-names = "npu";
+		cache-slices = <&llcc 23>;
+		clocks = <&clock_npucc NPU_CC_CAL_DP_CLK>,
+				<&clock_npucc NPU_CC_CAL_DP_CLK_SRC>,
+				<&clock_npucc NPU_CC_XO_CLK>,
+				<&clock_npucc NPU_CC_ARMWIC_CORE_CLK>,
+				<&clock_npucc NPU_CC_BTO_CORE_CLK>,
+				<&clock_npucc NPU_CC_BWMON_CLK>,
+				<&clock_npucc NPU_CC_CAL_DP_CDC_CLK>,
+				<&clock_npucc NPU_CC_COMP_NOC_AXI_CLK>,
+				<&clock_npucc NPU_CC_CONF_NOC_AHB_CLK>,
+				<&clock_npucc NPU_CC_NPU_CORE_APB_CLK>,
+				<&clock_npucc NPU_CC_NPU_CORE_ATB_CLK>,
+				<&clock_npucc NPU_CC_NPU_CORE_CLK>,
+				<&clock_npucc NPU_CC_NPU_CORE_CLK_SRC>,
+				<&clock_npucc NPU_CC_NPU_CORE_CTI_CLK>,
+				<&clock_npucc NPU_CC_NPU_CPC_CLK>,
+				<&clock_npucc NPU_CC_NPU_CPC_TIMER_CLK>,
+				<&clock_npucc NPU_CC_PERF_CNT_CLK>,
+				<&clock_npucc NPU_CC_QTIMER_CORE_CLK>,
+				<&clock_npucc NPU_CC_SLEEP_CLK>;
+		clock-names = "cal_dp_clk",
+				"cal_dp_clk_src",
+				"xo_clk",
+				"armwic_core_clk",
+				"bto_core_clk",
+				"bwmon_clk",
+				"cal_dp_cdc_clk",
+				"comp_noc_axi_clk",
+				"conf_noc_ahb_clk",
+				"npu_core_apb_clk",
+				"npu_core_atb_clk",
+				"npu_core_clk",
+				"npu_core_clk_src",
+				"npu_core_cti_clk",
+				"npu_cpc_clk",
+				"npu_cpc_timer_clk",
+				"perf_cnt_clk",
+				"qtimer_core_clk",
+				"sleep_clk";
+		vdd-supply = <&npu_core_gdsc>;
+		vdd_cx-supply = <&pm8150l_s6_level>;
+		qcom,proxy-reg-names ="vdd", "vdd_cx";
+		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+		mboxes = <&qmp_npu0 0>, <&qmp_npu1 0>;
+		mbox-names = "npu_low", "npu_high";
+		#cooling-cells = <2>;
+		qcom,npubw-dev = <&npu_npu_ddr_bw>;
+		qcom,npu-pwrlevels {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "qcom,npu-pwrlevels";
+			initial-pwrlevel = <4>;
+			qcom,npu-pwrlevel@0 {
+				reg = <0>;
+				clk-freq = <9600000
+						9600000
+						19200000
+						19200000
+						19200000
+						19200000
+						9600000
+						60000000
+						19200000
+						19200000
+						30000000
+						19200000
+						19200000
+						19200000
+						19200000
+						19200000
+						9600000
+						19200000
+						0>;
+			};
+			qcom,npu-pwrlevel@1 {
+				reg = <1>;
+				clk-freq = <300000000
+						300000000
+						19200000
+						100000000
+						19200000
+						19200000
+						300000000
+						150000000
+						19200000
+						19200000
+						60000000
+						100000000
+						100000000
+						37500000
+						100000000
+						19200000
+						300000000
+						19200000
+						0>;
+			};
+			qcom,npu-pwrlevel@2 {
+				reg = <2>;
+				clk-freq = <350000000
+						350000000
+						19200000
+						150000000
+						19200000
+						19200000
+						350000000
+						200000000
+						37500000
+						19200000
+						120000000
+						150000000
+						150000000
+						75000000
+						150000000
+						19200000
+						350000000
+						19200000
+						0>;
+			};
+			qcom,npu-pwrlevel@3 {
+				reg = <3>;
+				clk-freq = <400000000
+						400000000
+						19200000
+						200000000
+						19200000
+						19200000
+						400000000
+						300000000
+						37500000
+						19200000
+						120000000
+						200000000
+						200000000
+						75000000
+						200000000
+						19200000
+						400000000
+						19200000
+						0>;
+			};
+			qcom,npu-pwrlevel@4 {
+				reg = <4>;
+				clk-freq = <600000000
+						600000000
+						19200000
+						300000000
+						19200000
+						19200000
+						600000000
+						403000000
+						75000000
+						19200000
+						240000000
+						300000000
+						300000000
+						150000000
+						300000000
+						19200000
+						600000000
+						19200000
+						0>;
+			};
+			qcom,npu-pwrlevel@5 {
+				reg = <5>;
+				clk-freq = <715000000
+						715000000
+						19200000
+						350000000
+						19200000
+						19200000
+						715000000
+						533000000
+						75000000
+						19200000
+						240000000
+						350000000
+						350000000
+						150000000
+						350000000
+						19200000
+						715000000
+						19200000
+						0>;
+			};
+		};
+	};
diff --git a/bindings/msm_mhi_dev.txt b/bindings/msm_mhi_dev.txt
index 52d20dde..18e6f9bb 100755
--- a/bindings/msm_mhi_dev.txt
+++ b/bindings/msm_mhi_dev.txt
@@ -43,6 +43,8 @@ Required properties:
 Optional property:
   - qcom,mhi-ethernet-interface;: If property is present use ethernet packet
 	parsing support.
+  - qcom,tx_rx_reqs: If property present it will override the number of elements
+	in rx and tx queues for mhi_dev_net device.(Default:128)
 
 Example:
 	mhi: qcom,msm-mhi-dev {
diff --git a/bindings/net/qcom-qrtr-genpool.yaml b/bindings/net/qcom-qrtr-genpool.yaml
index 9d25994d..37f11f82 100755
--- a/bindings/net/qcom-qrtr-genpool.yaml
+++ b/bindings/net/qcom-qrtr-genpool.yaml
@@ -24,26 +24,36 @@ properties:
       Phandle reference to a client which has a dedicated memory region for
       sharing between Virtual Machine and Digital Signal Processor subsystem.
 
-  genpool-poll:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      If set, enables polling mode for RX.
-
-  genpool-poll-sleep:
-    $ref: /schemas/types.yaml#/definitions/uint32
-    maxItems: 1
-    description:
-      Sleep (ms) between each poll. If not set, the default interval is 100ms.
+  interrupts:
+    description: |
+      IRQs for setting up and transferring data from and to an edge.
+    items:
+      - description: IRQ from an edge to check if FIFO and memory is setup
+      - description: IRQ from an edge informing there is data to consume
+
+  mboxes:
+    description: |
+      List of phandles to mailbox channels used for setting up and transferring
+      data from and to an edge.
+    items:
+      - description: mailbox for signaling an edge that FIFO and memory is setup
+      - description: mailbox for signaling an edge there is data to consume
 
 required:
   -compatible
   -gen-pool
+  -interrupt-parent
+  -interrupts
+  -mboxes
 
 examples:
   - |
     qrtr-genpool {
         compatible = "qcom,qrtr-genpool";
         gen-pool = <&fastrpc_compute_cb1>;
-        genpool-poll;
-        genpool-poll-sleep = <1000>;
+        interrupt-parent = <&ipcc_mproc_ns1>;
+        interrupts = <IPCC_CLIENT_CDSP 0 IRQ_TYPE_EDGE_RISING>,
+                <IPCC_CLIENT_CDSP 1 IRQ_TYPE_EDGE_RISING>;
+        mboxes = <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 0>,
+                <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 1>;
     };
diff --git a/bindings/pci/msm_ep_pcie.txt b/bindings/pci/msm_ep_pcie.txt
index 425bddc9..351eb34c 100755
--- a/bindings/pci/msm_ep_pcie.txt
+++ b/bindings/pci/msm_ep_pcie.txt
@@ -75,6 +75,7 @@ Optional Properties:
 	- qcom,msm-bus,vectors-KBps
   - qcom,pcie-m2-autonomous: Enable L1ss sleep/exit to support M2 autonomous mode.
   - qcom,mhi-soc-reset-offset: AXI register offset to initiate a SOC reset.
+  - qcom,override-disable-sriov: Set to report as SRIOV capability disable with client (MHI) driver.
 
 Example:
 
diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt
index cdf1976c..4879cc92 100755
--- a/bindings/pci/pci-msm.txt
+++ b/bindings/pci/pci-msm.txt
@@ -244,6 +244,11 @@ interconnects:
 	Value type: <bool>
 	Definition: Support clock power management
 
+- qcom,gdsc-clk-drv-ss-nonvotable:
+	Usage: optional
+	Value type: <bool>
+	Definition: gdsc clock can't be turned off during DRV process.
+
 - qcom,n-fts:
 	Usage: optional
 	Value type: <u32>
@@ -510,6 +515,7 @@ Example
 		qcom,boot-option = <0x1>;
 		qcom,drv-name = "lpass";
 		qcom,use-19p2mhz-aux-clk;
+		qcom,gdsc-clk-drv-ss-nonvotable;
 		qcom,common-clk-en;
 		qcom,clk-power-manage-en;
 		qcom,n-fts = <0x50>;
diff --git a/bindings/pinctrl/qcom,crow-pinctrl.yaml b/bindings/pinctrl/qcom,crow-pinctrl.yaml
new file mode 100755
index 00000000..4a27f5b4
--- /dev/null
+++ b/bindings/pinctrl/qcom,crow-pinctrl.yaml
@@ -0,0 +1,135 @@
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,crow-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. CROW TLMM block
+
+maintainers:
+  - Naini Singh  <nainsing@qti.qualcomm.com>
+
+description: |
+  This binding describes the Top Level Mode Multiplexer block.
+
+properties:
+  compatible:
+    oneOf:
+      const: qcom,crow-pinctrl
+
+  reg:
+    items:
+      - description: Base address of TLMM register space
+      - description: Size of TLMM register space
+
+  interrupts:
+    minItems: 0
+    maxItems: 1
+    items:
+      - const: TLMM summary IRQ
+
+  interrupt-controller: true
+
+  '#interrupt-cells':
+    const: 2
+
+  gpio-controller: true
+
+  '#gpio-cells':
+    const: 2
+
+  wakeup-parent:
+    maxItems: 1
+    description:
+      Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+      a general description of GPIO and interrupt bindings.
+
+      Please refer to pinctrl-bindings.txt in this directory for details of the
+      common pinctrl bindings used by client devices, including the meaning of the
+      phrase "pin configuration node".
+
+      The pin configuration nodes act as a container for an arbitrary number of
+      subnodes. Each of these subnodes represents some desired configuration for a
+      pin, a group, or a list of pins or groups. This configuration can include the
+      mux function to select on those pin(s)/group(s), and various pin configuration
+      parameters, such as pull-up, drive strength, etc.
+
+
+# PIN CONFIGURATION NODES
+patternPropetries:
+  '^.*$':
+    if:
+      type: object
+    then:
+      properties:
+        pins:
+          description:
+            List of gpio pins affected by the properties specified in
+            this subnode.
+          items:
+            oneOf:
+              - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])"
+              - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
+            minItems: 1
+            maxItems: 36
+        function:
+          description:
+            Specify the alternative function to be configured for the
+            specified pins. Functions are only valid for gpio pins.
+          enum: [gpio, aon_cam, atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
+            atest_usb0, atest_usb00, atest_usb01, atest_usb02, atest_usb03, audio_ref, cam_mclk,
+            cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
+            cmu_rng0, cmu_rng1, cmu_rng2, cmu_rng3, coex_uart1, coex_uart2, cri_trng, cri_trng0,
+            cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, gcc_gp1,
+            gcc_gp2, gcc_gp3, ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
+            mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws, mi2s2_data0, mi2s2_data1,
+            mi2s2_sck, mi2s2_ws, mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12,
+            mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, mss_grfc7, mss_grfc8, mss_grfc9,
+            nav_0, nav_1, nav_2, pcie0_clkreqn, pcie1_clkreqn, phase_flag0, phase_flag1,
+            phase_flag10, phase_flag11, phase_flag12, phase_flag13, phase_flag14, phase_flag15,
+            phase_flag16, phase_flag17, phase_flag18, phase_flag19, phase_flag2, phase_flag20,
+            phase_flag21, phase_flag22, phase_flag23, phase_flag24, phase_flag25, phase_flag26,
+            phase_flag27, phase_flag28, phase_flag29, phase_flag3, phase_flag30, phase_flag31,
+            phase_flag4, phase_flag5, phase_flag6, phase_flag7, phase_flag8, phase_flag9, pll_bist,
+            pll_clk, pri_mi2s, prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio,
+            qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14,
+            qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, qdss_gpio7,
+            qdss_gpio8, qdss_gpio9, qlink0_enable, qlink0_request, qlink0_wmss, qlink1_enable,
+            qlink1_request, qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, qspi0, qspi1,
+            qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14, qup15,
+            qup16, qup17, qup18, qup19, qup2, qup20, qup21, qup3, qup4, qup5, qup6, qup7, qup8,
+            qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd,
+            sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tmess_prng0, tmess_prng1,
+            tmess_prng2, tmess_prng3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, uim0_present,
+            uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset, usb2phy_ac, usb_phy, vfr_0,
+            vfr_1, vsense_trigger]
+        drive-strength:
+          enum: [2, 4, 6, 8, 10, 12, 14, 16]
+          default: 2
+          description:
+            Selects the drive strength for the specified pins, in mA.
+        qcom,i2c_pull: true
+        description:
+            Configures additions 2.2k drive strength for the specified pin.
+        bias-pull-down: true
+        bias-pull-up: true
+        bias-disable: true
+        output-high: true
+        output-low: true
+      required:
+        - pins
+        - function
+      additionalProperties: false
+
+examples:
+  - |
+    tlmm: pinctrl@03000000 {
+      compatible = "qcom,crow-pinctrl";
+      reg = <0x03000000 0xdc2000>;
+      interrupts = <0 208 0>;
+      gpio-controller;
+      #gpio-cells = <2>;
+      interrupt-controller;
+      #interrupt-cells = <2>;
+      wakeup-parent = <&pdc>;
+    };
+
diff --git a/bindings/pinctrl/qcom,monaco_auto-pinctrl.yaml b/bindings/pinctrl/qcom,monaco_auto-pinctrl.yaml
new file mode 100755
index 00000000..19921572
--- /dev/null
+++ b/bindings/pinctrl/qcom,monaco_auto-pinctrl.yaml
@@ -0,0 +1,148 @@
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,monaco_auto-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. MONACO_AUTO TLMM block
+
+description: |
+  This binding describes the Top Level Mode Multiplexer block found in the
+  Monaco Auto platform.
+
+properties:
+  compatible:
+      Usage: required
+      Value type: <string>
+      Definition: must be "qcom,monaco_auto-pinctrl"
+
+  reg:
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: the base address and size of the TLMM register space.
+
+  interrupts:
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: should specify the TLMM summary IRQ.
+
+  interrupt-controller:
+      Usage: required
+      Value type: <none>
+      Definition: identifies this node as an interrupt controller
+
+  #interrupt-cells:
+      Usage: required
+      Value type: <u32>
+      Definition: must be 2. Specifying the pin number and flags, as defined
+                  in <dt-bindings/interrupt-controller/irq.h>
+
+  gpio-controller:
+      Usage: required
+      Value type: <none>
+      Definition: identifies this node as a gpio controller
+
+  #gpio-cells:
+      Usage: required
+      Value type: <u32>
+      Definition: must be 2. Specifying the pin number and flags, as defined
+                  in <dt-bindings/gpio/gpio.h>
+
+  wakeup-parent:
+      Usage: optional
+      Value type: <phandle>
+      Definition: A phandle to the wakeup interrupt controller for the SoC.
+
+  Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+  a general description of GPIO and interrupt bindings.
+
+  Please refer to pinctrl-bindings.txt in this directory for details of the
+  common pinctrl bindings used by client devices, including the meaning of the
+  phrase "pin configuration node".
+
+  The pin configuration nodes act as a container for an arbitrary number of
+  subnodes. Each of these subnodes represents some desired configuration for a
+  pin, a group, or a list of pins or groups. This configuration can include the
+  mux function to select on those pin(s)/group(s), and various pin configuration
+  parameters, such as pull-up, drive strength, etc.
+
+
+  PIN CONFIGURATION NODES:
+
+  The name of each subnode is not important; all subnodes should be enumerated
+  and processed purely based on their content.
+
+  Each subnode only affects those parameters that are explicitly listed. In
+  other words, a subnode that lists a mux function but no pin configuration
+  parameters implies no information about any pin configuration parameters.
+  Similarly, a pin subnode that describes a pullup parameter implies no
+  information about e.g. the mux function.
+
+
+  The following generic properties as defined in pinctrl-bindings.txt are valid
+  to specify in a pin configuration subnode:
+
+  pins:
+        Usage: required
+        Value type: <string-array>
+        Definition: List of gpio pins affected by the properties specified in
+                    this subnode.
+
+        Valid pins:
+                  gpio0-gpio148
+                  Supports mux, bias and drive-strength
+
+                  sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
+                  sdc2_data sdc1_rclk
+                  Supports bias and drive-strength
+
+  function:
+        Usage: required
+        Value type: <string>
+        Definition: Specify the alternative function to be configured for the
+                    specified pins. Functions are only valid for gpio pins.
+
+  bias-disable:
+    Usage: optional
+    Value type: <none>
+    Definition: The specified pins should be configured as no pull.
+
+  bias-pull-down:
+    Usage: optional
+    Value type: <none>
+    Definition: The specified pins should be configured as pull down.
+
+  bias-pull-up:
+    Usage: optional
+    Value type: <none>
+    Definition: The specified pins should be configured as pull up.
+
+  output-high:
+    Usage: optional
+    Value type: <none>
+    Definition: The specified pins are configured in output mode, driven high.
+                  Not valid for sdc pins.
+
+  output-low:
+    Usage: optional
+    Value type: <none>
+    Definition: The specified pins are configured in output mode, driven low.
+                  Not valid for sdc pins.
+
+  drive-strength:
+    Usage: optional
+    Value type: <u32>
+    Definition: Selects the drive strength for the specified pins, in mA.
+    Valid values: 2, 4, 6, 8, 10, 12, 14 and 16
+
+examples:
+  - |
+    tlmm: pinctrl@03000000 {
+      compatible = "qcom,monaco_auto-pinctrl";
+      reg = <0x03000000 0xdc2000>;
+      interrupts = <0 208 0>;
+      gpio-controller;
+      #gpio-cells = <2>;
+      interrupt-controller;
+      #interrupt-cells = <2>;
+      wakeup-parent = <&pdc>;
+    };
diff --git a/bindings/pinctrl/qcom,pmic-gpio.txt b/bindings/pinctrl/qcom,pmic-gpio.txt
index 1c6a7002..fa125bf1 100755
--- a/bindings/pinctrl/qcom,pmic-gpio.txt
+++ b/bindings/pinctrl/qcom,pmic-gpio.txt
@@ -56,6 +56,7 @@ PMIC's from Qualcomm.
 		    "qcom,pm5100-gpio"
 		    "qcom,pm8775-gpio"
 		    "qcom,pm2250-gpio"
+		    "qcom,pm8009-gpio"
 
 		    And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio"
 		    if the device is on an spmi bus or an ssbi bus respectively
diff --git a/bindings/power/supply/qcom/qcom,qbg.yaml b/bindings/power/supply/qcom/qcom,qbg.yaml
index d5543d89..cfa61c5e 100755
--- a/bindings/power/supply/qcom/qcom,qbg.yaml
+++ b/bindings/power/supply/qcom/qcom,qbg.yaml
@@ -66,6 +66,11 @@ properties:
     $ref: /schemas/types.yaml#/definitions/uint32
     description: Resistance of the battery connector in mOhms.
 
+  qcom,qbg-vbatt-empty-threshold-mv:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: Vbatt empty threshold in mv at which QBG generates low Vbatt
+      interrupt.
+
   nvmem-cell-names:
     minItems: 2
     maxItems: 3
diff --git a/bindings/power/supply/qcom/smb1390-charger-psy.txt b/bindings/power/supply/qcom/smb1390-charger-psy.txt
new file mode 100755
index 00000000..b5bcb13f
--- /dev/null
+++ b/bindings/power/supply/qcom/smb1390-charger-psy.txt
@@ -0,0 +1,119 @@
+Qualcomm Technologies, Inc. SMB1390 Charger Specific Bindings
+
+SMB1390 charge pump is paired with QTI family of standalone chargers to
+enable a high current, high efficiency Li+ battery charging system.
+
+=======================
+Required Node Structure
+=======================
+
+SMB1390 Charger must be described in two levels of device nodes.
+
+==================================
+First Level Node - SMB1390 Charger
+==================================
+
+Charger specific properties:
+- compatible
+  Usage:      required
+  Value type: <string>
+  Definition: "qcom,smb1390-charger-psy" for master SMB1390 and
+	      "qcom,smb1390-slave" for slave SMB1390.
+
+- qcom,pmic-revid
+  Usage:      required
+  Value type: phandle
+  Definition: Should specify the phandle of SMB's revid module. This is used
+	      to identify the SMB subtype.
+
+- io-channels
+- io-channel-names
+  Usage:      required
+  Value type: <phandle>
+  Definition: For details about IIO bindings see:
+	      Documentation/devicetree/bindings/iio/iio-bindings.txt
+
+- qcom,min-ilim-ua
+  Usage:      optional
+  Value type: <u32>
+  Definition: Minimum ILIM supported, if requested ILIM goes below this value
+	      disable SMB1390. If this values is not specified default minimum
+	      ILIM is 1A.
+
+- qcom,max-temp-alarm-degc
+  Usage:      optional
+  Value type: <u32>
+  Definition: Maximum die temperature to trigger temp alarm. The value
+	      must be one of the following:
+	      80, 90, 105, 115.
+	      If this value is not specified or is not one of the above
+	      then default value is 105.
+
+- qcom,max-cutoff-soc
+  Usage:      optional
+  Value type: <u32>
+  Definition: SOC beyond which SMB1390 is kept disabled.
+	      If this value is not specified then default value is 85%.
+
+- qcom,parallel-output-mode
+  Usage:      optional
+  Value type: <u32>
+  Definition: Defines the SMB1390 output connection topology.
+		This should be one of the following:
+		0 - If SMB1390 output is not connected to anything;
+		1 - If SMB1390 output is connected to VPH_PWR;
+		2 - If SMB1390 output is connected to VBATT.
+		If this value is not specified then default value is 1.
+
+- qcom,parallel-input-mode
+  Usage:      optional
+  Value type: <u32>
+  Definition: Defines the SMB1390 input connection topology.
+		This should be one of the following:
+		0 - If SMB1390 input is not connected to anything;
+		1 - If SMB1390 input is connected to USBIN;
+		3 - If SMB1390 input is connected to USBMID.
+		If this value is not specified then default value is 3.
+
+================================================
+Second Level Nodes - SMB1390 Charger Peripherals
+================================================
+
+Peripheral specific properties:
+- interrupts
+  Usage:      required
+  Value type: <prop-encoded-array>
+  Definition: Peripheral interrupt specifier.
+
+- interrupt-names
+  Usage:      required
+  Value type: <stringlist>
+  Definition: Interrupt names.  This list must match up 1-to-1 with the
+	      interrupts specified in the 'interrupts' property.
+
+=======
+Example
+=======
+
+smb1390_charger: qcom,charge_pump {
+	compatible = "qcom,smb1390-charger-psy";
+	qcom,pmic-revid = <&smb1390_revid>;
+	interrupt-parent = <&smb1390>;
+	status = "disabled";
+
+	io-channels = <&pm8150b_vadc ADC_AMUX_THM2>;
+	io-channel-names = "cp_die_temp";
+
+	qcom,core {
+		interrupts = <0x10 0x0 IRQ_TYPE_EDGE_RISING>,
+			     <0x10 0x1 IRQ_TYPE_EDGE_RISING>,
+			     <0x10 0x2 IRQ_TYPE_EDGE_RISING>,
+			     <0x10 0x3 IRQ_TYPE_EDGE_RISING>,
+			     <0x10 0x4 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "switcher-off-window",
+				  "switcher-off-fault",
+				  "vph-ov-soft",
+				  "ilim",
+				  "temp-alarm";
+	};
+};
diff --git a/bindings/qdsp/msm-fastrpc.txt b/bindings/qdsp/msm-fastrpc.txt
index d839212b..6ce414b3 100755
--- a/bindings/qdsp/msm-fastrpc.txt
+++ b/bindings/qdsp/msm-fastrpc.txt
@@ -98,3 +98,9 @@ Example:
                memory-region = <&adsp_mem>;
                restrict-access;
        };
+
+       qcom,mdsprpc-mem {
+               compatible = "qcom,msm-mdsprpc-mem-region";
+               memory-region = <&mdsp_mem>;
+               restrict-access;
+       };
diff --git a/bindings/regulator/cpr-regulator.txt b/bindings/regulator/cpr-regulator.txt
new file mode 100755
index 00000000..0f5e27a2
--- /dev/null
+++ b/bindings/regulator/cpr-regulator.txt
@@ -0,0 +1,961 @@
+QTI CPR (Core Power Reduction) Regulator
+
+CPR regulator device is for QTI RBCPR (RapidBridge CPR) on
+	application processor core. It takes voltage corner level
+	as input and converts it to actual voltage based on the
+	suggestions from factory production process. When CPR is
+	enabled for application processer core, it will suggest
+	scaling the voltage up or down for best performance and
+	power of the core. The scaling based on factory production
+	process is called PVS (Process Voltage Scaling) with efuse
+	bits to indicate what bin (and voltage range) a chip is in.
+
+Required properties:
+- compatible:			Must be "qcom,cpr-regulator"
+- reg:				Register addresses for RBCPR, RBCPR clock
+				select, PVS and CPR eFuse address
+- reg-names:			Register names. Must be "rbcpr" and "efuse_addr".
+				"rbcpr_clk" is optional.
+- regulator-name:		A string used to describe the regulator
+- interrupts:			Interrupt line from RBCPR to interrupt controller.
+- qcom,cpr-fuse-corners:	Number of fuse corners present.  Many other properties
+				are sized based upon this value.
+- regulator-min-microvolt:	Minimum corner value which should be 1 to
+				represent the lowest supported corner.
+- regulator-max-microvolt:	Maximum corner value which should be equal to
+				qcom,cpr-fuse-corners if consumers request fuse
+				corners or the length of qcom,cpr-corner-map if
+				consumers request virtual corners.
+- qcom,cpr-voltage-ceiling:	Array of ceiling voltages in microvolts for fuse
+				corners ordered from lowest voltage corner to highest
+				voltage corner.  This property must be of length
+				defined by qcom,cpr-fuse-corners.
+- qcom,cpr-voltage-floor:	Array of floor voltages in microvolts for fuse
+				corners ordered from lowest voltage corner to highest
+				voltage corner.  This property must be of length
+				defined by qcom,cpr-fuse-corners.
+- vdd-apc-supply:		Regulator to supply VDD APC power
+- qcom,vdd-apc-step-up-limit:	Limit of vdd-apc-supply steps for scaling up.
+- qcom,vdd-apc-step-down-limit:	Limit of vdd-apc-supply steps for scaling down.
+- qcom,cpr-ref-clk:		The reference clock in kHz.
+- qcom,cpr-timer-delay:		The delay in microseconds for the timer interval.
+- qcom,cpr-timer-cons-up:	Consecutive number of timer interval (qcom,cpr-timer-delay)
+				occurred before issuing UP interrupt.
+- qcom,cpr-timer-cons-down:	Consecutive number of timer interval (qcom,cpr-timer-delay)
+				occurred before issuing DOWN interrupt.
+- qcom,cpr-irq-line:		Internal interrupt route signal of RBCPR, one of 0, 1 or 2.
+- qcom,cpr-step-quotient:	Defines the number of CPR quotient (i.e. Ring Oscillator(RO)
+				count) per vdd-apc-supply output voltage step.  A single
+				integer value may be specified which is to be used for all
+				RO's.  Alternatively, 8 integer values may be specified which
+				define the step quotients for RO0 to RO7 in order.
+- qcom,cpr-up-threshold:	The threshold for CPR to issue interrupt when
+				error_steps is greater than it when stepping up.
+- qcom,cpr-down-threshold:	The threshold for CPR to issue interrupt when
+				error_steps is greater than it when stepping down.
+- qcom,cpr-idle-clocks:		Idle clock cycles RO can be in.
+- qcom,cpr-gcnt-time:		The time for gate count in microseconds.
+- qcom,cpr-apc-volt-step:	The voltage in microvolt per CPR step, such as 5000uV.
+- qcom,cpr-fuse-row:		Array of row number of CPR fuse and method to read that row. It should have
+				index and value like this:
+				 [0] => the fuse row number
+				 [1] => fuse reading method, 0 for direct reading or 1 for SCM reading
+- qcom,cpr-fuse-target-quot:	Array of bit positions in the primary CPR fuse row defined
+				by qcom,cpr-fuse-row for the target quotients of each
+				fuse corner.  Each bit position corresponds to the LSB
+				of the quotient parameter.  The elements in the array
+				are ordered from lowest voltage corner to highest voltage
+				corner.  This property must be of length defined by
+				qcom,cpr-fuse-corners.
+- qcom,cpr-fuse-ro-sel:		Array of bit positions in the primary CPR fuse row defined
+				by qcom,cpr-fuse-row for the ring oscillator selection for each
+				fuse corner.  Each bit position corresponds to the LSB
+				of the RO select parameter.  The elements in the array
+				are ordered from lowest voltage corner to highest voltage
+				corner.  This property must be of length defined by
+				qcom,cpr-fuse-corners.
+
+Optional properties:
+- vdd-mx-supply:		Regulator to supply memory power as dependency
+				of VDD APC.
+- qcom,vdd-mx-vmax:		The maximum voltage in uV for vdd-mx-supply. This
+				is required when vdd-mx-supply is present.
+- qcom,vdd-mx-vmin-method:	The method to determine the minimum voltage for
+				vdd-mx-supply, which can be one of following
+				choices compared with VDD APC:
+				  0 => equal to the voltage(vmin) of VDD APC
+				  1 => equal to PVS corner ceiling voltage
+				  2 => equal to slow speed corner ceiling
+				  3 => equal to qcom,vdd-mx-vmax
+				  4 => equal to VDD_APC fuse corner mapped vdd-mx voltage
+				  5 => equal to VDD_APC virtual corner mapped vdd-mx voltage
+				This is required when vdd-mx-supply is present.
+- qcom,vdd-mx-corner-map:	Array of integers which defines the mapping from VDD_APC
+				voltage corners to vdd-mx-supply voltages.
+				Each element is a voltage to request from vdd-mx for the
+				corresponding fuse corner or virtual corner. The elements
+				in the array are ordered from lowest voltage corner
+				to highest voltage corner.  The length of this property
+				depends on the value of qcom,vdd-mx-vmin-method property.
+				When qcom,vdd-mx-vmin-method property has a value of 4, the length
+				of this property must be equal to the value defined by qcom,cpr-fuse-corners.
+				When qcom,vdd-mx-vmin-method property has a value of 5, the length of
+				this property must be equal to the number of elements in the qcom,cpr-corner-map
+				property.
+- qcom,pvs-voltage-table: 	Array of N-tuples in which each tuple specifies the
+				initial voltage in microvolts of the PVS bin for each
+				fuse voltage corner.  The location or 0-based index
+				of a tuple in the list corresponds to the PVS bin number.
+				Each tuple must be of length defined by qcom,cpr-fuse-corners.
+				A given cpr-regulator device must have either
+				qcom,pvs-voltage-table specified or
+				qcom,cpr-fuse-init-voltage (and its associated properties).
+- qcom,pvs-fuse-redun-sel:	Array of 5 elements to indicate where to read the bits, what value to
+				compare with in order to decide if the redundant PVS fuse bits would be
+				used instead of the original bits and method to read fuse row, reading
+				register through SCM or directly. The 5 elements with index [0..4] are:
+				  [0] => the fuse row number of the selector
+				  [1] => LSB bit position of the bits
+				  [2] => number of bits
+				  [3] => the value to indicate redundant selection
+				  [4] => fuse reading method, 0 for direct reading or 1 for SCM reading
+				When the value of the fuse bits specified by first 3 elements equals to
+				the value in 4th element, redundant PVS fuse bits should be selected.
+				Otherwise, the original PVS bits should be selected. If the 5th
+				element is 0, read the fuse row from register directly. Otherwise,
+				read it through SCM.
+				This property is required if qcom,pvs-voltage-table is present.
+- qcom,pvs-fuse:		Array of 4 elements to indicate the bits for PVS fuse and read method.
+				The array should have index and value like this:
+				  [0] => the PVS fuse row number
+				  [1] => LSB bit position of the bits
+				  [2] => number of bits
+				  [3] => fuse reading method, 0 for direct reading or 1 for SCM reading
+				This property is required if qcom,pvs-voltage-table is present.
+- qcom,pvs-fuse-redun:		Array of 4 elements to indicate the bits for redundant PVS fuse.
+				The array should have index and value like this:
+				  [0] => the redundant PVS fuse row number
+				  [1] => LSB bit position of the bits
+				  [2] => number of bits
+				  [3] => fuse reading method, 0 for direct reading or 1 for SCM reading
+				This property is required if qcom,pvs-voltage-table is present.
+- qcom,cpr-fuse-redun-sel:	Array of 5 elements to indicate where to read the bits, what value to
+				compare with in order to decide if the redundant CPR fuse bits would be
+				used instead of the original bits and method to read fuse row, using SCM
+				to read or read register directly. The 5 elements with index [0..4] are:
+				  [0] => the fuse row number of the selector
+				  [1] => LSB bit position of the bits
+				  [2] => number of bits
+				  [3] => the value to indicate redundant selection
+				  [4] => fuse reading method, 0 for direct reading or 1 for SCM reading
+				When the value of the fuse bits specified by first 3 elements equals to
+				the value in 4th element, redundant CPR fuse bits should be selected.
+				Otherwise, the original CPR bits should be selected. If the 5th element
+				is 0, read the fuse row from register directly. Otherwise, read it through
+				SCM.
+- qcom,cpr-fuse-redun-row:	Array of row number of redundant CPR fuse and method to read that
+				row. It should have index and value like this:
+				 [0] => the redundant fuse row number
+				 [1] => the value to indicate reading the fuse row directly or using SCM
+				This property is required if qcom,cpr-fuse-redun-sel is present.
+- qcom,cpr-fuse-redun-target-quot:	Array of bit positions in the redundant CPR fuse row defined
+				by qcom,cpr-fuse-redun-row for the target quotients of each
+				fuse corner.  Each bit position corresponds to the LSB
+				of the quotient parameter.  The elements in the array
+				are ordered from lowest voltage corner to highest voltage corner.
+				This property must be of length defined by qcom,cpr-fuse-corners.
+				This property is required if qcom,cpr-fuse-redun-sel is present.
+- qcom,cpr-fuse-redun-ro-sel:	Array of bit positions in the redundant CPR fuse row defined
+				by qcom,cpr-fuse-redun-row for the ring oscillator select of each
+				fuse corner.  Each bit position corresponds to the LSB of the RO
+				select parameter.  The elements in the array are ordered from
+				lowest voltage corner to highest voltage corner.
+				This property must be of length defined by qcom,cpr-fuse-corners.
+				This property is required if qcom,cpr-fuse-redun-sel is present.
+- qcom,cpr-fuse-redun-bp-cpr-disable:	Redundant bit position of the bit to indicate if CPR should be disable
+- qcom,cpr-fuse-redun-bp-scheme:	Redundant bit position of the bit to indicate if it's a global/local scheme
+					This property is required if cpr-fuse-redun-bp-cpr-disable
+					is present, and vise versa.
+- qcom,cpr-fuse-bp-cpr-disable:	Bit position of the bit to indicate if CPR should be disabled
+- qcom,cpr-fuse-bp-scheme:     Bit position of the bit to indicate if it's a global/local scheme
+- qcom,cpr-fuse-revision:	Array of 4 integer elements which define the location of the bits for
+				the CPR fusing revision fuse parameter.  The 4 elements are:
+				[0]: => the fuse row number of the bits
+				[1]: => LSB bit position of the bits
+				[2]: => the number of bits
+				[3]: => fuse reading method, 0 for direct reading or 1 for SCM reading
+				The fusing revision value is used to determine which specific adjustments
+				are required on some chips.
+- qcom,cpr-fuse-target-quot-size:	Array of target quotient parameter bit sizes in the primary
+				or redundant CPR fuse row for each fuse corner.  The elements in the
+				array are ordered from lowest voltage corner to highest voltage corner.
+				If this property is not present, then all target quotient fuse values
+				are assumed to be the default length of 12 bits.
+- qcom,cpr-fuse-target-quot-scale:	Array of doubles which defines the scaling coefficients to decode
+				the target quotients of each fuse corner.  The first element in each
+				double represents the offset to add to the scaled quotient.  The second
+				element represents the multiplier to scale the quotient by.  For example,
+				given a tuple <A B>, quot_decoded = A + (B * quot_raw).
+				The doubles in the array are ordered from lowest voltage corner to highest
+				voltage corner.  This property must contain a number of doubles equal to
+				the value of qcom,cpr-fuse-corners.  If this property is not present,
+				then all target quotient parameters are assumed to have an offset of 0
+				and a multiplier of 1 (i.e. no decoding needed).
+- qcom,cpr-enable:		Present: CPR enabled by default.
+				Not Present: CPR disable by default.
+- qcom,cpr-fuse-cond-min-volt-sel:	Array of 5 elements to indicate where to read the bits,  what value to
+				compare with in order to decide if the conditional minimum apc voltage needs
+				to be applied and the fuse reading method.
+				The 5 elements with index[0..4] are:
+				[0] => the fuse row number;
+				[1] => LSB bit position of the bits;
+				[2] => number of the bits;
+				[3] => the expected data to read;
+				[4] => fuse reading method, 0 for direct reading or 1 for SCM reading;
+				When the value of the fuse bits specified by first 3 elements is not equal to
+				the value in 4th element, then set the apc voltage for all parts running
+				at each voltage corner to be not lower than the voltage defined
+				using "qcom,cpr-cond-min-voltage".
+- qcom,cpr-cond-min-voltage:	Minimum voltage in microvolts allowed for cpr-regulator output if the fuse bits
+				defined in qcom,cpr-fuse-cond-min-volt-sel have not been programmed with the
+				expected data. This is required if cpr-fuse-cond-min-volt-sel is present.
+- qcom,cpr-fuse-uplift-sel: 	Array of 5 elements to indicate where to read the bits, what value to
+				compare with in order to enable or disable the pvs voltage uplift workaround,
+				and the fuse reading method.
+				The 5 elements with index[0..4] are:
+				[0]: => the fuse row number of the selector;
+				[1]: => LSB bit position of the bits;
+				[2]: => number of the bits;
+				[3]: => the value to indicate if the apc pvs voltage uplift workaround will
+					be enabled;
+				[4]: => fuse reading method, 0 for direct reading or 1 for SCM reading.
+				When the value of the fuse bits specified by first 3 elements equals to the
+				value in 4th element, the pvs voltage uplift workaround will be enabled.
+- qcom,speed-bin-fuse-sel:	Array of 4 elements to indicate where to read the speed bin of the processor,
+				and the fuse reading method.
+				The 4 elements with index[0..3] are:
+				[0]: => the fuse row number of the selector;
+				[1]: => LSB bit position of the bits;
+				[2]: => number of the bits;
+				[3]: => fuse reading method, 0 for direct reading or 1 for SCM reading.
+				This is required if cpr-fuse-uplift-disable-sel is present.
+- qcom,cpr-uplift-voltage:	Uplift in microvolts used for increasing pvs init voltage. If this property is present,
+				This is required if cpr-fuse-uplift-disable-sel is present.
+- qcom,cpr-uplift-max-volt:	Maximum voltage in microvolts used for pvs voltage uplift workaround to limit
+				the maximum pvs voltage.
+				This is required if cpr-fuse-uplift-disable-sel is present.
+- qcom,cpr-uplift-quotient:	Array of target quotient increments to add to the fused quotients of each
+				fuse corner as part of the PVS voltage uplift workaround.
+				The elements in the array are ordered from lowest voltage
+				corner to highest voltage corner.  This property must be of
+				length defined by qcom,cpr-fuse-corners.  This is required
+				if cpr-fuse-uplift-disable-sel is present.
+- qcom,cpr-uplift-speed-bin:	The speed bin value corresponding to one type of processor which needs to apply the
+				pvs voltage uplift workaround.
+				This is required if cpr-fuse-uplift-disable-sel is present.
+- qcom,cpr-fuse-version-map:	Array of integer tuples which each match to a given combination of CPR
+				fuse parameter values.  Each tuple consists of N + 3 elements.  Where
+				N is the number of fuse corners defined by the qcom,cpr-fuse-corners
+				property.  The elements in one tuple are:
+				[0]: =>		the speed bin of the CPU
+				[1]: =>		the PVS version of the CPU
+				[2]: =>		the CPR fuse revision
+				[3 - N+2]: =>	the ring oscillator select value of each fuse corner
+						ordered from lowest to highest
+				Any element in a tuple may use the value 0xffffffff as a wildcard
+				which will match against any fuse parameter value.  The first tuple
+				that matches against the fuse values read from hardware will be used.
+				This property is used by several properties to provide an index into
+				their lists.
+- qcom,cpr-allowed:		Integer values that specifies whether the closed loop CPR is allowed or
+				not for a particular fuse revision. If the qcom,cpr-fuse-version-map
+				property is specified, then qcom,cpr-allowed must contain the same number
+				of integers as that of the number of tuples in qcom,cpr-fuse-version-map.
+				If the integer value has a value 0 for a particular fuse revision, then it
+				is treated as if the closed loop operation is disabled in the fuse. If the
+				integer value has a value 1 for a particular fuse revision, then the closed
+				loop operation is enabled for that fuse revision. If nothing is specified
+				for a particular fuse revision, then the closed loop operation is enabled
+				for that fuse revision by default.
+- qcom,cpr-quotient-adjustment:	Array of integer tuples of target quotient adjustments to add to the fused
+				quotients of each fuse corner.  The elements in a tuple are ordered from
+				lowest voltage corner to highest voltage corner.  Each tuple must be of
+				length defined by qcom,cpr-fuse-corners.  If the qcom,cpr-fuse-version-map
+				property is specified, then qcom,cpr-quotient-adjustment must contain the
+				same number of tuples as qcom,cpr-fuse-version-map.  These tuples are then
+				mapped one-to-one in the order specified.  E.g. if the second
+				qcom,cpr-fuse-version-map tuple matches for a given device, then the quotient
+				adjustments defined in the second qcom,cpr-quotient-adjustment tuple will
+				be applied.  If the qcom,cpr-fuse-version-map property is not specified,
+				then qcom,cpr-quotient-adjustment must contain a single tuple which is then
+				applied unconditionally.  If this property is specified, then the quotient
+				adjustment values are added to the target quotient values read from fuses
+				before writing them into the CPR GCNT target control registers.
+				This property can be used to add or subtract static voltage margin from the
+				regulator managed by the CPR controller.
+- qcom,cpr-init-voltage-adjustment:  Array of integer tuples of initial voltage adjustments in microvolts to
+				add to the fused initial voltage values of each fuse corner.  The elements
+				in a tuple are ordered from lowest voltage corner to highest voltage corner.
+				Each tuple must be of the length defined by qcom,cpr-fuse-corners.  If the
+				qcom,cpr-fuse-version-map property is specified, then
+				qcom,cpr-init-voltage-adjustment must contain the same number of tuples as
+				qcom,cpr-fuse-version-map.  These tuples are then mapped one-to-one in the
+				order specified.  E.g. if the second qcom,cpr-fuse-version-map tuple matches
+				for a given device, then the initial voltage adjustments defined in the
+				second qcom,cpr-init-voltage-adjustment tuple will be applied.  If the
+				qcom,cpr-fuse-version-map property is not specified, then
+				qcom,cpr-init-voltage-adjustment must contain a single tuple which is then
+				applied unconditionally.  This property can be used to add or subtract
+				static initial voltage margin from the regulator managed by the CPR
+				controller.
+- qcom,cpr-quot-offset-adjustment:	Array of integer tuples of target quotient offset adjustments to add
+				to the fused quotient offsets of each fuse corner. The elements in a tuple
+				are ordered from lowest voltage corner to highest voltage corner. Each tuple
+				must be of length defined by qcom,cpr-fuse-corners. If the qcom,cpr-fuse-version-map
+				property is specified, then qcom,cpr-quot-offset-adjustment must contain the
+				same number of tuples as qcom,cpr-fuse-version-map.  These tuples are then
+				mapped one-to-one in the order specified.  E.g. if the second
+				qcom,cpr-fuse-version-map tuple matches for a given device, then the quotient
+				offset adjustments defined in the second qcom,cpr-quot-offset-adjustment tuple
+				will be applied. If the qcom,cpr-fuse-version-map property is not specified,
+				then qcom,cpr-quot-offset-adjustment must contain a single tuple which is then
+				applied unconditionally.  If this property is specified, then the quotient
+				offset adjustment values are added to the target quotient offset values read
+				from fuses.
+				This property can be used to add or subtract static quotient offset margin from
+				the regulator managed by the CPR controller.
+- qcom,cpr-clamp-timer-interval:	The number of 64 reference clock cycle blocks to delay for whenever
+					the clamp signal, sensor mask registers or sensor bypass registers
+					change.  The CPR controller loop is disabled during this delay.
+					Supported values are 0 to 255.  If this property is not specified,
+					then a value of 0 is assumed.  Note that if this property has a
+					value greater than 0, then software cannot accurately determine the
+					error_steps value that corresponds to a given CPR measurement
+					unless processor power collapsing is disabled.  If this property
+					has a value of 0, then the CPR controller loop is not disabled and
+					re-enabled while idle if the clamp signal changes.  Instead, it
+					will remain idle until software issues an ACK or NACK command.
+					This ensures that software can read the error_steps value which
+					resulted in the CPR up or down interrupt.  Setting this property to
+					a value greater than 0 is useful for resetting the CPR sensors of a
+					processor that uses BHS type voltage switches in order to avoid
+					anomalous CPR up interrupts when exiting from power collapse.
+- vdd-apc-optional-prim-supply:	Present: Regulator of highest priority to supply VDD APC power
+				Not Present: No such regulator.
+- vdd-apc-optional-sec-supply:	Present: Regulator of second highest priority to supply VDD APC power.
+				Not Present: No such regulator.
+- qcom,cpr-speed-bin-max-corners: Array of (N+2)-tuples in which each tuple maps a CPU speed bin and PVS version to
+				the maximum virtual voltage corner corresponding to each fuse corner.  The value N
+				corresponds to the number of fuse corners specified by qcom,cpr-fuse-corners.
+				The elements in one tuple are:
+				[0]: =>		the speed bin of the CPU. It may use the value 0xffffffff as a
+						wildcard to match any speed bin values.
+				[1]: =>		the PVS version of the CPU. It may use the value 0xffffffff as
+						a wildcard to match any PVS version values.
+				[2 - N+1]: =>	the max virtual voltage corner value corresponding to each fuse corner
+						for this speed bin, ordered from lowest voltage corner to highest
+						voltage corner.
+				No CPR target quotient scaling is applied on chips which have a speed bin + PVS version
+				pair that does not appear in one of the tuples in this property. If the property is
+				specified, then quotient scaling is enabled for the highest voltage corner. If this property is
+				not specified, then no quotient scaling can take place.
+- qcom,cpr-corner-map:		Array of elements of fuse corner value for each virtual corner.
+				The location or 1-based index of an element in the list corresponds to
+				the virtual corner value. For example, the first element in the list is the fuse corner
+				value that virtual corner 1 maps to.
+				This property is required if qcom,cpr-speed-bin-max-corners is present.
+- qcom,cpr-corner-frequency-map: Array of tuples in which a tuple describes a corner to application processor frequency
+				mapping.
+				The 2 elements in one tuple are:
+				[0]: => a virtual voltage corner.
+				[1]: => the application processor frequency in Hz corresponding to the virtual corner.
+				This property is required if qcom,cpr-speed-bin-max-corners is present.
+- qcom,pvs-version-fuse-sel:	Array of 4 elements to indicate where to read the pvs version of the processor,
+				and the fuse reading method.
+				The 4 elements with index[0..3] are:
+				[0]: => the fuse row number of the selector;
+				[1]: => LSB bit position of the bits;
+				[2]: => the number of bits;
+				[3]: => fuse reading method, 0 for direct reading or 1 for SCM reading.
+- qcom,cpr-voltage-ceiling-override: Array of (N+2)-tuples in which each tuple maps a CPU speed bin and PVS version
+				to the ceiling voltage to apply for each virtual voltage corner.  The value N
+				corresponds to the number of virtual corners as specified by the number of elements
+				in the qcom,cpr-corner-map property.
+				The elements in one tuple are:
+				[0]: =>		the speed bin of the CPU. It may use the value 0xffffffff as a
+						wildcard to match any speed bin values.
+				[1]: =>		the PVS version of the CPU. It may use the value 0xffffffff as a
+						wildcard to match any PVS version values.
+				[2 - N+1]: =>	the ceiling voltage value in microvolts corresponding to each virtual
+						corner for this speed bin, ordered from lowest voltage corner to
+						highest voltage corner.
+				No ceiling override is applied on chips which have a speed bin + PVS version
+				pair that does not appear in one of the tuples in this property.  If the property is
+				specified and the speed bin + PVS version matches, then the per-virtual-corner ceiling
+				voltages will be used in place of the per-fuse-corner ceiling voltages defined in the
+				qcom,cpr-voltage-ceiling property.  If this property is not specified, then the
+				per-fuse-corner ceiling voltages will always be used.
+- qcom,cpr-voltage-floor-override: Array of (N+2)-tuples in which each tuple maps a CPU speed bin and PVS version
+				to the floor voltage to apply for each virtual voltage corner.  The value N
+				corresponds to the number of virtual corners as specified by the number of elements
+				in the qcom,cpr-corner-map property.
+				The elements in one tuple are:
+				[0]: =>		the speed bin of the CPU. It may use the value 0xffffffff as a
+						wildcard to match any speed bin values.
+				[1]: =>		the PVS version of the CPU. It may use the value 0xffffffff as a
+						wildcard to match any PVS version values.
+				[2 - N+1]: =>	the floor voltage value in microvolts corresponding to each virtual
+						corner for this speed bin, ordered from lowest voltage corner to
+						highest voltage corner.
+				No floor override is applied on chips which have a speed bin + PVS version
+				pair that does not appear in one of the tuples in this property.  If the property is
+				specified and the speed bin + PVS version matches, then the per-virtual-corner floor
+				voltages will be used in place of the per-fuse-corner floor voltages defined in the
+				qcom,cpr-voltage-floor property.  If this property is not specified, then the
+				per-fuse-corner floor voltages will always be used.
+- qcom,cpr-floor-to-ceiling-max-range:	Array of integer tuples of floor-to-ceiling max range values in microvolts
+				to be subtracted from the ceiling voltage values of each virtual corner.
+				Supported values are those greater than or equal 0, or (-1). The value 0 for a corner
+				implies that the floor value for that corner has to equal to its ceiling value.
+				The value (-1) for a corner implies that no modification to the default floor voltage
+				is required. The elements in a tuple are ordered from lowest voltage corner to highest
+				voltage corner. Each tuple must be of the length equal to the number of virtual corners
+				as specified by the number of elements in the qcom,cpr-corner-map property. If the
+				qcom,cpr-fuse-version-map property is specified, then
+				qcom,cpr-dynamic-floor-override-adjustment must contain the same number of
+				tuples as qcom,cpr-fuse-version-map.  These tuples are then mapped one-to-one in the
+				order specified.  E.g. if the second qcom,cpr-fuse-version-map tuple matches
+				for a given device, then voltage adjustments defined in the second
+				qcom,cpr-dynamic-floor-override-adjustment tuple will be applied.  If the
+				qcom,cpr-fuse-version-map property is not specified, then
+				qcom,cpr-dynamic-floor-override-adjustment must contain a single tuple which
+				is then applied unconditionally.
+- qcom,cpr-virtual-corner-init-voltage-adjustment: Array of integer tuples of voltage adjustments in microvolts to be
+				added to the initial voltage values of each virtual corner.  The elements
+				in a tuple are ordered from lowest voltage corner to highest voltage corner.
+				Each tuple must be of the length equal to the number of virtual corners as
+				specified by the number of elements in the qcom,cpr-corner-map property. If the
+				qcom,cpr-fuse-version-map property is specified, then
+				qcom,cpr-virtual-corner-init-voltage-adjustment must contain the same number of
+				tuples as qcom,cpr-fuse-version-map.  These tuples are then mapped one-to-one in the
+				order specified.  E.g. if the second qcom,cpr-fuse-version-map tuple matches
+				for a given device, then voltage adjustments defined in the second
+				qcom,cpr-virtual-corner-init-voltage-adjustment tuple will be applied.  If the
+				qcom,cpr-fuse-version-map property is not specified, then
+				qcom,cpr-virtual-corner-init-voltage-adjustment must contain a single tuple which
+				is then applied unconditionally.
+- qcom,cpr-virtual-corner-quotient-adjustment: Array of integer tuples of quotient offsets to be added to
+				the scaled target quotient of each virtual corner. The elements
+				in a tuple are ordered from lowest voltage corner to highest voltage corner.
+				Each tuple must be of the length equal to the number of virtual corners as
+				specified by the number of elements in the qcom,cpr-corner-map property.
+				If the qcom,cpr-fuse-version-map property is specified, then
+				qcom,cpr-virtual-corner-quotient-adjustment must contain the same number of tuples as
+				qcom,cpr-fuse-version-map.  These tuples are then mapped one-to-one in the
+				order specified.  E.g. if the second qcom,cpr-fuse-version-map tuple matches
+				for a given device, then quotient adjustments defined in the second
+				qcom,cpr-virtual-corner-quotient-adjustment tuple will be applied.  If the
+				qcom,cpr-fuse-version-map property is not specified, then
+				qcom,cpr-virtual-corner-quotient-adjustment must contain a single tuple which is then
+				applied unconditionally.
+- qcom,cpr-cpus:		Array of CPU phandles which correspond to the cores that this cpr-regulator
+				device must monitor when adjusting the voltage and/or target quotient based
+				upon the number of online cores or make sure that one of them must be online
+				when performing de-aging measurements. This property must be specified in order to
+				utilize the qcom,cpr-online-cpu-virtual-corner-init-voltage-adjustment or
+				qcom,cpr-online-cpu-virtual-corner-quotient-adjustment or qcom,cpr-aging-sensor-id properties.
+- qcom,cpr-online-cpu-virtual-corner-init-voltage-adjustment:	Array of tuples where each tuple specifies
+				the voltage adjustment for each corner. These adjustments apply to the
+				initial voltage of each corner. The size of each tuple must be equal
+				to qcom,cpr-fuse-corners if consumers request fuse corners or the length of
+				qcom,cpr-corner-map if consumers request virtual corners. In each tuple, the
+				value corresponds to the voltage adjustment when running at that corner at
+				init, from lowest to highest. The tuples must be organized into 1 group if
+				qcom,cpr-fuse-version-map is not specified or the same number of groups as
+				the number of tuples in qcom,cpr-fuse-version-map. The i-th group of tuples
+				corresponds to the voltage adjustments for i-th fuse version map tuple. In
+				each group, there are 1 plus length of qcom,cpr-cpus tuples, each tuple
+				corresponds to the number of cores online, from 0 to the number of elements
+				in qcom,cpr-cpus.
+- qcom,cpr-online-cpu-init-voltage-as-ceiling:	Boolean which indicates that the ceiling voltage used for a
+				given virtual corner may be reduced to the per number of cores online,
+				per-virtual corner ceiling voltage value. This property takes precedence
+				over qcom,cpr-scaled-init-voltage-as-ceiling if both are specified.
+- qcom,cpr-online-cpu-virtual-corner-quotient-adjustment:	Array of tuples where each tuple specifies
+				the quotient adjustment for each corner. These adjustments will be applied
+				to each corner at run time. The size of each tuple must be equal to
+				qcom,cpr-fuse-corners if consumers request fuse corners or the length of
+				qcom,cpr-corner-map if consumers request virtual corners. In each tuple,
+				the value corresponds to the quotient adjustment when running at that corner,
+				from lowest to highest. The tuples must be organized into 1 group if
+				qcom,cpr-fuse-version-map is not specified or the same number of groups
+				as the number of tuples in qcom,cpr-fuse-version-map. The i-th group of
+				tuples corresponds to the quotient adjustments for i-th fuse version map
+				tuple. In each group, there are 1 plus length of qcom,cpr-cpus tuples,
+				each tuple corresponds to the number of cores online, from 0 to the
+				number of elements in qcom,cpr-cpus.
+- qcom,cpr-init-voltage-as-ceiling: Boolean which indicates that the ceiling voltage used for a given virtual
+				corner may be reduced to the per-fuse-corner initial voltage fuse value.
+- qcom,cpr-scaled-init-voltage-as-ceiling: Boolean which indicates that the ceiling voltage used for a given
+				virtual corner may be reduced to the interpolated, per-virtual-corner initial
+				voltage value.  Note that if both qcom,cpr-init-voltage-as-ceiling and
+				qcom,cpr-scaled-init-voltage-as-ceiling are specified, then
+				qcom,cpr-scaled-init-voltage-as-ceiling will take precedence since the interpolated
+				voltages are necessarily less than or equal to the fused initial voltage values.
+- qcom,cpr-voltage-scaling-factor-max: Array of values which define the maximum allowed scaling factor to apply
+				when calculating per-corner initial voltage values for each fuse corner.  The
+				array must be of length equal to the value of the qcom,cpr-fuse-corners property.
+				Each element in the array maps to the fuse corners in increasing order.
+				The elements have units of uV/MHz.  Each element corresponds to 'max_factor' in
+				the following equation:
+				init_voltage_min(f) = fuse_init_voltage(f) - (fuse_f_max - f) * max_factor
+				If this property is not specified, then the initial voltage for each virtual
+				corner will be set to the initial voltage of the associated fuse corner.
+- qcom,cpr-quot-adjust-scaling-factor-max: Array of values which define the maximum allowed scaling factor to
+				apply when calculating per-virtual-corner target quotients for each fuse
+				corner.  Two data formats are allowed for this property.  The primary one
+				requires that the array be of length equal to the value of the
+				qcom,cpr-fuse-corners property.  When using this format, each element in the
+				array maps to the fuse corners in increasing order.  The second depreciated
+				format allows for only a single element to be specified which defines the
+				maximum scaling factor for the highest fuse corner.  In this case, a value of
+				0 is assumed for the lower fuse corners.  The elements of this property have
+				units of QUOT/GHz.  Each element corresponds to 'max_factor' in the following
+				equation:
+				quot_min(f) = fuse_quot(f) - (fuse_f_max - f) * max_factor / 1000
+				where f and fuse_f_max have units of MHz.
+				This property is required if qcom,cpr-speed-bin-max-corners is present.
+- qcom,cpr-fuse-init-voltage:	Array of quadruples in which each quadruple specifies a fuse location to
+				read in order to get an initial voltage for a fuse corner. The fuse values
+				are encoded as voltage steps higher or lower than the voltages defined in
+				qcom,cpr-voltage-ceiling. Each step corresponds to the voltage defined by
+				the qcom,cpr-init-voltage-step property.
+				The 4 elements in one quadruple are:
+				[0]: => the fuse row number of the bits
+				[1]: => LSB bit position of the bits
+				[2]: => number of the bits
+				[3]: => fuse reading method, 0 for direct reading or 1 for SCM reading
+				The quadruples are ordered from the lowest voltage fuse corner to the
+				highest voltage fuse corner.
+				A given cpr-regulator device must have either qcom,cpr-fuse-init-voltage
+				specified or qcom,pvs-voltage-table (and its associated properties).
+- qcom,cpr-fuse-redun-init-voltage: Array of quadruples in which each quadruple specifies a fuse location
+				to read in order to get the redundant initial voltage for a fuse corner.
+				This property is the same as qcom,cpr-fuse-init-voltage except that it is
+				only utilized if a chip is configured to use the redundant set of fuse
+				values.  This property is required if qcom,cpr-fuse-redun-sel and
+				qcom,cpr-fuse-init-voltage are specified.
+- qcom,cpr-init-voltage-ref:	Array of reference voltages in microvolts used when decoding the initial
+				voltage fuse values.  The elements in the array are ordered from lowest
+				voltage corner to highest voltage corner.  This property must be of length
+				defined by qcom,cpr-fuse-corners.
+				This property is required if qcom,cpr-fuse-init-voltage is present.
+- qcom,cpr-init-voltage-step:	The voltage step size in microvolts of the CPR initial voltage fuses described by the
+				qcom,cpr-fuse-init-voltage property.
+				This property is required if qcom,cpr-fuse-init-voltage is present.
+- mem-acc-supply:		Regulator to vote for the memory accelerator configuration.
+				Not Present: memory accelerator configuration not supported.
+- qcom,mem-acc-corner-map:	Array of integer which defines the mapping from mem-acc corner value for each
+				virtual corner. Each element is a mem-acc state for the corresponding virtual corner.
+				The elements in the array are ordered from lowest voltage corner to highest voltage corner.
+- qcom,fuse-remap-source:	Array of quadruples in which each quadruple specifies a fuse location to
+				remap.  The 4 elements in one quadruple are:
+				[0]: => the fuse row number of the bits
+				[1]: => LSB bit position of the bits
+				[2]: => the number of bits
+				[3]: => fuse reading method, 0 for direct reading or 1 for SCM reading
+				The fuse bits for all quadruples are packed together in the order specified
+				into 64-bit virtual fuse rows beginning at the row number defined in the
+				qcom,fuse-remap-base-row property.  The remapped rows may be used by any
+				other properties.
+				Example:
+					qcom,fuse-remap-base-row = <1000>;
+					qcom,fuse-remap-source =
+							<13 57 2 0>,
+							<14 30 3 0>,
+							<20 1 7 0>,
+							<40 47 120 0>;
+
+					This results in the following bit remapping:
+
+					Row   Bits       Remap Row  Remap Bits
+					13    57..58  -->  1000      0..1
+					14    30..32  -->  1000      2..4
+					20     1..7   -->  1000      5..11
+					40    47..63  -->  1000     12..28
+					41     0..34  -->  1000     29..63
+					41    35..63  -->  1001      0..28
+					42     0..34  -->  1001     29..63
+					42    35..38  -->  1002      0..3
+
+					A tuple like this could then be used to reference some of the
+					concatenated bits from rows 13, 14, and 20:
+
+					qcom,cpr-fuse-init-voltage = <1000 0 6 0>;
+- qcom,fuse-remap-base-row:	Integer which defines the virtual row number to use as a base when remapping
+				fuse bits.  The remap base row number can be any value as long as it is
+				greater than all of the real row numbers addressed in other properties of
+				the cpr-regulator device node.  This property is required if
+				qcom,fuse-remap-source is specified.
+- qcom,cpr-quot-min-diff:	Integer which defines the minimum target-quotient difference between
+				the highest and (highest - 1) fuse corner to keep CPR enabled. If this
+				property is not specified a default value of 50 is used.
+- qcom,cpr-fuse-quot-offset:	Array of quadruples in which each quadruple specifies a fuse location to
+				read in order to get the quotient offset for a fuse corner. The fuse values
+				are encoded as the difference between quotients of that fuse corner and its
+				adjacent lower fuse corner divided by an unpacking multiplier value defined
+				under qcom,cpr-fuse-quot-offset-scale property.
+				The 4 elements in one quadruple are:
+				[0]: => the fuse row number of the bits
+				[1]: => LSB bit position of the bits
+				[2]: => number of the bits
+				[3]: => fuse reading method, 0 for direct reading or 1 for SCM reading
+				The quadruples are ordered from the lowest fuse corner to the highest
+				fuse corner.
+				Quotient offset read from the fuse locations above can be overridden with
+				the property qcom,cpr-quot-adjust-scaling-factor-max.
+- qcom,cpr-fuse-quot-offset-scale:	Array of integer values which defines the multipliers to decode the quotient offsets
+				of each fuse corner. The elements in the array are ordered from the lowest voltage fuse corner
+				to the highest voltage fuse corner. If this property is not present, then all target quotient
+				parameters are assumed to have a multiplier of 1 (i.e. no decoding needed).
+- qcom,cpr-redun-fuse-quot-offset: Array of quadruples in which each quadruple specifies a fuse location to
+				read in order to get the redundant quotient offset for a fuse corner. This
+				property is the same as qcom,cpr-fuse-quot-offset except that it is only
+				utilized if a chip is configured to use the redundant set of fuse values.
+- qcom,cpr-fuse-min-quot-diff:	Array of values which define the minimum difference allowed between the adjusted
+				quotients of the fuse corners. The length of the array should be equal to the value
+				of the qcom,cpr-fuse-corners property. Where each element in the array maps to the
+				fuse corners in increasing order.
+- qcom,cpr-min-quot-diff-adjustment:	Array of integer tuples of target quotient offsets to be added to
+				the adjusted target quotients of each fuse corner. When the quotient difference
+				between two adjacent fuse corners is insufficient, the quotient for the higher fuse corner is
+				replaced with that of the lower fuse corner plus the adjustment value.
+				The elements in a tuple are ordered from lowest voltage corner to highest voltage corner.
+				Each tuple must be of the length defined by qcom,cpr-fuse-corners.
+				If the qcom,cpr-fuse-version-map property is specified, then qcom,cpr-min-quot-diff-adjustment
+				must contain the same number of tuples as qcom,cpr-fuse-version-map.  These tuples are then mapped
+				one-to-one in the order specified.  E.g. if the second qcom,cpr-fuse-version-map tuple matches
+				for a given device, then the quotient adjustments defined in the
+				second qcom,cpr-min-quot-diff-adjustment tuple will be applied.  If the
+				qcom,cpr-fuse-version-map property is not specified, then
+				qcom,cpr-min-quot-diff-adjustment must contain a single tuple which is then
+				applied unconditionally. The qcom,cpr-min-quot-diff-adjustment property must be specified
+				if the qcom,cpr-fuse-min-quot-diff property is specified.
+- qcom,cpr-skip-voltage-change-during-suspend: Boolean property which indicates that the CPR voltage
+				should not be adjusted based upon the number of online cores while
+				entering or exiting system suspend.
+- rpm-apc-supply:		Regulator to notify RPM of the APC operating
+				corner
+- qcom,rpm-apc-corner-map:	Array of integers which define the mapping of
+				the RPM corner to the corresponding APC virtual
+				corner. This property must be defined if
+				'rpm-apc-supply' is present.
+- qcom,vsens-corner-map:	Array of integers which define the mapping of the VSENS corner to the
+				corresponding APC fuse corner. The qcom,vsens-corner-map and
+				vdd-vsense-corner-supply properties must both be specified for a given
+				cpr-regulator device or neither must be specified.
+- vdd-vsens-corner-supply:	Regulator to specify the current operating fuse corner to the Voltage Sensor.
+- vdd-vsens-voltage-supply:	Regulator to specify the corner floor/ceiling voltages to the Voltage Sensor.
+- qcom,cpr-aging-sensor-id:	Array of CPR sensor IDs to be used in the CPR de-aging algorithm. The number
+				of values should be equal to number of sensors selected for age calibration.
+				If this property is not specified, then the de-aging procedure is not enabled.
+- qcom,cpr-de-aging-allowed:	Integer values that specify whether the CPR de-aging procedure is allowed or
+				not for a particular fuse revision. If the qcom,cpr-fuse-version-map
+				property is specified, then qcom,cpr-de-aging-allowed must contain the same number
+				of elements as there are tuples in qcom,cpr-fuse-version-map. If qcom,cpr-fuse-version-map
+				is not specified, then qcom,cpr-de-aging-allowed must contain a single value that
+				is used unconditionally. An element value of 1 means that the CPR de-aging procedure
+				can be performed for parts with the corresponding fuse revision. An element value of 0
+				means that CPR de-aging cannot be performed.
+				This property is required if the qcom,cpr-aging-sensor-id property has been specified.
+- qcom,cpr-aging-ref-corner:	The vdd-apc-supply reference virtual voltage corner to be set during the CPR de-aging
+				measurements. This corner value is needed to set appropriate voltage on
+				the dependent voltage rails such as vdd-mx and mem-acc.
+				This property is required if the qcom,cpr-aging-sensor-id property has been specified.
+- qcom,cpr-aging-ref-voltage:	The vdd-apc-supply reference voltage in microvolts to be set during the
+				CPR de-aging measurements.
+				This property is required if the qcom,cpr-aging-sensor-id property has been specified.
+- qcom,cpr-max-aging-margin:	The maximum allowed aging voltage margin in microvolts. This is used to limit
+				the calculated aging voltage margin.
+				This property is required if the qcom,cpr-aging-sensor-id property has been specified.
+- qcom,cpr-non-collapsible-sensors: Array of CPR sensor IDs which are in non-collapsible domain. The sensor IDs not
+				specified in the array should be bypassed for the de-aging procedure. The number of
+				elements should be less than or equal to 32. The values of the array elements should
+				be greater than or equal to 0 and less than or equal to 31.
+				This property is required for power-domains with bypass mux present in HW.
+				This property can be required if the qcom,cpr-aging-sensor-id property has been specified.
+- qcom,cpr-aging-ro-scaling-factor:	The aging ring oscillator (RO) scaling factor with units of QUOT/V.
+				This value is used for calculating a voltage margin from RO measurements.
+				This property is required if the qcom,cpr-aging-sensor-id property has been specified.
+- qcom,cpr-ro-scaling-factor:	Array of scaling factors with units of QUOT/V for each ring oscillator ordered
+				from the lowest to the highest RO. These values are used to calculate
+				the aging voltage margin adjustment for all of the ROs. Since CPR2 supports
+				exactly 8 ROs, the array must contain 8 elements corresponding to RO0 through RO7 in order.
+				If a given RO is unused for a fuse corner, then its scaling factor may be specified as 0.
+				This property is required if the qcom,cpr-aging-sensor-id property has been specified.
+- qcom,cpr-aging-derate:	Array of scaling factors which define the amount of derating to apply to the reference
+				aging voltage margin adjustment for each of the fuse corners. Each element has units
+				of uV/mV. This property must be of length defined by qcom,cpr-fuse-corners.
+				The elements are ordered from the lowest to the highest fuse corner.
+				This property is required if the qcom,cpr-aging-sensor-id property has been specified.
+- qcom,cpr-fuse-aging-init-quot-diff:	Array of quadruples in which each quadruple specifies a fuse location to read in
+				order to get an initial quotient difference. The difference between quot min and quot max
+				is fused as the initial quotient difference.
+				The 4 elements in one quadruple are:
+				[0]: => the fuse row number of the bits
+				[1]: => LSB bit position of the bits
+				[2]: => number of the bits
+				[3]: => fuse reading method, 0 for direct reading or 1 for SCM reading
+				The number of quadruples should be equal to the number of values specified in
+				the qcom,cpr-aging-sensor-id property. This property is required if
+				the qcom,cpr-aging-sensor-id property has been specified.
+Example:
+	apc_vreg_corner: regulator@f9018000 {
+		status = "okay";
+		compatible = "qcom,cpr-regulator";
+		reg = <0xf9018000 0x1000>, <0xfc4b8000 0x1000>;
+		reg-names = "rbcpr", "efuse_addr";
+		interrupts = <0 15 0>;
+		regulator-name = "apc_corner";
+		qcom,cpr-fuse-corners = <3>;
+		regulator-min-microvolt = <1>;
+		regulator-max-microvolt = <12>;
+
+		qcom,pvs-fuse = <22 6 5 1>;
+		qcom,pvs-fuse-redun-sel = <22 24 3 2 1>;
+		qcom,pvs-fuse-redun = <22 27 5 1>;
+
+		qcom,pvs-voltage-table =
+			<1050000 1150000 1350000>,
+			<1050000 1150000 1340000>,
+			<1050000 1150000 1330000>,
+			<1050000 1150000 1320000>,
+			<1050000 1150000 1310000>,
+			<1050000 1150000 1300000>,
+			<1050000 1150000 1290000>,
+			<1050000 1150000 1280000>,
+			<1050000 1150000 1270000>,
+			<1050000 1140000 1260000>,
+			<1050000 1130000 1250000>,
+			<1050000 1120000 1240000>,
+			<1050000 1110000 1230000>,
+			<1050000 1100000 1220000>,
+			<1050000 1090000 1210000>,
+			<1050000 1080000 1200000>,
+			<1050000 1070000 1190000>,
+			<1050000 1060000 1180000>,
+			<1050000 1050000 1170000>,
+			<1050000 1050000 1160000>,
+			<1050000 1050000 1150000>,
+			<1050000 1050000 1140000>,
+			<1050000 1050000 1140000>,
+			<1050000 1050000 1140000>,
+			<1050000 1050000 1140000>,
+			<1050000 1050000 1140000>,
+			<1050000 1050000 1140000>,
+			<1050000 1050000 1140000>,
+			<1050000 1050000 1140000>,
+			<1050000 1050000 1140000>,
+			<1050000 1050000 1140000>,
+			<1050000 1050000 1140000>;
+		qcom,cpr-voltage-ceiling = <1050000 1150000 1280000>;
+		qcom,cpr-voltage-floor = <1050000 1050000 1100000>;
+		vdd-apc-supply = <&pm8226_s2>;
+		vdd-apc-optional-prim-supply = <&ncp6335d>;
+		vdd-apc-optional-sec-supply = <&fan53555>;
+		vdd-mx-supply = <&pm8226_l3_ao>;
+		qcom,vdd-mx-vmax = <1350000>;
+		qcom,vdd-mx-vmin-method = <1>;
+		qcom,vdd-apc-step-up-limit = <1>;
+		qcom,vdd-apc-step-down-limit = <1>;
+		qcom,cpr-ref-clk = <19200>;
+		qcom,cpr-timer-delay = <5000>;
+		qcom,cpr-timer-cons-up = <1>;
+		qcom,cpr-timer-cons-down = <2>;
+		qcom,cpr-irq-line = <0>;
+		qcom,cpr-step-quotient = <15>;
+		qcom,cpr-up-threshold = <1>;
+		qcom,cpr-down-threshold = <2>;
+		qcom,cpr-idle-clocks = <5>;
+		qcom,cpr-gcnt-time = <1>;
+		qcom,cpr-clamp-timer-interval = <1>;
+		qcom,cpr-apc-volt-step = <5000>;
+
+		qcom,vsens-corner-map = <1 2 2>;
+		vdd-vsens-corner-supply = <&vsens_apc0_corner>;
+		vdd-vsens-voltage-supply = <&vsens_apc0_voltage>;
+
+		rpm-apc-supply = <&rpm_apc_vreg>;
+		qcom,rpm-apc-corner-map = <4 4 5 5 7 7 7 7 7 7 7 7>;
+
+		qcom,cpr-fuse-row = <138 1>;
+		qcom,cpr-fuse-bp-cpr-disable = <36>;
+		qcom,cpr-fuse-bp-scheme = <37>;
+		qcom,cpr-fuse-target-quot = <24 12 0>;
+		qcom,cpr-fuse-target-quot-size = <12 12 12>;
+		qcom,cpr-fuse-ro-sel = <54 38 41>;
+		qcom,cpr-fuse-revision = <140 26 2 0>;
+		qcom,cpr-fuse-redun-sel = <138 57 1 1 1>;
+		qcom,cpr-fuse-redun-row = <139 1>;
+		qcom,cpr-fuse-redun-target-quot = <24 12 0>;
+		qcom,cpr-fuse-redun-ro-sel = <46 36 39>;
+		qcom,cpr-fuse-cond-min-volt-sel = <54 42 6 7 1>;
+		qcom,cpr-cond-min-voltage = <1140000>;
+		qcom,cpr-fuse-uplift-sel = <22 53 1 0 0>;
+		qcom,cpr-uplift-voltage = <50000>;
+		qcom,cpr-uplift-quotient = <0 0 120>;
+		qcom,cpr-uplift-max-volt = <1350000>;
+		qcom,cpr-uplift-speed-bin = <1>;
+		qcom,speed-bin-fuse-sel = <22 0 3 0>;
+		qcom,cpr-corner-map = <1 1 2 2 3 3 3 3 3 3 3 3>;
+		qcom,cpr-corner-frequency-map =
+				<1 300000000>,
+				<2 384000000>,
+				<3 600000000>,
+				<4 787200000>,
+				<5 998400000>,
+				<6 1094400000>,
+				<7 1190400000>,
+				<8 1305600000>,
+				<9 1344000000>,
+				<10 1401600000>,
+				<11 1497600000>,
+				<12 1593600000>;
+		qcom,pvs-version-fuse-sel = <22 4 2 0>;
+		qcom,cpr-speed-bin-max-corners =
+				<0 1 2 4 7>,
+				<1 1 2 4 12>,
+				<2 1 2 4 10>,
+				<5 1 2 4 14>;
+		qcom,cpr-fuse-target-quot-scale =
+				<0 1>,
+				<0 1>,
+				<0 1>;
+		qcom,cpr-quot-adjust-scaling-factor-max = <0 650 650>;
+		qcom,cpr-fuse-quot-offset =
+				<138 53 5 0>,
+				<138 53 5 0>,
+				<138 48 5 0>,
+				<138 58 5 0>;
+		qcom,cpr-fuse-redun-quot-offset =
+				<200 53 5 0>,
+				<200 53 5 0>,
+				<200 48 5 0>,
+				<200 58 5 0>;
+		qcom,cpr-fuse-init-voltage =
+				<27 36 6 0>,
+				<27 18 6 0>,
+				<27 0 6 0>;
+		qcom,cpr-fuse-redun-init-voltage =
+				<140 36 6 0>,
+				<140 18 6 0>,
+				<140 0 6 0>;
+		qcom,cpr-init-voltage-ref = <1050000 1150000 1280000>;
+		qcom,cpr-init-voltage-step = <10000>;
+		qcom,cpr-voltage-ceiling-override =
+				<1 1 1050000 1050000 1150000 1150000 1280000
+				     1280000 1280000 1280000 1280000 1280000
+				     1280000 1280000>;
+		qcom,cpr-voltage-floor-override =
+				<1 1 1050000 1050000 1050000 1050000 1060000
+				     1070000 1080000 1090000 1100000 1100000
+				     1100000 1100000>;
+		qcom,cpr-scaled-init-voltage-as-ceiling;
+
+		qcom,cpr-fuse-version-map =
+				<0xffffffff 0xffffffff 2 4 4 4>,
+				<0xffffffff 0xffffffff 2 6 6 6>,
+				<0xffffffff 0xffffffff 3 4 4 4>;
+		qcom,cpr-quotient-adjustment =
+				<0 0 (-210)>,
+				<0 0 (-60)>,
+				<0 0 (-94)>;
+		qcom,cpr-quot-offset-adjustment =
+				<0 0 (-5)>;
+		qcom,cpr-init-voltage-adjustment =
+				<0 0 (-100000)>,
+				<0 0 (-100000)>,
+				<0 0 (-45000)>;
+		qcom,cpr-fuse-min-quot-diff = <0 0 40>;
+		qcom,cpr-min-quot-diff-adjustment =
+					<0 0 0>,
+					<0 0 72>,
+					<0 0 104>;
+		qcom,cpr-floor-to-ceiling-max-range =
+			<(-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1)>,
+			<(-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1) (-1)>,
+			<(-1) (-1) (-1) (-1) (-1) (-1) (-1) 50000 50000 50000 50000 50000>;
+		qcom,cpr-virtual-corner-init-voltage-adjustment =
+			<0 0 0 (-10000) 0 0 0 0 0 0 0 0>,
+			<0 0 0 0 0 0 0 0 0 0 0 (-20000)>,
+			<0 0 0 0 0 0 0 0 0 0 0 (-30000)>;
+		qcom,cpr-virtual-corner-quotient-adjustment =
+			<0 0 0 100 0 0 0 0 0 0 0 0>,
+			<0 0 0 0 0 0 0 0 0 0 0 (-300)>,
+			<0 0 0 (-60) 0 0 0 0 0 0 0 0>;
+		qcom,cpr-cpus = <&CPU0 &CPU1 &CPU2 &CPU3>;
+		qcom,cpr-online-cpu-virtual-corner-init-voltage-adjustment =
+			/* 1st fuse version tuple matched */
+			<0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 0 CPUs online */
+			<0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 1 CPUs online */
+			<0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) >, /* 2 CPUs online */
+			<0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+			<0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+			/* 2nd fuse version tuple matched */
+			<0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 0 CPUs online */
+			<0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 1 CPUs online */
+			<0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) >, /* 2 CPUs online */
+			<0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+			<0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+			/* 3rd fuse version tuple matched */
+			<0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 0 CPUs online */
+			<0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 1 CPUs online */
+			<0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) >, /* 2 CPUs online */
+			<0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+			<0 0 0 0 0 0 0 0 0 0 0 0>; /* 4 CPUs online */
+		qcom,cpr-online-cpu-virtual-corner-quotient-adjustment =
+			/* 1st fuse version tuple matched */
+			<0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18)>, /* 0 CPUs online */
+			<0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18)>, /* 1 CPUs online */
+			<0 0 0 (-3) (-3) (-3) (-3) (-3) (-6) 0 (-6) (-6)>, /* 2 CPUs online */
+			<0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+			<0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+			/* 2nd fuse version tuple matched */
+			<0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18)>, /* 0 CPUs online */
+			<0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18)>, /* 1 CPUs online */
+			<0 0 0 (-3) (-3) (-3) (-3) (-3) (-6) 0 (-6) (-6)>, /* 2 CPUs online */
+			<0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+			<0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+			/* 3rd fuse version tuple matched */
+			<0 0 0 (-21) (-21) (-21) (-32) (-32) (-42) 0 (-42) (-63)>, /* 0 CPUs online */
+			<0 0 0 (-21) (-21) (-21) (-32) (-32) (-42) 0 (-42) (-63)>, /* 1 CPUs online */
+			<0 0 0 (-11) (-11) (-11) (-11) (-11) (-21) 0 (-21) (-21)>, /* 2 CPUs online */
+			<0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+			<0 0 0 0 0 0 0 0 0 0 0 0>; /* 4 CPUs online */
+		qcom,cpr-allowed =
+			<0>,
+			<1>,
+			<1>;
+
+		qcom,fuse-remap-base-row = <1000>;
+		qcom,fuse-remap-source =
+				<140 7 3 0>,
+				<138 45 5 0>;
+		qcom,cpr-fuse-quot-offset-scale = <5 5 5>;
+
+		qcom,cpr-aging-sensor-id = <17, 18>;
+		qcom,cpr-aging-ref-corner = <4>;
+		qcom,cpr-aging-ref-voltage = <1050000>;
+		qcom,cpr-max-aging-margin = <15000>;
+		qcom,cpr-de-aging-allowed =
+				<0>,
+				<0>,
+				<1>;
+		qcom,cpr-non-collapsible-sensors= <7 12 17 22>;
+		qcom,cpr-aging-ro-scaling-factor = <3500>;
+		qcom,cpr-ro-scaling-factor = <0 2500 2500 2500 0 0 0 0>;
+		qcom,cpr-aging-derate = <1000 1000 1250>;
+		qcom,cpr-fuse-aging-init-quot-diff =
+				<101 0 8 0>,
+				<101 8 8 0>;
+	};
diff --git a/bindings/regulator/mem-acc-regulator.txt b/bindings/regulator/mem-acc-regulator.txt
new file mode 100755
index 00000000..a681f485
--- /dev/null
+++ b/bindings/regulator/mem-acc-regulator.txt
@@ -0,0 +1,288 @@
+Qualcomm Technologies, Inc. Memory Accelerator
+
+Memory accelerator configures the power-mode (corner) for the
+accelerator.
+
+Required properties:
+- compatible:			Must be "qcom,mem-acc-regulator"
+- regulator-name:		A string used to describe the regulator
+- regulator-min-microvolt:	Minimum corner value as min constraint, which
+				should be 1 for SVS corner
+- regulator-max-microvolt:	Maximum corner value as max constraint, which
+				should be 4 for SUPER_TURBO or 3 for TURBO
+
+Optional properties:
+- reg:				Register addresses for acc-sel-l1, acc-sel-l2 control, acc-en,
+				MEM ACC eFuse address, acc-l1-custom , acc-l2-custom,
+				mem-acc-type1, mem-acc-type2, mem-acc-type3, mem-acc-type4,
+				mem-acc-type5 and mem-acc-type6.
+- reg-names:			Register names. Must be "acc-sel-l1",
+				"acc-sel-l2", "acc-en", "efuse_addr",
+				"acc-l1-custom", "acc-l2-custom", "mem-acc-type1",
+				"mem-acc-type2", "mem-acc-type3", "mem-acc-type4",
+				"mem-acc-type5", "mem-acc-type6".
+				A given mem-acc-regulator driver must have "acc-sel-l1" or
+				"acc-sel-l2" or "mem-acc-type*" reg-names property and
+				related register address property.
+- qcom,corner-acc-map		Array which maps the APC (application processor)
+				corner value to the accelerator corner. The number of elements
+				in this property defines the number of accelerator corners.
+				Either qcom,corner-acc-map property or qcom,cornerX-reg-config
+				properties should be specified.
+- qcom,acc-en-bit-pos		Array which specifies bit positions in the
+				'acc-en' register. Setting these bits forces the
+				the acclerator to use the corner value specified
+				in the 'acc-sel-l1' and 'acc-sel-l2' register.
+- qcom,acc-sel-l1-bit-size	Integer which specifies the number of bits in
+				the 'acc-sel-l1' register which define each L1
+				select parameter.  If this property is not
+				specified, then a default value of 2 is assumed.
+- qcom,acc-sel-l1-bit-pos	Array which specifies bit positions in the
+				'acc-sel-l1' register. Each element in this array
+				is the LSB of an N-bit value where 'N' is
+				defined by the qcom,acc-sel-l1-bit-size
+				property.  This N-bit value specifies the corner
+				value used by the accelerator for the L1 cache.
+- qcom,acc-sel-l2-bit-size	Integer which specifies the number of bits in
+				the 'acc-sel-l2' register which define each L2
+				select parameter.  If this property is not
+				specified, then a default value of 2 is assumed.
+- qcom,acc-sel-l2-bit-pos	Array which specifies bit positions in the
+				'acc-sel-l2' register. Each element in this array
+				is the LSB of an N-bit value where 'N' is
+				defined by the qcom,acc-sel-l2-bit-size
+				property.  This N-bit value specifies the corner
+				value used by the accelerator for the L2 cache.
+- qcom,l1-acc-custom-data:	Array which maps APC corner values to L1 ACC custom data values.
+				The corresponding custom data is written into the custom register
+				while switching between APC corners. The custom register address
+				is specified by "acc-11-custom" reg-property. The length of the array
+				should be equal to number of APC corners.
+- qcom,l2-acc-custom-data:	Array which maps APC corner values to L2 ACC custom data values.
+				The corresponding custom data is written into the custom register
+				while switching between APC corners. The custom register address
+				is specified by "acc-l2-custom" reg-property. The length of the array
+				should be equal to number of APC corners.
+- qcom,override-acc-fuse-sel:	Array of 4 elements which specify the way to read the override fuse.
+				The override fuse value is used by the qcom,override-fuse-version-map
+				to identify the correct set of override properties.
+				The 4 elements with index [0..4] are:
+				  [0] => the fuse row number of the selector
+				  [1] => LSB bit position of the bits
+				  [2] => number of bits
+				  [3] => fuse reading method, 0 for direct reading or 1 for SCM reading
+- qcom,override-fuse-version-map: Array of integers which each match to a override fuse value.
+				Any element in a tuple may use the value 0xffffffff as a wildcard.
+				The index of the first value (in the array) which matches the override fuse
+				is used to select the right tuples from the other override properties.
+- qcom,override-corner-acc-map:	Array of tuples which overrides the existing acc-corner map
+				(specified by qcom,corner-acc-map) with corner values selected
+				from this property. "qcom,override-corner-acc-map" must contain the
+				same number of tuples as "qcom,override-fuse-version-map". These tuples
+				are then mapped one-to-one in the order specified. If the
+				"qcom,override-fuse-version-map" property is not specified, then
+				"qcom,override-corner-acc-map" must contain a single tuple which is then
+				applied unconditionally.
+- qcom,override-l1-acc-custom-data:	Array of tuples of which overrides the existing l1-acc-custom data
+				(specified by qcom,l1-acc-custom-data), with values specified in this property.
+				The corresponding custom data is written into the custom register while
+				switching between APC corners. The custom register address is specified by
+				"acc-11-custom" reg-property. This property can only be specified if the
+				"qcom,l1-acc-custom-data" is already defined. If the
+				"qcom,override-fuse-version-map" property is specified, then
+				qcom,override-l1-acc-custom-data must contain the same number of tuples
+				as "qcom,override-fuse-version-map". These tuples are then mapped one-to-one
+				in the order specified. If the qcom,override-fuse-version-map property is
+				not specified, then "qcom,override-l1-acc-custom-data" must contain a single
+				tuple which is then applied unconditionally.
+- qcom,override-l2-acc-custom-data:	Array of tuples of which overrides the existing l1-acc-custom data
+				(specified by qcom,l2-acc-custom-data), with values specified in this property.
+				The corresponding custom data is written into the custom register while
+				switching between APC corners. The custom register address is specified by
+				"acc-12-custom" reg-property. This property can only be specified if the
+				"qcom,l2-acc-custom-data" is already defined. If the
+				"qcom,override-fuse-version-map" property is specified, then
+				"qcom,override-l2-acc-custom-data" must contain the same number of tuples
+				as "qcom,override-fuse-version-map". These tuples are then mapped one-to-one
+				in the order specified. If the qcom,override-fuse-version-map property is
+				not specified, then "qcom,override-l2-acc-custom-data" must contain a single
+				tuple which is then applied unconditionally.
+- qcom,mem-acc-type1:		Array which specifies the value to be written to the mem acc type1 register for each fuse
+				corner, from the lowest fuse corner to the highest fuse corner. The length of the array
+				must be equal to the number of APC fuse corners. This property must be present if reg names
+				specifies mem-acc-type1.
+- qcom,mem-acc-type2:		Same as qcom,mem-acc-type1 except for mem acc type2 register.
+- qcom,mem-acc-type3:		Same as qcom,mem-acc-type1 except for mem acc type3 register.
+- qcom,mem-acc-type4:		Same as qcom,mem-acc-type1 except for mem acc type4 register.
+- qcom,mem-acc-type5:		Same as qcom,mem-acc-type1 except for mem acc type5 register.
+- qcom,mem-acc-type6:		Same as qcom,mem-acc-type1 except for mem acc type6 register.
+- qcom,acc-reg-addr-list:	Array of register addresses which need to be programmed during any corner switch.
+				This property can be used when multi register configuration is needed during a corner switch.
+- qcom,acc-init-reg-config:	Array of tuples specify the multi register configuration sequence need to be programmed
+				one time during device boot.
+				The format of each tuple as below:
+					<register-address-index, value>
+				Where register-address-index is used as an index in to qcom,acc-reg-addr-list property
+				to get the required register address and the value is programmed in to the corresponding
+				mapped register address. This property is required if qcom,acc-corner-addr-val-map
+				property specified.
+- qcom,cornerX-reg-config:	Array of tuples specify the multi register configuration sequence need to be programmed
+				when switching from acc corner X to any other corner. The possible values for X are {1, N},
+				where N is the value defined in qcom,num-acc-corners.
+				The format of each tuple as below:
+					<register-address-index, value>
+				Where register-address-index is used as an index in to qcom,acc-reg-addr-list property
+				to get the required register address and the value is programmed in to the corresponding
+				mapped register address. Same index can be used multiple times when the register is
+				required to configure multiple times with different values in the sequence.
+				The number of register configuration sequences should be equal to N, where N is the
+				value specified in qcom,num-acc-corners property. Also, the number of tuples in each
+				register configuration sequence should be same and must be equal to the maximum required
+				register configurations in any sequence. The invalid register configuration can be
+				specified as <(-1) (-1)>.  This property can only be specified when qcom,acc-corner-addr-val-map
+				property already defined. Either this property or qcom,corner-acc-map should be specified.
+- qcom,num-acc-corners:		The number of acc corners supported. This property is required if qcom,cornerX-reg-config
+				property specified.
+- qcom,boot-acc-corner:		The acc corner used during device boot. This property is required if qcom,cornerX-reg-config
+				property specified.
+- qcom,override-cornerX-reg-config:	A grouping of register configuration sequence lists. Each list is same as
+				the qcom,cornerX-reg-config property. The possible values for X are {1, N} where N is
+				the value defined in qcom,num-acc-corners. This property is used to specify the different
+				register configuration sequence lists and select one list among them based on the selected
+				index in qcom,override-fuse-version-map property. The selected list overrides the existing
+				register configuration sequence list specified in "qcom,cornerX-reg-config". If the
+				"qcom,override-fuse-version-map" property is specified, then
+				"qcom,override-cornerX-reg-config" must contain the same number of register
+				configuration sequence lists as the number of tuples in "qcom,override-fuse-version-map".
+				These register configuration sequence lists are then mapped one-to-one
+				in the order specified. If the qcom,override-fuse-version-map property is
+				not specified, then "qcom,override-cornerX-reg-config" must contain a single
+				register configuration sequence list which is then applied unconditionally.
+				This property can only be specified if qcom,cornerX-reg-config property is already defined.
+- qcom,override-acc-range-fuse-list:	Array of tuples define the selection parameters used for selecting the override
+				mem-acc configuration. The fused values for these selection parameters are used by the
+				qcom,override-fuse-range-map to identify the correct set of override properties.
+				Each tuple contains 4 elements as defined below:
+				  [0] => the fuse row number of the selector
+				  [1] => LSB bit position of the bits
+				  [2] => number of bits
+				  [3] => fuse reading method, 0 for direct reading or 1 for SCM reading
+- qcom,override-fuse-range-map:	Array of tuples where each tuple specifies the allowed range for all the selection parameters
+				defined in qcom,override-acc-range-fuse-list. The fused values of these selection parameters
+				are compared against their allowed range in each tuple starting from 0th tuple and use the
+				first matched tuple index to select the right tuples from the other override properties.
+				Either qcom,override-fuse-range-map or qcom,override-fuse-version-map is used to select
+				the override configuration. The qcom,override-fuse-range-map is used if both the
+				properties are specified.
+
+mem_acc_vreg_corner: regulator@fd4aa044 {
+	compatible = "qcom,mem-acc-regulator";
+	reg = <0xfd4aa048 0x1>, <0xfd4aa044 0x1>, <0xfd4af000 0x1>,
+		<0x58000 0x1000>, <0x01942124 0x4>, <0xf900d084 1>,
+		<0xf900d088 1>, <0xf900d08c 1>, <0xf900d090 1>;
+	reg-names = "acc-en", "acc-sel-l1" , "acc-sel-l2",
+		"efuse_addr", "acc-l2-custom", "mem-acc-type1",
+		"mem-acc-type2", "mem-acc-type3", "mem-acc-type4";
+	regulator-name = "mem_acc_corner";
+	regulator-min-microvolt = <1>;
+	regulator-max-microvolt = <3>;
+
+	qcom,acc-en-bit-pos = <0>;
+	qcom,acc-sel-l1-bit-pos = <0>;
+	qcom,acc-sel-l2-bit-pos = <0>;
+	qcom,acc-sel-l1-bit-size = <2>;
+	qcom,acc-sel-l2-bit-size = <2>;
+	qcom,corner-acc-map = <0 1 3>;
+	qcom,l2-acc-custom-data = <0x0 0x3000 0x3000>;
+
+	qcom,override-acc-fuse-sel = <0 52 2 0>;
+	qcom,override-fuse-version-map = <0>,
+					 <2>,
+					 <(-1)>;
+	qcom,override-acc-range-fuse-list =
+					<37 40 3 0>,
+					<36 30 8 0>;
+	qcom,override-fuse-range-map =
+				<0 0>, <  0   0>, <49 63>,
+				<1 1>, <  0   0>, <50 63>,
+				<0 1>, < 95 255>, < 0 63>;
+	qcom,override-corner-acc-map =	<0 0 1>,
+					<0 1 2>,
+					<0 1 1>;
+	qcom,override-l2-acc-custom-data = <0x0	0x0	0x3000>,
+					  <0x0	0x3000	0x3000>,
+					  <0x0	0x0	0x0>;
+	qcom,mem-acc-type1 = <0x02 0x02 0x00>;
+	qcom,mem-acc-type2 = <0x02 0x02 0x00>;
+	qcom,mem-acc-type3 = <0x02 0x02 0x00>;
+	qcom,mem-acc-type4 = <0x02 0x02 0x00>;
+
+	qcom,acc-reg-addr-list = <0x01942130 0x01942124 0x01942120>;
+	qcom,acc-init-reg-config = <1 0x55> <2 0x02>;
+
+	qcom,num-acc-corners = <3>;
+	qcom,boot-acc-corner = <2>;
+	qcom,corner1-reg-config =
+		<(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, /* 1 -> 1 */
+		<  1 0x155>, <  2   0x0>, <  3 0x155>, /* 1 -> 2 */
+		<  1   0x0>, <  2 0x155>, <(-1) (-1)>; /* 1 -> 3 */
+
+	qcom,corner2-reg-config =
+		<  1 0x155>, <(-1) (-1)>, <(-1) (-1)>, /* 2 -> 1 */
+		<(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, /* 2 -> 2 */
+		<  1 0x155>, <  2   0x0>, <  3 0x155>; /* 2 -> 3 */
+
+	qcom,corner3-reg-config =
+		<  1   0x0>, <  2 0x155>, <(-1) (-1)>, /* 3 -> 1 */
+		<  1 0x155>, <(-1) (-1)>, <(-1) (-1)>, /* 3 -> 2 */
+		<(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>; /* 3 -> 3 */
+
+	qcom,override-corner1-reg-config =
+		/* 1st fuse version tuple matched */
+		<(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, /* 1 -> 1 */
+		<  1 0x155>, <  2   0x0>, <  3 0x155>, /* 1 -> 2 */
+		<  1   0x0>, <  2 0x155>, <(-1) (-1)>, /* 1 -> 3 */
+
+		/* 2nd fuse version tuple matched */
+		<(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, /* 1 -> 1 */
+		<  1 0x155>, <  2   0x0>, <  3 0x155>, /* 1 -> 2 */
+		<  1   0x0>, <  2 0x155>, <(-1) (-1)>, /* 1 -> 3 */
+
+		/* 3rd fuse version tuple matched */
+		<(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, /* 1 -> 1 */
+		<  1 0x155>, <  3  0x22>, <  3 0x155>, /* 1 -> 2 */
+		<  1   0x0>, <  2 0x155>, <  3 0x144>; /* 1 -> 3 */
+
+	qcom,override-corner2-reg-config =
+		/* 1st fuse version tuple matched */
+		<  1 0x144>, <  1  0x11>, <(-1) (-1)>, /* 2 -> 1 */
+		<(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, /* 2 -> 2 */
+		<  1 0x155>, <  2   0x0>, <  3 0x155>, /* 2 -> 3 */
+
+		/* 2nd fuse version tuple matched */
+		<  1 0x144>, <  2 0x133>, <(-1) (-1)>, /* 2 -> 1 */
+		<(-1) (-1)>, <  1  0x33>, <(-1) (-1)>, /* 2 -> 2 */
+		<  1 0x133>, <  2   0x0>, <  3 0x155>, /* 2 -> 3 */
+
+		/* 3rd fuse version tuple matched */
+		<  1 0x144>, <  1  0x11>, <(-1) (-1)>, /* 2 -> 1 */
+		<(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, /* 2 -> 2 */
+		<  1 0x155>, <  2  0x22>, <  3 0x155>; /* 2 -> 3 */
+
+
+	qcom,override-corner3-reg-config =
+		/* 1st fuse version tuple matched */
+		<  1   0x0>, <  2 0x155>, <(-1) (-1)>, /* 3 -> 1 */
+		<  1 0x155>, <(-1) (-1)>, <(-1) (-1)>, /* 3 -> 2 */
+		<(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, /* 3 -> 3 */
+
+		/* 2nd fuse version tuple matched */
+		<  1   0x0>, <  2 0x155>, <(-1) (-1)>, /* 3 -> 1 */
+		<  1 0x155>, <(-1) (-1)>, <(-1) (-1)>, /* 3 -> 2 */
+		<(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>, /* 3 -> 3 */
+
+		/* 3rd fuse version tuple matched */
+		<  1   0x0>, <  2 0x155>, <(-1) (-1)>, /* 3 -> 1 */
+		<  1 0x155>, <  3  0x11>, <(-1) (-1)>, /* 3 -> 2 */
+		<(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>; /* 3 -> 3 */
+};
diff --git a/bindings/regulator/spm-regulator.txt b/bindings/regulator/spm-regulator.txt
new file mode 100755
index 00000000..c3241577
--- /dev/null
+++ b/bindings/regulator/spm-regulator.txt
@@ -0,0 +1,61 @@
+Qualcomm Technologies Inc. SPM Regulators
+
+spm-regulator is a regulator device which supports PMIC processor supply
+regulators via the SPM module.
+
+Required properties:
+- compatible:      Must be "qcom,spm-regulator"
+- reg:             Specifies the SPMI address and size for this regulator device
+- regulator-name:  A string used as a descriptive name for the regulator
+
+Required structure:
+- A qcom,spm-regulator node must be a child of an SPMI node that has specified
+	the spmi-slave-container property
+
+Optional properties:
+- qcom,mode:       A string which specifies the mode to use for the regulator.
+		    Supported values are "pwm" and "auto".  PWM mode is more
+		    robust, but draws more current than auto mode.  If this
+		    property is not specified, then the regulator will remain
+		    in whatever mode hardware or bootloaders set it to.
+- qcom,cpu-num:    Specifies which CPU this regulator powers.  This property is
+		    not need when the SPM regulator is shared between all CPUs.
+- qcom,bypass-spm: Boolean flag which indicates that voltage control should not
+		    be managed by an SPM.  Instead, the voltage should be
+		    controlled via SPMI.
+- qcom,max-voltage-step:  Maximum single voltage step size in microvolts.
+- qcom,recal-mask: Bit mask of the APSS clusters to recalibrate after each
+		    voltage change.  Bit 0 corresponds to the first cluster,
+		    bit 1 corresponds to the second cluster, and so on.
+
+Optional structure:
+- A child node may be specified within a qcom,spm-regulator node which defines
+	an additional regulator which controls the AVS minimum and maximum
+	voltage limits.
+- The AVS child node must contain these properties defined in regulator.txt:
+	regulator-name, regulator-min-microvolt, regulator-max-microvolt.
+
+All properties specified within the core regulator framework can also be used.
+These bindings can be found in regulator.txt.
+
+Example:
+	qcom,spmi@fc4c0000 {
+
+		qcom,pm8226@1 {
+			spmi-slave-container;
+
+			spm-regulator@1700 {
+				compatible = "qcom,spm-regulator";
+				regulator-name = "8226_s2";
+				reg = <0x1700 0x100>;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1275000>;
+
+				avs-limit-regulator {
+					regulator-name = "8226_s2_avs_limit";
+					regulator-min-microvolt = <900000>;
+					regulator-max-microvolt = <1275000>;
+				}
+			};
+		};
+	};
diff --git a/bindings/remoteproc/qcom,adsp.txt b/bindings/remoteproc/qcom,adsp.txt
index 8d488c9c..aa535e6c 100755
--- a/bindings/remoteproc/qcom,adsp.txt
+++ b/bindings/remoteproc/qcom,adsp.txt
@@ -52,6 +52,9 @@ on the Qualcomm Technologies inc ADSP Hexagon core.
 		    "qcom,lemans-cdsp1-pas"
 		    "qcom,lemans-gpdsp0-pas"
 		    "qcom,lemans-gpdsp1-pas"
+		    "qcom,kona-adsp-pas"
+		    "qcom,kona-cdsp-pas"
+		    "qcom,kona-slpi-pas"
 
 - interrupts-extended:
 	Usage: required
@@ -166,6 +169,10 @@ on the Qualcomm Technologies inc ADSP Hexagon core.
 	Value type: <stringlist>
 	Definition: must be "stop"
 
+- legacy-wlan:
+	Usage: optional
+	Value type: <none>
+	Definition: indicates the presence of legacy WLAN
 
 = SUBNODES
 The adsp node may have an subnode named either "smd-edge" or "glink-edge" that
diff --git a/bindings/remoteproc/qcom,spss.txt b/bindings/remoteproc/qcom,spss.txt
index b9f8ef60..568feb3d 100755
--- a/bindings/remoteproc/qcom,spss.txt
+++ b/bindings/remoteproc/qcom,spss.txt
@@ -9,6 +9,7 @@ on the QTI Secure Processor.
 	Definition: must be one of:
 		    "qcom,waipio-spss-pas"
 		    "qcom,kalama-spss-pas"
+		    "qcom,kona-spss-pas"
 
 - reg:
         Usage: required
diff --git a/bindings/remoteproc/subsystem_notif_virt.txt b/bindings/remoteproc/subsystem_notif_virt.txt
new file mode 100755
index 00000000..0fd0983b
--- /dev/null
+++ b/bindings/remoteproc/subsystem_notif_virt.txt
@@ -0,0 +1,49 @@
+Subsystem Notification Virtual Driver
+
+The guest VM uses this driver to communicate
+subsystem state notifications to a backend driver
+via the virtual device's registers.
+
+[Root level node]
+Required Properties:
+-compatible : Should be "qcom,subsys-notif-virt"
+-reg : The start and size of the virtual device's
+	register set.
+-reg-names :  Should be "vdev_base" for virtual device's
+	base address.
+
+[Child nodes]
+-subsys-names : The name of the subsystem that the
+	driver is registering to notifications for.
+-offset : The offset from the virtual device's register
+	base where the subsystem state will be written.
+-type : The type of the subsystem.
+	"virtual" - When the subsystem is loaded by the host VM.
+	"native" - When the subsystem is loaded by the guest VM.
+
+Required Property for "virtual" subsystem types:
+-interrupts : Tuple defining the interrupt which the driver must
+		register for to receive subsystem state notifications
+		from the backend.
+-interrupt-names: Must be "state-irq"
+
+Example:
+
+	subsys_notif_virt: qcom,subsys_notif_virt@2D000000 {
+		compatible = "qcom,subsys-notif-virt";
+		reg = <0x2D000000 0x400>;
+		reg-names = "vdev_base";
+		adsp {
+			subsys-name = "adsp";
+			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "state-irq";
+			type = "virtual";
+			offset = <0>;
+		};
+		modem {
+			subsys-name = "modem";
+			type = "native";
+			offset = <256>;
+		};
+	};
+
diff --git a/bindings/serial/qcom,msm-geni-uart.txt b/bindings/serial/qcom,msm-geni-uart.txt
index 5975753a..0e1d3a25 100755
--- a/bindings/serial/qcom,msm-geni-uart.txt
+++ b/bindings/serial/qcom,msm-geni-uart.txt
@@ -21,6 +21,9 @@ Optional properties:
 - qcom,wakeup-byte: Byte to be injected in the tty layer during wakeup isr.
 - qcom,change-sampling-rate: This is a boolean parameter and use this to decide
   the samping rate at which sequencer engine runs.
+- qcom,compat-ioctl-support: This is a boolean parameter and use this to register
+  compat ioctl ops for ldisc tty pointer. This compat ioctl is required when we
+  have 32-bit user-space application running on 64-bit kernel.
 
 Example:
 qupv3_uart11: qcom,qup_uart@0xa88000 {
diff --git a/bindings/soc/qcom/hab.txt b/bindings/soc/qcom/hab.txt
index 32f79e7f..f91ff6f0 100755
--- a/bindings/soc/qcom/hab.txt
+++ b/bindings/soc/qcom/hab.txt
@@ -21,6 +21,8 @@ Required properties:
   - remote-vmids: When the local role is "fe", this is to tell which VM is the
     relevant BE. When it is "be", this is to tell which VMs it will support as
     BE.
+  - kernel_only: If the current mmid group can only be accessed by kernel hab
+    clients, please add this property.
 
 Example:
 	qcom,hab {
@@ -37,5 +39,6 @@ Example:
 			grp-start-id = <200>;
 			role = "fe";
 			remote-vmids = <0>;
+			kernel_only;
 		};
 	}
diff --git a/bindings/soc/qcom/qcom,aoss-qmp.txt b/bindings/soc/qcom/qcom,aoss-qmp.txt
index 7782e1c8..4f24b2eb 100755
--- a/bindings/soc/qcom/qcom,aoss-qmp.txt
+++ b/bindings/soc/qcom/qcom,aoss-qmp.txt
@@ -27,6 +27,7 @@ power-domains.
 		    "qcom,cinder-aoss-qmp"
 		    "qcom,sdxpinn-aoss-qmp"
 		    "qcom,sdxbaagha-aoss-qmp"
+		    "qcom,kona-aoss-qmp"
 
 - reg:
 	Usage: required
diff --git a/bindings/soc/qcom/qcom,power-state.txt b/bindings/soc/qcom/qcom,power-state.txt
index e0900417..2cb20e58 100755
--- a/bindings/soc/qcom/qcom,power-state.txt
+++ b/bindings/soc/qcom/qcom,power-state.txt
@@ -11,10 +11,19 @@ Required Properties:
 	Usage: required
 	Value type: <string>
 	Definition: must be "qcom,power-state"
+- subsys-name:
+	Usage: required
+	Value type: <string>
+	Description: subsystem names supported
+- rproc-handle:
+	Usage: required
+	Description: phandle to subsys defined in subsys-name.
 
 Example:
 
 	qcom,power-state {
 		compatible = "qcom,power-state";
+		qcom,subsys-name = "adsp", "modem";
+		qcom,rproc-handle = <&adsp_pas>, <&modem_pas>;
 	};
 
diff --git a/bindings/soc/qcom/qcom,slatecom_interface.txt b/bindings/soc/qcom/qcom,slatecom_interface.txt
index 2731a795..4525afb9 100755
--- a/bindings/soc/qcom/qcom,slatecom_interface.txt
+++ b/bindings/soc/qcom/qcom,slatecom_interface.txt
@@ -8,9 +8,11 @@ memory in the device.
 
 Required properties:
 - compatible:	      Must be "qcom,slate-daemon"
+- qcom,platform-reset-gpio:	This gpio state used to make boot decision for slate subsystem.
 
 Example:
 	qcom,slate-daemon {
 		compatible = "qcom,slate-daemon";
+		qcom,platform-reset-gpio = <&pm5100_gpios 15 0>;
 		};
 
diff --git a/bindings/soc/qcom/qti-pmic-lpm.yaml b/bindings/soc/qcom/qti-pmic-lpm.yaml
new file mode 100755
index 00000000..c60aa714
--- /dev/null
+++ b/bindings/soc/qcom/qti-pmic-lpm.yaml
@@ -0,0 +1,45 @@
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/soc/qcom/qti-pmic-lpm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. PMIC low power mode (PMIC LPM) binding
+
+description: |
+  Qualcomm Technologies, Inc. PMIC low power mode (PMIC LPM) reports entry and
+  exit of PMIC's low power modes DeepSleep/Hibernate/TWM to a companion chip
+  through the SDAM interface.
+
+properties:
+  compatible:
+    const: qti,pmic-lpm
+
+  reg:
+    description: Base address of the SDAM peripheral.
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+examples:
+  - |
+    spmi_bus {
+      #address-cells = <2>;
+      #size-cells = <0>;
+      interrupt-controller;
+      #interrupt-cells = <4>;
+
+      qcom,pm5100@0 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        pmic-lpm@7200 {
+          compatible = "qti,pmic-lpm";
+          reg = <0x7200>;
+          #address-cells = <1>;
+          #size-cells = <1>;
+        };
+      };
+    };
+...
diff --git a/bindings/sound/ti,tas5805m.txt b/bindings/sound/ti,tas5805m.txt
new file mode 100755
index 00000000..782aec44
--- /dev/null
+++ b/bindings/sound/ti,tas5805m.txt
@@ -0,0 +1,34 @@
+Texas Instruments TAS5805M audio amplifier
+
+The TAS5805M serial control bus communicates through I2C protocols.
+
+Required properties:
+	- compatible: "ti,tas5805m".
+	- reg: 7-bit I2C address.
+	- gpio,pdn: A GPIO spec to define which pin is connected to the
+			chip's active-low power down pin.
+
+Optional properties:
+	- gpio,hpd: GPIO used to detect external interrupt event. If specified,
+			the driver will mute tas5805m if this GPIO is high.
+			Unmute if this GPIO is low.
+
+
+Example:
+
+tas5805m@2d {
+	compatible = "ti,tas5805m";
+	reg = <0x2d>;
+	gpio,pdn = <&tlmm 127 0>;
+
+	interrupt-parent = <&tlmm>;
+	interrupts = <32 0>;
+	gpio,hpd = <&tlmm 32 0>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&spkr_2_sd_n_sleep &line_out_hpd_default>;
+};
+
+
+For more product information please see the link below:
+https://www.ti.com/product/TAS5805M
diff --git a/bindings/spmi/qcom,spmi-pmic-arb.txt b/bindings/spmi/qcom,spmi-pmic-arb.txt
index 17272330..8b9b40ab 100755
--- a/bindings/spmi/qcom,spmi-pmic-arb.txt
+++ b/bindings/spmi/qcom,spmi-pmic-arb.txt
@@ -47,6 +47,8 @@ Optional properties:
 		applicable to PMIC arbiter version 7 and beyond.
 		Support values: 0 = primary bus, 1 = secondary bus
 		Assumed to be 0 if unspecified.
+- qcom,mid : SPMI master ID of this controller. Supported values
+	     are 0, 1, 2 and 3.
 
 Consumer node optional properties:
 - qcom,pmic-arb : phandle for an spmi-pmic-arb device.  This can be used by
@@ -67,6 +69,7 @@ Example:
 
 		qcom,ee = <0>;
 		qcom,channel = <0>;
+		qcom,mid = <0>;
 
 		#address-cells = <2>;
 		#size-cells = <0>;
diff --git a/bindings/thermal/qti-virtual-sensor.txt b/bindings/thermal/qti-virtual-sensor.txt
index 57b4803a..29e083de 100755
--- a/bindings/thermal/qti-virtual-sensor.txt
+++ b/bindings/thermal/qti-virtual-sensor.txt
@@ -12,7 +12,7 @@ Properties:
 	Definition: must be "qcom,vs-sensor"
 
 	Virtual sensor driver properties:
-- qcom,sensors:
+- sensor-names:
 	Usage: required
 	Value type: <List of Thermal Zones>
 	Definition: List of thermal zones whom maximum or minimum temperature need to find out.
@@ -23,25 +23,25 @@ Properties:
 	Definition: It can be 1 or 0. 1 is identifier for maximum temperature and 0 is identifier
 			for minimum temperature.
 
-- qcom,sensor_id:
-	Usage: optional
-	value type: <integer>
-	Definition: It will be 0,1,2.. depending upon how many thermal sensors are present in the target.
-
 Example:
 	virtual_sensor: virtual-sensor {
 		compatible = "qcom,vs-sensor";
 		#thermal-sensor-cells = <1>;
 
 		cpu_max: cpu-max{
-			qcom,sensors = <&cpuss_0 &cpuss_1 &cpuss_2 &cpuss_3>;
+			sensor-names = "cpuss-0",
+				"cpuss-1",
+				"cpuss-2",
+				"cpuss-3";
 			qcom,logic = <1>;
-			qcom,sensor_id = <0>;
 		};
 
 		modem_max: modem-max{
-			qcom,sensors = <&modem_offline &modem_q6 & modem_offline_fec &modem_offline_phy_0 &modem_offline_phy_1>;
+			sensor-names = "modem_offline",
+				"modem_q6",
+				"modem_offline_fec",
+				"modem_offline_phy-0",
+				"modem_offline_phy-1";
 			qcom,logic = <1>;
-			qcom,sensor_id = <1>;
 		};
 	};
diff --git a/bindings/ufs/ufs-qcom.txt b/bindings/ufs/ufs-qcom.txt
index f186a428..c546aaea 100755
--- a/bindings/ufs/ufs-qcom.txt
+++ b/bindings/ufs/ufs-qcom.txt
@@ -14,6 +14,8 @@ Required properties:
 			 present on MSM8996 chipset.
 			"qcom,ufs-phy-qmp-v4-lahaina" for ufs phy
 			 present on SM8350 chipset.
+			"qcom,ufs-phy-qmp-v4-direwolf" for ufs phy
+			 present on SA8295 Makena chipset.
 			"qcom,ufs-phy-qrbtc-sdm845" for phy support
 			 for sdm845 emulation.
 			"qcom,ufs-phy-qmp-v3" for V3 ufs phy
@@ -24,6 +26,8 @@ Required properties:
 			 present on Kalama chipsets.
 			"qcom,ufs-phy-qmp-v4-khaje" for ufs phy
 			 present on khaje chipsets.
+			"qcom,ufs-phy-qmp-v4-kona" for ufs phy
+			 present on kona chipsets.
 - reg               : should contain PHY register address space (mandatory),
 - reg-names         : indicates various resources passed to driver (via reg proptery) by name.
                       Required "reg-names" is "phy_mem".
diff --git a/bindings/usb/msm-ssusb.txt b/bindings/usb/msm-ssusb.txt
index 9c7b9366..6e13eb32 100755
--- a/bindings/usb/msm-ssusb.txt
+++ b/bindings/usb/msm-ssusb.txt
@@ -101,6 +101,9 @@ Optional properties :
 	speed using "maximum-speed=super-speed" works only for device mode because we set speed to
 	DWC3_DCFG_SUPERSPEED in DCFG register. It does not change anything for host mode and
 	connected peripherals might still get enumerated in SSP.
+- qcom,msm-probe-core-init: If present, call dwc3_ext_event_notify() at the end of dwc3_msm_probe,
+	which will populate the dwc3 child node and initialize the dwc3 controller during bootup.
+	Otherwise core_init will be done after getting USB role from ADSP.
 
 Sub nodes:
 - Sub node for "DWC3- USB3 controller".
diff --git a/qcom/Makefile b/qcom/Makefile
index 2568dc72..384bba0c 100755
--- a/qcom/Makefile
+++ b/qcom/Makefile
@@ -74,6 +74,16 @@ kalama-overlays-dtb-$(CONFIG_ARCH_KALAMA) += $(KALAMA_BOARDS) $(NOAPQ_KALAMA_BOA
 kalama_le-overlays-dtb-$(CONFIG_ARCH_KALAMA) += $(KALAMA_BOARDS) $(NOAPQ_KALAMA_BOARDS) $(KALAMA_BASE_DTB) $(KALAMA_APQ_BASE_DTB)
 dtb-y += $(kalama-dtb-y)
 
+CROW_BASE_DTB += crow.dtb
+
+CROW_BOARDS += \
+		crow-rumi-overlay.dtbo
+
+kalama-dtb-$(CONFIG_ARCH_CROW) += \
+	$(call add-overlays, $(CROW_BOARDS) ,$(CROW_BASE_DTB))
+kalama-overlays-dtb-$(CONFIG_ARCH_CROW) += $(CROW_BOARDS) $(CROW_BASE_DTB)
+dtb-y += $(kalama-dtb-y)
+
 KHAJE_BASE_DTB += khaje.dtb khajep.dtb khajeq.dtb khajeg.dtb
 
 KHAJE_BOARDS += \
@@ -123,15 +133,20 @@ bengal-dtb-$(CONFIG_ARCH_KHAJE) += \
 bengal-overlays-dtb-$(CONFIG_ARCH_KHAJE) += $(KHAJE_BOARDS) $(KHAJE_BASE_DTB)
 dtb-y += $(bengal-dtb-y)
 
-KONA_BASE_DTB += kona-iot.dtb kona-iot-v2.dtb kona-iot-v2.1.dtb kona-7230-iot-v2.1.dtb qrb5165-iot.dtb qrb5165n-iot.dtb
+KONA_BASE_DTB += kona-iot.dtb kona-iot-v2.dtb kona-iot-v2.1.dtb kona-7230-iot-v2.1.dtb qrb5165-iot.dtb qrb5165n-iot.dtb qrb3165-iot.dtb qrb3165n-iot.dtb
 
 KONA_BOARDS += \
                  kona-iot-v2.1-rb5-overlay.dtbo \
-                 kona-iot-v2.1-vc-overlay.dtbo
+                 kona-iot-v2-rb5-overlay.dtbo \
+                 kona-hdk-overlay.dtbo \
+                 kona-rb5-HDMI-overlay.dtbo \
+                 kona-iot-v2.1-vc-overlay.dtbo \
+		 kona-rb5-overlay.dtbo
 
 kona-dtb-$(CONFIG_ARCH_KONA) += \
         $(call add-overlays, $(KONA_BOARDS) ,$(KONA_BASE_DTB))
 kona-overlays-dtb-$(CONFIG_ARCH_KONA) += $(KONA_BOARDS) $(KONA_BASE_DTB)
+kona_le-overlays-dtb-$(CONFIG_ARCH_KONA) += $(KONA_BOARDS) $(KONA_BASE_DTB)
 dtb-y += $(kona-dtb-y)
 
 MONACO_BASE_DTB += monaco.dtb monacop.dtb
@@ -162,9 +177,34 @@ cinder-dtb-$(CONFIG_ARCH_CINDER) += cinder-ru-rumi.dtb \
 	cinder-v2-ru-idp.dtb \
 	cinder-v2-ru-idp-2gb.dtb \
 	cinder-v2-du-idp.dtb \
-	cinder-v2-du-x100.dtb
+	cinder-v2-du-x100.dtb \
+	cinder-v2-ru-rumi.dtb \
+	cinder-v2-du-rumi.dtb
 dtb-y += $(cinder-dtb-y)
 
+QCS405_BASE_DTB += qcs405.dtb
+
+QCS405_BOARDS += qcs405-iot-sku1-overlay.dtbo \
+	qcs405-iot-sku2-overlay.dtbo \
+	qcs405-iot-sku3-overlay.dtbo \
+	qcs405-iot-sku4-overlay.dtbo \
+	qcs405-iot-sku5-overlay.dtbo \
+	qcs405-iot-sku6-overlay.dtbo \
+	qcs405-iot-sku7-overlay.dtbo \
+	qcs405-iot-sku8-overlay.dtbo \
+	qcs405-iot-sku9-overlay.dtbo \
+	qcs405-iot-sku10-overlay.dtbo \
+	qcs407-iot-sku12-overlay.dtbo \
+	qcs407-iot-sku13-overlay.dtbo \
+	qcs407-iot-sku4-overlay.dtbo   \
+	qcs407-iot-sku6-overlay.dtbo   \
+	qcs407-iot-sku9-overlay.dtbo
+
+qcs405-dtb-$(CONFIG_ARCH_QCS405) += \
+        $(call add-overlays, $(QCS405_BOARDS) ,$(QCS405_BASE_DTB))
+
+qcs405-overlays-dtb-$(CONFIG_ARCH_QCS405) += $(QCS405_BOARDS) $(QCS405_BASE_DTB)
+dtb-y += $(qcs405-dtb-y)
 
 kaka-dtb-$(CONFIG_ARCH_KAKA) += kaka-rumi.dtb
 dtb-y += $(kaka-dtb-y)
@@ -236,6 +276,15 @@ gen4auto-overlays-dtb-$(CONFIG_ARCH_LEMANS) +=  \
 	$(LEMANS_IVI_BOARDS) $(LEMANS_ADAS_HIGH_BOARDS) $(LEMANS_IVI_BASE_DTB) $(LEMANS_ADAS_HIGH_BASE_DTB) \
 	$(LEMANS_IVI_ADAS_BOARDS) $(LEMANS_IVI_ADAS_BASE_DTB)
 
+MONACO_AUTO_BASE_DTB	+= monaco_auto-rumi.dtb
+MONACO_AUTO_BOARDS	+= monaco_auto-rumi-overlay.dtbo
+
+gen4auto-dtb-$(CONFIG_ARCH_MONACO_AUTO) += \
+	$(call add-overlays, $(MONACO_AUTO_BOARDS),$(MONACO_AUTO_BASE_DTB))
+
+gen4auto-overlays-dtb-$(CONFIG_ARCH_MONACO_AUTO) +=  \
+	$(MONACO_AUTO_BOARDS) $(MONACO_AUTO_BASE_DTB)
+
 dtb-y += $(gen4auto-dtb-y)
 
 sdxpinn-dtb-$(CONFIG_ARCH_SDXPINN) += sdxpinn-rumi.dtb sa525m-rumi.dtb \
@@ -280,23 +329,39 @@ DIREWOLF_LA_GVM_BASE_DTB += direwolf-vm-la.dtb
 DIREWOLF_LA_GVM_BOARDS += \
                    direwolf-vm-la-overlay.dtbo
 
+DIREWOLF_MULTI_GVM_BASE_DTB += \
+		direwolf-vm-la-mt.dtb \
+		direwolf-vm-lv-mt.dtb
+
+DIREWOLF_MULTI_GVM_BOARDS += \
+		direwolf-vm-la-mt-overlay.dtbo \
+		direwolf-vm-lv-mt-overlay.dtbo
+
 SA8195_LA_GVM_BASE_DTB += sa8195-vm-la.dtb
 
 SA8195_LA_GVM_BOARDS += \
                    sa8195-vm-la-overlay.dtbo
 
+DIREWOLF_LV_GVM_HEADLESS_BASE_DTB += direwolf-vm-lv-headless-mt.dtb
+
+DIREWOLF_LV_GVM_HEADLESS_BOARDS += \
+                   direwolf-vm-lv-headless-mt-overlay.dtbo
+
 autogvm-dtb-$(CONFIG_QTI_QUIN_GVM) += \
 	$(call add-overlays, $(SA8155_LA_GVM_BOARDS),$(SA8155_LA_GVM_BASE_DTB)) \
 	$(call add-overlays, $(DIREWOLF_LV_GVM_BOARDS),$(DIREWOLF_LV_GVM_BASE_DTB)) \
 	$(call add-overlays, $(SA8195_LA_GVM_BOARDS),$(SA8195_LA_GVM_BASE_DTB)) \
 	$(call add-overlays, $(DIREWOLF_LA_GVM_BOARDS),$(DIREWOLF_LA_GVM_BASE_DTB)) \
 	$(call add-overlays, $(LEMANS_LV_GVM_BOARDS),$(LEMANS_LV_GVM_BASE_DTB)) \
-	$(call add-overlays, $(LEMANS_LA_GVM_BOARDS),$(LEMANS_LA_GVM_BASE_DTB))
+	$(call add-overlays, $(LEMANS_LA_GVM_BOARDS),$(LEMANS_LA_GVM_BASE_DTB)) \
+	$(call add-overlays, $(DIREWOLF_LV_GVM_HEADLESS_BOARDS),$(DIREWOLF_LV_GVM_HEADLESS_BASE_DTB)) \
+	$(call add-overlays, $(DIREWOLF_MULTI_GVM_BOARDS),$(DIREWOLF_MULTI_GVM_BASE_DTB))
 
 autogvm-overlays-dtb-$(CONFIG_QTI_QUIN_GVM) += \
 	$(SA8155_LA_GVM_BOARDS) $(DIREWOLF_LV_GVM_BOARDS) $(SA8155_LA_GVM_BASE_DTB) $(DIREWOLF_LV_GVM_BASE_DTB) \
 	$(SA8195_LA_GVM_BOARDS) $(SA8195_LA_GVM_BASE_DTB) $(DIREWOLF_LA_GVM_BOARDS) $(DIREWOLF_LA_GVM_BASE_DTB) \
-	$(LEMANS_LA_GVM_BOARDS) $(LEMANS_LA_GVM_BASE_DTB) $(LEMANS_LV_GVM_BOARDS) $(LEMANS_LV_GVM_BASE_DTB)
+	$(LEMANS_LA_GVM_BOARDS) $(LEMANS_LA_GVM_BASE_DTB) $(LEMANS_LV_GVM_BOARDS) $(LEMANS_LV_GVM_BASE_DTB) \
+	$(DIREWOLF_LV_GVM_HEADLESS_BOARDS) $(DIREWOLF_LV_GVM_HEADLESS_BASE_DTB) $(DIREWOLF_MULTI_GVM_BOARDS) $(DIREWOLF_MULTI_GVM_BASE_DTB)
 
 dtb-y += $(autogvm-dtb-y)
 
diff --git a/qcom/cinder-ru.dtsi b/qcom/cinder-ru.dtsi
index 7d1f2607..94eb3387 100755
--- a/qcom/cinder-ru.dtsi
+++ b/qcom/cinder-ru.dtsi
@@ -16,7 +16,7 @@
 		reg = <0x0 0x80000000 0x0 0x600000>;
 	};
 
-	xbl_dt_log_mem: xbl_dt_log@80600000 {
+	xbl_dtlog_mem: xbl_dtlog_region@80600000 {
 		no-map;
 		reg = <0x0 0x80600000 0x0 0x40000>;
 	};
@@ -57,7 +57,10 @@
 		reg = <0x0 0x808e4000 0x0 0x10000>;
 	};
 
-	/* secdata region can be reused by apps */
+	secdata_apss_mem: secdata_apss_region@808ff000 {
+		no-map;
+		reg = <0x0 0x808ff000 0x0 0x1000>;
+	};
 
 	smem_mem: smem_region@80900000 {
 		no-map;
@@ -91,7 +94,7 @@
 		reg = <0x0 0x82300000 0x0 0x500000>;
 	};
 
-	ta_mem: ta_region@82800000 {
+	trusted_apps_mem: trusted_apps_region@82800000 {
 		no-map;
 		reg = <0x0 0x82800000 0x0 0xa00000>;
 	};
@@ -133,19 +136,19 @@
 		reg = <0x0 0x9ec00000 0x0 0x80000>;
 	};
 
-	oem_tenx_mem: oem_tenx_region@a0000000 {
+	abl_mem: abl_region@9fa00000 {
 		no-map;
-		reg = <0x0 0xa0000000 0x0 0x6400000>;
+		reg = <0x0 0x9fa00000 0x0 0x100000>;
 	};
 
-	mpss_diag_buffer_mem: tenx_sp_region@aea00000 {
+	modem_sample_capture_buffer_mem: modem_sample_capture_buffer_region@a0000000 {
 		no-map;
-		reg = <0x0 0xaea00000 0x0 0x6400000>;
+		reg = <0x0 0xa0000000 0x0 0x6400000>;
 	};
 
-	tenx_q6_buffer_mem: tenx_q6_buffer_region@b4e00000 {
+	oem_tenx_mem: oem_tenx_region@aea00000 {
 		no-map;
-		reg = <0x0 0xb4e00000 0x0 0x3200000>;
+		reg = <0x0 0xaea00000 0x0 0x9600000>;
 	};
 };
 
diff --git a/qcom/cinder-thermal.dtsi b/qcom/cinder-thermal.dtsi
index 8ea903ac..b95a2b3e 100755
--- a/qcom/cinder-thermal.dtsi
+++ b/qcom/cinder-thermal.dtsi
@@ -17,12 +17,19 @@
 		#thermal-sensor-cells = <1>;
 
 		cpu_max: cpu-max {
-			qcom,sensors = <&cpuss_0 &cpuss_1 &cpuss_2 &cpuss_3>;
+			sensor-names = "cpuss-0",
+					"cpuss-1",
+					"cpuss-2",
+					"cpuss-3";
 			qcom,logic = <1>;
 		};
 
 		modem_max: modem-max {
-			qcom,sensors = <&modem_q6 &modem_offline_fec &modem_offline_phy_0 &modem_offline_phy_1 &modem_offline>;
+			sensor-names = "modem_q6",
+					"modem_offline_fec",
+					"modem_offline_phy-0",
+					"modem_offline_phy-1",
+					"modem_offline";
 			qcom,logic = <1>;
 		};
 	};
@@ -87,7 +94,7 @@
 		};
 	};
 
-	cpuss_0: cpuss-0 {
+	cpuss-0 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
 		thermal-sensors = <&tsens0 1>;
@@ -112,7 +119,7 @@
 		};
 	};
 
-	cpuss_1: cpuss-1 {
+	cpuss-1 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
 		thermal-sensors = <&tsens0 2>;
@@ -137,7 +144,7 @@
 		};
 	};
 
-	cpuss_2: cpuss-2 {
+	cpuss-2 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
 		thermal-sensors = <&tsens0 3>;
@@ -162,7 +169,7 @@
 		};
 	};
 
-	cpuss_3: cpuss-3 {
+	cpuss-3 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
 		thermal-sensors = <&tsens0 4>;
@@ -187,7 +194,7 @@
 		};
 	};
 
-	modem_q6: modem_q6 {
+	modem_q6 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
 		thermal-sensors = <&tsens0 5>;
@@ -206,7 +213,7 @@
 		};
 	};
 
-	modem_offline_fec: modem_offline_fec {
+	modem_offline_fec {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
 		thermal-sensors = <&tsens0 6>;
@@ -225,7 +232,7 @@
 		};
 	};
 
-	modem_offline_phy_0: modem_offline_phy-0 {
+	modem_offline_phy-0 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
 		thermal-sensors = <&tsens0 7>;
@@ -244,7 +251,7 @@
 		};
 	};
 
-	modem_offline_phy_1: modem_offline_phy-1 {
+	modem_offline_phy-1 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
 		thermal-sensors = <&tsens0 8>;
@@ -339,7 +346,7 @@
 		};
 	};
 
-	modem_offline: modem_offline {
+	modem_offline {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
 		thermal-sensors = <&tsens0 13>;
diff --git a/qcom/cinder-usb.dtsi b/qcom/cinder-usb.dtsi
index 6a05c105..78dceed2 100755
--- a/qcom/cinder-usb.dtsi
+++ b/qcom/cinder-usb.dtsi
@@ -41,6 +41,7 @@
 				<&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_USB3_0>;
 
 		extcon = <&eud>;
+		qcom,msm-probe-core-init;
 
 		dwc3@a600000 {
 			compatible = "snps,dwc3";
diff --git a/qcom/cinder-v2-du-idp.dts b/qcom/cinder-v2-du-idp.dts
index 386a812f..cab7a40d 100755
--- a/qcom/cinder-v2-du-idp.dts
+++ b/qcom/cinder-v2-du-idp.dts
@@ -6,5 +6,5 @@
 / {
 	model = "Qualcomm Technologies, Inc. Cinder V2 DU IDP";
 	compatible = "qcom,cinder-idp", "qcom,cinder", "qcom,idp";
-	qcom,board-id = <0x20022 0x0>;
+	qcom,board-id = <0x22 0x0>;
 };
diff --git a/qcom/cinder-v2-du-rumi.dts b/qcom/cinder-v2-du-rumi.dts
new file mode 100755
index 00000000..243ab459
--- /dev/null
+++ b/qcom/cinder-v2-du-rumi.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+/memreserve/ 0x80C40000 0x00020000;
+
+#include "cinder-v2-du.dtsi"
+#include "cinder-rumi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Cinder V2 DU RUMI";
+	compatible = "qcom,cinder-rumi", "qcom,cinder", "qcom,rumi";
+	qcom,board-id = <0xF 0x0>;
+};
diff --git a/qcom/cinder-v2-du-x100.dts b/qcom/cinder-v2-du-x100.dts
index ee37c4d6..1ac252a0 100755
--- a/qcom/cinder-v2-du-x100.dts
+++ b/qcom/cinder-v2-du-x100.dts
@@ -6,5 +6,5 @@
 / {
 	model = "Qualcomm Technologies, Inc. Cinder V2 DU X100";
 	compatible = "qcom,cinder-x100", "qcom,cinder", "qcom,x100";
-	qcom,board-id = <0x20027 0x0>;
+	qcom,board-id = <0x27 0x0>;
 };
diff --git a/qcom/cinder-v2-ru-idp-2gb.dts b/qcom/cinder-v2-ru-idp-2gb.dts
index 2daf9148..7eadd142 100755
--- a/qcom/cinder-v2-ru-idp-2gb.dts
+++ b/qcom/cinder-v2-ru-idp-2gb.dts
@@ -6,5 +6,5 @@
 / {
 	model = "Qualcomm Technologies, Inc. Cinder V2 RU IDP";
 	compatible = "qcom,cinder-idp", "qcom,cinder", "qcom,idp";
-	qcom,board-id = <0x20022 0x400>;
+	qcom,board-id = <0x22 0x400>;
 };
diff --git a/qcom/cinder-v2-ru-idp.dts b/qcom/cinder-v2-ru-idp.dts
index 6f966c09..f74fb440 100755
--- a/qcom/cinder-v2-ru-idp.dts
+++ b/qcom/cinder-v2-ru-idp.dts
@@ -6,5 +6,5 @@
 / {
 	model = "Qualcomm Technologies, Inc. Cinder V2 RU IDP";
 	compatible = "qcom,cinder-idp", "qcom,cinder", "qcom,idp";
-	qcom,board-id = <0x20022 0x0>;
+	qcom,board-id = <0x22 0x600>;
 };
diff --git a/qcom/cinder-v2-ru-rumi.dts b/qcom/cinder-v2-ru-rumi.dts
new file mode 100755
index 00000000..873d7e4f
--- /dev/null
+++ b/qcom/cinder-v2-ru-rumi.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+/memreserve/ 0x80C40000 0x00020000;
+
+#include "cinder-v2-ru.dtsi"
+#include "cinder-rumi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Cinder V2 RU RUMI";
+	compatible = "qcom,cinder-rumi", "qcom,cinder", "qcom,rumi";
+	qcom,board-id = <0xF 0x600>;
+};
diff --git a/qcom/cinder-v2.dtsi b/qcom/cinder-v2.dtsi
index b06264c7..dac2d670 100755
--- a/qcom/cinder-v2.dtsi
+++ b/qcom/cinder-v2.dtsi
@@ -27,3 +27,15 @@
 			"mhi-virt-device-int-13", "mhi-virt-device-int-14",
 			"mhi-virt-device-int-15";
 };
+
+&gcc {
+	compatible = "qcom,cinder-gcc-v2", "syscon";
+};
+
+&debugcc {
+	compatible = "qcom,cinder-debugcc-v2", "syscon";
+};
+
+&ecpricc {
+	compatible = "qcom,cinder-ecpricc-v2", "syscon";
+};
diff --git a/qcom/cinder.dtsi b/qcom/cinder.dtsi
index 11247a10..cb8ab10e 100755
--- a/qcom/cinder.dtsi
+++ b/qcom/cinder.dtsi
@@ -19,7 +19,7 @@
 
 
 	chosen: chosen {
-			bootargs = "cpufreq.default_governor=performance msm_rtb.filter=0x237 ftrace_dump_on_oops";
+			bootargs = "cpufreq.default_governor=performance msm_rtb.filter=0x237 ftrace_dump_on_oops lpm_levels.sleep_disabled=1";
 	};
 
 	aliases {
@@ -509,6 +509,7 @@
 		#gpio-cells = <2>;
 		interrupt-controller;
 		#interrupt-cells = <2>;
+		qcom,gpios-reserved = <28 29>;
 	};
 
 	eud: qcom,msm-eud@88e0000 {
@@ -1193,8 +1194,12 @@
 		qcom,ecpricc = <&ecpricc>;
 		qcom,apsscc = <&apsscc>;
 		qcom,mccc = <&mccc>;
-		clock-names = "xo_clk_src";
-		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clocks = <&rpmhcc RPMH_CXO_CLK>,
+			 <&ecpricc 0>,
+			 <&gcc 0>;
+		clock-names = "xo_clk_src",
+			      "ecpricc",
+			      "gcc";
 		#clock-cells = <1>;
 	};
 
@@ -1476,10 +1481,6 @@
 			status = "disabled";
 	};
 
-	ecpri_iommu_group: ecpri_common_iommu_group {
-		qcom,iommu-dma = "default";
-	};
-
 	mhi_device: mhi_dev@1c04000 {
 		compatible = "qcom,msm-mhi-dev";
 		reg = <0x1c04000 0x1000>;
@@ -1509,11 +1510,9 @@
 			 <&apps_smmu 0x0410 0x0>,
 			 <&apps_smmu 0x0414 0x0>,
 			 <&apps_smmu 0x0418 0x0>,
-			 <&apps_smmu 0x041C 0x0>,
-			 <&apps_smmu 0x0802 0x0>,
-			 <&apps_smmu 0x0C02 0x0>;
-		qcom,iommu-group = <&ecpri_iommu_group>;
+			 <&apps_smmu 0x041C 0x0>;
 		dma-coherent;
+		qcom,iommu-dma = "default";
 
 		status = "ok";
 	};
diff --git a/qcom/crow-dma-heaps.dtsi b/qcom/crow-dma-heaps.dtsi
new file mode 100755
index 00000000..7d55c87a
--- /dev/null
+++ b/qcom/crow-dma-heaps.dtsi
@@ -0,0 +1,26 @@
+#include <dt-bindings/arm/msm/qcom_dma_heap_dt_constants.h>
+
+&soc {
+	qcom,dma-heaps {
+		compatible = "qcom,dma-heaps";
+
+		qcom,qseecom {
+			qcom,dma-heap-name = "qcom,qseecom";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&qseecom_mem>;
+		};
+
+		qcom,qseecom_ta {
+			qcom,dma-heap-name = "qcom,qseecom-ta";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&qseecom_ta_mem>;
+		};
+
+		qcom,user_contig {
+			qcom,dma-heap-name = "qcom,user-contig";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&user_contig_mem>;
+		};
+
+	};
+};
diff --git a/qcom/crow-pinctrl.dtsi b/qcom/crow-pinctrl.dtsi
new file mode 100755
index 00000000..0c99fd8a
--- /dev/null
+++ b/qcom/crow-pinctrl.dtsi
@@ -0,0 +1,56 @@
+&soc {
+	tlmm: pinctrl@f000000 {
+		compatible = "qcom,crow-pinctrl";
+		reg = <0x0F000000 0x1000000>;
+		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		qcom,gpios-reserved = <32 33 34 35>;
+		wakeup-parent = <&pdc>;
+	};
+};
+
+&tlmm {
+	qupv3_se5_2uart_pins: qupv3_se5_2uart_pins {
+		qupv3_se5_2uart_tx_active: qupv3_se5_2uart_tx_active {
+			mux {
+				pins = "gpio22";
+				function = "qup0_se5_l2";
+			};
+
+			config {
+				pins = "gpio22";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se5_2uart_rx_active: qupv3_se5_2uart_rx_active {
+			mux {
+				pins = "gpio23";
+				function = "qup0_se5_l3";
+			};
+
+			config {
+				pins = "gpio23";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se5_2uart_sleep: qupv3_se5_2uart_sleep {
+			mux {
+				pins = "gpio22", "gpio23";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio22", "gpio23";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+	};
+};
diff --git a/qcom/crow-qupv3.dtsi b/qcom/crow-qupv3.dtsi
new file mode 100755
index 00000000..96fa3cf0
--- /dev/null
+++ b/qcom/crow-qupv3.dtsi
@@ -0,0 +1,28 @@
+&soc {
+	/* QUPv3_0 Wrapper Instance */
+	qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
+		compatible = "qcom,geni-se-qup";
+		reg = <0x8c0000 0x2000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		clock-names = "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		ranges;
+		status = "ok";
+
+		/* Debug UART Instance */
+		qupv3_se5_2uart: qcom,qup_uart@894000 {
+			compatible = "qcom,geni-debug-uart";
+			reg = <0x894000 0x4000>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se5_2uart_tx_active>, <&qupv3_se5_2uart_rx_active>;
+			pinctrl-1 = <&qupv3_se5_2uart_sleep>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/qcom/crow-reserved-memory.dtsi b/qcom/crow-reserved-memory.dtsi
new file mode 100755
index 00000000..7c039d4b
--- /dev/null
+++ b/qcom/crow-reserved-memory.dtsi
@@ -0,0 +1,207 @@
+&reserved_memory {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	ranges;
+
+	gunyah_hyp_mem: gunyah_hyp_region@80000000 {
+		no-map;
+		reg = <0x0 0x80000000 0x0 0xa00000>;
+	};
+
+	cpusys_vm_mem: cpusys_vm_region@80a00000 {
+		no-map;
+		reg = <0x0 0x80a00000 0x0 0x400000>;
+	};
+
+	hyp_tags_mem: hyp_tags_region@80e00000 {
+		no-map;
+		reg = <0x0 0x80e00000 0x0 0x3d0000>;
+	};
+
+	hyp_reserved_mem: hyp_reserved_region@811d0000 {
+		no-map;
+		reg = <0x0 0x811d0000 0x0 0x30000>;
+	};
+
+	xbl_dtlog_mem: xbl_dtlog_region@81a00000 {
+		no-map;
+		reg = <0x0 0x81a00000 0x0 0x40000>;
+	};
+
+	xbl_ramdump_mem: xbl_ramdump_region@81a40000 {
+		no-map;
+		reg = <0x0 0x81a40000 0x0 0x1c0000>;
+	};
+
+	aop_image_mem: aop_image_region@81c00000 {
+		no-map;
+		reg = <0x0 0x81c00000 0x0 0x60000>;
+	};
+
+	aop_cmd_db_mem: aop_cmd_db_region@81c60000 {
+		compatible = "qcom,cmd-db";
+		no-map;
+		reg = <0x0 0x81c60000 0x0 0x20000>;
+	};
+
+	aop_config_mem: aop_config_region@81c80000 {
+		no-map;
+		reg = <0x0 0x81c80000 0x0 0x20000>;
+	};
+
+	tme_crash_dump_mem: tme_crash_dump_region@81ca0000 {
+		no-map;
+		reg = <0x0 0x81ca0000 0x0 0x40000>;
+	};
+
+	tme_log_mem: tme_log_region@81ce0000 {
+		no-map;
+		reg = <0x0 0x81ce0000 0x0 0x4000>;
+	};
+
+	uefi_log_mem: uefi_log_region@81ce4000 {
+		no-map;
+		reg = <0x0 0x81ce4000 0x0 0x10000>;
+	};
+
+	secdata_apss_mem: secdata_apss_region@81cff000 {
+		no-map;
+		reg = <0x0 0x81cff000 0x0 0x1000>;
+	};
+
+	smem_mem: smem_region@81d00000 {
+		no-map;
+		reg = <0x0 0x81d00000 0x0 0x200000>;
+	};
+
+	adsp_mhi_mem: adsp_mhi_region@81f00000 {
+		no-map;
+		reg = <0x0 0x81f00000 0x0 0x20000>;
+	};
+
+	global_sync_mem: global_sync_region@82600000 {
+		no-map;
+		reg = <0x0 0x82600000 0x0 0x100000>;
+	};
+
+	tz_stat_mem: tz_stat_region@82700000 {
+		no-map;
+		reg = <0x0 0x82700000 0x0 0x100000>;
+	};
+
+	wlan_msa_moselle_mem: wlan_msa_moselle_region@82800000 {
+		no-map;
+		reg = <0x0 0x82800000 0x0 0xc00000>;
+	};
+
+	mpss_mem: mpss_region@8a800000 {
+		no-map;
+		reg = <0x0 0x8a800000 0x0 0x10800000>;
+	};
+
+	q6_mpss_dtb_mem: q6_mpss_dtb_region@9b000000 {
+		no-map;
+		reg = <0x0 0x9b000000 0x0 0x80000>;
+	};
+
+	ipa_fw_mem: ipa_fw_region@9b080000 {
+		no-map;
+		reg = <0x0 0x9b080000 0x0 0x10000>;
+	};
+
+	ipa_gsi_mem: ipa_gsi_region@9b090000 {
+		no-map;
+		reg = <0x0 0x9b090000 0x0 0xa000>;
+	};
+
+	gpu_microcode_mem: gpu_microcode_region@9b09a000 {
+		no-map;
+		reg = <0x0 0x9b09a000 0x0 0x2000>;
+	};
+
+	camera_mem: camera_region@9b09c000 {
+		no-map;
+		reg = <0x0 0x9b09c000 0x0 0x700000>;
+	};
+
+	video_mem: video_region@9b79c000 {
+		no-map;
+		reg = <0x0 0x9b79c000 0x0 0x700000>;
+	};
+
+	cdsp_mem: cdsp_region@9be9c000 {
+		no-map;
+		reg = <0x0 0x9be9c000 0x0 0xf00000>;
+	};
+
+	q6_cdsp_dtb_mem: q6_cdsp_dtb_region@9cd9c000 {
+		no-map;
+		reg = <0x0 0x9cd9c000 0x0 0x80000>;
+	};
+
+	q6_adsp_dtb_mem: q6_adsp_dtb_region@9ce1c000 {
+		no-map;
+		reg = <0x0 0x9ce1c000 0x0 0x80000>;
+	};
+
+	adsp_mem: adsp_region@9ce9c000 {
+		no-map;
+		reg = <0x0 0x9ce9c000 0x0 0x2800000>;
+	};
+
+	wpss_moselle_mem: wpss_moselle_region@9f69c000 {
+		no-map;
+		reg = <0x0 0x9f69c000 0x0 0x1900000>;
+	};
+
+	mpss_dsm_mem: mpss_dsm_region@d4d00000 {
+		no-map;
+		reg = <0x0 0xd4d00000 0x0 0x3300000>;
+	};
+
+	tz_reserved_mem: tz_reserved_region@d8000000 {
+		no-map;
+		reg = <0x0 0xd8000000 0x0 0x100000>;
+	};
+
+	xbl_sc_mem: xbl_sc_region@d8100000 {
+		no-map;
+		reg = <0x0 0xd8100000 0x0 0x40000>;
+	};
+
+	cpucp_fw_mem: cpucp_fw_region@d8140000 {
+		no-map;
+		reg = <0x0 0xd8140000 0x0 0x1c0000>;
+	};
+
+	qtee_mem: qtee_region@d8300000 {
+		no-map;
+		reg = <0x0 0xd8300000 0x0 0x500000>;
+	};
+
+	ta_mem: ta_region@d8800000 {
+		no-map;
+		reg = <0x0 0xd8800000 0x0 0x7400000>;
+	};
+
+	tz_tags_mem: tz_tags_region@dfc00000 {
+		no-map;
+		reg = <0x0 0xdfc00000 0x0 0x2140000>;
+	};
+
+	tui_vm_mem: tui_vm_region@f3800000 {
+		no-map;
+		reg = <0x0 0xf3800000 0x0 0x4200000>;
+	};
+
+	oem_vm_mem: oem_vm_region@f7a00000 {
+		no-map;
+		reg = <0x0 0xf7a00000 0x0 0x4a00000>;
+	};
+
+	llcc_lpi_mem: llcc_lpi_region@ff800000 {
+		no-map;
+		reg = <0x0 0xff800000 0x0 0x600000>;
+	};
+
+};
diff --git a/qcom/crow-rumi-overlay.dts b/qcom/crow-rumi-overlay.dts
new file mode 100755
index 00000000..8568dc1c
--- /dev/null
+++ b/qcom/crow-rumi-overlay.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+/plugin/;
+
+#include "crow-rumi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Crow RUMI";
+	compatible = "qcom,crow-rumi", "qcom,crow", "qcom,rumi";
+	qcom,msm-id = <608 0x10000>;
+	qcom,board-id = <0x1000F 0>;
+};
diff --git a/qcom/crow-rumi.dts b/qcom/crow-rumi.dts
new file mode 100755
index 00000000..99318eff
--- /dev/null
+++ b/qcom/crow-rumi.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+/memreserve/ 0x90000000 0x00001000;
+
+#include "crow.dtsi"
+#include "crow-rumi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Crow RUMI";
+	compatible = "qcom,crow-rumi", "qcom,crow", "qcom,rumi";
+	qcom,board-id = <15 0>;
+};
diff --git a/qcom/crow-rumi.dtsi b/qcom/crow-rumi.dtsi
new file mode 100755
index 00000000..680d91a2
--- /dev/null
+++ b/qcom/crow-rumi.dtsi
@@ -0,0 +1,44 @@
+&arch_timer {
+	clock-frequency = <500000>;
+};
+
+&memtimer {
+	clock-frequency = <500000>;
+};
+
+&soc {
+	disp_rsc: rsc@af20000 {
+		status = "disabled";
+	};
+
+	usb_nop_phy: usb_nop_phy {
+		compatible = "usb-nop-xceiv";
+	};
+
+	usb_emu_phy: phy@a784000 {
+		compatible = "qcom,usb-emu-phy";
+		reg = <0x0a784000 0x9500>;
+
+		qcom,emu-init-seq = <0xfffff 0x4
+		     0xffff3 0x4
+		     0xffff0 0x4
+		     0x100000 0x20
+		     0x0 0x20
+		     0x000101F0 0x20
+		     0x00100000 0x3c
+		     0x0 0x3c
+		     0x0010060 0x3c
+		     0x0 0x4>;
+	};
+};
+
+&usb0 {
+	dwc3@a600000 {
+		usb-phy = <&usb_emu_phy>, <&usb_nop_phy>;
+		maximum-speed = "high-speed";
+	};
+};
+
+&qupv3_se5_2uart {
+	qcom,rumi_platform;
+};
diff --git a/qcom/crow-stub-regulators.dtsi b/qcom/crow-stub-regulators.dtsi
new file mode 100755
index 00000000..b361fe99
--- /dev/null
+++ b/qcom/crow-stub-regulators.dtsi
@@ -0,0 +1,583 @@
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+
+/ {
+	VDD_LPI_CX_LEVEL:
+	L2C_LEVEL:
+	pm_v6c_l2_level: regulator-pm-v6c-l2_level {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm_v6c_l2_level";
+		qcom,hpm-min-load = <30000>;
+		regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+		regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+	};
+
+	VDD_LPI_MX_LEVEL:
+	L3C_LEVEL:
+	pm_v6c_l3_level: regulator-pm-v6c-l3-level {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm_v6c_l3_level";
+		qcom,hpm-min-load = <30000>;
+		regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+		regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+	};
+
+	VDD_MXA_LEVEL:
+	S5B_LEVEL:
+	pm7550_s5_level: regulator-pm7550-s5-level {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm7550_s5_level";
+		regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+		regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+		qcom,hpm-min-load = <10000>;
+	};
+
+	VDD_CX_LEVEL:
+	S1C_LEVEL:
+	pm_v6c_s1_level: regulator-pm-v6c-s1-level {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm_v6c_s1_level";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+		regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+	};
+
+	VDD_MODEM_LEVEL:
+	S4C_LEVEL:
+	pm_v6c_s4_level: regulator-pm-v6c-s4-level {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm_v6c_s4_level";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+		regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+	};
+
+	VDD_MXC_LEVEL:
+	VDD_MM_MXC_VOTER_LEVEL:
+	VDD_GFX_MXC_VOTER_LEVEL:
+	S6C_LEVEL:
+	pm_v6c_s6_level: regulator-pm-v6c-s6-level {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm_v6c_s6_level";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+		regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+	};
+
+	VDD_GFX_LEVEL:
+	S1D_LEVEL:
+	pm_v6d_s1_level: regulator-pm-v6d-s1-level {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm_v6d_s1_level";
+		qcom,hpm-min-load = <30000>;
+		regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+		regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+	};
+
+	VDD_EBI_LEVEL:
+	S3D_LEVEL:
+	pm_v6d_s3_level: regulator-pm-v6d-s3-level {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm_v6d_s3_level";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+		regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+	};
+
+	S1B: pm7550_s1: regulator-pm7550-s1 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm7550_s1";
+		regulator-min-microvolt = <1856000>;
+		regulator-max-microvolt = <2040000>;
+		qcom,hpm-min-load = <10000>;
+	};
+
+	S2B: pm7550_s2: regulator-pm7550-s2-level {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm7550_s2";
+		regulator-min-microvolt = <1256000>;
+		regulator-max-microvolt = <2050000>;
+		qcom,hpm-min-load = <10000>;
+	};
+
+	S3B: pm7550_s3: regulator-pm7550-s3 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm7550_s3";
+		regulator-min-microvolt = <880000>;
+		regulator-max-microvolt = <1040000>;
+		qcom,hpm-min-load = <10000>;
+	};
+
+	S4B: pm7550_s4: regulator-pm7550-s4 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm7550_s4";
+		regulator-min-microvolt = <2200000>;
+		regulator-max-microvolt = <2200000>;
+		qcom,hpm-min-load = <10000>;
+	};
+
+	S6D: pm_v6d_s6: regulator-pm-v6d-s6 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm_v6d_s6";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <1010000>;
+		regulator-max-microvolt = <1170000>;
+	};
+
+	L1C: pm_v6c_l1: regulator-pm-v6c-l1 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm_v6c_l1";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <300000>;
+		regulator-max-microvolt = <650000>;
+	};
+
+	L1B: pm7550_l1: regulator-pm7550-l1 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm7550_l1";
+		regulator-min-microvolt = <880000>;
+		regulator-max-microvolt = <912000>;
+		qcom,hpm-min-load = <10000>;
+	};
+
+	L2B: pm7550_l2: regulator-pm7550-l2 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm7550_l2";
+		regulator-min-microvolt = <880000>;
+		regulator-max-microvolt = <912000>;
+		qcom,hpm-min-load = <10000>;
+	};
+
+	L3B: pm7550_l3: regulator-pm7550-l3 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm7550_l3";
+		regulator-min-microvolt = <880000>;
+		regulator-max-microvolt = <912000>;
+		qcom,hpm-min-load = <10000>;
+	};
+
+	L4B: pm7550_l4: regulator-pm7550-l4 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm7550_l4";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		qcom,hpm-min-load = <10000>;
+	};
+
+	L5B: pm7550_l5: regulator-pm7550-l5 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm7550_l5";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		qcom,hpm-min-load = <10000>;
+	};
+
+	L7B: pm7550_l7: regulator-pm7550-l7 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm7550_l7";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		qcom,hpm-min-load = <10000>;
+	};
+
+	L8B: pm7550_l8: regulator-pm7550-l8 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm7550_l8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		qcom,hpm-min-load = <10000>;
+	};
+
+	L9B: pm7550_l9: regulator-pm7550-l9 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm7550_l9";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		qcom,hpm-min-load = <10000>;
+	};
+
+	L10B: pm7550_l10: regulator-pm7550-l10 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm7550_l10";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		qcom,hpm-min-load = <10000>;
+	};
+
+	L11B: pm7550_l11: regulator-pm7550-l11 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm7550_l11";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		qcom,hpm-min-load = <10000>;
+	};
+
+	L12B: pm7550_l12: regulator-pm7550-l12 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm7550_l12";
+
+	/*
+	 * Removed min/max and init for UFS_VCC,
+	 * as voltage set from the BOOT should not
+	 * be changed
+	 */
+
+	};
+
+	L13B: pm7550_l13: regulator-pm7550-l13 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm7550_l13";
+		regulator-min-microvolt = <2700000>;
+		regulator-max-microvolt = <3300000>;
+		qcom,hpm-min-load = <10000>;
+	};
+
+	L14B: pm7550_l14: regulator-pm7550-l14 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm7550_l14";
+		regulator-min-microvolt = <2650000>;
+		regulator-max-microvolt = <2950000>;
+		qcom,hpm-min-load = <10000>;
+	};
+
+	L16B: pm7550_l16: regulator-pm7550-l16 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm7550_l16";
+		regulator-min-microvolt = <3008000>;
+		regulator-max-microvolt = <3008000>;
+		qcom,hpm-min-load = <10000>;
+	};
+
+	L17B: pm7550_l17: regulator-pm7550-l17 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm7550_l17";
+		regulator-min-microvolt = <3104000>;
+		regulator-max-microvolt = <3104000>;
+		qcom,hpm-min-load = <10000>;
+	};
+
+	L18B: pm7550_l18: regulator-pm7550-l18 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm7550_l18";
+		regulator-min-microvolt = <2800000>;
+		regulator-max-microvolt = <2800000>;
+		qcom,hpm-min-load = <10000>;
+	};
+
+	L19B: pm7550_l19: regulator-pm7550-l19 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm7550_l19";
+		regulator-min-microvolt = <3000000>;
+		regulator-max-microvolt = <3000000>;
+		qcom,hpm-min-load = <10000>;
+	};
+
+	L20B: pm7550_l20: regulator-pm7550-l20 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm7550_l20";
+		regulator-min-microvolt = <1620000>;
+		regulator-max-microvolt = <3544000>;
+		qcom,hpm-min-load = <10000>;
+	};
+
+	L21B: pm7550_l21: regulator-pm7550-l21 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm7550_l21";
+		regulator-min-microvolt = <1620000>;
+		regulator-max-microvolt = <3544000>;
+		qcom,hpm-min-load = <10000>;
+	};
+
+	L22B: pm7550_l22: regulator-pm7550-l22 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm7550_l22";
+		regulator-min-microvolt = <3200000>;
+		regulator-max-microvolt = <3200000>;
+		qcom,hpm-min-load = <10000>;
+	};
+
+	L23B: pm7550_l23: regulator-pm7550-l23 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm7550_l23";
+		regulator-min-microvolt = <1650000>;
+		regulator-max-microvolt = <3544000>;
+		qcom,hpm-min-load = <10000>;
+	};
+
+	L1D:
+	pm_v6d_l1: regulator-pm-v6d-l1 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm_v6d_l1";
+		regulator-min-microvolt = <870000>;
+		regulator-max-microvolt = <970000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L2D:
+	pm_v6d_l2: regulator-pm-v6d-l2 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm_v6d_l2";
+		regulator-min-microvolt = <1140000>;
+		regulator-max-microvolt = <1950000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L3D:
+	pm_v6d_l3: regulator-pm-v6d-l3 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm_v6d_l3";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L1M:
+	pm8010m_l1: regulator-pm8010m-l1 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8010m_l1";
+		regulator-min-microvolt = <1050000>;
+		regulator-max-microvolt = <1180000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L2M:
+	pm8010m_l2: regulator-pm8010m-l2 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8010m_l2";
+		regulator-min-microvolt = <950000>;
+		regulator-max-microvolt = <1150000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L3M:
+	pm8010m_l3: regulator-pm8010m-l3 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8010m_l3";
+		regulator-min-microvolt = <2700000>;
+		regulator-max-microvolt = <2900000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L4M:
+	pm8010m_l4: regulator-pm8010m-l4 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8010m_l4";
+		regulator-min-microvolt = <2700000>;
+		regulator-max-microvolt = <2900000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L5M:
+	pm8010m_l5: regulator-pm8010m-l5 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8010m_l5";
+		regulator-min-microvolt = <1700000>;
+		regulator-max-microvolt = <1900000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L6M:
+	pm8010m_l6: regulator-pm8010m-l6 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8010m_l6";
+		regulator-min-microvolt = <2700000>;
+		regulator-max-microvolt = <2900000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L7M:
+	pm8010m_l7: regulator-pm8010m-l7 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8010m_l7";
+		regulator-min-microvolt = <2700000>;
+		regulator-max-microvolt = <3000000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L1N:
+	pm8010n_l1: regulator-pm8010n-l1 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8010n_l1";
+		regulator-min-microvolt = <1050000>;
+		regulator-max-microvolt = <1200000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L2N:
+	pm8010n_l2: regulator-pm8010n-l2 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8010n_l2";
+		regulator-min-microvolt = <950000>;
+		regulator-max-microvolt = <115000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L3N:
+	pm8010n_l3: regulator-pm8010n-l3 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8010n_l3";
+		regulator-min-microvolt = <1792000>;
+		regulator-max-microvolt = <1980000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L4N:
+	pm8010n_l4: regulator-pm8010n-l4 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8010n_l4";
+		regulator-min-microvolt = <1792000>;
+		regulator-max-microvolt = <1900000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L5N:
+	pm8010n_l5: regulator-pm8010n-l5 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8010n_l5";
+		regulator-min-microvolt = <2700000>;
+		regulator-max-microvolt = <2900000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L7N:
+	pm8010n_l7: regulator-pm8010n-l7 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8010n_l7";
+		regulator-min-microvolt = <2500000>;
+		regulator-max-microvolt = <3300000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	BOB: pm7550_bob: regulator-pm7550-bob {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm7550_bob";
+		regulator-min-microvolt = <3008000>;
+		regulator-max-microvolt = <3960000>;
+	};
+
+	L1P:
+	pm8010p_l1: regulator-pm8010p-l1 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8010p_l1";
+		regulator-min-microvolt = <1050000>;
+		regulator-max-microvolt = <1180000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L2P:
+	pm8010p_l2: regulator-pm8010p-l2 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8010p_l2";
+		regulator-min-microvolt = <950000>;
+		regulator-max-microvolt = <1150000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L3P:
+	pm8010p_l3: regulator-pm8010p-l3 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8010p_l3";
+		regulator-min-microvolt = <2700000>;
+		regulator-max-microvolt = <2900000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L4P:
+	pm8010p_l4: regulator-pm8010p-l4 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8010p_l4";
+		regulator-min-microvolt = <2700000>;
+		regulator-max-microvolt = <2900000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L5P:
+	pm8010p_l5: regulator-pm8010p-l5 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8010p_l5";
+		regulator-min-microvolt = <1700000>;
+		regulator-max-microvolt = <1900000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L6P:
+	pm8010p_l6: regulator-pm8010p-l6 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8010p_l6";
+		regulator-min-microvolt = <2700000>;
+		regulator-max-microvolt = <2900000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L7P:
+	pm8010p_l7: regulator-pm8010p-l7 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8010p_l7";
+		regulator-min-microvolt = <2700000>;
+		regulator-max-microvolt = <3000000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L1Q:
+	pm8010q_l1: regulator-pm8010q-l1 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8010q_l1";
+		regulator-min-microvolt = <1050000>;
+		regulator-max-microvolt = <1200000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L2Q:
+	pm8010q_l2: regulator-pm8010q-l2 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8010q_l2";
+		regulator-min-microvolt = <950000>;
+		regulator-max-microvolt = <115000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L3Q:
+	pm8010q_l3: regulator-pm8010q-l3 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8010q_l3";
+		regulator-min-microvolt = <1620000>;
+		regulator-max-microvolt = <1980000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L4Q:
+	pm8010q_l4: regulator-pm8010q-l4 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8010q_l4";
+		regulator-min-microvolt = <1700000>;
+		regulator-max-microvolt = <1900000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L5Q:
+	pm8010q_l5: regulator-pm8010q-l5 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8010q_l5";
+		regulator-min-microvolt = <2700000>;
+		regulator-max-microvolt = <2900000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L6Q:
+	pm8010q_l6: regulator-pm8010q-l6 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8010q_l6";
+		regulator-min-microvolt = <1504000>;
+		regulator-max-microvolt = <3544000>;
+		qcom,hpm-min-load = <30000>;
+	};
+
+	L7Q:
+	pm8010q_l7: regulator-pm8010q-l7 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8010q_l7";
+		regulator-min-microvolt = <2500000>;
+		regulator-max-microvolt = <3300000>;
+		qcom,hpm-min-load = <30000>;
+	};
+};
+
diff --git a/qcom/crow-usb.dtsi b/qcom/crow-usb.dtsi
new file mode 100755
index 00000000..4852e6ce
--- /dev/null
+++ b/qcom/crow-usb.dtsi
@@ -0,0 +1,46 @@
+#include <dt-bindings/clock/qcom,gcc-crow.h>
+
+&soc {
+	usb0: ssusb@a600000 {
+		compatible = "qcom,dwc-usb3-msm";
+		reg = <0xa600000 0x100000>;
+		reg-names = "core_base";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+			<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+			<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+			<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+			<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
+		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+					"utmi_clk", "sleep_clk";
+
+		resets = <&gcc GCC_USB30_PRIM_BCR>;
+		reset-names = "core_reset";
+
+		interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "pwr_event_irq";
+
+		qcom,core-clk-rate = <200000000>;
+		qcom,core-clk-rate-hs = <66666667>;
+
+		dwc3@a600000 {
+			compatible = "snps,dwc3";
+			reg = <0xa600000 0xd93c>;
+
+			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+			snps,has-lpm-erratum;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			snps,is-utmi-l1-suspend;
+			snps,dis-u1-entry-quirk;
+			snps,dis-u2-entry-quirk;
+			snps,dis_u2_susphy_quirk;
+			snps,ssp-u3-u0-quirk;
+			dr_mode = "peripheral";
+			maximum-speed = "super-speed-plus";
+		};
+	};
+};
diff --git a/qcom/crow.dts b/qcom/crow.dts
new file mode 100755
index 00000000..5ab19694
--- /dev/null
+++ b/qcom/crow.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "crow.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Crow SoC";
+	compatible = "qcom,crow";
+	qcom,board-id = <0 0>;
+};
diff --git a/qcom/crow.dtsi b/qcom/crow.dtsi
new file mode 100755
index 00000000..d2445a1d
--- /dev/null
+++ b/qcom/crow.dtsi
@@ -0,0 +1,818 @@
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,camcc-crow.h>
+#include <dt-bindings/clock/qcom,dispcc-crow.h>
+#include <dt-bindings/clock/qcom,gcc-crow.h>
+#include <dt-bindings/clock/qcom,gpucc-crow.h>
+#include <dt-bindings/clock/qcom,tcsrcc-kalama.h>
+#include <dt-bindings/clock/qcom,videocc-crow.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/qcom,ipcc.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+
+/ {
+	model = "Qualcomm Technologies, Inc. Crow";
+	compatible = "qcom,crow";
+	qcom,msm-id = <608 0x10000>;
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen: chosen { };
+
+	memory { device_type = "memory"; reg = <0 0 0 0>; };
+
+	reserved_memory: reserved-memory { };
+
+	firmware: firmware {};
+
+	aliases {
+		serial0 = &qupv3_se5_2uart;
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+			L2_0: l2-cache {
+				compatible = "arm,arch-cache";
+				cache-level = <2>;
+				next-level-cache = <&L3_0>;
+				L3_0: l3-cache {
+					compatible = "arm,arch-cache";
+					cache-level = <3>;
+				};
+			};
+		};
+
+		CPU1: cpu@100 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
+
+		CPU2: cpu@200 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x200>;
+			enable-method = "psci";
+			next-level-cache = <&L2_2>;
+			L2_2: l2-cache {
+				compatible = "arm,arch-cache";
+				cache-level = <2>;
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU3: cpu@300 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x300>;
+			enable-method = "psci";
+			next-level-cache = <&L2_2>;
+		};
+
+		CPU4: cpu@400 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x400>;
+			enable-method = "psci";
+			next-level-cache = <&L2_4>;
+			L2_4: l2-cache {
+				compatible = "arm,arch-cache";
+				cache-level = <2>;
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU5: cpu@500 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x500>;
+			enable-method = "psci";
+			next-level-cache = <&L2_5>;
+			L2_5: l2-cache {
+				compatible = "arm,arch-cache";
+				cache-level = <2>;
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU6: cpu@600 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x600>;
+			enable-method = "psci";
+			next-level-cache = <&L2_6>;
+			L2_6: l2-cache {
+				compatible = "arm,arch-cache";
+				cache-level = <2>;
+				next-level-cache = <&L3_0>;
+				};
+		};
+
+		CPU7: cpu@700 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x700>;
+			enable-method = "psci";
+			next-level-cache = <&L2_7>;
+			L2_7: l2-cache {
+				compatible = "arm,arch-cache";
+				cache-level = <2>;
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+
+				core1 {
+					cpu = <&CPU1>;
+				};
+
+				core2 {
+					cpu = <&CPU2>;
+				};
+
+				core3 {
+					cpu = <&CPU3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&CPU4>;
+				};
+
+				core1 {
+					cpu = <&CPU5>;
+				};
+
+				core2 {
+					cpu = <&CPU6>;
+				};
+			};
+
+			cluster2 {
+				core0 {
+					cpu = <&CPU7>;
+				};
+			};
+		};
+	};
+
+	soc: soc { };
+};
+
+#include "crow-reserved-memory.dtsi"
+#include "crow-dma-heaps.dtsi"
+
+&reserved_memory {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	ranges;
+
+	/* global autoconfigured region for contiguous allocations */
+	system_cma: linux,cma {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x2000000>;
+		linux,cma-default;
+	};
+
+	user_contig_mem: user_contig_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x1000000>;
+	};
+
+	qseecom_mem: qseecom_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x1400000>;
+	};
+
+	qseecom_ta_mem: qseecom_ta_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x1000000>;
+	};
+};
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0 0 0 0xffffffff>;
+	compatible = "simple-bus";
+
+	intc: interrupt-controller@17100000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		#redistributor-regions = <1>;
+		redistributor-stride = <0x0 0x40000>;
+		reg = <0x17100000 0x10000>,/* GICD */
+			<0x17180000 0x200000>;/* GICR * 8 */
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	apps_rsc: rsc@17a00000 {
+		label = "apps_rsc";
+		compatible = "qcom,rpmh-rsc";
+		reg = <0x17a00000 0x10000>,
+		      <0x17a10000 0x10000>,
+		      <0x17a20000 0x10000>;
+		reg-names = "drv-0", "drv-1", "drv-2";
+		qcom,drv-count = <3>;
+		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+
+		apps_rsc_drv2: drv@2 {
+			qcom,drv-id = <2>;
+			qcom,tcs-offset = <0xd00>;
+			channel@0 {
+				qcom,tcs-config = <ACTIVE_TCS    3>,
+						  <SLEEP_TCS     2>,
+						  <WAKE_TCS      2>,
+						  <CONTROL_TCS   0>,
+						  <FAST_PATH_TCS 1>;
+			};
+		};
+	};
+
+	disp_rsc: rsc@af20000 {
+		label = "disp_rsc";
+		compatible = "qcom,rpmh-rsc";
+		reg = <0xaf20000 0x10000>;
+		reg-names = "drv-0";
+		qcom,drv-count = <1>;
+		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+		/*Clock node to add here*/
+
+		disp_rsc_drv0: drv@0 {
+			qcom,drv-id = <0>;
+			qcom,tcs-offset = <0x1c00>;
+			channel@0 {
+				qcom,tcs-config = <ACTIVE_TCS    0>,
+						  <SLEEP_TCS     1>,
+						  <WAKE_TCS      1>,
+						  <CONTROL_TCS   0>,
+						  <FAST_PATH_TCS 0>;
+			};
+		};
+	};
+
+	pdc: interrupt-controller@b220000 {
+		compatible = "qcom,crow-pdc", "qcom,pdc";
+		reg = <0xb220000 0x30000>, <0x174000f0 0x64>;
+		qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>,
+				  <126 716 12>, <138 470 5>;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&intc>;
+		interrupt-controller;
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <19200000>;
+	};
+
+	memtimer: timer@17420000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		compatible = "arm,armv7-timer-mem";
+		reg = <0x17420000 0x1000>;
+		clock-frequency = <19200000>;
+
+		frame@17421000 {
+			frame-number = <0>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17421000 0x1000>,
+				<0x17422000 0x1000>;
+		};
+
+		frame@17423000 {
+			frame-number = <1>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17423000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17425000 {
+			frame-number = <2>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17425000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17427000 {
+			frame-number = <3>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17427000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17429000 {
+			frame-number = <4>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17429000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@1742b000 {
+			frame-number = <5>;
+			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x1742b000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@1742d000 {
+			frame-number = <6>;
+			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x1742d000 0x1000>;
+			status = "disabled";
+		};
+	};
+
+	ipcc_mproc: qcom,ipcc@408000 {
+		compatible = "qcom,ipcc";
+		reg = <0x408000 0x1000>;
+		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		#mbox-cells = <2>;
+	};
+
+	aoss_qmp: power-controller@c300000 {
+		compatible = "qcom,kalama-aoss-qmp";
+		reg = <0xc300000 0x400>;
+		interrupt-parent = <&ipcc_mproc>;
+		interrupts = <IPCC_CLIENT_AOP
+			      IPCC_MPROC_SIGNAL_GLINK_QMP
+			      IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
+			  IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+		#power-domain-cells = <1>;
+		#clock-cells = <0>;
+	};
+
+	qmp_aop: qcom,qmp-aop {
+		compatible = "qcom,qmp-mbox";
+		qcom,qmp = <&aoss_qmp>;
+		label = "aop";
+		#mbox-cells = <1>;
+	};
+
+	qmp_tme: qcom,qmp-tme {
+		compatible = "qcom,qmp-mbox";
+		qcom,remote-pid = <14>;
+		mboxes = <&ipcc_mproc IPCC_CLIENT_TME
+			  IPCC_MPROC_SIGNAL_GLINK_QMP>;
+		mbox-names = "tme_qmp";
+		interrupt-parent = <&ipcc_mproc>;
+		interrupts = <IPCC_CLIENT_TME
+			      IPCC_MPROC_SIGNAL_GLINK_QMP
+			      IRQ_TYPE_EDGE_RISING>;
+
+		label = "tme";
+		qcom,early-boot;
+		priority = <0>;
+		mbox-desc-offset = <0x0>;
+		#mbox-cells = <1>;
+	};
+
+	tcsr_mutex_block: syscon@1f40000 {
+		compatible = "syscon";
+		reg = <0x1f40000 0x20000>;
+	};
+
+	tcsr_mutex: hwlock {
+		compatible = "qcom,tcsr-mutex";
+		syscon = <&tcsr_mutex_block 0 0x1000>;
+		#hwlock-cells = <1>;
+	};
+
+	smem: qcom,smem {
+		compatible = "qcom,smem";
+		memory-region = <&smem_mem>;
+		depends-on-supply = <&tcsr_mutex>;
+		hwlocks = <&tcsr_mutex 3>;
+	};
+
+	qcom,smp2p-adsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <443>, <429>;
+		interrupt-parent = <&ipcc_mproc>;
+		interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
+			      IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
+			  IPCC_MPROC_SIGNAL_SMP2P>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <2>;
+
+		adsp_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		adsp_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		sleepstate_smp2p_out: sleepstate-out {
+			qcom,entry-name = "sleepstate";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		sleepstate_smp2p_in: qcom,sleepstate-in {
+			qcom,entry-name = "sleepstate_see";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	qcom,smp2p-cdsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <94>, <432>;
+		interrupt-parent = <&ipcc_mproc>;
+		interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
+			      IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <5>;
+
+		cdsp_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		cdsp_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	qcom,smp2p-modem {
+		compatible = "qcom,smp2p";
+		qcom,smem = <435>, <428>;
+		interrupt-parent = <&ipcc_mproc>;
+		interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P
+			      IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <1>;
+
+		modem_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		modem_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	qcom,smp2p_sleepstate {
+		compatible = "qcom,smp2p-sleepstate";
+		qcom,smem-states = <&sleepstate_smp2p_out 0>;
+		interrupt-parent = <&sleepstate_smp2p_in>;
+		interrupts = <0 0>;
+		interrupt-names = "smp2p-sleepstate-in";
+	};
+
+	qcom,smp2p-wpss {
+		compatible = "qcom,smp2p";
+		qcom,smem = <617>, <616>;
+		interrupt-parent = <&ipcc_mproc>;
+		interrupts = <IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P
+			IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <13>;
+
+		wpss_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		wpss_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		smp2p_wlan_1_in: qcom,smp2p-wlan-1-in {
+			qcom,entry-name = "wlan";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		smp2p_wlan_1_out: qcom,smp2p-wlan-1-out {
+			qcom,entry-name = "wlan";
+			#qcom,smem-state-cells = <1>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	clocks {
+		xo_board: xo_board {
+			compatible = "fixed-clock";
+			clock-frequency = <19200000>;
+			clock-output-names = "xo_board";
+			#clock-cells = <0>;
+		};
+
+		sleep_clk: sleep_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32000>;
+			clock-output-names = "sleep_clk";
+			#clock-cells = <0>;
+		};
+
+		gcc_jdr_ctrl_pll_tcg_mux_clk_src: gcc_jdr_ctrl_pll_tcg_mux_clk_src {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			clock-output-names = "gcc_jdr_ctrl_pll_tcg_mux_clk_src";
+			#clock-cells = <0>;
+		};
+
+		pcie_0_pipe_clk: pcie_0_pipe_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			clock-output-names = "pcie_0_pipe_clk";
+			#clock-cells = <0>;
+		};
+
+		pcie_1_phy_aux_clk: pcie_1_phy_aux_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			clock-output-names = "pcie_1_phy_aux_clk";
+			#clock-cells = <0>;
+		};
+
+		pcie_1_pipe_clk: pcie_1_pipe_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			clock-output-names = "pcie_1_pipe_clk";
+			#clock-cells = <0>;
+		};
+
+		ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			clock-output-names = "ufs_phy_rx_symbol_0_clk";
+			#clock-cells = <0>;
+		};
+
+		ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			clock-output-names = "ufs_phy_rx_symbol_1_clk";
+			#clock-cells = <0>;
+		};
+
+		ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			clock-output-names = "ufs_phy_tx_symbol_0_clk";
+			#clock-cells = <0>;
+		};
+
+		usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
+			#clock-cells = <0>;
+		};
+	};
+
+	cxo: bi_tcxo {
+		compatible = "fixed-factor-clock";
+		clocks = <&xo_board>;
+		clock-mult = <1>;
+		clock-div = <1>;
+		#clock-cells = <0>;
+		clock-output-names = "bi_tcxo";
+	};
+
+	cxo_a: bi_tcxo_ao {
+		compatible = "fixed-factor-clock";
+		clocks = <&xo_board>;
+		clock-mult = <1>;
+		clock-div = <1>;
+		#clock-cells = <0>;
+		clock-output-names = "bi_tcxo_ao";
+	};
+
+	rpmhcc: clock-controller {
+		compatible = "fixed-clock";
+		clock-output-names = "rpmh_clocks";
+		clock-frequency = <19200000>;
+		#clock-cells = <1>;
+	};
+
+	camcc: clock-controller@adb0000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "camcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	dispcc: clock-controller@af00000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "dispcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	gcc: clock-controller@100000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "gcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	gpucc: clock-controller@3d90000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "gpucc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	tcsrcc: clock-controller@1fc0000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "tcsrcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	videocc: clock-controller@aaf0000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "videocc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	qcom_qseecom: qseecom@c1700000 {
+		compatible = "qcom,qseecom";
+		memory-region = <&qseecom_mem>;
+		qseecom_mem = <&qseecom_mem>;
+		qseecom_ta_mem = <&qseecom_ta_mem>;
+		user_contig_mem = <&user_contig_mem>;
+		qcom,hlos-num-ce-hw-instances = <1>;
+		qcom,hlos-ce-hw-instance = <0>;
+		qcom,qsee-ce-hw-instance = <0>;
+		qcom,disk-encrypt-pipe-pair = <2>;
+		qcom,no-clock-support;
+		qcom,appsbl-qseecom-support;
+		qcom,commonlib64-loaded-by-uefi;
+		qcom,qsee-reentrancy-support = <2>;
+	};
+
+	qcom_tzlog: tz-log@146AA720 {
+		compatible = "qcom,tz-log";
+		reg = <0x146AA720 0x3000>;
+		qcom,hyplog-enabled;
+		hyplog-address-offset = <0x410>;
+		hyplog-size-offset = <0x414>;
+	};
+};
+
+&firmware {
+	qcom_scm {
+		compatible = "qcom,scm";
+	};
+
+	qcom_smcinvoke {
+		compatible = "qcom,smcinvoke";
+	};
+
+	qtee_shmbridge {
+		compatible = "qcom,tee-shared-memory-bridge";
+	};
+};
+
+#include "crow-pinctrl.dtsi"
+#include "crow-usb.dtsi"
+#include "crow-stub-regulators.dtsi"
+#include "kalama-gdsc.dtsi"
+#include "crow-qupv3.dtsi"
+
+&qupv3_se5_2uart {
+	status = "ok";
+};
+
+&cam_cc_camss_top_gdsc {
+	compatible = "qcom,stub-regulator";
+	status = "ok";
+};
+
+&disp_cc_mdss_core_gdsc {
+	compatible = "qcom,stub-regulator";
+	status = "ok";
+};
+
+&disp_cc_mdss_core_int2_gdsc {
+	compatible = "qcom,stub-regulator";
+	status = "ok";
+};
+
+&gcc_pcie_0_gdsc {
+	compatible = "qcom,stub-regulator";
+	status = "ok";
+};
+
+&gcc_pcie_0_phy_gdsc {
+	compatible = "qcom,stub-regulator";
+	status = "ok";
+};
+
+&gcc_pcie_1_gdsc {
+	compatible = "qcom,stub-regulator";
+	status = "ok";
+};
+
+&gcc_pcie_1_phy_gdsc {
+	compatible = "qcom,stub-regulator";
+	status = "ok";
+};
+
+&gcc_ufs_mem_phy_gdsc {
+	compatible = "qcom,stub-regulator";
+	status = "ok";
+};
+
+&gcc_ufs_phy_gdsc {
+	compatible = "qcom,stub-regulator";
+	status = "ok";
+};
+
+&gcc_usb30_prim_gdsc {
+	compatible = "qcom,stub-regulator";
+	status = "ok";
+};
+
+&gcc_usb3_phy_gdsc {
+	compatible = "qcom,stub-regulator";
+	status = "ok";
+};
+
+&gpu_cc_cx_gdsc {
+	compatible = "qcom,stub-regulator";
+	status = "ok";
+};
+
+&gpu_cc_gx_gdsc {
+	compatible = "qcom,stub-regulator";
+	status = "ok";
+};
+
+&video_cc_mvs0_gdsc {
+	compatible = "qcom,stub-regulator";
+	reg = <0xaaf805c 0x4>;
+	status = "ok";
+};
+
+&video_cc_mvs0c_gdsc {
+	compatible = "qcom,stub-regulator";
+	reg = <0xaaf8034 0x4>;
+	status = "ok";
+};
diff --git a/qcom/direwolf-pinctrl.dtsi b/qcom/direwolf-pinctrl.dtsi
index 1b667faf..7dc9a831 100755
--- a/qcom/direwolf-pinctrl.dtsi
+++ b/qcom/direwolf-pinctrl.dtsi
@@ -2178,6 +2178,7 @@
 		config {
 			pins = "gpio126";
 			drive-strength = <2>;
+			output-low;
 			bias-pull-down;
 		};
 	};
@@ -2208,6 +2209,19 @@
 		};
 	};
 
+	conn_power_pa_active2: conn_power_pa2_active2 {
+		mux {
+			pins = "gpio216";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio216";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
 	emac {
 		emac_mdc: emac_mdc {
 			mux {
diff --git a/qcom/direwolf-qupv3.dtsi b/qcom/direwolf-qupv3.dtsi
index a9926ffe..03fc2344 100755
--- a/qcom/direwolf-qupv3.dtsi
+++ b/qcom/direwolf-qupv3.dtsi
@@ -326,18 +326,17 @@
 			compatible = "qcom,msm-geni-serial-hs";
 			reg = <0x998000 0x4000>;
 			reg-names = "se_phys";
-			interrupts = <&intc GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts-extended = <&intc GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>,
+						<&tlmm 157 IRQ_TYPE_LEVEL_HIGH>;
 			clock-names = "se-clk";
 			clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
-			pinctrl-names = "default", "active", "sleep", "shutdown";
+			pinctrl-names = "default", "active", "sleep";
 			pinctrl-0 = <&qupv3_se6_default_cts>,
 			<&qupv3_se6_default_rtsrx>, <&qupv3_se6_default_tx>;
 			pinctrl-1 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,
 			<&qupv3_se6_tx>;
 			pinctrl-2 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,
 			<&qupv3_se6_tx>;
-			pinctrl-3 = <&qupv3_se6_default_cts>,
-			<&qupv3_se6_default_rtsrx>, <&qupv3_se6_default_tx>;
 			qcom,wakeup-byte = <0xFD>;
 			status = "disabled";
 		};
diff --git a/qcom/direwolf-vm-headless.dtsi b/qcom/direwolf-vm-headless.dtsi
new file mode 100755
index 00000000..4ff5f61d
--- /dev/null
+++ b/qcom/direwolf-vm-headless.dtsi
@@ -0,0 +1,60 @@
+#include "quin-vm-common.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Direwolf Virtual Machine";
+	qcom,msm-name = "SA_DIREWOLF_IVI";
+	qcom,msm-id = <460 0x10000>;
+
+};
+
+&soc {
+	qtee_shmbridge {
+		compatible = "qcom,tee-shared-memory-bridge";
+		/*Boolean property to disable shmbridge*/
+		qcom,disable-shmbridge-support;
+	};
+
+	qcom_qseecom: qseecom@c1800000 {
+		compatible = "qcom,qseecom";
+		reg = <0xc1800000 0x3900000>;
+		reg-names = "secapp-region";
+		memory-region = <&qseecom_mem>;
+		qcom,hlos-num-ce-hw-instances = <1>;
+		qcom,hlos-ce-hw-instance = <0>;
+		qcom,qsee-ce-hw-instance = <0>;
+		qcom,disk-encrypt-pipe-pair = <2>;
+		qcom,no-clock-support;
+		qcom,commonlib-loaded-by-hostvm;
+		qcom,qsee-reentrancy-support = <2>;
+	};
+
+	qcom_rng_ee3: qrng@10d3000 {
+		compatible = "qcom,msm-rng";
+		reg = <0x10d3000 0x1000>;
+		qcom,no-qrng-config;
+		clocks = <&dummycc RPMH_HWKM_CLK>;
+		clock-names = "km_clk_src";
+	};
+};
+
+&firmware {
+	scm {
+		compatible = "qcom,scm";
+	};
+};
+
+&spmi_bus {
+	status = "disabled";
+};
+
+&regulator {
+	status = "disabled";
+};
+
+&gcc {
+	status = "disabled";
+};
+
+&scc {
+	status = "disabled";
+};
diff --git a/qcom/direwolf-vm-la-mt-overlay.dts b/qcom/direwolf-vm-la-mt-overlay.dts
new file mode 100755
index 00000000..5258208c
--- /dev/null
+++ b/qcom/direwolf-vm-la-mt-overlay.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	model = "Qualcomm Technologies, Inc. Direwolf Multi LA Virtual Machine";
+	compatible = "qcom,direwolf", "qcom,quinvm";
+	qcom,msm-id = <460 0x10000>;
+	qcom,board-id = <0 0x2000001>;
+};
diff --git a/qcom/direwolf-vm-la-mt.dts b/qcom/direwolf-vm-la-mt.dts
new file mode 100755
index 00000000..8807639c
--- /dev/null
+++ b/qcom/direwolf-vm-la-mt.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "direwolf-vm.dtsi"
+#include "direwolf-vm-la-mt.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Direwolf Multi LA Virtual Machine";
+	compatible = "qcom,direwolf", "qcom,quinvm";
+	qcom,board-id = <0 0x2000001>;
+};
diff --git a/qcom/direwolf-vm-la-mt.dtsi b/qcom/direwolf-vm-la-mt.dtsi
new file mode 100755
index 00000000..bad51479
--- /dev/null
+++ b/qcom/direwolf-vm-la-mt.dtsi
@@ -0,0 +1,67 @@
+&reserved_memory {
+	secure_display_memory: secure_display_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x0a000000>;
+	};
+};
+
+&qcom_dma_heaps {
+	qcom,display {
+		qcom,dma-heap-name = "qcom,display";
+		qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+		qcom,max-align = <9>;
+		memory-region = <&secure_display_memory>;
+	};
+};
+
+&qcom_rng_ee3 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+};
+
+&usb2_phy0 {
+	status = "okay";
+};
+
+&usb_qmp_dp_phy0 {
+	status = "okay";
+};
+
+&qupv3_0 {
+	iommus = <&apps_smmu 0x0578 0x0>;
+};
+
+&qupv3_1 {
+	iommus = <&apps_smmu 0x0098 0x0>;
+};
+
+&qupv3_2 {
+	iommus = <&apps_smmu 0x00BB 0x0>;
+};
+
+/ {
+	rename_devices: rename_devices {
+		compatible = "qcom,rename-devices";
+		rename_blk: rename_blk {
+			device-type = "block";
+			actual-dev = "vda", "vdb", "vdc",
+					"vdd", "vde", "vdf",
+					"vdg", "vdh", "vdi",
+					"vdj", "vdk", "vdl",
+					"vdm", "vdn", "vdo",
+					"vdp", "vdq";
+			rename-dev = "super", "userdata", "metadata",
+					"persist", "modem_a","bluetooth_a",
+					"misc", "vbmeta_a", "vbmeta_b",
+					"boot_a", "dtbo_a","dsp_a",
+					"modem_b", "bluetooth_b", "boot_b",
+					 "dtbo_b", "dsp_b";
+		};
+	};
+};
diff --git a/qcom/direwolf-vm-la.dtsi b/qcom/direwolf-vm-la.dtsi
index 23ba2342..d3558686 100755
--- a/qcom/direwolf-vm-la.dtsi
+++ b/qcom/direwolf-vm-la.dtsi
@@ -24,6 +24,50 @@
 	status = "okay";
 };
 
+&usb0 {
+	status = "okay";
+};
+
+&usb2_phy0 {
+	status = "okay";
+};
+
+&usb_qmp_dp_phy0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
+
+&usb2_phy1 {
+	status = "okay";
+};
+
+&usb_qmp_dp_phy1 {
+	status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+};
+
+&pcie2a_msi_snps {
+	status = "okay";
+};
+
+&pcie4 {
+	status = "okay";
+};
+
+&pcie4_msi_snps {
+	status = "okay";
+};
+
+&qupv3_se2_4uart {
+	status = "okay";
+};
+
 / {
 	rename_devices: rename_devices {
 		compatible = "qcom,rename-devices";
diff --git a/qcom/direwolf-vm-lv-headless-mt-overlay.dts b/qcom/direwolf-vm-lv-headless-mt-overlay.dts
new file mode 100755
index 00000000..06688de4
--- /dev/null
+++ b/qcom/direwolf-vm-lv-headless-mt-overlay.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+/plugin/;
+
+
+/ {
+	model = "Qualcomm Technologies, Inc. Direwolf Multi Headless LV Virtual Machine";
+	compatible = "qcom,direwolf", "qcom,quinvm";
+	qcom,board-id = <0 0x4000002>;
+};
diff --git a/qcom/direwolf-vm-lv-headless-mt.dts b/qcom/direwolf-vm-lv-headless-mt.dts
new file mode 100755
index 00000000..b42bf70a
--- /dev/null
+++ b/qcom/direwolf-vm-lv-headless-mt.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "direwolf-vm-headless.dtsi"
+#include "direwolf-vm-lv-headless-mt.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Direwolf Multi Headless LV Virtual Machine";
+	compatible = "qcom,direwolf", "qcom,quinvm";
+	qcom,board-id = <0 0x4000002>;
+};
diff --git a/qcom/direwolf-vm-lv-headless-mt.dtsi b/qcom/direwolf-vm-lv-headless-mt.dtsi
new file mode 100755
index 00000000..1bfe1071
--- /dev/null
+++ b/qcom/direwolf-vm-lv-headless-mt.dtsi
@@ -0,0 +1,14 @@
+&hab {
+	vmid = <6>;
+	/delete-node/ mmidgrp100;
+	/delete-node/ mmidgrp200;
+	/delete-node/ mmidgrp300;
+	/delete-node/ mmidgrp400;
+	/delete-node/ mmidgrp500;
+	/delete-node/ mmidgrp800;
+	/delete-node/ mmidgrp1000;
+	/delete-node/ mmidgrp1100;
+	/delete-node/ mmidgrp1200;
+	/delete-node/ mmidgrp1300;
+	/delete-node/ mmidgrp1500;
+};
diff --git a/qcom/direwolf-vm-lv-mt-overlay.dts b/qcom/direwolf-vm-lv-mt-overlay.dts
new file mode 100755
index 00000000..6c60451f
--- /dev/null
+++ b/qcom/direwolf-vm-lv-mt-overlay.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	model = "Qualcomm Technologies, Inc. Direwolf Multi LV Virtual Machine";
+	compatible = "qcom,direwolf", "qcom,quinvm";
+	qcom,msm-id = <460 0x10000>;
+	qcom,board-id = <0 0x2000002>;
+};
diff --git a/qcom/direwolf-vm-lv-mt.dts b/qcom/direwolf-vm-lv-mt.dts
new file mode 100755
index 00000000..152bd6ab
--- /dev/null
+++ b/qcom/direwolf-vm-lv-mt.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "direwolf-vm.dtsi"
+#include "direwolf-vm-lv-mt.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Direwolf Multi LV Virtual Machine";
+	compatible = "qcom,direwolf", "qcom,quinvm";
+	qcom,board-id = <0 0x2000002>;
+};
diff --git a/qcom/direwolf-vm-lv-mt.dtsi b/qcom/direwolf-vm-lv-mt.dtsi
new file mode 100755
index 00000000..695d83c7
--- /dev/null
+++ b/qcom/direwolf-vm-lv-mt.dtsi
@@ -0,0 +1,38 @@
+&hab {
+	vmid = <3>;
+};
+
+&usb1 {
+	status = "okay";
+};
+
+&usb2_phy1 {
+	status = "okay";
+};
+
+&usb_qmp_dp_phy1 {
+	status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+};
+
+&pcie2a_msi_snps {
+	status = "okay";
+};
+
+&qupv3_0 {
+	iommus = <&apps_smmu 0x56C 0x0>;
+	status = "disabled";
+};
+
+&qupv3_1 {
+	iommus = <&apps_smmu 0x8C 0x0>;
+	status = "disabled";
+};
+
+&qupv3_2 {
+	iommus = <&apps_smmu 0xAC 0x0>;
+	status = "disabled";
+};
diff --git a/qcom/direwolf-vm-lv-overlay.dts b/qcom/direwolf-vm-lv-overlay.dts
index e19fce27..324a0df2 100755
--- a/qcom/direwolf-vm-lv-overlay.dts
+++ b/qcom/direwolf-vm-lv-overlay.dts
@@ -5,5 +5,6 @@
 / {
 	model = "Qualcomm Technologies, Inc. Direwolf Single LV Virtual Machine";
 	compatible = "qcom,direwolf", "qcom,quinvm";
+	qcom,msm-id = <460 0x10000>;
 	qcom,board-id = <0 0x1000002>;
 };
diff --git a/qcom/direwolf-vm-lv.dtsi b/qcom/direwolf-vm-lv.dtsi
index 5d003425..b0061052 100755
--- a/qcom/direwolf-vm-lv.dtsi
+++ b/qcom/direwolf-vm-lv.dtsi
@@ -17,6 +17,10 @@
 	};
 };
 
+&system_cma {
+	size = <0x0 0x3c00000>;
+};
+
 &soc {
 	tlmm: pinctrl@f000000 {
 		compatible = "qcom,direwolf-pinctrl";
@@ -89,3 +93,15 @@
 &pcie4_msi_snps {
 	status = "okay";
 };
+
+&ufs2phy_mem {
+	status = "ok";
+};
+
+&ufshc2_mem {
+	status = "ok";
+};
+
+&qcom_rng_ee3 {
+	status = "okay";
+};
diff --git a/qcom/direwolf-vm-qupv3.dtsi b/qcom/direwolf-vm-qupv3.dtsi
new file mode 100755
index 00000000..48745e7b
--- /dev/null
+++ b/qcom/direwolf-vm-qupv3.dtsi
@@ -0,0 +1,176 @@
+&soc {
+	/* QUPv3 SE Instances
+	 * Qup0 0: SE 0
+	 * Qup0 1: SE 1
+	 * Qup0 2: SE 2
+	 * Qup0 3: SE 3
+	 * Qup0 4: SE 4
+	 * Qup0 5: SE 5
+	 * Qup0 6: SE 6
+	 * Qup0 7: SE 7
+	 * Qup1 0: SE 8
+	 * Qup1 1: SE 9
+	 * Qup1 2: SE 10
+	 * Qup1 3: SE 11
+	 * Qup1 4: SE 12
+	 * Qup1 5: SE 13
+	 * Qup1 6: SE 14
+	 * Qup1 7: SE 15
+	 * Qup2 0: SE 16
+	 * Qup2 1: SE 17
+	 * Qup2 2: SE 18
+	 * Qup2 3: SE 19
+	 * Qup2 4: SE 20
+	 * Qup2 5: SE 21
+	 * Qup2 6: SE 22
+	 * Qup2 7: SE 23
+	 */
+	/* QUPv3_0  wrapper  instance */
+	qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
+		compatible = "qcom,geni-se-qup";
+		reg = <0x9c0000 0x2000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		clock-names = "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		iommus = <&apps_smmu 0x563 0x0>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
+		qcom,iommu-geometry = <0x40000000 0x10000000>;
+		qcom,iommu-dma = "fastmap";
+		status = "ok";
+
+		qupv3_se1_i2c: i2c@984000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x984000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se1_i2c_active>;
+			pinctrl-1 = <&qupv3_se1_i2c_sleep>;
+			status = "disabled";
+		};
+
+		/* 4-wire HSUART Instance */
+		qupv3_se2_4uart: qcom,qup_uart@988000 {
+			compatible = "qcom,msm-geni-serial-hs";
+			reg = <0x988000 0x4000>;
+			reg-names = "se_phys";
+			interrupts-extended = <&intc GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
+							<&tlmm 124 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+			pinctrl-names = "default", "active", "sleep";
+			pinctrl-0 = <&qupv3_se2_default_cts>,
+						<&qupv3_se2_default_rtsrx>, <&qupv3_se2_default_tx>;
+			pinctrl-1 = <&qupv3_se2_ctsrx>, <&qupv3_se2_rts>,
+						<&qupv3_se2_tx>;
+			pinctrl-2 = <&qupv3_se2_ctsrx>, <&qupv3_se2_rts>,
+						<&qupv3_se2_tx>;
+			qcom,wakeup-byte = <0xFD>;
+			status = "disabled";
+		};
+
+		qupv3_se4_spi: spi@990000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x990000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se4_spi_active>;
+			pinctrl-1 = <&qupv3_se4_spi_sleep>;
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se6_4uart: qcom,qup_uart@998000 {
+			compatible = "qcom,msm-geni-serial-hs";
+			reg = <0x998000 0x4000>;
+			reg-names = "se_phys";
+			interrupts-extended = <&intc GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>,
+						<&tlmm 157 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+			pinctrl-names = "default", "active", "sleep";
+			pinctrl-0 = <&qupv3_se6_default_cts>,
+				<&qupv3_se6_default_rtsrx>, <&qupv3_se6_default_tx>;
+			pinctrl-1 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,
+				<&qupv3_se6_tx>;
+			pinctrl-2 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,
+				<&qupv3_se6_tx>;
+			qcom,wakeup-byte = <0xFD>;
+			status = "disabled";
+		};
+	};
+
+	/* QUPv3_1  wrapper  instance */
+	qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
+		compatible = "qcom,geni-se-qup";
+		reg = <0xac0000 0x2000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		clock-names = "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		iommus = <&apps_smmu 0x83 0x0>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
+		qcom,iommu-geometry = <0x40000000 0x10000000>;
+		qcom,iommu-dma = "fastmap";
+		status = "ok";
+
+		/* GNSS UART Instance */
+		qupv3_se13_2uart: qcom,qup_uart@a94000 {
+			compatible = "qcom,msm-geni-serial-hs";
+			reg = <0xa94000 0x4000>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+			pinctrl-names = "default", "active", "sleep";
+			pinctrl-0 = <&qupv3_se13_2uart_default>;
+			pinctrl-1 = <&qupv3_se13_2uart_active>;
+			pinctrl-2 = <&qupv3_se13_2uart_sleep>;
+			status = "disabled";
+		};
+	};
+
+	/* QUPv3_2  wrapper  instance */
+	qupv3_2: qcom,qupv3_2_geni_se@8c0000 {
+		compatible = "qcom,geni-se-qup";
+		reg = <0x8c0000 0x2000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		clock-names = "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		iommus = <&apps_smmu 0xa3  0x0>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
+		qcom,iommu-geometry = <0x40000000 0x10000000>;
+		qcom,iommu-dma = "fastmap";
+		status = "ok";
+
+		/* Debug UART Instance */
+		qupv3_se17_2uart: qcom,qup_uart@884000 {
+			compatible = "qcom,geni-debug-uart";
+			reg = <0x884000 0x4000>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se17_2uart_active>;
+			pinctrl-1 = <&qupv3_se17_2uart_sleep>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/qcom/direwolf-vm-ufs.dtsi b/qcom/direwolf-vm-ufs.dtsi
new file mode 100755
index 00000000..254b1b6c
--- /dev/null
+++ b/qcom/direwolf-vm-ufs.dtsi
@@ -0,0 +1,182 @@
+&regulator {
+	L8G0: pm8540_g0_l8: regulator-pm8540_g0-l8 {
+		regulator-name = "ldog8";
+		regulator-min-microvolt = <825000>;
+		regulator-max-microvolt = <925000>;
+	};
+
+	L3G0: pm8540_g0_l3: regulator-pm8540_g0-l3 {
+		regulator-name = "ldog3";
+		regulator-min-microvolt = <1130000>;
+		regulator-max-microvolt = <1260000>;
+	};
+
+	gcc_ufs_card_gdsc: gcc_ufs_card_gdsc {
+		regulator-name = "gcc_ufs_card_gdsc";
+	};
+
+	L10C0: pm8540_c0_l10: regulator-pm8540_c0-l10 {
+		regulator-name = "ldoc10";
+		regulator-min-microvolt = <2400000>;
+		regulator-max-microvolt = <2960000>;
+		qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+	};
+
+	L3C0: pm8540_c0_l3: regulator-pm8540_c0-l3 {
+		regulator-name = "ldoc3";
+		regulator-min-microvolt = <1080000>;
+		regulator-max-microvolt = <1304000>;
+		qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+	};
+};
+
+&soc {
+	ufs2phy_mem: ufsphy_mem@1da7000 {
+		compatible = "qcom,ufs-phy-qmp-v4-direwolf";
+
+		reg = <0x1da7000 0xe10>;
+		reg-names = "phy_mem";
+		#phy-cells = <0>;
+
+		lanes-per-direction = <2>;
+
+		vdda-phy-supply = <&L8G0>;
+		vdda-pll-supply = <&L3G0>;
+		vdda-phy-max-microamp = <85700>;
+		vdda-pll-max-microamp = <18300>;
+
+		clock-names = "ref_clk_src",
+			"ref_clk",
+			"ref_aux_clk",
+			"ref_clk_parent";
+		clocks = <&dummycc RPMH_CXO_CLK>,
+			<&gcc GCC_UFS_1_CARD_CLKREF_CLK>,
+			<&gcc GCC_UFS_CARD_PHY_AUX_CLK>,
+			<&gcc GCC_UFS_REF_CLKREF_CLK>;
+		resets = <&ufshc2_mem 0>;
+		status = "disabled";
+	};
+
+	ufshc2_mem: ufshc@1da4000 {
+		compatible = "qcom,ufshc";
+		reg = <0x1da4000 0x3000>;
+		reg-names = "ufs_mem";
+		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+		phys = <&ufs2phy_mem>;
+		phy-names = "ufsphy";
+		#reset-cells = <1>;
+
+		lanes-per-direction = <2>;
+		dev-ref-clk-freq = <0>; /* 19.2 MHz */
+
+		vdd-hba-supply = <&gcc_ufs_card_gdsc>;
+		vdd-hba-fixed-regulator;
+
+		vcc-supply = <&L10C0>;
+		vcc-voltage-level = <2504000 2504000>;
+		vcc-max-microamp = <800000>;
+
+		vccq-supply = <&L3C0>;
+		vccq-max-microamp = <750000>;
+
+		qcom,vddp-ref-clk-supply = <&L3C0>;
+		qcom,vddp-ref-clk-max-microamp = <100>;
+		clock-names =
+			"core_clk",
+			"bus_aggr_clk",
+			"iface_clk",
+			"core_clk_unipro",
+			"core_clk_ice",
+			"ref_clk",
+			"tx_lane0_sync_clk",
+			"rx_lane0_sync_clk",
+			"rx_lane1_sync_clk";
+		clocks =
+			<&gcc GCC_UFS_CARD_AXI_CLK>,
+			<&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
+			<&gcc GCC_UFS_CARD_AHB_CLK>,
+			<&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
+			<&gcc GCC_UFS_CARD_ICE_CORE_CLK>,
+			<&dummycc RPMH_CXO_CLK>,
+			<&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
+			<&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
+			<&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
+		freq-table-hz =
+			<75000000 300000000>,
+			<0 0>,
+			<0 0>,
+			<75000000 300000000>,
+			<75000000 300000000>,
+			<0 0>,
+			<0 0>,
+			<0 0>,
+			<0 0>;
+
+		qcom,ufs-bus-bw,name = "ufshc_mem";
+		qcom,ufs-bus-bw,num-cases = <26>;
+		qcom,ufs-bus-bw,num-paths = <2>;
+		qcom,ufs-bus-bw,vectors-KBps =
+		/*
+		 * During HS G3 UFS runs at nominal voltage corner, vote
+		 * higher bandwidth to push other buses in the data path
+		 * to run at nominal to achieve max throughput.
+		 * 4GBps pushes BIMC to run at nominal.
+		 * 200MBps pushes CNOC to run at nominal.
+		 * Vote for half of this bandwidth for HS G3 1-lane.
+		 * For max bandwidth, vote high enough to push the buses
+		 * to run in turbo voltage corner.
+		 */
+		<0 0>, <0 0>,          /* No vote */
+		<922 0>, <1000 0>,     /* PWM G1 */
+		<1844 0>, <1000 0>,    /* PWM G2 */
+		<3688 0>, <1000 0>,    /* PWM G3 */
+		<7376 0>, <1000 0>,    /* PWM G4 */
+		<1844 0>, <1000 0>,    /* PWM G1 L2 */
+		<3688 0>, <1000 0>,    /* PWM G2 L2 */
+		<7376 0>, <1000 0>,    /* PWM G3 L2 */
+		<14752 0>, <1000 0>,   /* PWM G4 L2 */
+		<127796 0>, <1000 0>,  /* HS G1 RA */
+		<255591 0>, <1000 0>,  /* HS G2 RA */
+		<1492582 0>, <102400 0>,  /* HS G3 RA */
+		<2915200 0>, <204800 0>,  /* HS G4 RA */
+		<255591 0>, <1000 0>,  /* HS G1 RA L2 */
+		<511181 0>, <1000 0>,  /* HS G2 RA L2 */
+		<1492582 0>, <204800 0>, /* HS G3 RA L2 */
+		<2915200 0>, <409600 0>, /* HS G4 RA L2 */
+		<149422 0>, <1000 0>,  /* HS G1 RB */
+		<298189 0>, <1000 0>,  /* HS G2 RB */
+		<1492582 0>, <102400 0>,  /* HS G3 RB */
+		<2915200 0>, <204800 0>,  /* HS G4 RB */
+		<298189 0>, <1000 0>,  /* HS G1 RB L2 */
+		<596378 0>, <1000 0>,  /* HS G2 RB L2 */
+		/* As UFS working in HS G3 RB L2 mode, aggregated
+		 * bandwidth (AB) should take care of providing
+		 * optimum throughput requested. However, as tested,
+		 * in order to scale up CNOC clock, instantaneous
+		 * bindwidth (IB) needs to be given a proper value too.
+		 */
+		<1492582 0>, <204800 409600>, /* HS G3 RB L2 KBPs */
+		<2915200 0>, <409600 409600>, /* HS G4 RB L2 */
+		<7643136 0>, <307200 0>; /* Max. bandwidth */
+
+		qcom,bus-vector-names = "MIN",
+		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
+		"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
+		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
+		"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
+		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
+		"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
+		"MAX";
+
+		reset-gpios = <&tlmm 229 GPIO_ACTIVE_LOW>;
+
+		resets = <&gcc GCC_UFS_CARD_BCR>;
+		reset-names = "rst";
+
+		iommus = <&apps_smmu 0x4a0 0x0>;
+		qcom,iommu-dma = "fastmap";
+		dma-coherent;
+
+		status = "disabled";
+	};
+};
diff --git a/qcom/direwolf-vm.dtsi b/qcom/direwolf-vm.dtsi
index a38f885d..0a978442 100755
--- a/qcom/direwolf-vm.dtsi
+++ b/qcom/direwolf-vm.dtsi
@@ -1,12 +1,12 @@
 #include <dt-bindings/clock/qcom,gcc-direwolf.h>
 #include "quin-vm-common.dtsi"
-
 / {
 	model = "Qualcomm Technologies, Inc. Direwolf Virtual Machine";
 	qcom,msm-name = "SA_DIREWOLF_IVI";
 	qcom,msm-id = <460 0x10000>;
 
 	aliases {
+		ufshc2 = &ufshc2_mem;
 		hsuart0 = &qupv3_se2_4uart;
 		pci-domain0 = &pcie0; /* PCIe0 domain */
 		pci-domain1 = &pcie1; /* PCIe1 domain */
@@ -14,6 +14,141 @@
 		pci-domain3 = &pcie3; /* PCIe3 domain */
 		pci-domain4 = &pcie4; /* PCIe4 domain */
 	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cluster_0_opp_table: opp-table0 {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			opp-2592000000 {
+				opp-hz = /bits/ 64 <2592000000>;
+				opp-microvolt = <952000>;
+			};
+		};
+
+		cluster_1_opp_table: opp-table1 {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			opp-2246400000 {
+				opp-hz = /bits/ 64 <2246400000>;
+				opp-microvolt = <952000>;
+			};
+		};
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x0>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			operating-points-v2 = <&cluster_0_opp_table>;
+		};
+
+		CPU1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x1>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			operating-points-v2 = <&cluster_0_opp_table>;
+		};
+
+		CPU2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x2>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			operating-points-v2 = <&cluster_0_opp_table>;
+		};
+
+		CPU3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x3>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			operating-points-v2 = <&cluster_0_opp_table>;
+		};
+
+		CPU4: cpu@4 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x4>;
+			capacity-dmips-mhz = <943>;
+			dynamic-power-coefficient = <100>;
+			operating-points-v2 = <&cluster_1_opp_table>;
+		};
+
+		CPU5: cpu@5 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x5>;
+			capacity-dmips-mhz = <943>;
+			dynamic-power-coefficient = <100>;
+			operating-points-v2 = <&cluster_1_opp_table>;
+		};
+
+		CPU6: cpu@6 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x6>;
+			capacity-dmips-mhz = <943>;
+			dynamic-power-coefficient = <100>;
+			operating-points-v2 = <&cluster_1_opp_table>;
+		};
+
+		CPU7: cpu@7 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x7>;
+			capacity-dmips-mhz = <943>;
+			dynamic-power-coefficient = <100>;
+			operating-points-v2 = <&cluster_1_opp_table>;
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+
+				core1 {
+					cpu = <&CPU1>;
+				};
+
+				core2 {
+					cpu = <&CPU2>;
+				};
+
+				core3 {
+					cpu = <&CPU3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&CPU4>;
+				};
+
+				core1 {
+					cpu = <&CPU5>;
+				};
+
+				core2 {
+					cpu = <&CPU6>;
+				};
+
+				core3 {
+					cpu = <&CPU7>;
+				};
+			};
+		};
+	};
 };
 
 &firmware {
@@ -23,6 +158,34 @@
 };
 
 &soc {
+	/* Rome 3.3V supply */
+	vreg_wlan: vreg_wlan {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "vreg_wlan";
+	};
+
+	/* PWR_CTR2_VDD_1P8 supply */
+	vreg_conn_1p8: vreg_conn_1p8 {
+		compatible = "regulator-fixed";
+		regulator-name = "vreg_conn_1p8";
+		pinctrl-names = "default";
+		pinctrl-0 = <&conn_power_1p8_active>;
+		startup-delay-us = <4000>;
+		enable-active-high;
+		gpio = <&tlmm 128 0>;
+	};
+
+	/* PWR_CTR1_VDD_PA supply */
+	vreg_conn_pa: vreg_conn_pa {
+		compatible = "regulator-fixed";
+		regulator-name = "vreg_conn_pa";
+		pinctrl-names = "default";
+		pinctrl-0 = <&conn_power_pa_active>;
+		startup-delay-us = <4000>;
+		enable-active-high;
+		gpio = <&tlmm 129 0>;
+	};
+
 	apps_smmu: apps-smmu@15000000 {
 		compatible = "qcom,qsmmu-v500";
 		reg = <0x15000000 0x100000>,
@@ -310,26 +473,15 @@
 		#clock-cells = <0>;
 	};
 
-	/* PWR_CTR2_VDD_1P8 supply */
-	vreg_conn_1p8: vreg_conn_1p8 {
+	/* PWR_CTR1_VDD_PA supply for wlan2 */
+	vreg_conn_pa2: vreg_conn_pa2 {
 		compatible = "regulator-fixed";
-		regulator-name = "vreg_conn_1p8";
+		regulator-name = "vreg_conn_pa2";
 		pinctrl-names = "default";
-		pinctrl-0 = <&conn_power_1p8_active>;
+		pinctrl-0 = <&conn_power_pa_active2>;
 		startup-delay-us = <4000>;
 		enable-active-high;
-		gpio = <&tlmm 128 0>;
-	};
-
-	/* PWR_CTR1_VDD_PA supply */
-	vreg_conn_pa: vreg_conn_pa {
-		compatible = "regulator-fixed";
-		regulator-name = "vreg_conn_pa";
-		pinctrl-names = "default";
-		pinctrl-0 = <&conn_power_pa_active>;
-		startup-delay-us = <4000>;
-		enable-active-high;
-		gpio = <&tlmm 129 0>;
+		gpio = <&tlmm 216 0>;
 	};
 };
 
@@ -442,6 +594,11 @@
 };
 
 &soc {
+	virt_smmuv3: qcom,virt-smmuv3 {
+		#iommu-cells = <1>;
+		compatible = "arm,virt-smmu-v3";
+	};
+
 	tcsr_compute_signal_glb: syscon@0x1fd8000 {
 		compatible = "syscon";
 		reg = <0x1fd8000 0x1000>;
@@ -506,9 +663,9 @@
 #include "pm8540-vm.dtsi"
 #include "direwolf-pinctrl.dtsi"
 #include "direwolf-vm-pcie.dtsi"
-#include "direwolf-qupv3.dtsi"
+#include "direwolf-vm-qupv3.dtsi"
 #include "direwolf-vm-usb.dtsi"
-
+#include "direwolf-vm-ufs.dtsi"
 &qupv3_0 {
 	qcom,iommu-dma = "bypass";
 };
diff --git a/qcom/kalama-coresight.dtsi b/qcom/kalama-coresight.dtsi
index 7c7abc95..f7661b42 100755
--- a/qcom/kalama-coresight.dtsi
+++ b/qcom/kalama-coresight.dtsi
@@ -4086,6 +4086,12 @@
 
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
+
+		trig-conns {
+			cpu = <&CPU0>;
+			arm,trig-in-sigs = <0 1 2 3 4 5 6 7 8 9>;
+			arm,trig-out-sigs = <0 1 2 3 4 5 6 7 8 9>;
+		};
 	};
 
 	spss_cti: cti@10881000 {
@@ -4110,6 +4116,12 @@
 
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
+
+		trig-conns {
+			cpu = <&CPU1>;
+			arm,trig-in-sigs = <0 1 2 3 4 5 6 7 8 9>;
+			arm,trig-out-sigs = <0 1 2 3 4 5 6 7 8 9>;
+		};
 	};
 
 	cpu2: cti@12030000 {
@@ -4121,6 +4133,12 @@
 
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
+
+		trig-conns {
+			cpu = <&CPU2>;
+			arm,trig-in-sigs = <0 1 2 3 4 5 6 7 8 9>;
+			arm,trig-out-sigs = <0 1 2 3 4 5 6 7 8 9>;
+		};
 	};
 
 	cpu3: cti@12040000 {
@@ -4132,6 +4150,12 @@
 
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
+
+		trig-conns {
+			cpu = <&CPU3>;
+			arm,trig-in-sigs = <0 1 2 3 4 5 6 7 8 9>;
+			arm,trig-out-sigs = <0 1 2 3 4 5 6 7 8 9>;
+		};
 	};
 
 	cpu4: cti@12050000 {
@@ -4143,6 +4167,12 @@
 
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
+
+		trig-conns {
+			cpu = <&CPU4>;
+			arm,trig-in-sigs = <0 1 2 3 4 5 6 7 8 9>;
+			arm,trig-out-sigs = <0 1 2 3 4 5 6 7 8 9>;
+		};
 	};
 
 	cpu5: cti@112060000 {
@@ -4154,6 +4184,12 @@
 
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
+
+		trig-conns {
+			cpu = <&CPU5>;
+			arm,trig-in-sigs = <0 1 2 3 4 5 6 7 8 9>;
+			arm,trig-out-sigs = <0 1 2 3 4 5 6 7 8 9>;
+		};
 	};
 
 	cpu6: cti@12070000 {
@@ -4165,6 +4201,12 @@
 
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
+
+		trig-conns {
+			cpu = <&CPU6>;
+			arm,trig-in-sigs = <0 1 2 3 4 5 6 7 8 9>;
+			arm,trig-out-sigs = <0 1 2 3 4 5 6 7 8 9>;
+		};
 	};
 
 	cpu7: cti@12080000 {
@@ -4176,6 +4218,12 @@
 
 		clocks = <&aoss_qmp>;
 		clock-names = "apb_pclk";
+
+		trig-conns {
+			cpu = <&CPU7>;
+			arm,trig-in-sigs = <0 1 2 3 4 5 6 7 8 9>;
+			arm,trig-out-sigs = <0 1 2 3 4 5 6 7 8 9>;
+		};
 	};
 
 	ipcb_tgu: tgu@10b0e000 {
diff --git a/qcom/kalama-eva.dtsi b/qcom/kalama-eva.dtsi
deleted file mode 100755
index 15eb44ff..00000000
--- a/qcom/kalama-eva.dtsi
+++ /dev/null
@@ -1,110 +0,0 @@
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/soc/qcom,ipcc.h>
-#include <dt-bindings/interconnect/qcom,kalama.h>
-#include <dt-bindings/clock/qcom,videocc-kalama.h>
-
-&soc {
-	msm_cvp: qcom,cvp@ab00000 {
-		compatible = "qcom,msm-cvp", "qcom,kalama-cvp";
-		status = "ok";
-		reg = <0xab00000 0x100000>;
-		interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
-
-		/* LLCC Cache */
-		cache-slice-names = "cvp";
-
-		/* Supply */
-		cvp-supply = <&video_cc_mvs1c_gdsc>;
-		cvp-core-supply = <&video_cc_mvs1_gdsc>;
-
-		/* Clocks */
-		clock-names = "gcc_video_axi1", "cvp_clk", "core_clk",
-				"video_cc_mvs1_clk_src";
-		clock-ids = <GCC_VIDEO_AXI1_CLK VIDEO_CC_MVS1C_CLK
-			VIDEO_CC_MVS1_CLK VIDEO_CC_MVS1_CLK_SRC>;
-		clocks = <&gcc GCC_VIDEO_AXI1_CLK>,
-			<&videocc VIDEO_CC_MVS1C_CLK>,
-			<&videocc VIDEO_CC_MVS1_CLK>,
-			<&videocc VIDEO_CC_MVS1_CLK_SRC>;
-		qcom,proxy-clock-names = "gcc_video_axi1",
-			"cvp_clk", "core_clk", "video_cc_mvs1_clk_src";
-
-		qcom,clock-configs = <0x0 0x0 0x0 0x1>;
-		qcom,allowed-clock-rates = <350000000 450000000 500000000 550000000>;
-
-		resets = <&gcc GCC_VIDEO_AXI1_CLK_ARES>,
-			<&videocc VIDEO_CC_MVS1C_CLK_ARES>;
-		reset-names = "cvp_axi_reset", "cvp_core_reset";
-		reset-power-status = <0x2 0x2>;
-
-		qcom,reg-presets = <0xB0088 0x0>;
-		qcom,ipcc-reg = <0x400000 0x100000>;
-		qcom,gcc-reg = <0x110000 0x40000>;
-
-		pas-id = <26>;
-		memory-region = <&cvp_mem>;
-
-		/* CVP Firmware ELF image name */
-		cvp,firmware-name = "evass";
-
-		/* Buses */
-		cvp_cnoc {
-			compatible = "qcom,msm-cvp,bus";
-			label = "cvp-cnoc";
-			qcom,bus-master = <MASTER_APPSS_PROC>;
-			qcom,bus-slave = <SLAVE_VENUS_CFG>;
-			qcom,bus-governor = "performance";
-			qcom,bus-range-kbps = <1000 1000>;
-		};
-
-		cvp_bus_ddr {
-			compatible = "qcom,msm-cvp,bus";
-			label = "cvp-ddr";
-			qcom,bus-master = <MASTER_VIDEO_PROC>;
-			qcom,bus-slave = <SLAVE_EBI1>;
-			qcom,bus-governor = "performance";
-			qcom,bus-range-kbps = <1000 6533000>;
-		};
-
-		/* MMUs */
-		cvp_non_secure_cb {
-			compatible = "qcom,msm-cvp,context-bank";
-			label = "cvp_hlos";
-			iommus =
-				<&apps_smmu 0x1920 0x0000>;
-			buffer-types = <0xfff>;
-			dma-coherent;
-			qcom,iommu-faults = "non-fatal";
-			qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>;
-		};
-
-
-		cvp_secure_nonpixel_cb {
-			compatible = "qcom,msm-cvp,context-bank";
-			label = "cvp_sec_nonpixel";
-			iommus =
-				<&apps_smmu 0x1924 0x0000>;
-			buffer-types = <0x741>;
-			qcom,iommu-faults = "non-fatal";
-			qcom,iommu-dma-addr-pool = <0x01000000 0x25800000>;
-			qcom,iommu-vmid = <0xB>;
-		};
-
-		cvp_secure_pixel_cb {
-			compatible = "qcom,msm-cvp,context-bank";
-			label = "cvp_sec_pixel";
-			iommus =
-				<&apps_smmu 0x1923 0x0000>;
-			buffer-types = <0x106>;
-			qcom,iommu-faults = "non-fatal";
-			qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>;
-			qcom,iommu-vmid = <0xA>;
-		};
-
-		/* Memory Heaps */
-		qcom,msm-cvp,mem_cdsp {
-			compatible = "qcom,msm-cvp,mem-cdsp";
-			memory-region = <&cdsp_eva_mem>;
-		};
-	};
-};
diff --git a/qcom/kalama-gdsc.dtsi b/qcom/kalama-gdsc.dtsi
new file mode 100755
index 00000000..7080ef47
--- /dev/null
+++ b/qcom/kalama-gdsc.dtsi
@@ -0,0 +1,322 @@
+&soc {
+	/* CAM_CC GDSCs */
+	cam_cc_camss_top_gdsc: qcom,gdsc@add5004 {
+		compatible = "qcom,gdsc";
+		reg = <0xadd5004 0x4>;
+		regulator-name = "cam_cc_camss_top_gdsc";
+		qcom,retain-regs;
+		status = "disabled";
+	};
+
+	cam_cc_bps_gdsc: qcom,gdsc@adf0004 {
+		compatible = "qcom,gdsc";
+		reg = <0xadf0004 0x4>;
+		regulator-name = "cam_cc_bps_gdsc";
+		qcom,gds-timeout = <1500>;
+		qcom,support-hw-trigger;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	cam_cc_ife_0_gdsc: qcom,gdsc@adf1004 {
+		compatible = "qcom,gdsc";
+		reg = <0xadf1004 0x4>;
+		regulator-name = "cam_cc_ife_0_gdsc";
+		qcom,gds-timeout = <1500>;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	cam_cc_ife_1_gdsc: qcom,gdsc@adf2004 {
+		compatible = "qcom,gdsc";
+		reg = <0xadf2004 0x4>;
+		regulator-name = "cam_cc_ife_1_gdsc";
+		qcom,gds-timeout = <1500>;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	cam_cc_ife_2_gdsc: qcom,gdsc@adf2294 {
+		compatible = "qcom,gdsc";
+		reg = <0xadf2294 0x4>;
+		regulator-name = "cam_cc_ife_2_gdsc";
+		qcom,gds-timeout = <1500>;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	cam_cc_ipe_0_gdsc: qcom,gdsc@adf03b8 {
+		compatible = "qcom,gdsc";
+		reg = <0xadf03b8 0x4>;
+		regulator-name = "cam_cc_ipe_0_gdsc";
+		qcom,gds-timeout = <1500>;
+		qcom,support-hw-trigger;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	cam_cc_sbi_gdsc: qcom,gdsc@adf052c {
+		compatible = "qcom,gdsc";
+		reg = <0xadf052c 0x4>;
+		regulator-name = "cam_cc_sbi_gdsc";
+		qcom,gds-timeout = <1500>;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	cam_cc_sfe_0_gdsc: qcom,gdsc@adf3280 {
+		compatible = "qcom,gdsc";
+		reg = <0xadf3280 0x4>;
+		regulator-name = "cam_cc_sfe_0_gdsc";
+		qcom,gds-timeout = <1500>;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	cam_cc_sfe_1_gdsc: qcom,gdsc@adf33e0 {
+		compatible = "qcom,gdsc";
+		reg = <0xadf33e0 0x4>;
+		regulator-name = "cam_cc_sfe_1_gdsc";
+		qcom,gds-timeout = <1500>;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	cam_cc_titan_top_gdsc: qcom,gdsc@adf4058 {
+		compatible = "qcom,gdsc";
+		reg = <0xadf4058 0x4>;
+		regulator-name = "cam_cc_titan_top_gdsc";
+		proxy-supply = <&cam_cc_titan_top_gdsc>;
+		qcom,gds-timeout = <1500>;
+		qcom,proxy-consumer-enable;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	/* DISP_CC GDSCs */
+	disp_cc_mdss_core_gdsc: qcom,gdsc@af09000 {
+		compatible = "qcom,gdsc";
+		reg = <0xaf09000 0x4>;
+		regulator-name = "disp_cc_mdss_core_gdsc";
+		proxy-supply = <&disp_cc_mdss_core_gdsc>;
+		qcom,gds-timeout = <1500>;
+		qcom,proxy-consumer-enable;
+		qcom,support-hw-trigger;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	disp_cc_mdss_core_int2_gdsc: qcom,gdsc@af0b000 {
+		compatible = "qcom,gdsc";
+		reg = <0xaf0b000 0x4>;
+		regulator-name = "disp_cc_mdss_core_int2_gdsc";
+		qcom,gds-timeout = <1500>;
+		qcom,support-hw-trigger;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	gcc_apcs_gdsc_vote_ctrl: syscon@152020 {
+		compatible = "syscon";
+		reg = <0x152020 0x4>;
+	};
+
+	/* GCC GDSCs */
+	gcc_pcie_0_gdsc: qcom,gdsc@16b004 {
+		compatible = "qcom,gdsc";
+		reg = <0x16b004 0x4>;
+		regulator-name = "gcc_pcie_0_gdsc";
+		qcom,gds-timeout = <1500>;
+		qcom,retain-regs;
+		qcom,no-status-check-on-disable;
+		qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 0>;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	gcc_pcie_0_phy_gdsc: qcom,gdsc@16c000 {
+		compatible = "qcom,gdsc";
+		reg = <0x16c000 0x4>;
+		regulator-name = "gcc_pcie_0_phy_gdsc";
+		qcom,gds-timeout = <1500>;
+		qcom,retain-regs;
+		qcom,no-status-check-on-disable;
+		qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 3>;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	gcc_pcie_1_gdsc: qcom,gdsc@18d004 {
+		compatible = "qcom,gdsc";
+		reg = <0x18d004 0x4>;
+		regulator-name = "gcc_pcie_1_gdsc";
+		qcom,gds-timeout = <1500>;
+		qcom,retain-regs;
+		qcom,no-status-check-on-disable;
+		qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 1>;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	gcc_pcie_1_phy_gdsc: qcom,gdsc@18e000 {
+		compatible = "qcom,gdsc";
+		reg = <0x18e000 0x4>;
+		regulator-name = "gcc_pcie_1_phy_gdsc";
+		qcom,gds-timeout = <1500>;
+		qcom,retain-regs;
+		qcom,no-status-check-on-disable;
+		qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 4>;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	gcc_ufs_mem_phy_gdsc: qcom,gdsc@19e000 {
+		compatible = "qcom,gdsc";
+		reg = <0x19e000 0x4>;
+		regulator-name = "gcc_ufs_mem_phy_gdsc";
+		qcom,gds-timeout = <1500>;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	gcc_ufs_phy_gdsc: qcom,gdsc@177004 {
+		compatible = "qcom,gdsc";
+		reg = <0x177004 0x4>;
+		regulator-name = "gcc_ufs_phy_gdsc";
+		proxy-supply = <&gcc_ufs_phy_gdsc>;
+		qcom,gds-timeout = <1500>;
+		qcom,proxy-consumer-enable;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	gcc_usb30_prim_gdsc: qcom,gdsc@139004 {
+		compatible = "qcom,gdsc";
+		reg = <0x139004 0x4>;
+		proxy-supply = <&gcc_usb30_prim_gdsc>;
+		qcom,gds-timeout = <1500>;
+		qcom,proxy-consumer-enable;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	gcc_usb3_phy_gdsc: qcom,gdsc@150018 {
+		compatible = "qcom,gdsc";
+		reg = <0x150018 0x4>;
+		qcom,gds-timeout = <1500>;
+		qcom,proxy-consumer-enable;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	/* GPU_CC GDSCs */
+	gpu_cc_cx_gdsc_hw_ctrl: syscon@3d9953c {
+		compatible = "syscon";
+		reg = <0x3d9953c 0x4>;
+	};
+
+	gpu_cc_cx_gdsc: qcom,gdsc@3d99108 {
+		compatible = "qcom,gdsc";
+		reg = <0x3d99108 0x4>;
+		regulator-name = "gpu_cc_cx_gdsc";
+		hw-ctrl-addr = <&gpu_cc_cx_gdsc_hw_ctrl>;
+		qcom,no-status-check-on-disable;
+		qcom,clk-dis-wait-val = <8>;
+		qcom,gds-timeout = <1500>;
+		qcom,retain-regs;
+		status = "disabled";
+	};
+
+	gpu_cc_gx_domain_addr: syscon@3d99504 {
+		compatible = "syscon";
+		reg = <0x3d99504 0x4>;
+	};
+
+	gpu_cc_gx_sw_reset: syscon@3d99058 {
+		compatible = "syscon";
+		reg = <0x3d99058 0x4>;
+	};
+
+	gpu_cc_gx_acd_reset: syscon@3d99358 {
+		compatible = "syscon";
+		reg = <0x3d99358 0x4>;
+	};
+
+	gpu_cc_gx_acd_iroot_reset: syscon@3d9958c {
+		compatible = "syscon";
+		reg = <0x3d9958c 0x4>;
+	};
+
+	gpu_cc_gx_gdsc: qcom,gdsc@3d9905c {
+		compatible = "qcom,gdsc";
+		reg = <0x3d9905c 0x4>;
+		regulator-name = "gpu_cc_gx_gdsc";
+		domain-addr = <&gpu_cc_gx_domain_addr>;
+		sw-reset = <&gpu_cc_gx_sw_reset>,
+			   <&gpu_cc_gx_acd_reset>,
+			   <&gpu_cc_gx_acd_iroot_reset>;
+		qcom,reset-aon-logic;
+		qcom,gds-timeout = <1500>;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	/* VIDEO_CC GDSCs */
+	video_cc_mvs0_gdsc: qcom,gdsc@abf80a4 {
+		compatible = "qcom,gdsc";
+		reg = <0xabf80a4 0x4>;
+		regulator-name = "video_cc_mvs0_gdsc";
+		qcom,gds-timeout = <1500>;
+		qcom,support-hw-trigger;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	video_cc_mvs0c_gdsc: qcom,gdsc@abf804c {
+		compatible = "qcom,gdsc";
+		reg = <0xabf804c 0x4>;
+		regulator-name = "video_cc_mvs0c_gdsc";
+		qcom,gds-timeout = <1500>;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	video_cc_mvs1_gdsc: qcom,gdsc@abf80cc {
+		compatible = "qcom,gdsc";
+		reg = <0xabf80cc 0x4>;
+		regulator-name = "video_cc_mvs1_gdsc";
+		qcom,gds-timeout = <1500>;
+		qcom,support-hw-trigger;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+
+	video_cc_mvs1c_gdsc: qcom,gdsc@abf8078 {
+		compatible = "qcom,gdsc";
+		reg = <0xabf8078 0x4>;
+		regulator-name = "video_cc_mvs1c_gdsc";
+		qcom,gds-timeout = <1500>;
+		qcom,retain-regs;
+		qcom,support-cfg-gdscr;
+		status = "disabled";
+	};
+};
diff --git a/qcom/kalama-pcie.dtsi b/qcom/kalama-pcie.dtsi
index b000b559..8c37f1e1 100755
--- a/qcom/kalama-pcie.dtsi
+++ b/qcom/kalama-pcie.dtsi
@@ -115,6 +115,7 @@
 		qcom,slv-addr-space-size = <0x4000000>;
 		qcom,ep-latency = <10>;
 		qcom,num-parf-testbus-sel = <0xb9>;
+		qcom,config-recovery;
 
 		qcom,pcie-phy-ver = <101>;
 		qcom,phy-status-offset = <0x214>;
diff --git a/qcom/kalama-pinn.dtsi b/qcom/kalama-pinn.dtsi
index 7473d300..dd8dc479 100755
--- a/qcom/kalama-pinn.dtsi
+++ b/qcom/kalama-pinn.dtsi
@@ -205,6 +205,10 @@
 	#address-cells = <5>;
 	#size-cells = <0>;
 
+	cnss_pci1 {
+		reg = <0x100 0x0 0x0 0x0 0x0>;
+	};
+
 	mhi0: qcom,mhi@0 {
 		reg = <0 0 0 0 0 >;
 
diff --git a/qcom/kalama-qcm.dtsi b/qcom/kalama-qcm.dtsi
index 701f84a5..ba45e497 100755
--- a/qcom/kalama-qcm.dtsi
+++ b/qcom/kalama-qcm.dtsi
@@ -5,3 +5,27 @@
 	compatible = "qcom,kalama";
 	qcom,msm-id = <604 0x20000>;
 };
+
+&video_mem {
+	reg = <0x0 0x9bb00000 0x0 0x1000000>;
+};
+
+&cvp_mem {
+	reg = <0x0 0x9cb00000 0x0 0x700000>;
+};
+
+&cdsp_mem {
+	reg = <0x0 0x9d200000 0x0 0x2000000>;
+};
+
+&q6_cdsp_dtb_mem {
+	reg = <0x0 0x9f200000 0x0 0x80000>;
+};
+
+&q6_adsp_dtb_mem {
+	reg = <0x0 0x9f280000 0x0 0x80000>;
+};
+
+&adspslpi_mem {
+	reg = <0x0 0x9f300000 0x0 0x4080000>;
+};
diff --git a/qcom/kalama-qrd.dtsi b/qcom/kalama-qrd.dtsi
index 97bf468f..73b93563 100755
--- a/qcom/kalama-qrd.dtsi
+++ b/qcom/kalama-qrd.dtsi
@@ -1,6 +1,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/clock/qcom,gcc-kalama.h>
+#include <dt-bindings/phy/qcom,usb3-4nm-qmp-combo.h>
 
 #include "kalama-pmic-overlay.dtsi"
 #include "kalama-thermal-overlay.dtsi"
@@ -88,6 +89,60 @@
 		qcom,wf-vmax-mv = <1800>;
 		qcom,wf-pattern-period-us = <5880>;
 	};
+
+	primitive_0 {
+		/* NOOP */
+		qcom,wf-vmax-mv = <2400>;
+		qcom,wf-pattern-period-us = <5880>;
+	};
+
+	primitive_1 {
+		/* CLICK */
+		qcom,wf-vmax-mv = <2400>;
+		qcom,wf-pattern-period-us = <5880>;
+	};
+
+	primitive_2 {
+		/* THUD */
+		qcom,wf-vmax-mv = <2400>;
+		qcom,wf-pattern-period-us = <5880>;
+	};
+
+	primitive_3 {
+		/* SPIN */
+		qcom,wf-vmax-mv = <2400>;
+		qcom,wf-pattern-period-us = <5880>;
+	};
+
+	primitive_4 {
+		/* QUICK_RISE */
+		qcom,wf-vmax-mv = <2400>;
+		qcom,wf-pattern-period-us = <5880>;
+	};
+
+	primitive_5 {
+		/* SLOW_RISE */
+		qcom,wf-vmax-mv = <2400>;
+		qcom,wf-pattern-period-us = <5880>;
+	};
+
+	primitive_6 {
+		/* QUICK_FALL */
+		qcom,wf-vmax-mv = <2400>;
+		qcom,wf-pattern-period-us = <5880>;
+	};
+
+	primitive_7 {
+		/* LIGHT_TICK */
+		qcom,wf-vmax-mv = <2400>;
+		qcom,wf-pattern-period-us = <5880>;
+	};
+
+	primitive_8 {
+		/* LOW_TICK */
+		qcom,wf-vmax-mv = <2400>;
+		qcom,wf-pattern-period-us = <5880>;
+	};
 };
 
 &ufsphy_mem {
@@ -200,6 +255,13 @@
 
 &usb_qmp_dp_phy {
 	pinctrl-names = "unused";
+
+	qcom,qmp-phy-override-seq =
+		/* <reg_offset,		value> */
+		<USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4		0xEE
+		USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4		0x0D
+		USB3_DP_QSERDES_RXB_RX_MODE_00_LOW		0x3F
+		USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4		0x0E>;
 };
 
 &qupv3_hub_i2c2 {
@@ -248,13 +310,15 @@
 	qcom,param-override-seq =
 		/* <value reg_offset> */
 		/* Adjust HS trasmit amplitude */
-		<0xd 0x51
+		<0xf 0x51
 		/* Squelch detection threshold */
 		 0x3 0x54
 		/* Tx pre-emphasis tuning */
 		 0x7 0x57
 		/* HS disconnect threshold */
-		 0x6 0x53>;
+		 0x6 0x53
+		/* slew rate */
+		 0x2 0x59>;
 };
 
 &eusb2_phy0 {
@@ -269,6 +333,10 @@
 			remote-endpoint = <&usb_port0_connector>;
 		};
 	};
+
+	dwc3@a600000 {
+		snps,usb2-gadget-lpm-disable;
+	};
 };
 
 &ucsi {
diff --git a/qcom/kalama-sg-hhg.dtsi b/qcom/kalama-sg-hhg.dtsi
index 8bdefc2c..376667df 100755
--- a/qcom/kalama-sg-hhg.dtsi
+++ b/qcom/kalama-sg-hhg.dtsi
@@ -104,6 +104,19 @@
 	status = "disabled";
 };
 
+&pm8550b_eusb2_repeater {
+	qcom,param-override-seq =
+		/* <value reg_offset> */
+		/* Adjust HS trasmit amplitude */
+		<0xd 0x51
+		/* Squelch detection threshold */
+		 0x3 0x54
+		/* Tx pre-emphasis tuning */
+		 0x7 0x57
+		/* HS disconnect threshold */
+		 0x6 0x53>;
+};
+
 &pm8550_gpios {
 	pwr_en_gpio {
 		pwr_en_gpio_default: pwr_en_gpio_default {
diff --git a/qcom/kalama.dtsi b/qcom/kalama.dtsi
index 7b7c182f..b5b57b2f 100755
--- a/qcom/kalama.dtsi
+++ b/qcom/kalama.dtsi
@@ -43,7 +43,7 @@
 	aliases: aliases {
 		serial0 = &qupv3_se7_2uart;
 		hsuart0 = &qupv3_se14_4uart;
-		sdhc2 = &sdhc_2;
+		mmc1 = &sdhc_2; /* SD card slot */
 		ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
 	};
 
@@ -645,7 +645,7 @@
 		size = <0x0 0x1000000>;
 	};
 
-	glink_contig_mem: glink_contig_region {
+	qmc_dma_mem: qmc_dma_region {
 		compatible = "shared-dma-pool";
 		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
 		reusable;
@@ -700,6 +700,9 @@
 	ranges = <0 0 0 0xffffffff>;
 	compatible = "simple-bus";
 
+	disp_rdump_region {
+	};
+
 	dsi_pll_codes {
 	};
 
@@ -1052,6 +1055,11 @@
 			#clock-cells = <1>;
 		};
 
+		scmi_cpufreqstat: protocol@84 {
+			reg = <0x84>;
+			#clock-cells = <1>;
+		};
+
 		scmi_pmu: protocol@86 {
 			reg = <0x86>;
 			#clock-cells = <1>;
@@ -1525,6 +1533,25 @@
 			qcom,allocate-on-request;
 			label = "modem";
 		};
+
+		qcom,client_4 {
+			compatible = "qcom,memshare-peripheral";
+			qcom,peripheral-size = <0x1000000>;
+			qcom,client-id = <5>;
+			qcom,allocate-on-request;
+			qcom,shared;
+			memory-region = <&qmc_dma_mem>;
+			label = "modem";
+		};
+
+		qcom,client_5 {
+			compatible = "qcom,memshare-peripheral";
+			qcom,peripheral-size = <0x400000>;
+			qcom,client-id = <6>;
+			qcom,allocate-on-request;
+			qcom,shared;
+			label = "modem";
+		};
 	};
 
 	clocks {
@@ -1775,360 +1802,6 @@
 				      <&cpufreq_hw 2>;
 	};
 
-	/* CAM_CC GDSCs */
-	cam_cc_bps_gdsc: qcom,gdsc@adf0004 {
-		compatible = "qcom,gdsc";
-		reg = <0xadf0004 0x4>;
-		regulator-name = "cam_cc_bps_gdsc";
-		clock-names = "ahb_clk";
-		clocks = <&gcc GCC_CAMERA_AHB_CLK>;
-		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
-		qcom,gds-timeout = <1500>;
-		qcom,support-hw-trigger;
-		qcom,retain-regs;
-		qcom,support-cfg-gdscr;
-	};
-
-	cam_cc_ife_0_gdsc: qcom,gdsc@adf1004 {
-		compatible = "qcom,gdsc";
-		reg = <0xadf1004 0x4>;
-		regulator-name = "cam_cc_ife_0_gdsc";
-		clock-names = "ahb_clk";
-		clocks = <&gcc GCC_CAMERA_AHB_CLK>;
-		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
-		qcom,gds-timeout = <1500>;
-		qcom,retain-regs;
-		qcom,support-cfg-gdscr;
-	};
-
-	cam_cc_ife_1_gdsc: qcom,gdsc@adf2004 {
-		compatible = "qcom,gdsc";
-		reg = <0xadf2004 0x4>;
-		regulator-name = "cam_cc_ife_1_gdsc";
-		clock-names = "ahb_clk";
-		clocks = <&gcc GCC_CAMERA_AHB_CLK>;
-		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
-		qcom,gds-timeout = <1500>;
-		qcom,retain-regs;
-		qcom,support-cfg-gdscr;
-	};
-
-	cam_cc_ife_2_gdsc: qcom,gdsc@adf2294 {
-		compatible = "qcom,gdsc";
-		reg = <0xadf2294 0x4>;
-		regulator-name = "cam_cc_ife_2_gdsc";
-		clock-names = "ahb_clk";
-		clocks = <&gcc GCC_CAMERA_AHB_CLK>;
-		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
-		qcom,gds-timeout = <1500>;
-		qcom,retain-regs;
-		qcom,support-cfg-gdscr;
-	};
-
-	cam_cc_ipe_0_gdsc: qcom,gdsc@adf03b8 {
-		compatible = "qcom,gdsc";
-		reg = <0xadf03b8 0x4>;
-		regulator-name = "cam_cc_ipe_0_gdsc";
-		clock-names = "ahb_clk";
-		clocks = <&gcc GCC_CAMERA_AHB_CLK>;
-		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
-		qcom,gds-timeout = <1500>;
-		qcom,support-hw-trigger;
-		qcom,retain-regs;
-		qcom,support-cfg-gdscr;
-	};
-
-	cam_cc_sbi_gdsc: qcom,gdsc@adf052c {
-		compatible = "qcom,gdsc";
-		reg = <0xadf052c 0x4>;
-		regulator-name = "cam_cc_sbi_gdsc";
-		clock-names = "ahb_clk";
-		clocks = <&gcc GCC_CAMERA_AHB_CLK>;
-		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
-		qcom,gds-timeout = <1500>;
-		qcom,retain-regs;
-		qcom,support-cfg-gdscr;
-	};
-
-	cam_cc_sfe_0_gdsc: qcom,gdsc@adf3280 {
-		compatible = "qcom,gdsc";
-		reg = <0xadf3280 0x4>;
-		regulator-name = "cam_cc_sfe_0_gdsc";
-		clock-names = "ahb_clk";
-		clocks = <&gcc GCC_CAMERA_AHB_CLK>;
-		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
-		qcom,gds-timeout = <1500>;
-		qcom,retain-regs;
-		qcom,support-cfg-gdscr;
-	};
-
-	cam_cc_sfe_1_gdsc: qcom,gdsc@adf33e0 {
-		compatible = "qcom,gdsc";
-		reg = <0xadf33e0 0x4>;
-		regulator-name = "cam_cc_sfe_1_gdsc";
-		clock-names = "ahb_clk";
-		clocks = <&gcc GCC_CAMERA_AHB_CLK>;
-		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
-		qcom,gds-timeout = <1500>;
-		qcom,retain-regs;
-		qcom,support-cfg-gdscr;
-	};
-
-	cam_cc_titan_top_gdsc: qcom,gdsc@adf4058 {
-		compatible = "qcom,gdsc";
-		reg = <0xadf4058 0x4>;
-		regulator-name = "cam_cc_titan_top_gdsc";
-		clock-names = "ahb_clk";
-		clocks = <&gcc GCC_CAMERA_AHB_CLK>;
-		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
-		proxy-supply = <&cam_cc_titan_top_gdsc>;
-		interconnects = <&mmss_noc MASTER_CAMNOC_HF &mmss_noc SLAVE_MNOC_HF_MEM_NOC>;
-		interconnect-names = "mmnoc";
-		qcom,gds-timeout = <1500>;
-		qcom,proxy-consumer-enable;
-		qcom,retain-regs;
-		qcom,support-cfg-gdscr;
-	};
-
-	/* DISP_CC GDSCs */
-	disp_cc_mdss_core_gdsc: qcom,gdsc@af09000 {
-		compatible = "qcom,gdsc";
-		reg = <0xaf09000 0x4>;
-		regulator-name = "disp_cc_mdss_core_gdsc";
-		clock-names = "ahb_clk";
-		clocks = <&gcc GCC_DISP_AHB_CLK>;
-		parent-supply = <&VDD_MM_LEVEL>;
-		proxy-supply = <&disp_cc_mdss_core_gdsc>;
-		qcom,gds-timeout = <1500>;
-		qcom,proxy-consumer-enable;
-		qcom,support-hw-trigger;
-		qcom,retain-regs;
-		qcom,support-cfg-gdscr;
-	};
-
-	disp_cc_mdss_core_int2_gdsc: qcom,gdsc@af0b000 {
-		compatible = "qcom,gdsc";
-		reg = <0xaf0b000 0x4>;
-		regulator-name = "disp_cc_mdss_core_int2_gdsc";
-		clock-names = "ahb_clk";
-		clocks = <&gcc GCC_DISP_AHB_CLK>;
-		parent-supply = <&VDD_MM_LEVEL>;
-		qcom,gds-timeout = <1500>;
-		qcom,support-hw-trigger;
-		qcom,retain-regs;
-		qcom,support-cfg-gdscr;
-	};
-
-	gcc_apcs_gdsc_vote_ctrl: syscon@152020{
-		compatible = "syscon";
-		reg = <0x152020 0x4>;
-	};
-
-	/* GCC GDSCs */
-	gcc_pcie_0_gdsc: qcom,gdsc@16b004 {
-		compatible = "qcom,gdsc";
-		reg = <0x16b004 0x4>;
-		regulator-name = "gcc_pcie_0_gdsc";
-		parent-supply = <&VDD_CX_LEVEL>;
-		clocks = <&gcc 0>;
-		qcom,gds-timeout = <1500>;
-		qcom,retain-regs;
-		qcom,no-status-check-on-disable;
-		qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 0>;
-		qcom,support-cfg-gdscr;
-	};
-
-	gcc_pcie_0_phy_gdsc: qcom,gdsc@16c000 {
-		compatible = "qcom,gdsc";
-		reg = <0x16c000 0x4>;
-		regulator-name = "gcc_pcie_0_phy_gdsc";
-		parent-supply = <&VDD_MXA_LEVEL>;
-		clocks = <&gcc 0>;
-		qcom,gds-timeout = <1500>;
-		qcom,retain-regs;
-		qcom,no-status-check-on-disable;
-		qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 3>;
-		qcom,support-cfg-gdscr;
-	};
-
-	gcc_pcie_1_gdsc: qcom,gdsc@18d004 {
-		compatible = "qcom,gdsc";
-		reg = <0x18d004 0x4>;
-		regulator-name = "gcc_pcie_1_gdsc";
-		parent-supply = <&VDD_CX_LEVEL>;
-		clocks = <&gcc 0>;
-		qcom,gds-timeout = <1500>;
-		qcom,retain-regs;
-		qcom,no-status-check-on-disable;
-		qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 1>;
-		qcom,support-cfg-gdscr;
-	};
-
-	gcc_pcie_1_phy_gdsc: qcom,gdsc@18e000 {
-		compatible = "qcom,gdsc";
-		reg = <0x18e000 0x4>;
-		regulator-name = "gcc_pcie_1_phy_gdsc";
-		parent-supply = <&VDD_MXA_LEVEL>;
-		clocks = <&gcc 0>;
-		qcom,gds-timeout = <1500>;
-		qcom,retain-regs;
-		qcom,no-status-check-on-disable;
-		qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 4>;
-		qcom,support-cfg-gdscr;
-	};
-
-	gcc_ufs_mem_phy_gdsc: qcom,gdsc@19e000 {
-		compatible = "qcom,gdsc";
-		reg = <0x19e000 0x4>;
-		regulator-name = "gcc_ufs_mem_phy_gdsc";
-		clocks = <&gcc 0>;
-		qcom,gds-timeout = <1500>;
-		parent-supply = <&VDD_MXA_LEVEL>;
-		qcom,retain-regs;
-		qcom,support-cfg-gdscr;
-	};
-
-	gcc_ufs_phy_gdsc: qcom,gdsc@177004 {
-		compatible = "qcom,gdsc";
-		reg = <0x177004 0x4>;
-		regulator-name = "gcc_ufs_phy_gdsc";
-		parent-supply = <&VDD_CX_LEVEL>;
-		proxy-supply = <&gcc_ufs_phy_gdsc>;
-		clocks = <&gcc 0>;
-		qcom,gds-timeout = <1500>;
-		qcom,proxy-consumer-enable;
-		qcom,retain-regs;
-		qcom,support-cfg-gdscr;
-	};
-
-	gcc_usb30_prim_gdsc: qcom,gdsc@139004 {
-		compatible = "qcom,gdsc";
-		reg = <0x139004 0x4>;
-		regulator-name = "gcc_usb30_prim_gdsc";
-		proxy-supply = <&gcc_usb30_prim_gdsc>;
-		clocks = <&gcc 0>;
-		qcom,gds-timeout = <1500>;
-		qcom,proxy-consumer-enable;
-		qcom,retain-regs;
-		qcom,support-cfg-gdscr;
-	};
-
-	gcc_usb3_phy_gdsc: qcom,gdsc@150018 {
-		compatible = "qcom,gdsc";
-		reg = <0x150018 0x4>;
-		regulator-name = "gcc_usb3_phy_gdsc";
-		clocks = <&gcc 0>;
-		qcom,gds-timeout = <1500>;
-		parent-supply = <&VDD_MXA_LEVEL>;
-		qcom,proxy-consumer-enable;
-		qcom,retain-regs;
-		qcom,support-cfg-gdscr;
-	};
-
-	/* GPU_CC GDSCs */
-	gpu_cc_cx_gdsc_hw_ctrl: syscon@3d9953c {
-		compatible = "syscon";
-		reg = <0x3d9953c 0x4>;
-	};
-
-	gpu_cc_cx_gdsc: qcom,gdsc@3d99108 {
-		compatible = "qcom,gdsc";
-		reg = <0x3d99108 0x4>;
-		regulator-name = "gpu_cc_cx_gdsc";
-		parent-supply = <&VDD_CX_LEVEL>;
-		hw-ctrl-addr = <&gpu_cc_cx_gdsc_hw_ctrl>;
-		qcom,no-status-check-on-disable;
-		qcom,clk-dis-wait-val = <8>;
-		qcom,gds-timeout = <1500>;
-		qcom,retain-regs;
-	};
-
-	gpu_cc_gx_domain_addr: syscon@3d99504 {
-		compatible = "syscon";
-		reg = <0x3d99504 0x4>;
-	};
-
-	gpu_cc_gx_sw_reset: syscon@3d99058 {
-		compatible = "syscon";
-		reg = <0x3d99058 0x4>;
-	};
-
-	gpu_cc_gx_acd_reset: syscon@3d99358 {
-		compatible = "syscon";
-		reg = <0x3d99358 0x4>;
-	};
-
-	gpu_cc_gx_acd_iroot_reset: syscon@3d9958c {
-		compatible = "syscon";
-		reg = <0x3d9958c 0x4>;
-	};
-
-	gpu_cc_gx_gdsc: qcom,gdsc@3d9905c {
-		compatible = "qcom,gdsc";
-		reg = <0x3d9905c 0x4>;
-		regulator-name = "gpu_cc_gx_gdsc";
-		domain-addr = <&gpu_cc_gx_domain_addr>;
-		sw-reset = <&gpu_cc_gx_sw_reset>,
-			   <&gpu_cc_gx_acd_reset>,
-			   <&gpu_cc_gx_acd_iroot_reset>;
-		parent-supply = <&VDD_GFX_MXC_VOTER_LEVEL>;
-		qcom,reset-aon-logic;
-		qcom,gds-timeout = <1500>;
-		qcom,retain-regs;
-		qcom,support-cfg-gdscr;
-	};
-
-	/* VIDEO_CC GDSCs */
-	video_cc_mvs0_gdsc: qcom,gdsc@abf80a4 {
-		compatible = "qcom,gdsc";
-		reg = <0xabf80a4 0x4>;
-		regulator-name = "video_cc_mvs0_gdsc";
-		parent-supply = <&video_cc_mvs0c_gdsc>;
-		clock-names = "ahb_clk";
-		clocks = <&gcc GCC_VIDEO_AHB_CLK>;
-		qcom,gds-timeout = <1500>;
-		qcom,support-hw-trigger;
-		qcom,retain-regs;
-		qcom,support-cfg-gdscr;
-	};
-
-	video_cc_mvs0c_gdsc: qcom,gdsc@abf804c {
-		compatible = "qcom,gdsc";
-		reg = <0xabf804c 0x4>;
-		regulator-name = "video_cc_mvs0c_gdsc";
-		clock-names = "ahb_clk";
-		clocks = <&gcc GCC_VIDEO_AHB_CLK>;
-		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
-		qcom,gds-timeout = <1500>;
-		qcom,retain-regs;
-		qcom,support-cfg-gdscr;
-	};
-
-	video_cc_mvs1_gdsc: qcom,gdsc@abf80cc {
-		compatible = "qcom,gdsc";
-		reg = <0xabf80cc 0x4>;
-		regulator-name = "video_cc_mvs1_gdsc";
-		parent-supply = <&video_cc_mvs1c_gdsc>;
-		clock-names = "ahb_clk";
-		clocks = <&gcc GCC_VIDEO_AHB_CLK>;
-		qcom,gds-timeout = <1500>;
-		qcom,support-hw-trigger;
-		qcom,retain-regs;
-		qcom,support-cfg-gdscr;
-	};
-
-	video_cc_mvs1c_gdsc: qcom,gdsc@abf8078 {
-		compatible = "qcom,gdsc";
-		reg = <0xabf8078 0x4>;
-		regulator-name = "video_cc_mvs1c_gdsc";
-		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
-		clock-names = "ahb_clk";
-		clocks = <&gcc GCC_VIDEO_AHB_CLK>;
-		qcom,gds-timeout = <1500>;
-		qcom,retain-regs;
-		qcom,support-cfg-gdscr;
-	};
-
 	sdhc2_opp_table: sdhc2-opp-table {
 		compatible = "operating-points-v2";
 
@@ -2603,6 +2276,18 @@
 			qcom,glinkpkt-ch-name = "bt_cp_ctrl";
 			qcom,glinkpkt-dev-name = "bt_cp_ctrl";
 		};
+
+		qcom,glinkpkt-qmc-dma {
+			qcom,glinkpkt-edge = "mpss";
+			qcom,glinkpkt-ch-name = "QMC_DMA_LINE";
+			qcom,glinkpkt-dev-name = "qmc_dma";
+		};
+
+		qcom,glinkpkt-qmc-cma {
+			qcom,glinkpkt-edge = "mpss";
+			qcom,glinkpkt-ch-name = "QMC_CMA_LINE";
+			qcom,glinkpkt-dev-name = "qmc_cma";
+		};
 	};
 
 	qcom,glink {
@@ -3945,10 +3630,10 @@
 #include "kalama-regulators.dtsi"
 #include "kalama-qupv3.dtsi"
 #include "kalama-usb.dtsi"
-#include "kalama-eva.dtsi"
 #include "kalama-pcie.dtsi"
 #include "msm-rdbg.dtsi"
 #include "kalama-thermal.dtsi"
+#include "kalama-gdsc.dtsi"
 
 &qupv3_se7_2uart {
 	status = "ok";
@@ -3961,3 +3646,169 @@
 		reg = <0x42>;
 	};
 };
+&cam_cc_bps_gdsc {
+	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
+	clock-names = "ahb_clk";
+	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
+	status = "ok";
+};
+
+&cam_cc_ife_0_gdsc {
+	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
+	clock-names = "ahb_clk";
+	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
+	status = "ok";
+};
+
+&cam_cc_ife_1_gdsc {
+	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
+	clock-names = "ahb_clk";
+	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
+	status = "ok";
+
+};
+
+&cam_cc_ife_2_gdsc {
+	clock-names = "ahb_clk";
+	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
+	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
+	status = "ok";
+};
+
+&cam_cc_ipe_0_gdsc {
+	clock-names = "ahb_clk";
+	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
+	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
+	status = "ok";
+};
+
+&cam_cc_sbi_gdsc {
+	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
+	clock-names = "ahb_clk";
+	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
+	status = "ok";
+};
+
+&cam_cc_sfe_0_gdsc {
+	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
+	clock-names = "ahb_clk";
+	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
+	status = "ok";
+};
+
+&cam_cc_sfe_1_gdsc {
+	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
+	clock-names = "ahb_clk";
+	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
+	status = "ok";
+};
+
+&cam_cc_titan_top_gdsc {
+	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
+	clock-names = "ahb_clk";
+	interconnects = <&mmss_noc MASTER_CAMNOC_HF &mmss_noc SLAVE_MNOC_HF_MEM_NOC>;
+	interconnect-names = "mmnoc";
+	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
+	status = "ok";
+};
+
+&disp_cc_mdss_core_gdsc {
+	clocks = <&gcc GCC_DISP_AHB_CLK>;
+	clock-names = "ahb_clk";
+	parent-supply = <&VDD_MM_LEVEL>;
+	status = "ok";
+};
+
+&disp_cc_mdss_core_int2_gdsc {
+	clocks = <&gcc GCC_DISP_AHB_CLK>;
+	clock-names = "ahb_clk";
+	parent-supply = <&VDD_MM_LEVEL>;
+	status = "ok";
+};
+
+&gcc_pcie_0_gdsc {
+	clocks = <&gcc 0>;
+	parent-supply = <&VDD_CX_LEVEL>;
+	status = "ok";
+};
+
+&gcc_pcie_0_phy_gdsc {
+	clocks = <&gcc 0>;
+	parent-supply = <&VDD_MXA_LEVEL>;
+	status = "ok";
+};
+
+&gcc_pcie_1_gdsc {
+	clocks = <&gcc 0>;
+	parent-supply = <&VDD_CX_LEVEL>;
+	status = "ok";
+};
+
+&gcc_pcie_1_phy_gdsc {
+	clocks = <&gcc 0>;
+	parent-supply = <&VDD_MXA_LEVEL>;
+	status = "ok";
+};
+
+&gcc_ufs_mem_phy_gdsc {
+	clocks = <&gcc 0>;
+	parent-supply = <&VDD_MXA_LEVEL>;
+	status = "ok";
+};
+
+&gcc_ufs_phy_gdsc {
+	clocks = <&gcc 0>;
+	parent-supply = <&VDD_CX_LEVEL>;
+	status = "ok";
+};
+
+&gcc_usb30_prim_gdsc {
+	clocks = <&gcc 0>;
+	regulator-name = "gcc_usb30_prim_gdsc";
+	status = "ok";
+};
+
+&gcc_usb3_phy_gdsc {
+	regulator-name = "gcc_usb3_phy_gdsc";
+	clocks = <&gcc 0>;
+	parent-supply = <&VDD_MXA_LEVEL>;
+	status = "ok";
+};
+
+&gpu_cc_cx_gdsc {
+	parent-supply = <&VDD_CX_LEVEL>;
+	status = "ok";
+};
+
+&gpu_cc_gx_gdsc {
+	parent-supply = <&VDD_GFX_MXC_VOTER_LEVEL>;
+	status = "ok";
+};
+
+&video_cc_mvs0_gdsc {
+	clocks = <&gcc GCC_VIDEO_AHB_CLK>;
+	clock-names = "ahb_clk";
+	parent-supply = <&video_cc_mvs0c_gdsc>;
+	status = "ok";
+};
+
+&video_cc_mvs0c_gdsc {
+	clocks = <&gcc GCC_VIDEO_AHB_CLK>;
+	clock-names = "ahb_clk";
+	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
+	status = "ok";
+};
+
+&video_cc_mvs1_gdsc {
+	clocks = <&gcc GCC_VIDEO_AHB_CLK>;
+	clock-names = "ahb_clk";
+	parent-supply = <&video_cc_mvs1c_gdsc>;
+	status = "ok";
+};
+
+&video_cc_mvs1c_gdsc {
+	clocks = <&gcc GCC_VIDEO_AHB_CLK>;
+	clock-names = "ahb_clk";
+	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
+	status = "ok";
+};
diff --git a/qcom/kalamap-qcs.dtsi b/qcom/kalamap-qcs.dtsi
index 3519daec..436d8bc5 100755
--- a/qcom/kalamap-qcs.dtsi
+++ b/qcom/kalamap-qcs.dtsi
@@ -5,3 +5,27 @@
 	compatible = "qcom,kalamap";
 	qcom,msm-id = <603 0x20000>;
 };
+
+&video_mem {
+	reg = <0x0 0x9bb00000 0x0 0x1000000>;
+};
+
+&cvp_mem {
+	reg = <0x0 0x9cb00000 0x0 0x700000>;
+};
+
+&cdsp_mem {
+	reg = <0x0 0x9d200000 0x0 0x2000000>;
+};
+
+&q6_cdsp_dtb_mem {
+	reg = <0x0 0x9f200000 0x0 0x80000>;
+};
+
+&q6_adsp_dtb_mem {
+	reg = <0x0 0x9f280000 0x0 0x80000>;
+};
+
+&adspslpi_mem {
+	reg = <0x0 0x9f300000 0x0 0x4080000>;
+};
diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi
index 198dede6..6625ff8f 100755
--- a/qcom/khaje.dtsi
+++ b/qcom/khaje.dtsi
@@ -855,6 +855,7 @@
 			     <1 3 0xf08>,
 			     <1 0 0xf08>;
 		clock-frequency = <19200000>;
+		qcom,erratum-858921;
 	};
 
 	dcc: dcc_v2@1be2000 {
@@ -1896,10 +1897,15 @@
 		};
 
 		pil@94c {
-			compatible = "qcom,msm-imem-pil";
+			compatible = "qcom,pil-reloc-info";
 			reg = <0x94c 0xc8>;
 		};
 
+		pil@6dc {
+			compatible = "qcom,msm-imem-pil-disable-timeout";
+			reg = <0x6dc 0x4>;
+		};
+
 		diag_dload@c8 {
 			compatible = "qcom,msm-imem-diag-dload";
 			reg = <0xc8 0xc8>;
@@ -2530,6 +2536,8 @@
 		non-removable;
 		supports-cqe;
 
+		cap-mmc-hw-reset;
+
 		nvmem-cells = <&boot_config>;
 		nvmem-cell-names = "boot_conf";
 
@@ -2937,8 +2945,14 @@
 		qcom,gpucc = <&gpucc>;
 		qcom,mccc = <&mccc_debug>;
 		qcom,apsscc = <&apsscc_debug>;
-		clock-names = "xo_clk_src";
-		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+			<&gcc 0>,
+			<&dispcc 0>,
+			<&gpucc 0>;
+		clock-names = "xo_clk_src",
+				"gcc",
+				"dispcc",
+				"gpucc";
 		#clock-cells = <1>;
 	};
 
@@ -3389,6 +3403,7 @@
 	modem_pas: remoteproc-mss@6080000 {
 		compatible = "qcom,khaje-modem-pas";
 		reg = <0x6080000 0x100>;
+		legacy-wlan;
 
 		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
 		clock-names = "xo";
diff --git a/qcom/kona-7230-iot-cpu.dtsi b/qcom/kona-7230-iot-cpu.dtsi
index 870694df..7cf16821 100755
--- a/qcom/kona-7230-iot-cpu.dtsi
+++ b/qcom/kona-7230-iot-cpu.dtsi
@@ -229,50 +229,48 @@
 		};
 	};
 
-};
+	cti_cpu4: cti@7420000 {
+		cpu = <&CPU2>;
+	};
 
-&cpufreq_hw {
-	/delete-node/ qcom,cpu-isolation;
-	qcom,cpu-isolation {
-		compatible = "qcom,cpu-isolate";
-		cpu0_isolate: cpu0-isolate {
-			qcom,cpu = <&CPU0>;
-			#cooling-cells = <2>;
-		};
+	cti_cpu5: cti@7520000 {
+		cpu = <&CPU3>;
+	};
 
-		cpu1_isolate: cpu1-isolate {
-			qcom,cpu = <&CPU1>;
-			#cooling-cells = <2>;
-		};
+	cti_cpu6: cti@7620000 {
+		cpu = <&CPU4>;
+	};
 
-		cpu4_isolate: cpu4-isolate {
-			qcom,cpu = <&CPU2>;
-			#cooling-cells = <2>;
-		};
+	cti_cpu7: cti@7720000 {
+		cpu = <&CPU5>;
+	};
 
-		cpu5_isolate: cpu5-isolate {
-			qcom,cpu = <&CPU3>;
-			#cooling-cells = <2>;
-		};
+	etm4: etm@7440000 {
+		cpu = <&CPU2>;
+	};
 
-		cpu6_isolate: cpu6-isolate {
-			qcom,cpu = <&CPU4>;
-			#cooling-cells = <2>;
-		};
+	etm5: etm@7540000 {
+		cpu = <&CPU3>;
+	};
 
-		cpu7_isolate: cpu7-isolate {
-			qcom,cpu = <&CPU5>;
-			#cooling-cells = <2>;
-		};
+	etm6: etm@7640000 {
+		cpu = <&CPU4>;
 	};
 
-	/delete-node/ cpu7-notify;
-	cpu7_notify: cpu7-notify {
-		qcom,cooling-cpu = <&CPU5>;
-		#cooling-cells = <2>;
+	etm7: etm@7740000 {
+		cpu = <&CPU5>;
+	};
+
+	funnel_apss: funnel@7800000 {
+		in-ports {
+			/delete-node/ port@3;
+			/delete-node/ port@4;
+		};
 	};
 };
 
+
+
 &qcom_memlat {
 	ddr {
 		silver {
@@ -327,3 +325,64 @@
 		};
 	};
 };
+
+&soc {
+	qcom,cpu-pause {
+		/delete-node/ cpu6-pause;
+		/delete-node/ cpu7-pause;
+		/delete-node/ pause-cpu6;
+		/delete-node/ pause-cpu7;
+	};
+
+	qcom,cpu-hotplug {
+		/delete-node/ cpu6-hotplug;
+		/delete-node/ cpu7-hotplug;
+	};
+
+	/delete-node/ cpufreq_cdev;
+	cpufreq_cdev: qcom,cpufreq-cdev {
+		compatible = "qcom,cpufreq-cdev";
+		qcom,cpus = <&CPU0 &CPU2 &CPU5>;
+	};
+
+};
+
+&thermal_zones {
+	cpu-1-2 {
+		cooling-maps {
+			/delete-node/ cpu12_cdev;
+		};
+	};
+
+	cpu-1-3 {
+		cooling-maps {
+			/delete-node/ cpu13_cdev;
+		};
+	};
+
+	cpu-1-6 {
+		cooling-maps {
+			/delete-node/ cpu16_cdev;
+		};
+	};
+
+	cpu-1-7 {
+		cooling-maps {
+			/delete-node/ cpu17_cdev;
+		};
+	};
+
+	ddr {
+		cooling-maps {
+			/delete-node/ cpu_cdev7;
+		};
+	};
+};
+
+&cpufreq_hw {
+	/delete-node/ cpu7-notify;
+	cpu7_notify: cpu7-notify {
+		qcom,cooling-cpu = <&CPU5>;
+		#cooling-cells = <2>;
+	};
+};
diff --git a/qcom/kona-coresight.dtsi b/qcom/kona-coresight.dtsi
new file mode 100755
index 00000000..69112e7b
--- /dev/null
+++ b/qcom/kona-coresight.dtsi
@@ -0,0 +1,3268 @@
+&soc {
+	replicator_qdss: replicator@6046000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb909>;
+
+		reg = <0x6046000 0x1000>;
+		reg-names = "replicator-base";
+
+		coresight-name = "coresight-replicator-qdss";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port@1 {
+				reg = <0>;
+				replicator_cx_in_swao_out: endpoint {
+					slave-mode;
+					remote-endpoint=
+						<&replicator_swao_out_cx_in>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				replicator0_out_tmc_etr: endpoint {
+					remote-endpoint=
+						<&tmc_etr_in_replicator0>;
+				};
+			};
+		};
+	};
+
+	replicator_swao: replicator@6b06000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb909>;
+
+		reg = <0x6b06000 0x1000>;
+		reg-names = "replicator-base";
+
+		coresight-name = "coresight-replicator-swao";
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Always have EUD before funnel leading to ETR. If both
+			 * sink are active we need to give preference to EUD
+			 * over ETR
+			 */
+			port@2 {
+				reg = <0>;
+				replicator_swao_in_tmc_etf_swao: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tmc_etf_swao_out_replicator_swao>;
+				};
+			};
+		};
+
+		out-ports {
+			port@0 {
+				reg = <1>;
+				replicator_swao_out_eud: endpoint {
+					remote-endpoint =
+					<&eud_in_replicator_swao>;
+				};
+			};
+
+			port@1 {
+				reg = <0>;
+				replicator_swao_out_cx_in: endpoint {
+					remote-endpoint =
+					<&replicator_cx_in_swao_out>;
+				};
+			};
+		};
+	};
+
+	dummy_eud: dummy_sink {
+
+		compatible = "qcom,coresight-dummy";
+		coresight-name = "coresight-eud";
+
+		qcom,dummy-sink;
+		in-ports {
+			port {
+				eud_in_replicator_swao: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&replicator_swao_out_eud>;
+				};
+			};
+		};
+	};
+
+
+	tmc_etf_swao: tmc@6b05000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb961>;
+
+		reg = <0x6b05000 0x1000>;
+		reg-names = "tmc-base";
+
+		coresight-name = "coresight-tmc-etf";
+		coresight-ctis = <&cti0_swao &cti3_swao>;
+		coresight-csr = <&swao_csr>;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port@1 {
+				reg = <0>;
+				tmc_etf_swao_in_funnel_swao: endpoint {
+					slave-mode;
+					remote-endpoint=
+						<&funnel_swao_out_tmc_etf_swao>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				tmc_etf_swao_out_replicator_swao: endpoint {
+					remote-endpoint=
+					<&replicator_swao_in_tmc_etf_swao>;
+				};
+			};
+		};
+	};
+
+
+	funnel_swao: funnel@6b04000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6b04000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-swao";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@1 {
+				reg = <3>;
+				funnel_swao_in_ssc_etm0: endpoint {
+					slave-mode;
+					remote-endpoint=
+						<&ssc_etm0_out_funnel_swao>;
+				};
+			};
+
+			port@2 {
+				reg = <0>;
+				funnel_swao_in_audio_etm0: endpoint {
+					slave-mode;
+					remote-endpoint=
+						<&audio_etm0_out_funnel_swao>;
+				};
+			};
+
+			port@3 {
+				reg = <6>;
+				funnel_swao_in_tpda_swao: endpoint {
+					slave-mode;
+					remote-endpoint=
+						<&tpda_swao_out_funnel_swao>;
+				};
+			};
+
+			port@4 {
+				reg = <7>;
+				funnel_swao_in_funnel_merg: endpoint {
+					slave-mode;
+					remote-endpoint=
+						<&funnel_merg_out_funnel_swao>;
+				};
+			};
+
+			port@5 {
+				reg = <5>;
+				funnel_swao_in_lpass_lpi: endpoint {
+					slave-mode;
+					remote-endpoint=
+						<&lpass_lpi_out_funnel_swao>;
+				};
+			};
+		};
+
+		out-ports {
+			port@0 {
+				reg = <0>;
+				funnel_swao_out_tmc_etf_swao: endpoint {
+					remote-endpoint =
+						<&tmc_etf_swao_in_funnel_swao>;
+				};
+			};
+		};
+	};
+
+
+	tpda_swao: tpda@6b08000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+		reg = <0x6b08000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda-swao";
+
+		qcom,tpda-atid = <71>;
+		qcom,dsb-elem-size = <1 32>;
+		qcom,cmb-elem-size = <0 64>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port@1 {
+				reg = <0>;
+				tpda_swao_in_tpdm_swao0: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_swao0_out_tpda_swao>;
+				};
+			};
+
+			port@2 {
+				reg = <1>;
+				tpda_swao_in_tpdm_swao1: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_swao1_out_tpda_swao>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				tpda_swao_out_funnel_swao: endpoint {
+					remote-endpoint =
+						<&funnel_swao_in_tpda_swao>;
+				};
+			};
+		};
+	};
+
+	tpdm_swao0: tpdm@6b09000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+
+		reg = <0x6b09000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-swao-0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_swao0_out_tpda_swao: endpoint {
+					remote-endpoint =
+						<&tpda_swao_in_tpdm_swao0>;
+				};
+			};
+		};
+	};
+
+	tpdm_swao1: tpdm@6b0a000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x6b0a000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name="coresight-tpdm-swao-1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		qcom,msr-fix-req;
+
+		out-ports {
+			port {
+				tpdm_swao1_out_tpda_swao: endpoint {
+					remote-endpoint =
+						<&tpda_swao_in_tpdm_swao1>;
+				};
+			};
+		};
+	};
+
+	tmc_etr: tmc@6048000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb961>;
+
+		reg = <0x6048000 0x1000>,
+			<0x6064000 0x15000>;
+		reg-names = "tmc-base", "bam-base";
+
+		iommus = <&apps_smmu 0x0480 0>,
+			<&apps_smmu 0x0520 0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		arm,buffer-size = <0x400000>;
+		arm,scatter-gather;
+
+		coresight-name = "coresight-tmc-etr";
+		qcom,mem_support;
+		qcom,sw-usb;
+		qcom,iommu-dma = "bypass";
+		coresight-ctis = <&cti0 &cti3_swao>;
+		coresight-csr = <&csr>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "byte-cntr-irq";
+
+		in-ports {
+			port {
+				tmc_etr_in_replicator0: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&replicator0_out_tmc_etr>;
+				};
+			};
+		};
+	};
+
+	funnel_merg: funnel@6045000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6045000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-merg";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port@1 {
+				reg = <0>;
+				funnel_merg_in_funnel_in0: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&funnel_in0_out_funnel_merg>;
+				};
+			};
+
+			port@2 {
+				reg = <1>;
+				funnel_merg_in_funnel_in1: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&funnel_in1_out_funnel_merg>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				funnel_merg_out_funnel_swao: endpoint {
+					remote-endpoint =
+						<&funnel_swao_in_funnel_merg>;
+				};
+			};
+		};
+	};
+
+	stm: stm@6002000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb962>;
+
+		reg = <0x6002000 0x1000>,
+			<0x16280000 0x180000>,
+			<0x7820f0 0x4>;
+		reg-names = "stm-base", "stm-stimulus-base", "stm-debug-status";
+
+		coresight-name = "coresight-stm";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				stm_out_funnel_in0: endpoint {
+					remote-endpoint = <&funnel_in0_in_stm>;
+				};
+			};
+		};
+	};
+
+	csr: csr@6001000 {
+		compatible = "qcom,coresight-csr";
+		reg = <0x6001000 0x1000>;
+		reg-names = "csr-base";
+
+		coresight-name = "coresight-csr";
+		qcom,usb-bam-support;
+		qcom,hwctrl-set-support;
+		qcom,set-byte-cntr-support;
+
+		qcom,blk-size = <1>;
+	};
+
+	swao_csr: csr@6b0c000 {
+		compatible = "qcom,coresight-csr";
+		reg = <0x6b0c000 0x1000>;
+		reg-names = "csr-base";
+
+		coresight-name = "coresight-swao-csr";
+		qcom,timestamp-support;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		qcom,blk-size = <1>;
+	};
+
+	funnel_in0: funnel@6041000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6041000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-in0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@1 {
+				reg = <6>;
+				funnel_in0_in_funnel_qatb: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&funnel_qatb_out_funnel_in0>;
+				};
+			};
+
+			port@2 {
+				reg = <7>;
+				funnel_in0_in_stm: endpoint {
+					slave-mode;
+					remote-endpoint = <&stm_out_funnel_in0>;
+				};
+			};
+		};
+
+		out-ports {
+			port@0 {
+				reg = <0>;
+				funnel_in0_out_funnel_merg: endpoint {
+					remote-endpoint =
+						<&funnel_merg_in_funnel_in0>;
+				};
+			};
+		};
+	};
+
+	funnel_in1: funnel@6042000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6042000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-in1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port@1 {
+				reg = <1>;
+				funnel_in1_in_funnel_dl_north: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&funnel_dl_north_out_funnel_in1>;
+				};
+			};
+
+			port@2 {
+				reg = <4>;
+				funnel_in1_in_funnel_apss_merg: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&funnel_apss_merg_out_funnel_in1>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				funnel_in1_out_funnel_merg: endpoint {
+					remote-endpoint =
+						<&funnel_merg_in_funnel_in1>;
+				};
+			};
+		};
+	};
+
+	funnel_gpu: funnel@6902000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6902000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-gpu";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		vddcx-supply = <&gpu_cx_gdsc>;
+		vdd-supply = <&gpu_gx_gdsc>;
+		regulator-names = "vddcx", "vdd";
+		qcom,proxy-regs = "vddcx", "vdd";
+
+		in-ports {
+			port@1 {
+				reg = <0>;
+				funnel_gpu_in_tpdm_gpu: endpoint {
+					slave-mode;
+					remote-endpoint =
+					  <&tpdm_gpu_out_funnel_gpu>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				funnel_gpu_out_tpda: endpoint {
+					remote-endpoint =
+					<&tpda_in_funnel_gpu>;
+				};
+			};
+		};
+	};
+
+	tpdm_gpu: tpdm@6900000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b968>;
+		reg = <0x6900000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-gpu";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		vddcx-supply = <&gpu_cx_gdsc>;
+		vdd-supply = <&gpu_gx_gdsc>;
+		regulator-names = "vddcx", "vdd";
+		qcom,proxy-regs  = "vddcx", "vdd";
+
+		out-ports {
+			port {
+				tpdm_gpu_out_funnel_gpu: endpoint {
+				remote-endpoint = <&funnel_gpu_in_tpdm_gpu>;
+				};
+			};
+		};
+	};
+
+	tpda: tpda@6004000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+		reg = <0x6004000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda";
+
+		qcom,tpda-atid = <65>;
+		qcom,bc-elem-size = <16 32>,
+				    <24 32>,
+				    <25 32>;
+		qcom,tc-elem-size = <16 32>,
+				    <25 32>;
+		qcom,dsb-elem-size = <1 32>,
+				     <6 32>,
+				     <7 32>,
+				     <10 32>,
+				     <11 32>,
+				     <12 32>,
+				     <13 32>,
+				     <14 32>,
+				     <16 32>,
+				     <19 32>,
+				     <24 32>,
+				     <25 32>;
+		qcom,cmb-elem-size = <7 64>,
+				     <13 32>,
+				     <15 32>,
+				     <16 32>,
+				     <17 32>,
+				     <18 64>,
+				     <20 64>,
+				     <21 64>,
+				     <22 32>,
+				     <23 32>,
+				     <25 64>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port@1 {
+				reg = <1>;
+				tpda_in_funnel_gpu: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&funnel_gpu_out_tpda>;
+				};
+			};
+
+			port@2 {
+				reg = <6>;
+				tpda_6_in_tpdm_venus: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_venus_out_tpda6>;
+				};
+			};
+
+			port@3 {
+				reg = <7>;
+				tpda_7_in_tpdm_mdss: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_mdss_out_tpda7>;
+				};
+			};
+
+			port@4 {
+				reg = <9>;
+				tpda_9_in_tpdm_mm: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_mm_out_tpda9>;
+				};
+			};
+
+			port@5 {
+				reg = <10>;
+				tpda_10_in_funnel_dl_center: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&funnel_dl_center_out_tpda_10>;
+				};
+			};
+
+			port@6 {
+				reg = <11>;
+				tpda_11_in_tpdm_ddr_ch02: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_ddr_ch02_out_tpda11>;
+				};
+			};
+
+			port@7 {
+				reg = <12>;
+				tpda_12_in_tpdm_ddr_ch13: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_ddr_ch13_out_tpda12>;
+				};
+			};
+
+			port@8 {
+				reg = <13>;
+				tpda_13_in_tpdm_ddr: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_ddr_out_tpda13>;
+				};
+			};
+
+			port@9 {
+				reg = <14>;
+				tpda_14_in_tpdm_turing: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_turing_out_tpda14>;
+				};
+			};
+
+			port@10 {
+				reg = <15>;
+				tpda_15_in_tpdm_llm_turing: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_llm_turing_out_tpda15>;
+				};
+			};
+
+			port@14 {
+				reg = <19>;
+				tpda_19_in_tpdm_dlct: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_dlct_out_tpda19>;
+				};
+			};
+
+			port@15 {
+				reg = <20>;
+				tpda_20_in_tpdm_ipcc: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_ipcc_out_tpda20>;
+				};
+			};
+
+			port@16 {
+				reg = <21>;
+				tpda_in_tpdm_vsense: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_vsense_out_tpda>;
+				};
+			};
+
+			port@17 {
+				reg = <22>;
+				tpda_in_tpdm_dcc: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_dcc_out_tpda>;
+				};
+			};
+
+			port@18 {
+				reg = <23>;
+				tpda_in_tpdm_prng: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_prng_out_tpda>;
+				};
+			};
+
+			port@19 {
+				reg = <24>;
+				tpda_in_tpdm_qm: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_qm_out_tpda>;
+				};
+			};
+
+			port@20 {
+				reg = <25>;
+				tpda_in_tpdm_pimem: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_pimem_out_tpda>;
+				};
+			};
+
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				tpda_out_funnel_qatb: endpoint {
+					remote-endpoint =
+						<&funnel_qatb_in_tpda>;
+				};
+			};
+		};
+	};
+
+	tpdm_dcc: tpdm@6870000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b968>;
+		reg = <0x6870000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-dcc";
+
+		qcom,hw-enable-check;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_dcc_out_tpda: endpoint {
+				remote-endpoint = <&tpda_in_tpdm_dcc>;
+				};
+			};
+		};
+	};
+
+	tpdm_vsense: tpdm@6840000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x6840000 0x1000>;
+		reg-names = "tpdm-base";
+
+		status = "disabled";
+		coresight-name = "coresight-tpdm-vsense";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_vsense_out_tpda: endpoint {
+				remote-endpoint = <&tpda_in_tpdm_vsense>;
+				};
+			};
+		};
+	};
+
+	tpdm_prng: tpdm@684c000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x684c000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-prng";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_prng_out_tpda: endpoint {
+				remote-endpoint = <&tpda_in_tpdm_prng>;
+				};
+			};
+		};
+	};
+
+	tpdm_pimem: tpdm@6850000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x6850000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-pimem";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_pimem_out_tpda: endpoint {
+				remote-endpoint = <&tpda_in_tpdm_pimem>;
+				};
+			};
+		};
+	};
+
+	funnel_lpass: funnel@6846000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6846000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-lpass";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port@1 {
+				reg = <0>;
+				funnel_lpass_in_tpdm_lpass: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_lpass_out_funnel_lpass>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				funnel_lpass_out_funnel_dl_center: endpoint {
+					remote-endpoint =
+						<&funnel_dl_center_in_funnel_lpass>;
+				};
+			};
+		};
+	};
+
+	tpdm_lpass: tpdm@6844000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x6844000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-lpass";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		qcom,msr-fix-req;
+
+		out-ports {
+			port {
+				tpdm_lpass_out_funnel_lpass: endpoint {
+				remote-endpoint = <&funnel_lpass_in_tpdm_lpass>;
+				};
+			};
+		};
+	};
+
+	tpdm_dl_north: tpdm@6ac0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x6ac0000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-dl-north";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		qcom,msr-fix-req;
+
+		out-ports {
+			port {
+				tpdm_dl_north_out_tpda_dl_north: endpoint {
+				remote-endpoint =
+					<&tpda_dl_north_in_tpdm_dl_north>;
+				};
+			};
+		};
+	};
+
+	tpdm_lpass_lpi: tpdm@6b26000 {
+		compatible = "qcom,coresight-dummy";
+
+		coresight-name = "coresight-tpdm-lpass-lpi";
+		qcom,dummy-source;
+
+		out-ports {
+			port {
+				lpass_lpi_out_funnel_swao: endpoint {
+					remote-endpoint =
+					<&funnel_swao_in_lpass_lpi>;
+				};
+			};
+		};
+	};
+
+	tpda_dl_north: tpda@6ac1000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+		reg = <0x06ac1000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda-dl-north";
+		qcom,tpda-atid = <97>;
+
+		qcom,dsb-elem-size = <0 32>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port@1 {
+				reg = <0>;
+				tpda_dl_north_in_tpdm_dl_north: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&tpdm_dl_north_out_tpda_dl_north>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				tpda_dl_north_out_funnel_dl_north: endpoint {
+					remote-endpoint =
+					<&funnel_dl_north_in_tpda_dl_north>;
+				};
+			};
+		};
+	};
+
+	funnel_dl_south: funnel@69c2000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+		reg = <0x69c2000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-dl-south";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port@1 {
+				reg = <0>;
+				funnel_dl_south_in_tpda_dl_south: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&tpda_dl_south_out_funnel_dl_south>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				funnel_south_out_funnel_dl_compute: endpoint {
+					remote-endpoint =
+					<&funnel_dl_compute_in_funnel_dl_south>;
+				};
+			};
+		};
+	};
+
+	tpda_dl_south: tpda@69c1000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+		reg = <0x69c1000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda-dl-south";
+
+		qcom,tpda-atid = <75>;
+		qcom,dsb-elem-size = <0 64>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port@1 {
+				reg = <0>;
+				tpda_dl_south_in_tpdm_dl_south: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&tpdm_dl_south_out_tpda_dl_south>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				tpda_dl_south_out_funnel_dl_south: endpoint {
+					remote-endpoint =
+					<&funnel_dl_south_in_tpda_dl_south>;
+				};
+			};
+		};
+	};
+
+	tpdm_dl_south: tpdm@69c0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x69c0000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-dl-south";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_dl_south_out_tpda_dl_south: endpoint {
+				remote-endpoint =
+					<&tpda_dl_south_in_tpdm_dl_south>;
+				};
+			};
+		};
+	};
+
+	funnel_dl_north: funnel@6ac2000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6ac2000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-dl-north";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port@1 {
+				reg = <0>;
+				funnel_dl_north_in_tpda_dl_north: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&tpda_dl_north_out_funnel_dl_north>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				funnel_dl_north_out_funnel_in1: endpoint {
+					remote-endpoint =
+					<&funnel_in1_in_funnel_dl_north>;
+				};
+			};
+		};
+	};
+
+	funnel_dl_compute: funnel@6c39000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6c39000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-dl-compute";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port@1 {
+				reg = <0>;
+				funnel_compute_in_funnel_turing: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&funnel_turing_out_funnel_dl_compute>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+				funnel_dl_compute_in_funnel_dl_south: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&funnel_south_out_funnel_dl_compute>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				funnel_compute_out_funnel_dl_center: endpoint {
+					remote-endpoint =
+					<&funnel_dl_center_in_funnel_compute>;
+				};
+			};
+		};
+	};
+
+	funnel_dl_center: funnel@6c2d000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6c2d000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-dl-center";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port@15 {
+				reg = <2>;
+				funnel_dl_center_in_funnel_dl_mm: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&funnel_dl_mm_out_funnel_dl_center>;
+				};
+			};
+
+			port@16 {
+				reg = <3>;
+				funnel_dl_center_in_funnel_lpass: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&funnel_lpass_out_funnel_dl_center>;
+				};
+			};
+
+			port@17 {
+				reg = <4>;
+				funnel_dl_center_in_funnel_ddr_0: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&funnel_ddr_0_out_funnel_dl_center>;
+				};
+			};
+
+			port@18 {
+				reg = <5>;
+				funnel_dl_center_in_funnel_compute: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&funnel_compute_out_funnel_dl_center>;
+				};
+			};
+
+			port@19 {
+				reg = <6>;
+				funnel_center_in_tpdm_dlct: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&tpdm_dlct_out_funnel_center>;
+				};
+			};
+
+			port@20 {
+				reg = <7>;
+				funnel_center_in_tpdm_ipcc: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&tpdm_ipcc_out_funnel_center>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				tpdm_venus_out_tpda6: endpoint {
+					remote-endpoint =
+						<&tpda_6_in_tpdm_venus>;
+					source = <&tpdm_venus>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				tpdm_mdss_out_tpda7: endpoint {
+					remote-endpoint =
+						<&tpda_7_in_tpdm_mdss>;
+					source = <&tpdm_mdss>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				tpdm_mm_out_tpda9: endpoint {
+					remote-endpoint =
+						<&tpda_9_in_tpdm_mm>;
+					source = <&tpdm_mm>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+				funnel_dl_center_out_tpda_10: endpoint {
+					remote-endpoint =
+						<&tpda_10_in_funnel_dl_center>;
+					source = <&tpdm_lpass>;
+				};
+			};
+
+			port@4 {
+				reg = <4>;
+				tpdm_ddr_ch02_out_tpda11: endpoint {
+					remote-endpoint =
+						<&tpda_11_in_tpdm_ddr_ch02>;
+					source = <&tpdm_ddr_ch02>;
+				};
+			};
+
+			port@5 {
+				reg = <5>;
+				tpdm_ddr_ch13_out_tpda12: endpoint {
+					remote-endpoint =
+						<&tpda_12_in_tpdm_ddr_ch13>;
+					source = <&tpdm_ddr_ch13>;
+				};
+			};
+
+			port@6 {
+				reg = <6>;
+				tpdm_ddr_out_tpda13: endpoint {
+					remote-endpoint =
+						<&tpda_13_in_tpdm_ddr>;
+					source = <&tpdm_ddr>;
+				};
+			};
+
+			port@7 {
+				reg = <7>;
+				tpdm_turing_out_tpda14: endpoint {
+					remote-endpoint =
+						<&tpda_14_in_tpdm_turing>;
+					source = <&tpdm_turing>;
+				};
+			};
+
+			port@8 {
+				reg = <8>;
+				tpdm_llm_turing_out_tpda15: endpoint {
+					remote-endpoint =
+						<&tpda_15_in_tpdm_llm_turing>;
+					source = <&tpdm_llm_turing>;
+				};
+			};
+
+			port@12 {
+				reg = <12>;
+				tpdm_dlct_out_tpda19: endpoint {
+					remote-endpoint =
+						<&tpda_19_in_tpdm_dlct>;
+					source = <&tpdm_dlct>;
+				};
+			};
+
+			port@13 {
+				reg = <13>;
+				tpdm_ipcc_out_tpda20: endpoint {
+					remote-endpoint =
+						<&tpda_20_in_tpdm_ipcc>;
+					source = <&tpdm_ipcc>;
+				};
+			};
+
+			port@14 {
+				reg = <14>;
+				funnel_dl_center_out_qatb3: endpoint {
+					remote-endpoint =
+					<&qatb3_in_funnel_dl_center>;
+				};
+			};
+		};
+	};
+
+	tpdm_dlct: tpdm@6c28000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x6c28000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-dlct";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_dlct_out_funnel_center: endpoint {
+				remote-endpoint = <&funnel_center_in_tpdm_dlct>;
+				};
+			};
+		};
+	};
+
+	tpdm_ipcc: tpdm@6c29000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x6c29000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-ipcc";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_ipcc_out_funnel_center: endpoint {
+				remote-endpoint = <&funnel_center_in_tpdm_ipcc>;
+				};
+			};
+		};
+	};
+
+	tpdm_qm: tpdm@69d0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x69d0000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-qm";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_qm_out_tpda: endpoint {
+				remote-endpoint = <&tpda_in_tpdm_qm>;
+				};
+			};
+		};
+	};
+
+	tpda_apss: tpda@7863000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+		reg = <0x7863000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda-apss";
+
+		qcom,tpda-atid = <66>;
+		qcom,dsb-elem-size = <3 32>;
+		qcom,cmb-elem-size = <0 32>,
+				     <1 32>,
+				     <2 64>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port@1 {
+				reg = <0>;
+				tpda_apss_in_tpdm_llm_silver: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_llm_silver_out_tpda_apss>;
+				};
+			};
+
+			port@2 {
+				reg = <1>;
+				tpda_apss_in_tpdm_llm_gold: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_llm_gold_out_tpda_apss>;
+				};
+			};
+
+			port@3 {
+				reg = <2>;
+				tpda_apss_in_tpdm_actpm: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_actpm_out_tpda_apss>;
+				};
+			};
+
+			port@4 {
+				reg = <3>;
+				tpda_apss_in_tpdm_apss: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_apss_out_tpda_apss>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				tpda_apss_out_funnel_apss_merg: endpoint {
+					remote-endpoint =
+						<&funnel_apss_merg_in_tpda_apss>;
+				};
+			};
+		};
+	};
+
+	tpdm_llm_silver: tpdm@78a0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x78a0000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-llm-silver";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_llm_silver_out_tpda_apss: endpoint {
+				remote-endpoint =
+					<&tpda_apss_in_tpdm_llm_silver>;
+				};
+			};
+		};
+	};
+
+	tpdm_llm_gold: tpdm@78b0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x78b0000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-llm-gold";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_llm_gold_out_tpda_apss: endpoint {
+				remote-endpoint =
+					<&tpda_apss_in_tpdm_llm_gold>;
+				};
+			};
+		};
+	};
+
+	tpdm_actpm: tpdm@7860000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x7860000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-actpm";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_actpm_out_tpda_apss: endpoint {
+				remote-endpoint =
+					<&tpda_apss_in_tpdm_actpm>;
+				};
+			};
+		};
+	};
+
+	tpdm_apss: tpdm@7861000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x7861000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-apss";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_apss_out_tpda_apss: endpoint {
+				remote-endpoint =
+					<&tpda_apss_in_tpdm_apss>;
+				};
+			};
+		};
+	};
+
+	funnel_dl_mm: funnel@6c0b000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6c0b000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-dl-mm";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port@1 {
+				reg = <0>;
+				funnel_dl_mm_in_funnel_venus: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&funnel_venus_out_funnel_dl_mm>;
+				};
+			};
+
+			port@2 {
+				reg = <1>;
+				funnel_dl_mm_in_tpdm_mdss: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_mdss_out_funnel_dl_mm>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+				funnel_dl_mm_in_tpdm_mm: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_mm_out_funnel_dl_mm>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				funnel_dl_mm_out_funnel_dl_center: endpoint {
+					remote-endpoint =
+						<&funnel_dl_center_in_funnel_dl_mm>;
+				};
+			};
+		};
+	};
+
+	funnel_venus: funnel@6832000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6832000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-venus";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port@1 {
+				reg = <0>;
+				funnel_venus_in_tpdm_venus: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_venus_out_funnel_venus>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				funnel_venus_out_funnel_dl_mm: endpoint {
+					remote-endpoint =
+						<&funnel_dl_mm_in_funnel_venus>;
+				};
+			};
+		};
+	};
+
+	tpdm_venus: tpdm@6830000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x6830000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-venus";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_venus_out_funnel_venus: endpoint {
+				remote-endpoint =
+					<&funnel_venus_in_tpdm_venus>;
+				};
+			};
+		};
+	};
+
+	tpdm_mdss: tpdm@6c60000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x6c60000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-mdss";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_mdss_out_funnel_dl_mm: endpoint {
+				remote-endpoint =
+					<&funnel_dl_mm_in_tpdm_mdss>;
+				};
+			};
+		};
+	};
+
+	tpdm_mm: tpdm@6c08000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x6c08000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-mm";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		qcom,msr-fix-req;
+
+		out-ports {
+			port {
+				tpdm_mm_out_funnel_dl_mm: endpoint {
+				remote-endpoint =
+					<&funnel_dl_mm_in_tpdm_mm>;
+				};
+			};
+		};
+	};
+
+	funnel_turing: funnel@6983000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6983000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-turing";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@1 {
+				reg = <0>;
+				funnel_turing_in_tpdm_turing: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_turing_out_funnel_turing>;
+				};
+			};
+
+			port@2 {
+				reg = <1>;
+				funnel_turing_in_tpdm_llm_turing: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_llm_turing_out_funnel_turing>;
+				};
+			};
+
+			port@3 {
+				reg = <2>;
+				funnel_turing_in_turing_etm0: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&turing_etm0_out_funnel_turing>;
+				};
+			};
+		};
+
+		out-ports {
+			port@0 {
+			reg = <0>;
+			funnel_turing_out_funnel_dl_compute: endpoint {
+				remote-endpoint =
+					<&funnel_compute_in_funnel_turing>;
+			};
+		};
+	};
+};
+
+
+	tpdm_turing: tpdm@6980000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x6980000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-turing";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		qcom,msr-fix-req;
+
+		out-ports {
+			port {
+				tpdm_turing_out_funnel_turing: endpoint {
+				remote-endpoint =
+					<&funnel_turing_in_tpdm_turing>;
+				};
+			};
+		};
+	};
+
+	tpdm_llm_turing: tpdm@69810000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x6981000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-turing-llm";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_llm_turing_out_funnel_turing: endpoint {
+				remote-endpoint =
+					<&funnel_turing_in_tpdm_llm_turing>;
+				};
+			};
+		};
+	};
+
+	funnel_ddr_0: funnel@6e04000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6e04000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-ddr-0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port@1 {
+				reg = <0>;
+				funnel_ddr_0_in_funnel_ddr_ch02: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&funnel_ddr_ch02_out_funnel_ddr_0>;
+				};
+			};
+
+			port@2 {
+				reg = <1>;
+				funnel_ddr_0_in_funnel_ddr_ch13: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&funnel_ddr_ch13_out_funnel_ddr_0>;
+				};
+			};
+
+			port@3 {
+				reg = <2>;
+				funnel_ddr_0_in_tpdm_ddr: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_ddr_out_funnel_ddr_0>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				funnel_ddr_0_out_funnel_dl_center: endpoint {
+					remote-endpoint =
+						<&funnel_dl_center_in_funnel_ddr_0>;
+				};
+			};
+		};
+	};
+
+	funnel_ddr_ch02: funnel@6e12000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6e12000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-ddr-ch02";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port@1 {
+				reg = <0>;
+				funnel_ddr_ch02_in_tpdm_ddr_ch02: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_ddr_ch02_out_funnel_ddr_ch02>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				funnel_ddr_ch02_out_funnel_ddr_0: endpoint {
+					remote-endpoint =
+						<&funnel_ddr_0_in_funnel_ddr_ch02>;
+				};
+			};
+		};
+	};
+
+	funnel_ddr_ch13: funnel@6e22000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6e22000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-ddr-ch13";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port@1 {
+				reg = <0>;
+				funnel_ddr_ch13_in_tpdm_ddr_ch13: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpdm_ddr_ch13_out_funnel_ddr_ch13>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				funnel_ddr_ch13_out_funnel_ddr_0: endpoint {
+					remote-endpoint =
+						<&funnel_ddr_0_in_funnel_ddr_ch13>;
+				};
+			};
+		};
+	};
+
+	tpdm_ddr_ch02: tpdm@6e10000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x06e10000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-ddr-ch02";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		qcom,msr-fix-req;
+
+		out-ports {
+			port {
+				tpdm_ddr_ch02_out_funnel_ddr_ch02: endpoint {
+				remote-endpoint =
+					<&funnel_ddr_ch02_in_tpdm_ddr_ch02>;
+				};
+			};
+		};
+	};
+
+	tpdm_ddr_ch13: tpdm@6e20000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x06e20000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-ddr-ch13";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		qcom,msr-fix-req;
+
+		out-ports {
+			port {
+				tpdm_ddr_ch13_out_funnel_ddr_ch13: endpoint {
+				remote-endpoint =
+					<&funnel_ddr_ch13_in_tpdm_ddr_ch13>;
+				};
+			};
+		};
+	};
+
+	tpdm_ddr: tpdm@6e00000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x06e00000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-ddr";
+
+		status = "disabled";
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_ddr_out_funnel_ddr_0: endpoint {
+				remote-endpoint = <&funnel_ddr_0_in_tpdm_ddr>;
+				};
+			};
+		};
+	};
+
+	funnel_qatb: funnel@6005000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6005000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-qatb";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port@1 {
+				reg = <0>;
+				funnel_qatb_in_tpda: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpda_out_funnel_qatb>;
+				};
+			};
+
+			port@2 {
+				reg = <3>;
+				qatb3_in_funnel_dl_center: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&funnel_dl_center_out_qatb3>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				funnel_qatb_out_funnel_in0: endpoint {
+					remote-endpoint =
+						<&funnel_in0_in_funnel_qatb>;
+				};
+			};
+		};
+	};
+
+	cti0_apss: cti@78e0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x78e0000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-apss_cti0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti1_apss: cti@78f0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x78f0000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-apss_cti1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti2_apss: cti@7900000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x7900000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-apss_cti2";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti0_ddr0: cti@6e01000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6e01000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-ddr_dl_0_cti_0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti1_ddr0: cti@6e02000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6e02000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-ddr_dl_0_cti_1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti2_ddr0: cti@6e03000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6e03000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-ddr_dl_0_cti_2";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti0_ddr1: cti@6e0c000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6e0c000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-ddr_dl_1_cti_0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti1_ddr1: cti@6e0d000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6e0d000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-ddr_dl_1_cti_1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti2_ddr1: cti@6e0e000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6e0e000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-ddr_dl_1_cti_2";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_ddr_ch02: cti@6e11000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6e11000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-ddr_ch02_dl_cti_0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_ddr_ch13: cti@6e21000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6e21000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-ddr_ch13_dl_cti_0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti0_dlmm: cti@6c09000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6c09000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-dlmm_cti0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti1_dlmm: cti@6c0a000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6c0a000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-dlmm_cti1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti0_dlct: cti@6c2a000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6c2a000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-dlct_cti0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti1_dlct: cti@6c2b000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6c2b000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-dlct_cti1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti2_dlct: cti@6c2c000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6c2c000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-dlct_cti2";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti0: cti@6010000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6010000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti1: cti@6011000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6011000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti2: cti@6012000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6012000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti2";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		qcom,cti-gpio-trigout = <4>;
+		pinctrl-names = "cti-trigout-pctrl";
+		pinctrl-0 = <&trigout_a>;
+	};
+
+	cti3: cti@6013000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6013000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti3";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti4: cti@6014000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6014000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti4";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti5: cti@6015000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6015000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti5";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti6: cti@6016000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6016000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti6";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti7: cti@6017000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6017000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti7";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti8: cti@6018000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6018000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti8";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti9: cti@6019000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6019000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti9";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti10: cti@601a000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x601a000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti10";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti11: cti@601b000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x601b000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti11";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti12: cti@601c000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x601c000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti12";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti13: cti@601d000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x601d000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti13";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti14: cti@601e000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x601e000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti14";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti15: cti@601f000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x601f000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti15";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti_cpu0: cti@7020000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x7020000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-cpu0";
+		cpu = <&CPU0>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti_cpu1: cti@7120000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x7120000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-cpu1";
+		cpu = <&CPU1>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_cpu2: cti@7220000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x7220000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-cpu2";
+		cpu = <&CPU2>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_cpu3: cti@7320000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x7320000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-cpu3";
+		cpu = <&CPU3>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_cpu4: cti@7420000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x7420000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-cpu4";
+		cpu = <&CPU4>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_cpu5: cti@7520000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x7520000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-cpu5";
+		cpu = <&CPU5>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_cpu6: cti@7620000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x7620000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-cpu6";
+		cpu = <&CPU6>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_cpu7: cti@7720000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x7720000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-cpu7";
+		cpu = <&CPU7>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_gpu_m3: cti@6962000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6962000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-gpu_cortex_m3";
+		status = "disabled";
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		vddcx-supply = <&gpu_cx_gdsc>;
+		vdd-supply = <&gpu_gx_gdsc>;
+		regulator-names = "vddcx", "vdd";
+		qcom,proxy-regs = "vddcx", "vdd";
+	};
+
+	cti_gpu_isdb: cti@6961000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6961000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-gpu_isdb_cti";
+		status = "disabled";
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		vddcx-supply = <&gpu_cx_gdsc>;
+		vdd-supply = <&gpu_gx_gdsc>;
+		regulator-names = "vddcx", "vdd";
+		qcom,proxy-regs = "vddcx", "vdd";
+	};
+
+	cti_iris: cti@6831000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6831000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-iris_dl_cti";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_lpass: cti@6845000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6845000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-lpass_dl_cti";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_lpass_lpi: cti@6b21000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6b21000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-lpass_lpi_cti";
+		status = "disabled";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_lpass_q6: cti@6b2b000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6b2b000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-lpass_q6_cti";
+		status = "disabled";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_mdss: cti@6c61000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6c61000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-mdss_dl_cti";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_npu_dl0: cti@6c42000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6c42000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-npu_dl_cti_0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_npu_dl1: cti@6c43000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6c43000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-npu_dl_cti_1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_npu: cti@6c4b000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6c4b000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-npu_q6_cti";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_titan: cti@6c13000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6c13000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-sierra_a6_cti";
+		status = "disabled";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_sdc: cti@6b40000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6b40000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-ssc_cortex_m3";
+		status = "disabled";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_ssc0: cti@6b4b000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6b4b000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-ssc_cti0_q6";
+		status = "disabled";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_ssc1: cti@6b41000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6b41000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-ssc_cti1";
+		status = "disabled";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_ssc4: cti@6b4e000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6b4e000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-ssc_cti_noc";
+		status = "disabled";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti0_swao:cti@6b00000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6b00000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-swao_cti0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti1_swao:cti@6b01000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6b01000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-swao_cti1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti2_swao:cti@6b02000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6b02000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-swao_cti2";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti3_swao:cti@6b03000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6b03000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-swao_cti3";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_turing:cti@6982000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6982000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-turing_dl_cti";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_turing_q6:cti@698b000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x698b000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-turing_q6_cti";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_compute:cti@6c38000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb9a8>;
+		reg = <0x6c38000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-compute_dl_cti";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	ipcb_tgu: tgu@6b0b000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb999>;
+		reg = <0x06b0b000 0x1000>;
+		reg-names = "tgu-base";
+		tgu-steps = <3>;
+		tgu-conditions = <4>;
+		tgu-regs = <4>;
+		tgu-timer-counters = <8>;
+
+		coresight-name = "coresight-tgu-ipcb";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	etm_turing: turing_etm0 {
+		compatible = "qcom,coresight-remote-etm";
+
+		coresight-name = "coresight-turing-etm0";
+		qcom,inst-id = <13>;
+
+		out-ports {
+			port {
+				turing_etm0_out_funnel_turing: endpoint {
+					remote-endpoint =
+					<&funnel_turing_in_turing_etm0>;
+				};
+			};
+		};
+	};
+
+		audio_etm0 {
+		compatible = "qcom,coresight-remote-etm";
+
+		coresight-name = "coresight-audio-etm0";
+		qcom,inst-id = <5>;
+
+		out-ports {
+			port {
+				audio_etm0_out_funnel_swao: endpoint {
+					remote-endpoint =
+					<&funnel_swao_in_audio_etm0>;
+				};
+			};
+		};
+	};
+
+		ssc_etm0 {
+		compatible = "qcom,coresight-remote-etm";
+
+		coresight-name = "coresight-ssc-etm0";
+		qcom,inst-id = <8>;
+
+		out-ports {
+			port {
+				ssc_etm0_out_funnel_swao: endpoint {
+					remote-endpoint =
+					<&funnel_swao_in_ssc_etm0>;
+				};
+			};
+		};
+	};
+
+	funnel_apss_merg: funnel@7810000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x7810000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-apss-merg";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port@1 {
+				reg = <0>;
+				funnel_apss_merg_in_funnel_apss: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&funnel_apss_out_funnel_apss_merg>;
+				};
+			};
+
+			port@2 {
+				reg = <3>;
+				funnel_apss_merg_in_tpda_apss: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&tpda_apss_out_funnel_apss_merg>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				funnel_apss_merg_out_funnel_in1: endpoint {
+					remote-endpoint =
+						<&funnel_in1_in_funnel_apss_merg>;
+				};
+			};
+		};
+	};
+
+	etm0: etm@7040000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb95d>;
+
+		reg = <0x7040000 0x1000>;
+		cpu = <&CPU0>;
+
+		qcom,tupwr-disable;
+		coresight-name = "coresight-etm0";
+		qcom,skip-power-up;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				etm0_out_funnel_apss: endpoint {
+				remote-endpoint = <&funnel_apss_in_etm0>;
+				};
+			};
+		};
+	};
+
+	etm1: etm@7140000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb95d>;
+
+		reg = <0x7140000 0x1000>;
+		cpu = <&CPU1>;
+
+		qcom,tupwr-disable;
+		coresight-name = "coresight-etm1";
+		qcom,skip-power-up;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				etm1_out_funnel_apss: endpoint {
+				remote-endpoint = <&funnel_apss_in_etm1>;
+				};
+			};
+		};
+	};
+
+	etm2: etm@7240000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb95d>;
+
+		reg = <0x7240000 0x1000>;
+		cpu = <&CPU2>;
+
+		qcom,tupwr-disable;
+		coresight-name = "coresight-etm2";
+		qcom,skip-power-up;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				etm2_out_funnel_apss: endpoint {
+				remote-endpoint = <&funnel_apss_in_etm2>;
+				};
+			};
+		};
+	};
+
+	etm3: etm@7340000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb95d>;
+
+		reg = <0x7340000 0x1000>;
+		cpu = <&CPU3>;
+
+		qcom,tupwr-disable;
+		coresight-name = "coresight-etm3";
+		qcom,skip-power-up;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				etm3_out_funnel_apss: endpoint {
+				remote-endpoint = <&funnel_apss_in_etm3>;
+				};
+			};
+		};
+	};
+
+	etm4: etm@7440000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb95d>;
+
+		reg = <0x7440000 0x1000>;
+		cpu = <&CPU4>;
+
+		qcom,tupwr-disable;
+		coresight-name = "coresight-etm4";
+		qcom,skip-power-up;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				etm4_out_funnel_apss: endpoint {
+					remote-endpoint = <&funnel_apss_in_etm4>;
+				};
+			};
+		};
+	};
+
+	etm5: etm@7540000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb95d>;
+
+		reg = <0x7540000 0x1000>;
+		cpu = <&CPU5>;
+
+		qcom,tupwr-disable;
+		coresight-name = "coresight-etm5";
+		qcom,skip-power-up;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				etm5_out_funnel_apss: endpoint {
+					remote-endpoint = <&funnel_apss_in_etm5>;
+				};
+			};
+		};
+	};
+
+	etm6: etm@7640000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb95d>;
+
+		reg = <0x7640000 0x1000>;
+		cpu = <&CPU6>;
+
+		qcom,tupwr-disable;
+		coresight-name = "coresight-etm6";
+		qcom,skip-power-up;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				etm6_out_funnel_apss: endpoint {
+					remote-endpoint = <&funnel_apss_in_etm6>;
+				};
+			};
+		};
+	};
+
+	etm7: etm@7740000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb95d>;
+
+		reg = <0x7740000 0x1000>;
+		cpu = <&CPU7>;
+
+		qcom,tupwr-disable;
+		coresight-name = "coresight-etm7";
+		qcom,skip-power-up;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				etm7_out_funnel_apss: endpoint {
+					remote-endpoint = <&funnel_apss_in_etm7>;
+				};
+			};
+		};
+	};
+
+	funnel_apss: funnel@7800000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x7800000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-apss";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port@1 {
+				reg = <0>;
+				funnel_apss_in_etm0: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&etm0_out_funnel_apss>;
+				};
+			};
+
+			port@2 {
+				reg = <1>;
+				funnel_apss_in_etm1: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&etm1_out_funnel_apss>;
+				};
+			};
+
+			port@3 {
+				reg = <2>;
+				funnel_apss_in_etm2: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&etm2_out_funnel_apss>;
+				};
+			};
+
+			port@4 {
+				reg = <3>;
+				funnel_apss_in_etm3: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&etm3_out_funnel_apss>;
+				};
+			};
+
+			port@5 {
+				reg = <4>;
+				funnel_apss_in_etm4: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&etm4_out_funnel_apss>;
+				};
+			};
+
+			port@6 {
+				reg = <5>;
+				funnel_apss_in_etm5: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&etm5_out_funnel_apss>;
+				};
+			};
+
+			port@7 {
+				reg = <6>;
+				funnel_apss_in_etm6: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&etm6_out_funnel_apss>;
+				};
+			};
+
+			port@8 {
+				reg = <7>;
+				funnel_apss_in_etm7: endpoint {
+					slave-mode;
+					remote-endpoint =
+						<&etm7_out_funnel_apss>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				funnel_apss_out_funnel_apss_merg: endpoint {
+					remote-endpoint =
+						<&funnel_apss_merg_in_funnel_apss>;
+				};
+			};
+		};
+	};
+
+	hwevent {
+		compatible = "qcom,coresight-hwevent";
+
+		coresight-name = "coresight-hwevent";
+		coresight-csr = <&csr>;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+};
diff --git a/qcom/kona-hdk-overlay.dts b/qcom/kona-hdk-overlay.dts
new file mode 100755
index 00000000..a208f497
--- /dev/null
+++ b/qcom/kona-hdk-overlay.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+/plugin/;
+
+#include "kona-hdk.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. kona HDK";
+	compatible = "qcom,kona-hdk", "qcom,kona", "qcom,hdk";
+	qcom,board-id = <0x01001f 0x01>;
+};
diff --git a/qcom/kona-hdk.dtsi b/qcom/kona-hdk.dtsi
new file mode 100755
index 00000000..fa9050d0
--- /dev/null
+++ b/qcom/kona-hdk.dtsi
@@ -0,0 +1,12 @@
+#include <dt-bindings/gpio/gpio.h>
+
+&tlmm {
+	key_factory_reset {
+		key_factory_reset_default: key_factory_reset_default {
+			pins = "gpio22";
+			function = "normal";
+			input-enable;
+			bias-pull-up;
+		};
+	};
+};
diff --git a/qcom/kona-iot-v2-rb5-overlay.dts b/qcom/kona-iot-v2-rb5-overlay.dts
new file mode 100755
index 00000000..20084e29
--- /dev/null
+++ b/qcom/kona-iot-v2-rb5-overlay.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+/plugin/;
+
+#include "kona-iot-v2-rb5.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. kona-iot RB5 v2";
+	compatible = "qcom,kona-iot-qrd", "qcom,kona-iot", "qcom,kona-qrd";
+	qcom,board-id = <0x305000b 0x0>;
+};
diff --git a/qcom/kona-iot-v2-rb5.dtsi b/qcom/kona-iot-v2-rb5.dtsi
new file mode 100755
index 00000000..8137efce
--- /dev/null
+++ b/qcom/kona-iot-v2-rb5.dtsi
@@ -0,0 +1,86 @@
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+&soc {
+	gpio_keys {
+		compatible = "gpio-keys";
+		label = "gpio-keys";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&key_vol_up_default>;
+
+		vol_up {
+			label = "volume_up";
+			gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			linux,code = <KEY_VOLUMEUP>;
+			gpio-key,wakeup;
+			debounce-interval = <15>;
+			linux,can-disable;
+		};
+	};
+};
+
+&qupv3_se12_2uart {
+		status = "ok";
+};
+
+&pcie2 {
+		status = "ok";
+		qcom,boot-option = <0x2>;
+		qcom,core-preset = <0x77777777>;
+};
+
+&usb1 {
+	/delete-property/ qcom,default-mode-none;
+	dwc3@a800000 {
+		dr_mode = "host";
+	};
+};
+
+&usb2_phy0 {
+	qcom,param-override-seq = <0x43 0x70>;
+};
+
+&ufsphy_mem {
+		compatible = "qcom,ufs-phy-qmp-v4-kona";
+		vdda-phy-supply = <&pm8150_l5>;
+		vdda-pll-supply = <&pm8150_l9>;
+		vdda-phy-max-microamp = <89900>;
+		vdda-pll-max-microamp = <18800>;
+		status = "ok";
+};
+
+&ufshc_mem {
+		vdd-hba-supply = <&ufs_phy_gdsc>;
+		vcc-supply = <&pm8150_l17>;
+		vccq-supply = <&pm8150_l6>;
+		vccq2-supply = <&pm8150_s4>;
+		vcc-max-microamp = <800000>;
+		vccq-max-microamp = <800000>;
+		vccq2-max-microamp = <800000>;
+
+		qcom,vddp-ref-clk-supply = <&pm8150_l6>;
+		qcom,vddp-ref-clk-max-microamp = <100>;
+		qcom,vccq-parent-supply = <&pm8150a_s8>;
+		qcom,vccq-parent-max-microamp = <210000>;
+		status = "ok";
+};
+
+&sdhc_2 {
+		vdd-supply = <&pm8150a_l9>;
+		qcom,vdd-voltage-level = <2950000 2960000>;
+		qcom,vdd-current-level = <200 800000>;
+
+		vdd-io-supply = <&pm8150a_l6>;
+		qcom,vdd-io-voltage-level = <1808000 2960000>;
+		qcom,vdd-io-current-level = <200 22000>;
+
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&sdc2_on>;
+		pinctrl-1 = <&sdc2_off>;
+
+		cd-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>;
+
+		status = "ok";
+};
diff --git a/qcom/kona-iot-v2.1-rb5.dtsi b/qcom/kona-iot-v2.1-rb5.dtsi
index d90c7e44..f9940cd2 100755
--- a/qcom/kona-iot-v2.1-rb5.dtsi
+++ b/qcom/kona-iot-v2.1-rb5.dtsi
@@ -1,12 +1,29 @@
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "kona-pmic-overlay.dtsi"
 
-&tlmm {
-	key_factory_reset {
-		key_factory_reset_default: key_factory_reset_default {
-			pins = "gpio22";
-			function = "normal";
-			input-enable;
-			bias-pull-up;
+&vendor {
+	kona_qrd_batterydata: qcom,battery-data {
+		qcom,batt-id-range-pct = <15>;
+	};
+};
+
+&soc {
+	gpio_keys {
+		compatible = "gpio-keys";
+		label = "gpio-keys";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&key_vol_up_default>;
+
+		vol_up {
+			label = "volume_up";
+			gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			linux,code = <KEY_VOLUMEUP>;
+			gpio-key,wakeup;
+			debounce-interval = <15>;
+			linux,can-disable;
 		};
 	};
 };
@@ -14,3 +31,360 @@
 &qupv3_se12_2uart {
 		status = "ok";
 };
+
+&ufsphy_mem {
+		compatible = "qcom,ufs-phy-qmp-v4-kona";
+		vdda-phy-supply = <&pm8150_l5>;
+		vdda-pll-supply = <&pm8150_l9>;
+		vdda-phy-max-microamp = <89900>;
+		vdda-pll-max-microamp = <18800>;
+		status = "ok";
+};
+
+&ufshc_mem {
+		vdd-hba-supply = <&ufs_phy_gdsc>;
+		vcc-supply = <&pm8150_l17>;
+		vccq-supply = <&pm8150_l6>;
+		vccq2-supply = <&pm8150_s4>;
+		vcc-max-microamp = <800000>;
+		vccq-max-microamp = <800000>;
+		vccq2-max-microamp = <800000>;
+
+		qcom,vddp-ref-clk-supply = <&pm8150_l6>;
+		qcom,vddp-ref-clk-max-microamp = <100>;
+		qcom,vccq-parent-supply = <&pm8150a_s8>;
+		qcom,vccq-parent-max-microamp = <210000>;
+		status = "ok";
+};
+
+&pcie2 {
+		status = "ok";
+		qcom,boot-option = <0x0>;
+		qcom,core-preset = <0x77777777>;
+		pinctrl-0 = <&pcie2_perst_default
+				&pcie2_clkreq_default
+				&pcie2_wake_default>;
+};
+
+&sdhc_2 {
+		vdd-supply = <&pm8150a_l9>;
+		qcom,vdd-voltage-level = <2950000 2960000>;
+		qcom,vdd-current-level = <200 800000>;
+
+		vdd-io-supply = <&pm8150a_l6>;
+		qcom,vdd-io-voltage-level = <1808000 2960000>;
+		qcom,vdd-io-current-level = <200 22000>;
+
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&sdc2_on>;
+		pinctrl-1 = <&sdc2_off>;
+
+		cd-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>;
+
+		status = "ok";
+};
+
+&pm8150l_gpios {
+	lt9611_rst_pin_out {
+		lt9611_rst_pin_out_default: lt9611_rst_pin_out_default {
+		pins = "gpio5";
+		function = "normal";
+		output-enable;
+		input-disable;
+		bias-pull-down;
+		power-source = <0>;
+		};
+	};
+
+	rb5_fan_controller_pin_init: rb5_fan_controller_pin_init {
+		pins = "gpio10";
+		function = "normal";
+		output-enable;
+		input-disable;
+		bias-pull-down;
+		power-source = <0>;
+	};
+};
+
+&L11C {
+	regulator-always-on;
+};
+
+&vreg_hap_boost {
+	status = "ok";
+};
+
+&pm8150b_pdphy {
+	#io-channel-cells = <1>;
+	io-channels = <&pm8150b_charger PSY_IIO_PD_ACTIVE>,
+		      <&pm8150b_charger PSY_IIO_TYPEC_CC_ORIENTATION>,
+		      <&pm8150b_charger PSY_IIO_CONNECTOR_TYPE>,
+		      <&pm8150b_charger PSY_IIO_TYPEC_POWER_ROLE>,
+		      <&pm8150b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>,
+		      <&pm8150b_charger PSY_IIO_TYPEC_SRC_RP>,
+		      <&pm8150b_charger PSY_IIO_PD_IN_HARD_RESET>,
+		      <&pm8150b_charger PSY_IIO_PD_CURRENT_MAX>,
+		      <&pm8150b_charger PSY_IIO_PR_SWAP>,
+		      <&pm8150b_charger PSY_IIO_PD_VOLTAGE_MIN>,
+		      <&pm8150b_charger PSY_IIO_PD_VOLTAGE_MAX>,
+		      <&pm8150b_charger PSY_IIO_USB_REAL_TYPE>,
+		      <&pm8150b_charger PSY_IIO_TYPEC_MODE>,
+		      <&pm8150b_charger PSY_IIO_PE_START>;
+	io-channel-names = "pd_active",
+			   "typec_cc_orientation",
+			   "connector_type",
+			   "typec_power_role",
+			   "pd_usb_suspend_supported",
+			   "typec_src_rp",
+			   "pd_in_hard_reset",
+			   "pr_current_max",
+			   "pr_swap",
+			   "pd_voltage_min",
+			   "pd_voltage_max",
+			   "real_type",
+			   "typec_mode",
+			   "pe_start";
+};
+
+&pm8150b_haptics {
+	qcom,vmax-mv = <1697>;
+	qcom,play-rate-us = <5882>;
+	vdd-supply = <&vreg_hap_boost>;
+
+	wf_0 {
+		/* CLICK */
+		qcom,wf-play-rate-us = <5882>;
+		qcom,wf-vmax-mv = <1697>;
+	};
+
+	wf_1 {
+		/* DOUBLE CLICK */
+		qcom,wf-play-rate-us = <5882>;
+		qcom,wf-vmax-mv = <1697>;
+	};
+
+	wf_2 {
+		/* TICK */
+		qcom,wf-play-rate-us = <5882>;
+		qcom,wf-vmax-mv = <1697>;
+	};
+
+	wf_3 {
+		/* THUD */
+		qcom,wf-play-rate-us = <5882>;
+		qcom,wf-vmax-mv = <1697>;
+	};
+
+	wf_4 {
+		/* POP */
+		qcom,wf-play-rate-us = <5882>;
+		qcom,wf-vmax-mv = <1697>;
+	};
+
+	wf_5 {
+		/* HEAVY CLICK */
+		qcom,wf-play-rate-us = <5882>;
+		qcom,wf-vmax-mv = <1697>;
+	};
+};
+
+&pm8150b_charger {
+	#io-channel-cells = <1>;
+	qcom,sec-charger-config = <1>;
+	qcom,auto-recharge-soc = <98>;
+	io-channels = <&pm8150b_vadc ADC5_USB_IN_V_16>,
+		      <&pm8150b_vadc ADC5_USB_IN_I>,
+		      <&pm8150b_vadc ADC5_SBUx>,
+		      <&pm8150b_vadc ADC5_VPH_PWR>,
+		      <&pm8150b_vadc ADC5_DIE_TEMP>,
+		      <&pm8150b_vadc ADC5_MID_CHG_DIV6>,
+		      <&pm8150b_vadc ADC5_CHG_TEMP>;
+	io-channel-names = "usb_in_voltage",
+			   "usb_in_current",
+			   "sbux_res",
+			   "vph_voltage",
+			   "die_temp",
+			   "mid_voltage",
+			   "chg_temp";
+	qcom,batteryless-platform;
+	qcom,lpd-disable;
+	qcom,sw-jeita-enable;
+	qcom,wd-bark-time-secs = <16>;
+	qcom,suspend-input-on-debug-batt;
+	qcom,fcc-stepping-enable;
+	qcom,smb-internal-pull-kohm = <0>;
+	qcom,thermal-mitigation = <5325000 4500000 4000000 3500000 3000000
+				2500000 2000000 1500000 1000000 500000>;
+};
+
+&pm8150b_fg {
+	status = "ok";
+	qcom,battery-data = <&kona_qrd_batterydata>;
+	qcom,hold-soc-while-full;
+	qcom,linearize-soc;
+	qcom,five-pin-battery;
+	qcom,cl-wt-enable;
+	qcom,soc-scale-mode-en;
+	/* ESR fast calibration */
+	qcom,fg-esr-timer-chg-fast = <0 7>;
+	qcom,fg-esr-timer-dischg-fast = <0 7>;
+	qcom,fg-esr-timer-chg-slow = <0 96>;
+	qcom,fg-esr-timer-dischg-slow = <0 96>;
+	qcom,fg-esr-cal-soc-thresh = <26 230>;
+	qcom,fg-esr-cal-temp-thresh = <10 40>;
+};
+
+&pm8150l_vadc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	vph_pwr@83 {
+		reg = <ADC5_VPH_PWR>;
+		label = "vph_pwr";
+		qcom,pre-scaling = <1 3>;
+	};
+
+	camera_flash_therm@4d {
+		reg = <ADC5_AMUX_THM1_100K_PU>;
+		label = "camera_flash_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	skin_msm_therm@4e {
+		reg = <ADC5_AMUX_THM2_100K_PU>;
+		label = "skin_msm_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pa_therm2@4f {
+		reg = <ADC5_AMUX_THM3_100K_PU>;
+		label = "pa_therm2";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+};
+
+&pm8150b_vadc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	conn_therm@4f {
+		reg = <ADC5_AMUX_THM3_100K_PU>;
+		label = "conn_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	mid_chg_div6@1e {
+		reg = <ADC5_MID_CHG_DIV6>;
+		label = "chg_mid";
+		qcom,pre-scaling = <1 6>;
+	};
+};
+
+&pm8150_vadc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	vph_pwr@83 {
+		reg = <ADC5_VPH_PWR>;
+		label = "vph_pwr";
+		qcom,pre-scaling = <1 3>;
+	};
+
+	xo_therm@4c {
+		reg = <ADC5_XO_THERM_100K_PU>;
+		label = "xo_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	skin_therm@4d {
+		reg = <ADC5_AMUX_THM1_100K_PU>;
+		label = "skin_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pa_therm1@4e {
+		reg = <ADC5_AMUX_THM2_100K_PU>;
+		label = "pa_therm1";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+};
+
+&pm8150b_adc_tm {
+	conn_therm@4f {
+		reg = <0>;
+		io-channels = <&pm8150b_vadc ADC5_AMUX_THM3_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+};
+
+&pm8150_adc_tm {
+	xo_therm@4c {
+		reg = <0>;
+		io-channels = <&pm8150_vadc ADC5_XO_THERM_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+
+	skin_therm@4d {
+		reg = <1>;
+		io-channels = <&pm8150_vadc ADC5_AMUX_THM1_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+
+	pa_therm1@4e {
+		reg = <2>;
+		io-channels = <&pm8150_vadc ADC5_AMUX_THM2_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+};
+
+&pm8150l_adc_tm {
+	camera_flash_therm@4d {
+		reg = <0>;
+		io-channels = <&pm8150l_vadc ADC5_AMUX_THM1_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+
+	skin_msm_therm@4e {
+		reg = <1>;
+		io-channels = <&pm8150l_vadc ADC5_AMUX_THM2_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+
+	pa_therm2@4f {
+		reg = <2>;
+		io-channels = <&pm8150l_vadc ADC5_AMUX_THM3_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+};
+
+&usb1 {
+	/delete-property/ qcom,default-mode-none;
+	dwc3@a800000 {
+		dr_mode = "host";
+	};
+};
+
+&usb2_phy0 {
+	qcom,param-override-seq = <0x43 0x70>;
+};
diff --git a/qcom/kona-iot-v2.1-vc.dtsi b/qcom/kona-iot-v2.1-vc.dtsi
index 5c17996d..01713786 100755
--- a/qcom/kona-iot-v2.1-vc.dtsi
+++ b/qcom/kona-iot-v2.1-vc.dtsi
@@ -1 +1,5 @@
 #include "kona-iot-vc.dtsi"
+
+&dwc1 {
+	dr_mode = "host";
+};
diff --git a/qcom/kona-iot-vc.dtsi b/qcom/kona-iot-vc.dtsi
index 21036bd0..1f120cdb 100755
--- a/qcom/kona-iot-vc.dtsi
+++ b/qcom/kona-iot-vc.dtsi
@@ -10,6 +10,15 @@
 };
 
 &tlmm {
+	key_camera_switch {
+		key_camera_switch_default: key_camera_switch_default {
+			pins = "gpio26";
+			function = "normal";
+			input-enable;
+			bias-pull-up;
+		};
+	};
+
 	key_factory_reset {
 		key_factory_reset_default: key_factory_reset_default {
 			pins = "gpio22";
@@ -18,8 +27,68 @@
 			bias-pull-up;
 		};
 	};
+
+	line_out_hpd {
+		line_out_hpd_default: line_out_hpd_default {
+			pins = "gpio32";
+			function = "gpio";
+			input-enable;
+			bias-pull-up;
+		};
+	};
+};
+
+&soc {
+	gpio_keys {
+		compatible = "gpio-keys";
+		label = "gpio-keys";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&key_vol_up_default &key_camera_switch_default &key_home_default &key_factory_reset_default>;
+
+		vol_up {
+			label = "volume_up";
+			gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			linux,code = <KEY_VOLUMEUP>;
+			gpio-key,wakeup;
+			debounce-interval = <15>;
+			linux,can-disable;
+		};
+
+		camera_switch {
+			label = "camera_switch";
+			gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			linux,code = <KEY_CAMERA>;
+			gpio-key,wakeup;
+			debounce-interval = <15>;
+			linux,can-disable;
+		};
+
+		mute {
+			label = "mute";
+			gpios = <&pm8150_gpios 1 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			linux,code = <KEY_MUTE>;
+			gpio-key,wakeup;
+			debounce-interval = <15>;
+			linux,can-disable;
+		};
+
+		factory_reset {
+			label = "factory_reset";
+			gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			linux,code = <KEY_F24>;
+			gpio-key,wakeup;
+			debounce-interval = <15>;
+			linux,can-disable;
+		};
+	};
 };
 
+
 &qupv3_se12_2uart {
 		status = "ok";
 };
@@ -145,7 +214,7 @@
 			   "die_temp",
 			   "mid_voltage",
 			   "chg_temp";
-	qcom,battery-data = <&kona_qrd_batterydata>;
+	qcom,batteryless-platform;
 	qcom,sw-jeita-enable;
 	qcom,wd-bark-time-secs = <16>;
 	qcom,suspend-input-on-debug-batt;
@@ -236,12 +305,6 @@
 		qcom,pre-scaling = <1 3>;
 	};
 
-	vcoin@85 {
-		reg = <ADC5_VCOIN>;
-		label = "vcoin";
-		qcom,pre-scaling = <1 3>;
-	};
-
 	xo_therm@4c {
 		reg = <ADC5_XO_THERM_100K_PU>;
 		label = "xo_therm";
@@ -268,93 +331,73 @@
 };
 
 &pm8150b_adc_tm {
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	io-channels = <&pm8150b_vadc ADC5_AMUX_THM3_100K_PU>;
-
 	conn_therm@4f {
-		reg = <ADC5_AMUX_THM3_100K_PU>;
+		reg = <0>;
+		io-channels = <&pm8150b_vadc ADC5_AMUX_THM3_100K_PU>;
 		qcom,ratiometric;
 		qcom,hw-settle-time = <200>;
 	};
 };
 
 &pm8150_adc_tm {
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	io-channels = <&pm8150_vadc ADC5_XO_THERM_100K_PU>,
-			<&pm8150_vadc ADC5_AMUX_THM1_100K_PU>,
-			<&pm8150_vadc ADC5_AMUX_THM2_100K_PU>;
-
 	xo_therm@4c {
-		reg = <ADC5_XO_THERM_100K_PU>;
+		reg = <0>;
+		io-channels = <&pm8150_vadc ADC5_XO_THERM_100K_PU>;
 		qcom,ratiometric;
 		qcom,hw-settle-time = <200>;
 	};
 
 	skin_therm@4d {
-		reg = <ADC5_AMUX_THM1_100K_PU>;
+		reg = <1>;
+		io-channels = <&pm8150_vadc ADC5_AMUX_THM1_100K_PU>;
 		qcom,ratiometric;
 		qcom,hw-settle-time = <200>;
 	};
 
 	pa_therm1@4e {
-		reg = <ADC5_AMUX_THM2_100K_PU>;
+		reg = <2>;
+		io-channels = <&pm8150_vadc ADC5_AMUX_THM2_100K_PU>;
 		qcom,ratiometric;
 		qcom,hw-settle-time = <200>;
 	};
 };
 
 &pm8150l_adc_tm {
-	#address-cells = <1>;
-	#size-cells = <0>;
-
 	camera_flash_therm@4d {
-		reg = <ADC5_AMUX_THM1_100K_PU>;
+		reg = <0>;
+		io-channels = <&pm8150l_vadc ADC5_AMUX_THM1_100K_PU>;
 		qcom,ratiometric;
 		qcom,hw-settle-time = <200>;
 	};
 
 	skin_msm_therm@4e {
-		reg = <ADC5_AMUX_THM2_100K_PU>;
+		reg = <1>;
+		io-channels = <&pm8150l_vadc ADC5_AMUX_THM2_100K_PU>;
 		qcom,ratiometric;
 		qcom,hw-settle-time = <200>;
 	};
 
 	pa_therm2@4f {
-		reg = <ADC5_AMUX_THM3_100K_PU>;
+		reg = <2>;
+		io-channels = <&pm8150l_vadc ADC5_AMUX_THM3_100K_PU>;
 		qcom,ratiometric;
 		qcom,hw-settle-time = <200>;
 	};
 };
 
 &thermal_zones {
-	status = "ok";
-	conn-therm-usr {
+	conn-therm {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
-		thermal-sensors = <&pm8150b_adc_tm ADC5_AMUX_THM3_100K_PU>;
-		wake-capable-sensor;
+		thermal-sensors = <&pm8150b_adc_tm 0>;
 		trips {
 			active-config0 {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
-		};
-	};
 
-	xo-therm-usr {
-		polling-delay-passive = <0>;
-		polling-delay = <0>;
-		thermal-governor = "user_space";
-		thermal-sensors = <&pm8150_adc_tm ADC5_XO_THERM_100K_PU>;
-		wake-capable-sensor;
-		trips {
-			active-config0 {
+			active-config1 {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
@@ -362,161 +405,144 @@
 		};
 	};
 
-	skin-therm-usr {
+	xo-therm {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
-		thermal-sensors = <&pm8150_adc_tm ADC5_AMUX_THM1_100K_PU>;
-		wake-capable-sensor;
+		thermal-sensors = <&pm8150_adc_tm 0>;
 		trips {
 			active-config0 {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
-		};
-	};
 
-	mmw-pa1-usr {
-		polling-delay-passive = <0>;
-		polling-delay = <0>;
-		thermal-governor = "user_space";
-		thermal-sensors = <&pm8150_adc_tm ADC5_AMUX_THM2_100K_PU>;
-		wake-capable-sensor;
-		trips {
-			active-config0 {
+			active-config1 {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
-		};
-	};
 
-	camera-therm-usr {
-		polling-delay-passive = <0>;
-		polling-delay = <0>;
-		thermal-governor = "user_space";
-		thermal-sensors = <&pm8150l_adc_tm ADC5_AMUX_THM1_100K_PU>;
-		wake-capable-sensor;
-		trips {
-			active-config0 {
-				temperature = <125000>;
-				hysteresis = <1000>;
+			xo_lvl0: xo-config0 {
+				temperature = <42000>;
+				hysteresis = <2000>;
 				type = "passive";
 			};
-		};
-	};
 
-	skin-msm-therm-usr {
-		polling-delay-passive = <0>;
-		polling-delay = <0>;
-		thermal-governor = "user_space";
-		thermal-sensors = <&pm8150l_adc_tm ADC5_AMUX_THM2_100K_PU>;
-		wake-capable-sensor;
-		trips {
-			active-config0 {
-				temperature = <125000>;
-				hysteresis = <1000>;
+			xo_lvl1: xo-config1 {
+				temperature = <46000>;
+				hysteresis = <2000>;
+				type = "passive";
+			};
+
+			xo_lvl2: xo-config2 {
+				temperature = <56000>;
+				hysteresis = <6000>;
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			xo_skin_lvl0 {
+				trip = <&xo_lvl0>;
+				cooling-device = <&modem_mmw_skin2 1 1>;
+			};
+
+			xo_skin_lvl1 {
+				trip = <&xo_lvl1>;
+				cooling-device = <&modem_mmw_skin2 2 2>;
+			};
+
+			xo_skin_lvl2 {
+				trip = <&xo_lvl2>;
+				cooling-device = <&modem_mmw_skin2 3 3>;
+			};
+		};
 	};
 
-	mmw-pa2-usr {
+	skin-therm {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
-		thermal-sensors = <&pm8150l_adc_tm ADC5_AMUX_THM3_100K_PU>;
-		wake-capable-sensor;
+		thermal-sensors = <&pm8150_adc_tm 1>;
 		trips {
 			active-config0 {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
-		};
-	};
 
-	skin-msm-therm-step {
-		polling-delay-passive = <0>;
-		polling-delay = <0>;
-		thermal-governor = "step_wise";
-		thermal-sensors = <&pm8150l_adc_tm ADC5_AMUX_THM2_100K_PU>;
-		wake-capable-sensor;
-		trips {
-			skin_trip: skin-config0 {
-				temperature = <46000>;
-				hysteresis = <0>;
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
 				type = "passive";
 			};
-		};
-
-	};
 
-	xo-therm-step {
-		polling-delay-passive = <0>;
-		polling-delay = <0>;
-		thermal-governor = "step_wise";
-		thermal-sensors = <&pm8150_adc_tm ADC5_XO_THERM_100K_PU>;
-
-		trips {
-			xo_lvl0: active-config0 {
-				temperature = <42000>;
-				hysteresis = <2000>;
+			skin_therm0: skin_therm-config0 {
+				temperature = <62000>;
+				hysteresis = <5000>;
 				type = "passive";
 			};
 
-			xo_lvl1: active-config1 {
-				temperature = <46000>;
-				hysteresis = <2000>;
+			skin_therm1: skin_therm-config1 {
+				temperature = <65000>;
+				hysteresis = <5000>;
 				type = "passive";
 			};
 
-			xo_lvl2: active-config2 {
-				temperature = <56000>;
-				hysteresis = <6000>;
+			skin_therm2: skin_therm-config2 {
+				temperature = <72000>;
+				hysteresis = <2000>;
 				type = "passive";
 			};
 		};
 
 		cooling-maps {
-			xo_skin_lvl0 {
-				trip = <&xo_lvl0>;
-				cooling-device = <&modem_mmw_skin2 1 1>;
+			skin_lvl0 {
+				trip = <&skin_therm0>;
+				cooling-device = <&modem_skin 1 1>;
 			};
 
-			xo_skin_lvl1 {
-				trip = <&xo_lvl1>;
-				cooling-device = <&modem_mmw_skin2 2 2>;
+			skin_lvl1 {
+				trip = <&skin_therm1>;
+				cooling-device = <&modem_skin 2 2>;
 			};
 
-			xo_skin_lvl2 {
-				trip = <&xo_lvl2>;
-				cooling-device = <&modem_mmw_skin2 3 3>;
+			skin_lvl2 {
+				trip = <&skin_therm2>;
+				cooling-device = <&modem_skin 3 3>;
 			};
 		};
 	};
 
-	mmw-pa1-step {
+	mmw-pa1 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "step_wise";
-		thermal-sensors = <&pm8150_adc_tm ADC5_AMUX_THM2_100K_PU>;
-
+		thermal-sensors = <&pm8150_adc_tm 2>;
 		trips {
-			pa1_lvl0: active-config0 {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			pa1_lvl0: mmw_pa1-config0 {
 				temperature = <44000>;
 				hysteresis = <5000>;
 				type = "passive";
 			};
 
-			pa1_lvl1: active-config1 {
+			pa1_lvl1: mmw_pa1-config1 {
 				temperature = <48000>;
 				hysteresis = <2000>;
 				type = "passive";
 			};
 
-			pa1_lvl2: active-config2 {
+			pa1_lvl2: mmw_pa1-config2 {
 				temperature = <56000>;
 				hysteresis = <6000>;
 				type = "passive";
@@ -541,95 +567,102 @@
 		};
 	};
 
-	mmw-pa2-step {
+	camera-therm {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "step_wise";
-		thermal-sensors = <&pm8150l_adc_tm ADC5_AMUX_THM3_100K_PU>;
-
+		thermal-sensors = <&pm8150l_adc_tm 0>;
 		trips {
-			pa2_lvl0: active-config0 {
-				temperature = <42000>;
-				hysteresis = <4000>;
-				type = "passive";
-			};
-
-			pa2_lvl1: active-config1 {
-				temperature = <46000>;
-				hysteresis = <2000>;
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
 				type = "passive";
 			};
 
-			pa2_lvl2: active-config2 {
-				temperature = <56000>;
-				hysteresis = <6000>;
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
 				type = "passive";
 			};
 		};
+	};
 
-		cooling-maps {
-			pa2_skin_lvl0 {
-				trip = <&pa2_lvl0>;
-				cooling-device = <&modem_mmw_skin1 1 1>;
+	skin-msm-therm {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm8150l_adc_tm 1>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
 			};
 
-			pa2_skin_lvl1 {
-				trip = <&pa2_lvl1>;
-				cooling-device = <&modem_mmw_skin1 2 2>;
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
 			};
 
-			pa2_skin_lvl2 {
-				trip = <&pa2_lvl2>;
-				cooling-device = <&modem_mmw_skin1 3 3>;
+			skin_trip: skin-config0 {
+				temperature = <46000>;
+				hysteresis = <0>;
+				type = "passive";
 			};
 		};
 	};
 
-	skin-therm-step {
+	mmw-pa2 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "step_wise";
-		thermal-sensors = <&pm8150_adc_tm ADC5_AMUX_THM1_100K_PU>;
-		wake-capable-sensor;
-		disable-thermal-zone;
-
+		thermal-sensors = <&pm8150l_adc_tm 2>;
 		trips {
-			skin_therm0: active-config0 {
-				temperature = <62000>;
-				hysteresis = <5000>;
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
 				type = "passive";
 			};
 
-			skin_therm1: active-config1 {
-				temperature = <65000>;
-				hysteresis = <5000>;
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
 				type = "passive";
 			};
 
-			skin_therm2: active-config2 {
-				temperature = <72000>;
+			pa2_lvl0: mmw_pa2-config0 {
+				temperature = <42000>;
+				hysteresis = <4000>;
+				type = "passive";
+			};
+
+			pa2_lvl1: mmw_pa2-config1 {
+				temperature = <46000>;
 				hysteresis = <2000>;
 				type = "passive";
 			};
+
+			pa2_lvl2: mmw_pa2-config2 {
+				temperature = <56000>;
+				hysteresis = <6000>;
+				type = "passive";
+			};
 		};
 
 		cooling-maps {
-			skin_lvl0 {
-				trip = <&skin_therm0>;
-				cooling-device = <&modem_skin 1 1>;
+			pa2_skin_lvl0 {
+				trip = <&pa2_lvl0>;
+				cooling-device = <&modem_mmw_skin1 1 1>;
 			};
 
-			skin_lvl1 {
-				trip = <&skin_therm1>;
-				cooling-device = <&modem_skin 2 2>;
+			pa2_skin_lvl1 {
+				trip = <&pa2_lvl1>;
+				cooling-device = <&modem_mmw_skin1 2 2>;
 			};
 
-			skin_lvl2 {
-				trip = <&skin_therm2>;
-				cooling-device = <&modem_skin 3 3>;
+			pa2_skin_lvl2 {
+				trip = <&pa2_lvl2>;
+				cooling-device = <&modem_mmw_skin1 3 3>;
 			};
 		};
-
 	};
 };
 
diff --git a/qcom/kona-pcie.dtsi b/qcom/kona-pcie.dtsi
index e2e5d57a..fe2772ec 100755
--- a/qcom/kona-pcie.dtsi
+++ b/qcom/kona-pcie.dtsi
@@ -91,7 +91,7 @@
 		clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
 					<0>, <0>, <0>, <0>, <100000000>, <0>, <0>;
 		clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
-					<0>, <0>, <0>, <0>, <0>;
+					<1>, <1>, <1>, <0>, <0>;
 
 		resets = <&gcc GCC_PCIE_0_BCR>,
 			<&gcc GCC_PCIE_0_PHY_BCR>;
@@ -113,6 +113,7 @@
 		qcom,slv-addr-space-size = <0x4000000>;
 		qcom,ep-latency = <10>;
 		qcom,num-parf-testbus-sel = <0xb9>;
+		qcom,gdsc-clk-drv-ss-nonvotable;
 
 		qcom,pcie-phy-ver = <1102>;
 		qcom,phy-status-offset = <0x814>;
@@ -383,6 +384,7 @@
 		qcom,slv-addr-space-size = <0x20000000>;
 		qcom,ep-latency = <10>;
 		qcom,num-parf-testbus-sel = <0xb9>;
+		qcom,gdsc-clk-drv-ss-nonvotable;
 
 		qcom,pcie-phy-ver = <1102>;
 		qcom,phy-status-offset = <0xa14>;
@@ -688,6 +690,7 @@
 		qcom,slv-addr-space-size = <0x4000000>;
 		qcom,ep-latency = <10>;
 		qcom,num-parf-testbus-sel = <0xb9>;
+		qcom,gdsc-clk-drv-ss-nonvotable;
 
 		qcom,pcie-phy-ver = <1102>;
 		qcom,phy-status-offset = <0xa14>;
diff --git a/qcom/kona-pmic-overlay.dtsi b/qcom/kona-pmic-overlay.dtsi
index a3a9b2d0..1c290005 100755
--- a/qcom/kona-pmic-overlay.dtsi
+++ b/qcom/kona-pmic-overlay.dtsi
@@ -35,6 +35,33 @@
 	};
 };
 
+&pm8150_0 {
+	/delete-node/ qcom,power-on@800;
+	qcom,power-on@800 {
+		compatible = "qcom,qpnp-power-on";
+		reg = <0x800>;
+		interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>,
+			     <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>;
+		interrupt-names = "kpdpwr", "resin";
+		qcom,pon-dbc-delay = <15625>;
+		qcom,kpdpwr-sw-debounce;
+		qcom,system-reset;
+		qcom,store-hard-reset-reason;
+
+		qcom,pon_1 {
+			qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
+			linux,code = <KEY_POWER>;
+			qcom,pull-up;
+		};
+
+		qcom,pon_2 {
+			qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;
+			linux,code = <KEY_VOLUMEDOWN>;
+			qcom,pull-up;
+		};
+	};
+};
+
 &pm8150_gpios {
 	key_home {
 		key_home_default: key_home_default {
@@ -152,6 +179,24 @@
 	nvmem = <&pm8150_sdam_2>;
 };
 
+&pm8150b_charger {
+	status = "ok";
+	dpdm-supply = <&usb2_phy0>;
+	smb5_vconn: qcom,smb5-vconn {
+		regulator-name = "smb5-vconn";
+	};
+
+	smb5_vbus: qcom,smb5-vbus {
+		regulator-name = "smb5-vbus";
+	};
+};
+
+&pm8150b_pdphy {
+	vdd-pdphy-supply = <&pm8150_l2>;
+	vbus-supply = <&smb5_vbus>;
+	vconn-supply = <&smb5_vconn>;
+};
+
 &pm8150b_gpios {
 	haptics_boost {
 		haptics_boost_default: haptics_boost_default {
@@ -188,3 +233,11 @@
 		status = "okay";
 	};
 };
+
+&usb0 {
+	status = "ok";
+	extcon = <&pm8150b_pdphy>, <&eud>;
+	#io-channel-cells = <1>;
+	io-channels= <&pm8150b_charger PSY_IIO_USB_REAL_TYPE>;
+	io-channel-names = "chg_type";
+};
diff --git a/qcom/kona-rb5-HDMI-overlay.dts b/qcom/kona-rb5-HDMI-overlay.dts
new file mode 100755
index 00000000..f4eea066
--- /dev/null
+++ b/qcom/kona-rb5-HDMI-overlay.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+/plugin/;
+
+#include "kona-rb5-HDMI.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Robotics RB5 Platform with HDMI adapter card";
+	compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+	qcom,board-id = <0x5010008 0x0>;
+};
diff --git a/qcom/kona-rb5-HDMI.dtsi b/qcom/kona-rb5-HDMI.dtsi
new file mode 100755
index 00000000..ab445afb
--- /dev/null
+++ b/qcom/kona-rb5-HDMI.dtsi
@@ -0,0 +1,69 @@
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+&soc {
+	gpio_keys {
+		compatible = "gpio-keys";
+		label = "gpio-keys";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&key_vol_up_default>;
+
+		vol_up {
+			label = "volume_up";
+			gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			linux,code = <KEY_VOLUMEUP>;
+			gpio-key,wakeup;
+			debounce-interval = <15>;
+			linux,can-disable;
+		};
+	};
+};
+
+&qupv3_se12_2uart {
+		status = "ok";
+};
+
+&ufsphy_mem {
+		compatible = "qcom,ufs-phy-qmp-v4-kona";
+		vdda-phy-supply = <&pm8150_l5>;
+		vdda-pll-supply = <&pm8150_l9>;
+		vdda-phy-max-microamp = <89900>;
+		vdda-pll-max-microamp = <18800>;
+		status = "ok";
+};
+
+&ufshc_mem {
+		vdd-hba-supply = <&ufs_phy_gdsc>;
+		vcc-supply = <&pm8150_l17>;
+		vccq-supply = <&pm8150_l6>;
+		vccq2-supply = <&pm8150_s4>;
+		vcc-max-microamp = <800000>;
+		vccq-max-microamp = <800000>;
+		vccq2-max-microamp = <800000>;
+
+		qcom,vddp-ref-clk-supply = <&pm8150_l6>;
+		qcom,vddp-ref-clk-max-microamp = <100>;
+		qcom,vccq-parent-supply = <&pm8150a_s8>;
+		qcom,vccq-parent-max-microamp = <210000>;
+		status = "ok";
+};
+
+&sdhc_2 {
+		vdd-supply = <&pm8150a_l9>;
+		qcom,vdd-voltage-level = <2950000 2960000>;
+		qcom,vdd-current-level = <200 800000>;
+
+		vdd-io-supply = <&pm8150a_l6>;
+		qcom,vdd-io-voltage-level = <1808000 2960000>;
+		qcom,vdd-io-current-level = <200 22000>;
+
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&sdc2_on>;
+		pinctrl-1 = <&sdc2_off>;
+
+		cd-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>;
+
+		status = "ok";
+};
diff --git a/qcom/kona-rb5-overlay.dts b/qcom/kona-rb5-overlay.dts
new file mode 100755
index 00000000..d8832c7e
--- /dev/null
+++ b/qcom/kona-rb5-overlay.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+/plugin/;
+
+#include "kona-iot-v2.1-rb5.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Robotics RB5 Platform";
+	compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+	qcom,board-id = <0x4010008 0x0>;
+};
diff --git a/qcom/kona-smp2p.dtsi b/qcom/kona-smp2p.dtsi
new file mode 100755
index 00000000..d4da7157
--- /dev/null
+++ b/qcom/kona-smp2p.dtsi
@@ -0,0 +1,133 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/qcom,ipcc.h>
+
+&soc {
+
+	qcom,smp2p-adsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <443>, <429>;
+		interrupt-parent = <&ipcc_mproc>;
+		interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
+			      IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
+			  IPCC_MPROC_SIGNAL_SMP2P>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <2>;
+
+		adsp_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		adsp_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
+			qcom,entry-name = "rdbg";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
+			qcom,entry-name = "rdbg";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	qcom,smp2p-dsps {
+		compatible = "qcom,smp2p";
+		qcom,smem = <481>, <430>;
+		interrupt-parent = <&ipcc_mproc>;
+		interrupts = <IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_SMP2P
+			      IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc_mproc IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_SMP2P>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <3>;
+
+		dsps_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		dsps_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		sleepstate_smp2p_out: sleepstate-out {
+			qcom,entry-name = "sleepstate";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		sleepstate_smp2p_in: qcom,sleepstate-in {
+			qcom,entry-name = "sleepstate_see";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	qcom,smp2p-cdsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <94>, <432>;
+		interrupt-parent = <&ipcc_mproc>;
+		interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
+			      IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <5>;
+
+		cdsp_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		cdsp_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		smp2p_qvrexternal5_out: qcom,smp2p-qvrexternal5-out {
+			qcom,entry-name = "qvrexternal";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
+			qcom,entry-name = "rdbg";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
+			qcom,entry-name = "rdbg";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	qcom,smp2p-modem {
+		compatible = "qcom,smp2p";
+		qcom,smem = <435>, <428>;
+		interrupt-parent = <&ipcc_mproc>;
+		interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P
+			      IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <1>;
+
+		modem_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		modem_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+};
+
diff --git a/qcom/kona-thermal-overlay.dtsi b/qcom/kona-thermal-overlay.dtsi
new file mode 100755
index 00000000..80a1752d
--- /dev/null
+++ b/qcom/kona-thermal-overlay.dtsi
@@ -0,0 +1,124 @@
+#include <dt-bindings/thermal/thermal.h>
+
+&thermal_zones {
+	socd {
+		cooling-maps {
+			socd_cpu4 {
+				trip = <&socd_trip>;
+				cooling-device = <&cpu4_pause 1 1>;
+			};
+
+			socd_cpu5 {
+				trip = <&socd_trip>;
+				cooling-device = <&cpu5_pause 1 1>;
+			};
+
+			socd_cpu6 {
+				trip = <&socd_trip>;
+				cooling-device = <&cpu6_pause 1 1>;
+			};
+
+			socd_cpu7 {
+				trip = <&socd_trip>;
+				cooling-device = <&cpu7_pause 1 1>;
+			};
+		};
+	};
+
+	pm8150b-bcl-lvl0 {
+		cooling-maps {
+			vbat_cpu4 {
+				trip = <&b_bcl_lvl0>;
+				cooling-device = <&cpu4_pause 1 1>;
+			};
+
+			vbat_cpu5 {
+				trip = <&b_bcl_lvl0>;
+				cooling-device = <&cpu5_pause 1 1>;
+			};
+
+			vbat_gpu0 {
+				trip = <&b_bcl_lvl0>;
+				cooling-device = <&msm_gpu 2 2>;
+			};
+		};
+	};
+
+	pm8150b-bcl-lvl1 {
+		cooling-maps {
+			vbat_cpu6 {
+				trip = <&b_bcl_lvl1>;
+				cooling-device = <&cpu6_pause 1 1>;
+			};
+
+			vbat_cpu7 {
+				trip = <&b_bcl_lvl1>;
+				cooling-device = <&cpu7_pause 1 1>;
+			};
+
+			vbat_gpu1 {
+				trip = <&b_bcl_lvl1>;
+				cooling-device = <&msm_gpu 4 4>;
+			};
+		};
+	};
+
+	pm8150b-bcl-lvl2 {
+		cooling-maps {
+			vbat_gpu2 {
+				trip = <&b_bcl_lvl2>;
+				cooling-device = <&msm_gpu 4 THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	pm8150l-bcl-lvl0 {
+		disable-thermal-zone;
+		cooling-maps {
+			vph_cpu4 {
+				trip = <&l_bcl_lvl0>;
+				cooling-device = <&cpu4_pause 1 1>;
+			};
+
+			vph_cpu5 {
+				trip = <&l_bcl_lvl0>;
+				cooling-device = <&cpu5_pause 1 1>;
+			};
+
+			vph_gpu0 {
+				trip = <&l_bcl_lvl0>;
+				cooling-device = <&msm_gpu 2 2>;
+			};
+
+			vph_gpu1 {
+				trip = <&l_bcl_lvl1>;
+				cooling-device = <&msm_gpu 4 4>;
+			};
+		};
+	};
+
+	pm8150l-bcl-lvl1 {
+		disable-thermal-zone;
+		cooling-maps {
+			vph_cpu6 {
+				trip = <&l_bcl_lvl1>;
+				cooling-device = <&cpu6_pause 1 1>;
+			};
+
+			vph_cpu7 {
+				trip = <&l_bcl_lvl1>;
+				cooling-device = <&cpu7_pause 1 1>;
+			};
+		};
+	};
+
+	pm8150l-bcl-lvl2 {
+		disable-thermal-zone;
+		cooling-maps {
+			vph_gpu2 {
+				trip = <&l_bcl_lvl2>;
+				cooling-device = <&msm_gpu 4 THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+};
diff --git a/qcom/kona-thermal.dtsi b/qcom/kona-thermal.dtsi
index bf939ab6..3a249fbf 100755
--- a/qcom/kona-thermal.dtsi
+++ b/qcom/kona-thermal.dtsi
@@ -1,45 +1,156 @@
-#include <dt-bindings/thermal/thermal.h>
-#include <dt-bindings/thermal/qmi_thermal.h>
-
-&cpufreq_hw {
-	qcom,cpu-isolation {
-		compatible = "qcom,cpu-isolate";
-		cpu0_isolate: cpu0-isolate {
-			qcom,cpu = <&CPU0>;
+#include <dt-bindings/thermal/thermal_qti.h>
+
+&msm_gpu {
+	#cooling-cells = <2>;
+};
+
+&soc {
+	tsens0: tsens@c222000 {
+		compatible = "qcom,tsens24xx";
+		reg = <0xc222000 0x8>,
+			<0xc263000 0x1ff>;
+		reg-names = "tsens_srot_physical",
+				"tsens_tm_physical";
+		interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "tsens-upper-lower", "tsens-critical";
+		tsens-reinit-wa;
+		#thermal-sensor-cells = <1>;
+	};
+
+	tsens1: tsens@c223000 {
+		compatible = "qcom,tsens24xx";
+		reg = <0xc223000 0x8>,
+			<0xc265000 0x1ff>;
+		reg-names = "tsens_srot_physical",
+			"tsens_tm_physical";
+		interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "tsens-upper-lower", "tsens-critical";
+		tsens-reinit-wa;
+		#thermal-sensor-cells = <1>;
+	};
+
+	qcom,cpu-pause {
+		compatible = "qcom,thermal-pause";
+
+		cpu0_pause: cpu0-pause {
+			qcom,cpus = <&CPU0>;
 			#cooling-cells = <2>;
 		};
 
-		cpu1_isolate: cpu1-isolate {
+		cpu1_pause: cpu1-pause {
+			qcom,cpus = <&CPU1>;
+			#cooling-cells = <2>;
+		};
+
+		cpu2_pause: cpu2-pause {
+			qcom,cpus = <&CPU2>;
+			#cooling-cells = <2>;
+		};
+
+		cpu3_pause: cpu3-pause {
+			qcom,cpus = <&CPU3>;
+			#cooling-cells = <2>;
+		};
+
+		cpu4_pause: cpu4-pause {
+			qcom,cpus = <&CPU4>;
+			#cooling-cells = <2>;
+		};
+
+		cpu5_pause: cpu5-pause {
+			qcom,cpus = <&CPU5>;
+			#cooling-cells = <2>;
+		};
+
+		cpu6_pause: cpu6-pause {
+			qcom,cpus = <&CPU6>;
+			#cooling-cells = <2>;
+		};
+
+		cpu7_pause: cpu7-pause {
+			qcom,cpus = <&CPU7>;
+			#cooling-cells = <2>;
+		};
+
+		/* Thermal-engine cooling devices */
+
+		pause-cpu0 {
+			qcom,cpus = <&CPU0>;
+			qcom,cdev-alias = "pause-cpu0";
+		};
+
+		pause-cpu1 {
+			qcom,cpus = <&CPU1>;
+			qcom,cdev-alias = "pause-cpu1";
+		};
+
+		pause-cpu2 {
+			qcom,cpus = <&CPU2>;
+			qcom,cdev-alias = "pause-cpu2";
+		};
+
+		pause-cpu3 {
+			qcom,cpus = <&CPU3>;
+			qcom,cdev-alias = "pause-cpu3";
+		};
+
+		pause-cpu4 {
+			qcom,cpus = <&CPU4>;
+			qcom,cdev-alias = "pause-cpu4";
+		};
+
+		pause-cpu5 {
+			qcom,cpus = <&CPU5>;
+			qcom,cdev-alias = "pause-cpu5";
+		};
+
+		pause-cpu6 {
+			qcom,cpus = <&CPU6>;
+			qcom,cdev-alias = "pause-cpu6";
+		};
+
+		pause-cpu7 {
+			qcom,cpus = <&CPU7>;
+			qcom,cdev-alias = "pause-cpu7";
+		};
+	};
+
+	qcom,cpu-hotplug {
+		compatible = "qcom,cpu-hotplug";
+
+		cpu1_hotplug: cpu1-hotplug {
 			qcom,cpu = <&CPU1>;
 			#cooling-cells = <2>;
 		};
 
-		cpu2_isolate: cpu2-isolate {
+		cpu2_hotplug: cpu2-hotplug {
 			qcom,cpu = <&CPU2>;
 			#cooling-cells = <2>;
 		};
 
-		cpu3_isolate: cpu3-isolate {
+		cpu3_hotplug: cpu3-hotplug {
 			qcom,cpu = <&CPU3>;
 			#cooling-cells = <2>;
 		};
 
-		cpu4_isolate: cpu4-isolate {
+		cpu4_hotplug: cpu4-hotplug {
 			qcom,cpu = <&CPU4>;
 			#cooling-cells = <2>;
 		};
 
-		cpu5_isolate: cpu5-isolate {
+		cpu5_hotplug: cpu5-hotplug {
 			qcom,cpu = <&CPU5>;
 			#cooling-cells = <2>;
 		};
 
-		cpu6_isolate: cpu6-isolate {
+		cpu6_hotplug: cpu6-hotplug {
 			qcom,cpu = <&CPU6>;
 			#cooling-cells = <2>;
 		};
 
-		cpu7_isolate: cpu7-isolate {
+		cpu7_hotplug: cpu7-hotplug {
 			qcom,cpu = <&CPU7>;
 			#cooling-cells = <2>;
 		};
@@ -52,9 +163,7 @@
 		isens_vref_1p8-supply = <&pm8150_l12_ao>;
 		isens-vref-1p8-settings = <1800000 1800000 20000>;
 	};
-};
 
-&soc {
 	qmi-tmd-devices {
 		compatible = "qcom,qmi-cooling-devices";
 
@@ -168,23 +277,48 @@
 						"modem_tsens1";
 		};
 	};
+
+	cpufreq_cdev: qcom,cpufreq-cdev {
+		compatible = "qcom,cpufreq-cdev";
+		qcom,cpus = <&CPU0 &CPU4 &CPU7>;
+	};
+
+	qcom,devfreq-cdev {
+		compatible = "qcom,devfreq-cdev";
+		qcom,devfreq = <&msm_gpu>;
+	};
+
+	limits_stat: limits-stat {
+		compatible = "qcom,limits-stat";
+		qcom,limits-stat-sensor-names = "cpu-0-0",
+						"cpu-0-1",
+						"cpu-0-2",
+						"cpu-0-3",
+						"cpu-1-0",
+						"cpu-1-1",
+						"cpu-1-2",
+						"cpu-1-3",
+						"cpuss-0",
+						"gpuss-0",
+						"gpuss-1",
+						"npu",
+						"q6-hvx";
+	};
 };
 
 &thermal_zones {
-	aoss0-usr {
+	aoss-0 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
 		thermal-sensors = <&tsens0 0>;
-		wake-capable-sensor;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 
-			active-config1 {
+			reset-mon-cfg {
 				temperature = <115000>;
 				hysteresis = <1000>;
 				type = "passive";
@@ -192,104 +326,176 @@
 		};
 	};
 
-	cpu-0-0-usr {
+	cpu-0-0 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
 		thermal-sensors = <&tsens0 1>;
-		wake-capable-sensor;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 
-			active-config1 {
+			thermal-hal-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			cpu00_config: cpu00-config {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
 				temperature = <115000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			cpu00_cdev {
+				trip = <&cpu00_config>;
+				cooling-device = <&cpu0_pause 1 1>;
+			};
+		};
 	};
 
-	cpu-0-1-usr {
+	cpu-0-1 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
 		thermal-sensors = <&tsens0 2>;
-		wake-capable-sensor;
 		trips {
-			active-config0 {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 
-			active-config1 {
+			cpu01_config: cpu01-config {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
 				temperature = <115000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			cpu01_cdev {
+				trip = <&cpu01_config>;
+				cooling-device = <&cpu1_pause 1 1>;
+			};
+		};
 	};
 
-	cpu-0-2-usr {
+	cpu-0-2 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
 		thermal-sensors = <&tsens0 3>;
-		wake-capable-sensor;
 		trips {
-			active-config0 {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 
-			active-config1 {
+			cpu02_config: cpu02-config {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
 				temperature = <115000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			cpu02_cdev {
+				trip = <&cpu02_config>;
+				cooling-device = <&cpu2_pause 1 1>;
+			};
+		};
 	};
 
-	cpu-0-3-usr {
+	cpu-0-3 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
 		thermal-sensors = <&tsens0 4>;
-		thermal-governor = "user_space";
-		wake-capable-sensor;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 
-			active-config1 {
+			thermal-hal-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			cpu03_config: cpu03-config {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
 				temperature = <115000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			cpu03_cdev {
+				trip = <&cpu03_config>;
+				cooling-device = <&cpu3_pause 1 1>;
+			};
+		};
 	};
 
-	cpuss-0-usr {
+	cpuss-0 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
 		thermal-sensors = <&tsens0 5>;
-		thermal-governor = "user_space";
-		wake-capable-sensor;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 
-			active-config1 {
+			thermal-hal-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
 				temperature = <115000>;
 				hysteresis = <1000>;
 				type = "passive";
@@ -297,20 +503,24 @@
 		};
 	};
 
-	cpuss-1-usr {
+	cpuss-1 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
 		thermal-sensors = <&tsens0 6>;
-		thermal-governor = "user_space";
-		wake-capable-sensor;
 		trips {
-			active-config0 {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 
-			active-config1 {
+			reset-mon-cfg {
 				temperature = <115000>;
 				hysteresis = <1000>;
 				type = "passive";
@@ -318,377 +528,449 @@
 		};
 	};
 
-	cpu-1-0-usr {
-		polling-delay-passive = <0>;
+	cpu-1-0 {
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
 		thermal-sensors = <&tsens0 7>;
-		thermal-governor = "user_space";
-		wake-capable-sensor;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 
-			active-config1 {
+			thermal-hal-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			cpufreq_10_config: cpufreq-10-config {
+				temperature = <75000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu10_config: cpu10-config {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
 				temperature = <115000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			cpufreq_cdev {
+				trip = <&cpufreq_10_config>;
+				cooling-device = <&cpu7_notify 1 1>;
+			};
+
+			cpu10_cdev {
+				trip = <&cpu10_config>;
+				cooling-device = <&cpu4_pause 1 1>;
+			};
+		};
 	};
 
-	cpu-1-1-usr {
-		polling-delay-passive = <0>;
+	cpu-1-1 {
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
 		thermal-sensors = <&tsens0 8>;
-		thermal-governor = "user_space";
-		wake-capable-sensor;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 
-			active-config1 {
-				temperature = <115000>;
+			thermal-hal-config {
+				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
-		};
-	};
 
-	cpu-1-2-usr {
-		polling-delay-passive = <0>;
-		polling-delay = <0>;
-		thermal-sensors = <&tsens0 9>;
-		thermal-governor = "user_space";
-		wake-capable-sensor;
-		trips {
-			active-config0 {
-				temperature = <125000>;
-				hysteresis = <1000>;
+			cpufreq_11_config: cpufreq-11-config {
+				temperature = <75000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu11_config: cpu11-config {
+				temperature = <110000>;
+				hysteresis = <10000>;
 				type = "passive";
 			};
 
-			active-config1 {
+			reset-mon-cfg {
 				temperature = <115000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			cpufreq_cdev {
+				trip = <&cpufreq_11_config>;
+				cooling-device = <&cpu7_notify 1 1>;
+			};
+
+			cpu11_cdev {
+				trip = <&cpu11_config>;
+				cooling-device = <&cpu5_pause 1 1>;
+			};
+		};
 	};
 
-	cpu-1-3-usr {
-		polling-delay-passive = <0>;
+	cpu-1-2 {
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
-		thermal-sensors = <&tsens0 10>;
-		thermal-governor = "user_space";
-		wake-capable-sensor;
+		thermal-sensors = <&tsens0 9>;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 
-			active-config1 {
-				temperature = <115000>;
+			thermal-hal-config {
+				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
-		};
-	};
 
-	cpu-1-4-usr {
-		polling-delay-passive = <0>;
-		polling-delay = <0>;
-		thermal-sensors = <&tsens0 11>;
-		thermal-governor = "user_space";
-		wake-capable-sensor;
-		trips {
-			active-config0 {
-				temperature = <125000>;
-				hysteresis = <1000>;
+			cpufreq_12_config: cpufreq-12-config {
+				temperature = <75000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu12_config: cpu12-config {
+				temperature = <110000>;
+				hysteresis = <10000>;
 				type = "passive";
 			};
 
-			active-config1 {
+			reset-mon-cfg {
 				temperature = <115000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			cpufreq_cdev {
+				trip = <&cpufreq_12_config>;
+				cooling-device = <&cpu7_notify 1 1>;
+			};
+
+			cpu12_cdev {
+				trip = <&cpu12_config>;
+				cooling-device = <&cpu6_pause 1 1>;
+			};
+		};
 	};
 
-	cpu-1-5-usr {
-		polling-delay-passive = <0>;
+	cpu-1-3 {
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
-		thermal-sensors = <&tsens0 12>;
-		thermal-governor = "user_space";
-		wake-capable-sensor;
+		thermal-sensors = <&tsens0 10>;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 
-			active-config1 {
-				temperature = <115000>;
+			thermal-hal-config {
+				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
-		};
-	};
 
-	cpu-1-6-usr {
-		polling-delay-passive = <0>;
-		polling-delay = <0>;
-		thermal-sensors = <&tsens0 13>;
-		thermal-governor = "user_space";
-		wake-capable-sensor;
-		trips {
-			active-config0 {
-				temperature = <125000>;
-				hysteresis = <1000>;
+			cpufreq_13_config: cpufreq-13-config {
+				temperature = <75000>;
+				hysteresis = <5000>;
 				type = "passive";
 			};
 
-			active-config1 {
+			cpu13_config: cpu13-config {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
 				temperature = <115000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			cpufreq_cdev {
+				trip = <&cpufreq_13_config>;
+				cooling-device = <&cpu7_notify 1 1>;
+			};
+
+			cpu13_cdev {
+				trip = <&cpu13_config>;
+				cooling-device = <&cpu7_pause 1 1>;
+			};
+		};
 	};
 
-	cpu-1-7-usr {
-		polling-delay-passive = <0>;
+	cpu-1-4 {
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
-		thermal-sensors = <&tsens0 14>;
-		thermal-governor = "user_space";
-		wake-capable-sensor;
+		thermal-sensors = <&tsens0 11>;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 
-			active-config1 {
-				temperature = <115000>;
+			thermal-hal-config {
+				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
-		};
-	};
 
-	gpuss-0-usr {
-		polling-delay-passive = <0>;
-		polling-delay = <0>;
-		thermal-sensors = <&tsens0 15>;
-		thermal-governor = "user_space";
-		wake-capable-sensor;
-		trips {
-			active-config0 {
-				temperature = <125000>;
-				hysteresis = <1000>;
+			cpufreq_14_config: cpufreq-14-config {
+				temperature = <75000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu14_config: cpu14-config {
+				temperature = <110000>;
+				hysteresis = <10000>;
 				type = "passive";
 			};
 
-			active-config1 {
+			reset-mon-cfg {
 				temperature = <115000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			cpufreq_cdev {
+				trip = <&cpufreq_14_config>;
+				cooling-device = <&cpu7_notify 1 1>;
+			};
+
+			cpu14_cdev {
+				trip = <&cpu14_config>;
+				cooling-device = <&cpu4_pause 1 1>;
+			};
+		};
 	};
 
-	aoss-1-usr {
-		polling-delay-passive = <0>;
+	cpu-1-5 {
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
-		thermal-sensors = <&tsens1 0>;
-		thermal-governor = "user_space";
-		wake-capable-sensor;
+		thermal-sensors = <&tsens0 12>;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 
-			active-config1 {
-				temperature = <115000>;
+			thermal-hal-config {
+				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
-		};
-	};
 
-	cwlan-usr {
-		polling-delay-passive = <0>;
-		polling-delay = <0>;
-		thermal-sensors = <&tsens1 1>;
-		thermal-governor = "user_space";
-		wake-capable-sensor;
-		trips {
-			active-config0 {
-				temperature = <125000>;
-				hysteresis = <1000>;
+			cpufreq_15_config: cpufreq-15-config {
+				temperature = <75000>;
+				hysteresis = <5000>;
 				type = "passive";
 			};
 
-			active-config1 {
+			cpu15_config: cpu15-config {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
 				temperature = <115000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			cpufreq_cdev {
+				trip = <&cpufreq_15_config>;
+				cooling-device = <&cpu7_notify 1 1>;
+			};
+
+			cpu15_cdev {
+				trip = <&cpu15_config>;
+				cooling-device = <&cpu5_pause 1 1>;
+			};
+		};
 	};
 
-	video-usr {
-		polling-delay-passive = <0>;
+	cpu-1-6 {
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
-		thermal-sensors = <&tsens1 2>;
-		thermal-governor = "user_space";
-		wake-capable-sensor;
+		thermal-sensors = <&tsens0 13>;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 
-			active-config1 {
-				temperature = <115000>;
+			thermal-hal-config {
+				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
-		};
-	};
 
-	ddr-usr {
-		polling-delay-passive = <0>;
-		polling-delay = <0>;
-		thermal-sensors = <&tsens1 3>;
-		thermal-governor = "user_space";
-		wake-capable-sensor;
-		trips {
-			active-config0 {
-				temperature = <125000>;
-				hysteresis = <1000>;
+			cpufreq_16_config: cpufreq-16-config {
+				temperature = <75000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu16_config: cpu16-config {
+				temperature = <110000>;
+				hysteresis = <10000>;
 				type = "passive";
 			};
 
-			active-config1 {
+			reset-mon-cfg {
 				temperature = <115000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			cpufreq_cdev {
+				trip = <&cpufreq_16_config>;
+				cooling-device = <&cpu7_notify 1 1>;
+			};
+
+			cpu16_cdev {
+				trip = <&cpu16_config>;
+				cooling-device = <&cpu6_pause 1 1>;
+			};
+		};
 	};
 
-	q6-hvx-usr {
-		polling-delay-passive = <0>;
+	cpu-1-7 {
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
-		thermal-sensors = <&tsens1 4>;
-		thermal-governor = "user_space";
-		wake-capable-sensor;
+		thermal-sensors = <&tsens0 14>;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 
-			active-config1 {
-				temperature = <115000>;
+			thermal-hal-config {
+				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
-		};
-	};
 
-	camera-usr {
-		polling-delay-passive = <0>;
-		polling-delay = <0>;
-		thermal-sensors = <&tsens1 5>;
-		thermal-governor = "user_space";
-		wake-capable-sensor;
-		trips {
-			active-config0 {
-				temperature = <125000>;
-				hysteresis = <1000>;
+			cpufreq_17_config: cpufreq-17-config {
+				temperature = <75000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu17_config: cpu17-config {
+				temperature = <110000>;
+				hysteresis = <10000>;
 				type = "passive";
 			};
 
-			active-config1 {
+			reset-mon-cfg {
 				temperature = <115000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			cpufreq_cdev {
+				trip = <&cpufreq_17_config>;
+				cooling-device = <&cpu7_notify 1 1>;
+			};
+
+			cpu17_cdev {
+				trip = <&cpu17_config>;
+				cooling-device = <&cpu7_pause 1 1>;
+			};
+		};
 	};
 
-	cmpss-usr {
-		polling-delay-passive = <0>;
+	gpuss-0 {
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
-		thermal-sensors = <&tsens1 6>;
-		thermal-governor = "user_space";
-		wake-capable-sensor;
+		thermal-sensors = <&tsens0 15>;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 
-			active-config1 {
-				temperature = <115000>;
+			thermal-hal-config {
+				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
-		};
-	};
 
-	npu-usr {
-		polling-delay-passive = <0>;
-		polling-delay = <0>;
-		thermal-sensors = <&tsens1 7>;
-		thermal-governor = "user_space";
-		wake-capable-sensor;
-		trips {
-			active-config0 {
-				temperature = <125000>;
-				hysteresis = <1000>;
+			gpuss0_trip0: gpuss0-trip0 {
+				temperature = <95000>;
+				hysteresis = <0>;
 				type = "passive";
 			};
 
-			active-config1 {
+			reset-mon-cfg {
 				temperature = <115000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			gpu_cdev {
+				trip = <&gpuss0_trip0>;
+				cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+			};
+		};
 	};
 
-	gpuss-1-usr {
+	aoss-1 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
-		thermal-sensors = <&tsens1 8>;
-		wake-capable-sensor;
+		thermal-sensors = <&tsens1 0>;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
 
-			active-config1 {
+			reset-mon-cfg {
 				temperature = <115000>;
 				hysteresis = <1000>;
 				type = "passive";
@@ -696,395 +978,394 @@
 		};
 	};
 
-	apc-0-max-step {
-		polling-delay-passive = <0>;
+	cwlan {
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
-		thermal-governor = "step_wise";
-		wake-capable-sensor;
+		thermal-sensors = <&tsens1 1>;
 		trips {
-			silver-trip {
-				temperature = <120000>;
-				hysteresis = <0>;
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
 				type = "passive";
 			};
-		};
-	};
 
-	apc-1-max-step {
-		polling-delay-passive = <0>;
-		polling-delay = <0>;
-		thermal-governor = "step_wise";
-		wake-capable-sensor;
-		trips {
-			gold-trip {
-				temperature = <120000>;
-				hysteresis = <0>;
+			cwlan_trip0: cwlan-trip0 {
+				temperature = <100000>;
+				hysteresis = <5000>;
 				type = "passive";
 			};
-		};
-	};
 
-	pop-mem-step {
-		polling-delay-passive = <10>;
-		polling-delay = <0>;
-		thermal-sensors = <&tsens1 3>;
-		thermal-governor = "step_wise";
-		wake-capable-sensor;
-		trips {
-			pop_trip: pop-trip {
-				temperature = <95000>;
-				hysteresis = <0>;
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <1000>;
 				type = "passive";
 			};
 		};
 
 		cooling-maps {
-			pop_cdev4 {
-				trip = <&pop_trip>;
-				cooling-device =
-					<&CPU4 THERMAL_NO_LIMIT
-						THERMAL_NO_LIMIT>;
+			cdsp-cdev {
+				trip = <&cwlan_trip0>;
+				cooling-device = <&msm_cdsp_rm 3 3>;
 			};
 
+			gpu-cdev {
+				trip = <&cwlan_trip0>;
+				cooling-device = <&msm_gpu 1 1>;
+			};
+
+			modem-pa-cdev {
+				trip = <&cwlan_trip0>;
+				cooling-device = <&modem_pa 3 3>;
+			};
+
+			modem-tj-cdev {
+				trip = <&cwlan_trip0>;
+				cooling-device = <&modem_tj 3 3>;
+			};
 		};
 	};
 
-	cpu-0-0-step {
-		polling-delay-passive = <0>;
+	video {
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
-		thermal-governor = "step_wise";
-		thermal-sensors = <&tsens0 1>;
-		wake-capable-sensor;
+		thermal-sensors = <&tsens1 2>;
 		trips {
-			cpu00_config: cpu00-config {
-				temperature = <110000>;
-				hysteresis = <10000>;
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
 				type = "passive";
 			};
-		};
 
-		cooling-maps {
-			cpu00_cdev {
-				trip = <&cpu00_config>;
-				cooling-device = <&cpu0_isolate 1 1>;
+			video_trip0: video-trip0 {
+				temperature = <100000>;
+				hysteresis = <5000>;
+				type = "passive";
 			};
-		};
-	};
 
-	cpu-0-1-step {
-		polling-delay-passive = <0>;
-		polling-delay = <0>;
-		thermal-governor = "step_wise";
-		thermal-sensors = <&tsens0 2>;
-		wake-capable-sensor;
-		trips {
-			cpu01_config: cpu01-config {
-				temperature = <110000>;
-				hysteresis = <10000>;
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <1000>;
 				type = "passive";
 			};
 		};
 
 		cooling-maps {
-			cpu01_cdev {
-				trip = <&cpu01_config>;
-				cooling-device = <&cpu1_isolate 1 1>;
+			cdsp-cdev {
+				trip = <&video_trip0>;
+				cooling-device = <&msm_cdsp_rm 3 3>;
 			};
-		};
-	};
 
-	cpu-0-2-step {
-		polling-delay-passive = <0>;
-		polling-delay = <0>;
-		thermal-governor = "step_wise";
-		thermal-sensors = <&tsens0 3>;
-		wake-capable-sensor;
-		trips {
-			cpu02_config: cpu02-config {
-				temperature = <110000>;
-				hysteresis = <10000>;
-				type = "passive";
+			gpu-cdev {
+				trip = <&video_trip0>;
+				cooling-device = <&msm_gpu 1 1>;
+			};
+
+			modem-pa-cdev {
+				trip = <&video_trip0>;
+				cooling-device = <&modem_pa 3 3>;
 			};
-		};
 
+			modem-tj-cdev {
+				trip = <&video_trip0>;
+				cooling-device = <&modem_tj 3 3>;
+			};
+		};
 	};
 
-	cpu-0-3-step {
-		polling-delay-passive = <0>;
+	ddr {
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
-		thermal-sensors = <&tsens0 4>;
-		thermal-governor = "step_wise";
-		wake-capable-sensor;
+		thermal-sensors = <&tsens1 3>;
 		trips {
-			cpu03_config: cpu03-config {
-				temperature = <110000>;
-				hysteresis = <10000>;
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
 				type = "passive";
 			};
-		};
 
-	};
+			ddr_trip0: ddr-trip0 {
+				temperature = <95000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
 
-	cpu-1-0-step {
-		polling-delay-passive = <0>;
-		polling-delay = <0>;
-		thermal-sensors = <&tsens0 7>;
-		thermal-governor = "step_wise";
-		wake-capable-sensor;
-		trips {
-			cpufreq_10_config: cpufreq-10-config {
-				temperature = <75000>;
+			ddr_trip1: ddr-trip1 {
+				temperature = <100000>;
 				hysteresis = <5000>;
 				type = "passive";
 			};
 
-			cpu10_config: cpu10-config {
-				temperature = <110000>;
-				hysteresis = <10000>;
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <1000>;
 				type = "passive";
 			};
 		};
 
 		cooling-maps {
-			cpufreq_cdev {
-				trip = <&cpufreq_10_config>;
-				cooling-device = <&cpu7_notify 1 1>;
+			cdsp-cdev {
+				trip = <&ddr_trip0>;
+				cooling-device = <&msm_cdsp_rm 3 3>;
 			};
 
-			cpu10_cdev {
-				trip = <&cpu10_config>;
-				cooling-device = <&cpu4_isolate 1 1>;
+			gpu-cdev {
+				trip = <&ddr_trip0>;
+				cooling-device = <&msm_gpu 1 1>;
 			};
-		};
-	};
 
-	cpu-1-1-step {
-		polling-delay-passive = <0>;
-		polling-delay = <0>;
-		thermal-sensors = <&tsens0 8>;
-		thermal-governor = "step_wise";
-		wake-capable-sensor;
-		trips {
-			cpufreq_11_config: cpufreq-11-config {
-				temperature = <75000>;
-				hysteresis = <5000>;
-				type = "passive";
+			cpu_cdev4 {
+				trip = <&ddr_trip0>;
+				cooling-device = <&CPU4 THERMAL_NO_LIMIT
+						THERMAL_NO_LIMIT>;
 			};
 
-			cpu11_config: cpu11-config {
-				temperature = <110000>;
-				hysteresis = <10000>;
-				type = "passive";
+			cpu_cdev7 {
+				trip = <&ddr_trip0>;
+				cooling-device = <&CPU7 THERMAL_NO_LIMIT
+						THERMAL_NO_LIMIT>;
 			};
-		};
 
-		cooling-maps {
-			cpufreq_cdev {
-				trip = <&cpufreq_11_config>;
-				cooling-device = <&cpu7_notify 1 1>;
+			modem-pa-cdev {
+				trip = <&ddr_trip1>;
+				cooling-device = <&modem_pa 3 3>;
 			};
 
-			cpu11_cdev {
-				trip = <&cpu11_config>;
-				cooling-device = <&cpu5_isolate 1 1>;
+			modem-tj-cdev {
+				trip = <&ddr_trip1>;
+				cooling-device = <&modem_tj 3 3>;
 			};
 		};
 	};
 
-	cpu-1-2-step {
-		polling-delay-passive = <0>;
+	q6-hvx {
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
-		thermal-sensors = <&tsens0 9>;
-		thermal-governor = "step_wise";
-		wake-capable-sensor;
+		thermal-sensors = <&tsens1 4>;
 		trips {
-			cpufreq_12_config: cpufreq-12-config {
-				temperature = <75000>;
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			q6_hvx_trip0: q6-hvx-trip0 {
+				temperature = <100000>;
 				hysteresis = <5000>;
 				type = "passive";
 			};
 
-			cpu12_config: cpu12-config {
-				temperature = <110000>;
-				hysteresis = <10000>;
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <1000>;
 				type = "passive";
 			};
 		};
 
 		cooling-maps {
-			cpufreq_cdev {
-				trip = <&cpufreq_12_config>;
-				cooling-device = <&cpu7_notify 1 1>;
+			cdsp-cdev {
+				trip = <&q6_hvx_trip0>;
+				cooling-device = <&msm_cdsp_rm 3 3>;
 			};
 
-			cpu12_cdev {
-				trip = <&cpu12_config>;
-				cooling-device = <&cpu6_isolate 1 1>;
+			gpu-cdev {
+				trip = <&q6_hvx_trip0>;
+				cooling-device = <&msm_gpu 1 1>;
+			};
+
+			modem-pa-cdev {
+				trip = <&q6_hvx_trip0>;
+				cooling-device = <&modem_pa 3 3>;
+			};
+
+			modem-tj-cdev {
+				trip = <&q6_hvx_trip0>;
+				cooling-device = <&modem_tj 3 3>;
 			};
 		};
 	};
 
-	cpu-1-3-step {
-		polling-delay-passive = <0>;
+	camera {
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
-		thermal-sensors = <&tsens0 10>;
-		thermal-governor = "step_wise";
-		wake-capable-sensor;
+		thermal-sensors = <&tsens1 5>;
 		trips {
-			cpufreq_13_config: cpufreq-13-config {
-				temperature = <75000>;
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			camera_trip0: camera-trip0 {
+				temperature = <100000>;
 				hysteresis = <5000>;
 				type = "passive";
 			};
 
-			cpu13_config: cpu13-config {
-				temperature = <110000>;
-				hysteresis = <10000>;
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <1000>;
 				type = "passive";
 			};
 		};
 
 		cooling-maps {
-			cpufreq_cdev {
-				trip = <&cpufreq_13_config>;
-				cooling-device = <&cpu7_notify 1 1>;
+			cdsp-cdev {
+				trip = <&camera_trip0>;
+				cooling-device = <&msm_cdsp_rm 3 3>;
 			};
 
-			cpu13_cdev {
-				trip = <&cpu13_config>;
-				cooling-device = <&cpu7_isolate 1 1>;
+			gpu-cdev {
+				trip = <&camera_trip0>;
+				cooling-device = <&msm_gpu 1 1>;
+			};
+
+			modem-pa-cdev {
+				trip = <&camera_trip0>;
+				cooling-device = <&modem_pa 3 3>;
+			};
+
+			modem-tj-cdev {
+				trip = <&camera_trip0>;
+				cooling-device = <&modem_tj 3 3>;
 			};
 		};
 	};
 
-	cpu-1-4-step {
-		polling-delay-passive = <0>;
+	cmpss {
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
-		thermal-sensors = <&tsens0 11>;
-		thermal-governor = "step_wise";
-		wake-capable-sensor;
+		thermal-sensors = <&tsens1 6>;
 		trips {
-			cpufreq_14_config: cpufreq-14-config {
-				temperature = <75000>;
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			cmpss_trip0: cmpss-trip0 {
+				temperature = <100000>;
 				hysteresis = <5000>;
 				type = "passive";
 			};
 
-			cpu14_config: cpu14-config {
-				temperature = <110000>;
-				hysteresis = <10000>;
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <1000>;
 				type = "passive";
 			};
 		};
 
 		cooling-maps {
-			cpufreq_cdev {
-				trip = <&cpufreq_14_config>;
-				cooling-device = <&cpu7_notify 1 1>;
+			cdsp-cdev {
+				trip = <&cmpss_trip0>;
+				cooling-device = <&msm_cdsp_rm 3 3>;
 			};
 
-			cpu14_cdev {
-				trip = <&cpu14_config>;
-				cooling-device = <&cpu4_isolate 1 1>;
+			gpu-cdev {
+				trip = <&cmpss_trip0>;
+				cooling-device = <&msm_gpu 1 1>;
+			};
+
+			modem-pa-cdev {
+				trip = <&cmpss_trip0>;
+				cooling-device = <&modem_pa 3 3>;
+			};
+
+			modem-tj-cdev {
+				trip = <&cmpss_trip0>;
+				cooling-device = <&modem_tj 3 3>;
 			};
 		};
 	};
 
-	cpu-1-5-step {
-		polling-delay-passive = <0>;
+	npu {
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
-		thermal-sensors = <&tsens0 12>;
-		thermal-governor = "step_wise";
-		wake-capable-sensor;
+		thermal-sensors = <&tsens1 7>;
 		trips {
-			cpufreq_15_config: cpufreq-15-config {
-				temperature = <75000>;
-				hysteresis = <5000>;
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
 				type = "passive";
 			};
 
-			cpu15_config: cpu15-config {
-				temperature = <110000>;
-				hysteresis = <10000>;
+			thermal-hal-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
 				type = "passive";
 			};
-		};
 
-		cooling-maps {
-			cpufreq_cdev {
-				trip = <&cpufreq_15_config>;
-				cooling-device = <&cpu7_notify 1 1>;
-			};
-
-			cpu15_cdev {
-				trip = <&cpu15_config>;
-				cooling-device = <&cpu5_isolate 1 1>;
-			};
-		};
-	};
-
-	cpu-1-6-step {
-		polling-delay-passive = <0>;
-		polling-delay = <0>;
-		thermal-sensors = <&tsens0 13>;
-		thermal-governor = "step_wise";
-		wake-capable-sensor;
-		trips {
-			cpufreq_16_config: cpufreq-16-config {
-				temperature = <75000>;
+			npu_trip0: npu-trip0 {
+				temperature = <100000>;
 				hysteresis = <5000>;
 				type = "passive";
 			};
 
-			cpu16_config: cpu16-config {
-				temperature = <110000>;
-				hysteresis = <10000>;
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <1000>;
 				type = "passive";
 			};
 		};
 
 		cooling-maps {
-			cpufreq_cdev {
-				trip = <&cpufreq_16_config>;
-				cooling-device = <&cpu7_notify 1 1>;
+			cdsp-cdev {
+				trip = <&npu_trip0>;
+				cooling-device = <&msm_cdsp_rm 3 3>;
 			};
 
-			cpu16_cdev {
-				trip = <&cpu16_config>;
-				cooling-device = <&cpu6_isolate 1 1>;
+			gpu-cdev {
+				trip = <&npu_trip0>;
+				cooling-device = <&msm_gpu 1 1>;
+			};
+
+			modem-pa-cdev {
+				trip = <&npu_trip0>;
+				cooling-device = <&modem_pa 3 3>;
+			};
+
+			modem-tj-cdev {
+				trip = <&npu_trip0>;
+				cooling-device = <&modem_tj 3 3>;
 			};
 		};
 	};
 
-	cpu-1-7-step {
-		polling-delay-passive = <0>;
+	gpuss-1 {
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
-		thermal-sensors = <&tsens0 14>;
-		thermal-governor = "step_wise";
-		wake-capable-sensor;
+		thermal-sensors = <&tsens1 8>;
 		trips {
-			cpufreq_17_config: cpufreq-17-config {
-				temperature = <75000>;
-				hysteresis = <5000>;
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
 				type = "passive";
 			};
 
-			cpu17_config: cpu17-config {
-				temperature = <110000>;
-				hysteresis = <10000>;
+			thermal-hal-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
 				type = "passive";
 			};
-		};
 
-		cooling-maps {
-			cpufreq_cdev {
-				trip = <&cpufreq_17_config>;
-				cooling-device = <&cpu7_notify 1 1>;
+			gpuss1_trip0: gpuss1-trip0 {
+				temperature = <95000>;
+				hysteresis = <0>;
+				type = "passive";
 			};
 
-			cpu17_cdev {
-				trip = <&cpu17_config>;
-				cooling-device = <&cpu7_isolate 1 1>;
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			gpu_cdev {
+				trip = <&gpuss1_trip0>;
+				cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
 			};
 		};
 	};
@@ -1092,256 +1373,320 @@
 	modem-lte-sub6-pa1 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
 		thermal-sensors = <&qmi_sensor
 				(QMI_MODEM_NR_INST_ID+QMI_PA)>;
-		wake-capable-sensor;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
 		};
 	};
 
 	modem-lte-sub6-pa2 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
 		thermal-sensors = <&qmi_sensor
 				(QMI_MODEM_NR_INST_ID+QMI_PA_1)>;
-		wake-capable-sensor;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
 		};
 	};
 
-	modem-mmw0-usr {
+	modem-mmw0 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
 		thermal-sensors = <&qmi_sensor
 				(QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_0)>;
-		wake-capable-sensor;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
 		};
 	};
 
-	modem-mmw1-usr {
+	modem-mmw1 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
 		thermal-sensors = <&qmi_sensor
 				(QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_1)>;
-		wake-capable-sensor;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
 		};
 	};
 
-	modem-mmw2-usr {
+	modem-mmw2 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
 		thermal-sensors = <&qmi_sensor
 				(QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_2)>;
-		wake-capable-sensor;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
 		};
 	};
 
-	modem-mmw3-usr {
+	modem-mmw3 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
 		thermal-sensors = <&qmi_sensor
 				(QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_3)>;
-		wake-capable-sensor;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
 		};
 	};
 
-	modem-skin-usr {
+	modem-skin {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
 		thermal-sensors = <&qmi_sensor
 				(QMI_MODEM_NR_INST_ID+QMI_XO_THERM)>;
-		wake-capable-sensor;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
 		};
 	};
 
 	modem-wifi-usr {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
 		thermal-sensors = <&qmi_sensor
 				(QMI_MODEM_NR_INST_ID+QMI_SYS_THERM_1)>;
-		wake-capable-sensor;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
 		};
 	};
 
 	modem-ambient-usr {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
 		thermal-sensors = <&qmi_sensor
 				(QMI_MODEM_NR_INST_ID+QMI_SYS_THERM_2)>;
-		wake-capable-sensor;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
 		};
 	};
 
-	modem-0-usr {
+	modem-0 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
 		thermal-sensors = <&qmi_sensor
 				(QMI_MODEM_NR_INST_ID+QMI_MODEM_TSENS)>;
-		wake-capable-sensor;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
 		};
 	};
 
-	modem-1-usr {
+	modem-1 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
 		thermal-sensors = <&qmi_sensor
 				(QMI_MODEM_NR_INST_ID+QMI_MODEM_TSENS_1)>;
-		wake-capable-sensor;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
 		};
 	};
 
-	modem-streamer-usr {
+	modem-streamer {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
 		thermal-sensors = <&qmi_sensor
 				(QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_STREAMER_0)>;
-		wake-capable-sensor;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
 		};
 	};
 
-	modem-mmw0-mod-usr {
+	modem-mmw0-mod {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
 		thermal-sensors = <&qmi_sensor
 				(QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_0_MOD)>;
-		wake-capable-sensor;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
 		};
 	};
 
-	modem-mmw1-mod-usr {
+	modem-mmw1-mod {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
 		thermal-sensors = <&qmi_sensor
 				(QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_1_MOD)>;
-		wake-capable-sensor;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
 		};
 	};
 
-	modem-mmw2-mod-usr {
+	modem-mmw2-mod {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
 		thermal-sensors = <&qmi_sensor
 				(QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_2_MOD)>;
-		wake-capable-sensor;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
 		};
 	};
 
-	modem-mmw3-mod-usr {
+	modem-mmw3-mod {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
 		thermal-sensors = <&qmi_sensor
 				(QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_3_MOD)>;
-		wake-capable-sensor;
 		trips {
-			active-config0 {
+			thermal-engine-config {
 				temperature = <125000>;
 				hysteresis = <1000>;
 				type = "passive";
 			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
 		};
 	};
 };
diff --git a/qcom/kona-usb.dtsi b/qcom/kona-usb.dtsi
index 5c1c82a8..e1bf5196 100755
--- a/qcom/kona-usb.dtsi
+++ b/qcom/kona-usb.dtsi
@@ -53,7 +53,7 @@
 		interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>,
 				<&aggre1_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>,
 				<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>;
-		dwc3@a600000 {
+		dwc0: dwc3@a600000 {
 			compatible = "snps,dwc3";
 			reg = <0x0a600000 0xd93c>;
 			iommus = <&apps_smmu 0x0 0x0>;
@@ -300,7 +300,7 @@
 		clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
 			<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
 			<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>,
-			<&gcc USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK>,
+			<&usb3_phy_wrapper_gcc_usb30_pipe_clk>,
 			<&rpmhcc RPMH_CXO_CLK>,
 			<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
 		clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
@@ -373,7 +373,7 @@
 				<&aggre1_noc MASTER_USB3_1 &config_noc SLAVE_IPA_CFG>,
 				<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_1>;
 
-		dwc3@a800000 {
+		dwc1: dwc3@a800000 {
 			compatible = "snps,dwc3";
 			reg = <0xa800000 0xd93c>;
 			iommus = <&apps_smmu 0x20 0x0>;
@@ -538,7 +538,7 @@
 		clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
 			 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>,
 			 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK_SRC>,
-			 <&gcc USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK>,
+			 <&usb3_uni_phy_sec_gcc_usb30_pipe_clk>,
 			 <&rpmhcc RPMH_CXO_CLK>,
 			 <&gcc GCC_USB3_SEC_CLKREF_EN>,
 			 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
diff --git a/qcom/kona-v2.dtsi b/qcom/kona-v2.dtsi
index a8058ccc..9ef87e01 100755
--- a/qcom/kona-v2.dtsi
+++ b/qcom/kona-v2.dtsi
@@ -21,3 +21,125 @@
 &CPU7 {
 	dynamic-power-coefficient = <642>;
 };
+
+&qcom_pmu {
+	/delete-property/  qcom,pmu-events-tbl;
+	qcom,pmu-events-tbl =
+		< 0x0008 0xFF 0xFF 0xFF >,
+		< 0x0011 0xFF 0xFF 0xFF >,
+		< 0x0017 0xFF 0xFF 0xFF >,
+		< 0x002A 0xFF 0xFF 0xFF >,
+		< 0x1000 0xFF 0xFF 0xFF >;
+};
+
+&qcom_memlat {
+	ddr {
+		/delete-property/  qcom,miss-ev;
+		qcom,miss-ev = <0x1000>;
+		silver {
+			/delete-property/  qcom,cpufreq-memfreq-tbl;
+			qcom,cpufreq-memfreq-tbl =
+				<  300000  200000 >,
+				<  787200  451000 >,
+				< 1171200  547000 >,
+				< 1516800  768000 >,
+				< 1804800 1017000 >;
+		};
+
+		gold {
+			/delete-property/  qcom,cpufreq-memfreq-tbl;
+			qcom,cpufreq-memfreq-tbl =
+				<  300000  200000 >,
+				<  710400  451000 >,
+				<  825600  547000 >,
+				< 1056000  768000 >,
+				< 1286400 1017000 >,
+				< 1574400 1353000 >,
+				< 1862400 1555000 >,
+				< 2419200 1804000 >,
+				< 2745600 2092000 >,
+				< 2841600 2736000 >;
+		};
+
+		gold-compute {
+			/delete-property/  qcom,cpufreq-memfreq-tbl;
+			qcom,cpufreq-memfreq-tbl =
+				< 1862400  200000 >,
+				< 2745600 1017000 >,
+				< 2841600 2092000 >;
+		};
+	};
+
+	llcc {
+		silver {
+			/delete-property/  qcom,cpufreq-memfreq-tbl;
+			qcom,cpufreq-memfreq-tbl =
+				<  300000  150000 >,
+				<  787200  300000 >,
+				< 1516800  466000 >,
+				< 1804800  600000 >;
+		};
+
+		gold {
+			/delete-property/  qcom,cpufreq-memfreq-tbl;
+			qcom,cpufreq-memfreq-tbl =
+				<  300000  150000 >,
+				<  710400  300000 >,
+				< 1056000  466000 >,
+				< 1286400  600000 >,
+				< 1862400  806000 >,
+				< 2419200  933000 >,
+				< 2841600 1000000 >;
+		};
+	};
+
+	l3 {
+		silver {
+			/delete-property/  qcom,cpufreq-memfreq-tbl;
+			qcom,cpufreq-memfreq-tbl =
+				<  300000  300000 >,
+				<  403200  403200 >,
+				<  518400  518400 >,
+				<  691200  614400 >,
+				<  883200  825600 >,
+				< 1075200  921600 >,
+				< 1171200 1017600 >,
+				< 1344000 1132800 >,
+				< 1420800 1228800 >,
+				< 1516800 1324800 >,
+				< 1612800 1516800 >,
+				< 1804800 1612800 >;
+		};
+
+		gold {
+			/delete-property/  qcom,cpufreq-memfreq-tbl;
+			qcom,cpufreq-memfreq-tbl =
+				<  300000  300000 >,
+				<  825600  614400 >,
+				< 1171200  825600 >,
+				< 1478400 1017600 >,
+				< 1670400 1228800 >,
+				< 2054400 1324800 >,
+				< 2419200 1516800 >,
+				< 2841600 1612800 >;
+		};
+
+		prime {
+			/delete-property/  qcom,cpufreq-memfreq-tbl;
+			qcom,cpufreq-memfreq-tbl =
+				<  300000  300000 >,
+				<  825600  614400 >,
+				< 1171200  825600 >,
+				< 1478400 1017600 >,
+				< 1670400 1228800 >,
+				< 2054400 1324800 >,
+				< 2419200 1516800 >,
+				< 2841600 1612800 >;
+		};
+	};
+
+	ddrqos {
+		/delete-property/  qcom,miss-ev;
+		qcom,miss-ev = <0x1000>;
+	};
+};
diff --git a/qcom/kona.dtsi b/qcom/kona.dtsi
index 7ea3c798..8f8a0ed6 100755
--- a/qcom/kona.dtsi
+++ b/qcom/kona.dtsi
@@ -5,12 +5,14 @@
 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
 #include <dt-bindings/clock/qcom,npucc-sm8250.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 #include <dt-bindings/soc/qcom,ipcc.h>
 #include <dt-bindings/interconnect/qcom,icc.h>
 #include <dt-bindings/interconnect/qcom,kona.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/soc/qcom,dcc_v2.h>
 
 / {
 	model = "Qualcomm Technologies, Inc. kona";
@@ -22,8 +24,17 @@
 	#size-cells = <2>;
 	memory { device_type = "memory"; reg = <0 0 0 0>; };
 
+	mem-offline {
+		compatible = "qcom,mem-offline";
+		offline-sizes = <0x1 0x40000000 0x0 0x40000000>,
+				<0x1 0xc0000000 0x0 0x80000000>,
+				<0x2 0xc0000000 0x1 0x40000000>;
+		granule = <512>;
+		mboxes = <&qmp_aop 0>;
+	};
+
 	chosen {
-		bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off pcie_ports=compat";
+		bootargs = "console=ttyMSM0,115200n8 loglevel=6 kpti=0 log_buf_len=256K kernel.panic_on_rcu_stall=1 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops fw_devlink.strict=1 cpufreq.default_governor=performance printk.console_no_auto_verbose=1 kasan=off pcie_ports=compat";
 	};
 
 	reserved_memory: reserved-memory { };
@@ -46,6 +57,9 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x0>;
 			enable-method = "psci";
+			cpu-idle-states = <&SILVER_OFF>;
+			power-domains = <&CPU_PD0>;
+			power-domain-names = "psci";
 			cpu-release-addr = <0x0 0x90000000>;
 			next-level-cache = <&L2_0>;
 			qcom,freq-domain = <&cpufreq_hw 0>;
@@ -77,6 +91,9 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x100>;
 			enable-method = "psci";
+			cpu-idle-states = <&SILVER_OFF>;
+			power-domains = <&CPU_PD1>;
+			power-domain-names = "psci";
 			cpu-release-addr = <0x0 0x90000000>;
 			next-level-cache = <&L2_1>;
 			qcom,freq-domain = <&cpufreq_hw 0>;
@@ -102,6 +119,9 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x200>;
 			enable-method = "psci";
+			cpu-idle-states = <&SILVER_OFF>;
+			power-domains = <&CPU_PD2>;
+			power-domain-names = "psci";
 			cpu-release-addr = <0x0 0x90000000>;
 			next-level-cache = <&L2_2>;
 			qcom,freq-domain = <&cpufreq_hw 0>;
@@ -127,6 +147,9 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x300>;
 			enable-method = "psci";
+			cpu-idle-states = <&SILVER_OFF>;
+			power-domains = <&CPU_PD3>;
+			power-domain-names = "psci";
 			cpu-release-addr = <0x0 0x90000000>;
 			next-level-cache = <&L2_3>;
 			qcom,freq-domain = <&cpufreq_hw 0>;
@@ -152,6 +175,9 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x400>;
 			enable-method = "psci";
+			cpu-idle-states = <&GOLD_OFF>;
+			power-domains = <&CPU_PD4>;
+			power-domain-names = "psci";
 			cpu-release-addr = <0x0 0x90000000>;
 			next-level-cache = <&L2_4>;
 			qcom,freq-domain = <&cpufreq_hw 1>;
@@ -178,6 +204,9 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x500>;
 			enable-method = "psci";
+			cpu-idle-states = <&GOLD_OFF>;
+			power-domains = <&CPU_PD5>;
+			power-domain-names = "psci";
 			cpu-release-addr = <0x0 0x90000000>;
 			next-level-cache = <&L2_5>;
 			qcom,freq-domain = <&cpufreq_hw 1>;
@@ -203,6 +232,9 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x600>;
 			enable-method = "psci";
+			cpu-idle-states = <&GOLD_OFF>;
+			power-domains = <&CPU_PD6>;
+			power-domain-names = "psci";
 			cpu-release-addr = <0x0 0x90000000>;
 			next-level-cache = <&L2_6>;
 			qcom,freq-domain = <&cpufreq_hw 1>;
@@ -228,6 +260,9 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x700>;
 			enable-method = "psci";
+			cpu-idle-states = <&GOLD_OFF>;
+			power-domains = <&CPU_PD7>;
+			power-domain-names = "psci";
 			cpu-release-addr = <0x0 0x90000000>;
 			next-level-cache = <&L2_7>;
 			qcom,freq-domain = <&cpufreq_hw 2>;
@@ -291,6 +326,8 @@
 	};
 
 	idle-states {
+		entry-method = "psci";
+
 		SILVER_OFF: silver-c4 {  /* C4 */
 			compatible = "arm,idle-state";
 			idle-state-name = "rail-pc";
@@ -327,11 +364,57 @@
 	psci {
 		compatible = "arm,psci-1.0";
 		method = "smc";
+
+		CPU_PD0: cpu-pd0 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+		};
+
+		CPU_PD1: cpu-pd1 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+		};
+
+		CPU_PD2: cpu-pd2 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+		};
+
+		CPU_PD3: cpu-pd3 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+		};
+
+		CPU_PD4: cpu-pd4 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+		};
+
+		CPU_PD5: cpu-pd5 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+		};
+
+		CPU_PD6: cpu-pd6 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+		};
+
+		CPU_PD7: cpu-pd7 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+		};
+
+		CLUSTER_PD: cluster-pd {
+			#power-domain-cells = <0>;
+			domain-idle-states = <&APSS_OFF>;
+		};
 	};
 
 	firmware: firmware {
 		qcom_scm {
 			compatible = "qcom,scm";
+			qcom,dload-mode = <&tcsr 0x13000>;
 		};
 
 		qtee_shmbridge {
@@ -431,22 +514,22 @@
 		reg = <0x0 0x87300000 0x0 0x500000>;
 	};
 
-	pil_cdsp_mem: pil_cdsp_region@87800000 {
+	rproc_cdsp_mem: rproc_cdsp_region@87800000 {
 		no-map;
 		reg = <0x0 0x87800000 0x0 0x1400000>;
 	};
 
-	pil_slpi_mem: pil_slpi_region@88c00000 {
+	rproc_slpi_mem: rproc_slpi_region@88c00000 {
 		no-map;
 		reg = <0x0 0x88c00000 0x0 0x1500000>;
 	};
 
-	pil_adsp_mem: pil_adsp_region@8a100000 {
+	rproc_adsp_mem: rproc_adsp_region@8a100000 {
 		no-map;
 		reg = <0x0 0x8a100000 0x0 0x1d00000>;
 	};
 
-	pil_spss_mem: pil_spss_region@8be00000 {
+	rproc_spss_mem: rproc_spss_region@8be00000 {
 		no-map;
 		reg = <0x0 0x8be00000 0x0 0x100000>;
 	};
@@ -586,6 +669,42 @@
 	thermal_zones: thermal-zones {
 	};
 
+
+	slimbam: bamdma@3a84000 {
+		compatible = "qcom,bam-v1.7.0";
+		qcom,controlled-remotely;
+		reg = <0x3a84000 0x2c000>;
+		num-channels  = <31>;
+		interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
+		#dma-cells = <1>;
+		qcom,ee = <1>;
+		qcom,num-ees = <2>;
+		iommus = <&apps_smmu 0x1826 0x0>,
+			<&apps_smmu 0x182f 0x0>,
+			<&apps_smmu 0x1830 0x1>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
+		qcom,iommu-dma = "atomic";
+	};
+
+	slim_msm: slim@3ac0000 {
+		compatible = "qcom,slim-ngd-v1.5.0";
+		reg = <0x3ac0000 0x2c000>;
+		reg-names = "ctrl";
+		interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,apps-ch-pipes = <0x700000>;
+		qcom,ea-pc = <0x2d0>;
+		iommus = <&apps_smmu 0x1826 0x0>,
+			<&apps_smmu 0x182f 0x0>,
+			<&apps_smmu 0x1830 0x1>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
+		qcom,iommu-dma = "atomic";
+		dmas = <&slimbam 3>, <&slimbam 4>;
+		dma-names = "rx", "tx";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
 	intc: interrupt-controller@17a00000 {
 		compatible = "arm,gic-v3";
 		#interrupt-cells = <3>;
@@ -665,6 +784,26 @@
 		};
 	};
 
+	qcom_qseecom: qseecom@82400000 {
+			compatible = "qcom,qseecom";
+			reg = <0x82400000 0x3A00000>;
+			reg-names = "secapp-region";
+			memory-region = <&qseecom_mem>;
+			qseecom_mem = <&qseecom_mem>;
+			qseecom_ta_mem = <&qseecom_ta_mem>;
+			user_contig_mem = <&user_contig_mem>;
+			qcom,hlos-num-ce-hw-instances = <1>;
+			qcom,hlos-ce-hw-instance = <0>;
+			qcom,qsee-ce-hw-instance = <0>;
+			qcom,disk-encrypt-pipe-pair = <2>;
+			qcom,support-fde;
+			qcom,no-clock-support;
+			qcom,fde-key-size;
+			qcom,appsbl-qseecom-support;
+			qcom,commonlib64-loaded-by-uefi;
+			qcom,qsee-reentrancy-support = <2>;
+	};
+
 	cpu_pmu: cpu-pmu {
 		compatible = "arm,armv8-pmuv3";
 		qcom,irq-is-percpu;
@@ -701,6 +840,7 @@
 		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&CLUSTER_PD>;
 
 		apps_rsc_drv2: drv@2 {
 			qcom,drv-id = <2>;
@@ -731,6 +871,7 @@
 		reg-names = "drv-0";
 		qcom,drv-count = <1>;
 		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
 
 		disp_rsc_drv0: drv@0 {
 			qcom,drv-id = <0>;
@@ -759,6 +900,10 @@
 		interrupt-controller;
 	};
 
+	vendor_hooks: qcom,cpu-vendor-hooks {
+		compatible = "qcom,cpu-vendor-hooks";
+	};
+
 	clocks {
 		xo_board: xo-board {
 			compatible = "fixed-clock";
@@ -770,9 +915,23 @@
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
 			clock-frequency = <32000>;
-			clock-output-names = "chip_sleep_clk";
+			clock-output-names = "sleep_clk";
 			#clock-cells = <1>;
 		};
+
+		usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
+			#clock-cells = <0>;
+		};
+
+		usb3_uni_phy_sec_gcc_usb30_pipe_clk: usb3-uni-phy-sec-gcc-usb30-pipe-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			clock-output-names = "usb3_uni_phy_sec_gcc_usb30_pipe_clk";
+			#clock-cells = <0>;
+		};
 	};
 
 	gcc: clock-controller@100000 {
@@ -783,15 +942,21 @@
 		vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
 		vdd_mm-supply = <&VDD_MMCX_LEVEL>;
 		clocks = <&rpmhcc RPMH_CXO_CLK>,
-			<&rpmhcc RPMH_CXO_CLK_A>,
-			<&pcie_0_pipe_clk>,
-			<&pcie_1_pipe_clk>,
-			<&pcie_2_pipe_clk>;
+			 <&rpmhcc RPMH_CXO_CLK_A>,
+			 <&pcie_0_pipe_clk>,
+			 <&pcie_1_pipe_clk>,
+			 <&pcie_2_pipe_clk>,
+			 <&usb3_phy_wrapper_gcc_usb30_pipe_clk>,
+			 <&usb3_uni_phy_sec_gcc_usb30_pipe_clk>,
+			 <&sleep_clk>;
 		clock-names = "bi_tcxo",
-			"bi_tcxo_ao",
-			"pcie_0_pipe_clk",
-			"pcie_1_pipe_clk",
-			"pcie_2_pipe_clk";
+			      "bi_tcxo_ao",
+			      "pcie_0_pipe_clk",
+			      "pcie_1_pipe_clk",
+			      "pcie_2_pipe_clk",
+			      "usb3_phy_wrapper_gcc_usb30_pipe_clk",
+			      "usb3_uni_phy_sec_gcc_usb30_pipe_clk",
+			      "sleep_clk";
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
@@ -801,8 +966,12 @@
 		reg = <0x9800000 0x190000>;
 		reg-name = "cc_base";
 		vdd_cx-supply = <&VDD_CX_LEVEL>;
-		clocks = <&rpmhcc RPMH_CXO_CLK>;
-		clock-names = "bi_tcxo";
+		clocks = <&rpmhcc RPMH_CXO_CLK>,
+			 <&gcc GCC_NPU_GPLL0_DIV_CLK_SRC>,
+			 <&gcc GCC_NPU_GPLL0_CLK_SRC>;
+		clock-names = "bi_tcxo",
+			      "gcc_npu_gpll0_div_clk",
+			      "gcc_npu_gpll0_clk";
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
@@ -813,8 +982,14 @@
 		reg-names = "cc_base";
 		vdd_mx-supply = <&VDD_MX_LEVEL>;
 		vdd_mm-supply = <&VDD_MMCX_LEVEL>;
-		clock-names = "cfg_ahb_clk";
-		clocks = <&gcc GCC_VIDEO_AHB_CLK>;
+		clock-names = "cfg_ahb_clk",
+			      "bi_tcxo_ao",
+			      "bi_tcxo",
+			      "sleep_clk";
+		clocks = <&gcc GCC_VIDEO_AHB_CLK>,
+			 <&rpmhcc RPMH_CXO_CLK_A>,
+			 <&rpmhcc RPMH_CXO_CLK>,
+			 <&sleep_clk>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
@@ -825,8 +1000,14 @@
 		reg-names = "cc_base";
 		vdd_mx-supply = <&VDD_MX_LEVEL>;
 		vdd_mm-supply = <&VDD_MMCX_LEVEL>;
-		clock-names = "cfg_ahb_clk";
-		clocks = <&gcc GCC_CAMERA_AHB_CLK>;
+		clock-names = "cfg_ahb_clk",
+			      "bi_tcxo",
+			      "bi_tcxo_ao",
+			      "sleep_clk";
+		clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+			 <&rpmhcc RPMH_CXO_CLK>,
+			 <&rpmhcc RPMH_CXO_CLK_A>,
+			 <&sleep_clk>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
@@ -836,8 +1017,12 @@
 		reg = <0xaf00000 0x20000>;
 		reg-names = "cc_base";
 		vdd_mm-supply = <&VDD_MMCX_LEVEL>;
-		clock-names = "cfg_ahb_clk";
-		clocks = <&gcc GCC_DISP_AHB_CLK>;
+		clock-names = "cfg_ahb_clk",
+			      "bi_tcxo",
+			      "bi_tcxo_ao";
+		clocks = <&gcc GCC_DISP_AHB_CLK>,
+			 <&rpmhcc RPMH_CXO_CLK>,
+			 <&rpmhcc RPMH_CXO_CLK_A>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
@@ -848,6 +1033,12 @@
 		reg-names = "cc_base";
 		vdd_cx-supply = <&VDD_CX_LEVEL>;
 		vdd_mx-supply = <&VDD_MX_LEVEL>;
+		clocks = <&rpmhcc RPMH_CXO_CLK>,
+			 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,
+			 <&gcc GCC_GPU_GPLL0_CLK_SRC>;
+		clock-names = "bi_tcxo",
+			      "gcc_gpu_gpll0_div_clk_src",
+			      "gcc_gpu_gpll0_clk_src";
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
@@ -1290,7 +1481,6 @@
 
 	qcom_pmu: qcom,pmu {
 		compatible = "qcom,pmu";
-		qcom,long-counter;
 		qcom,pmu-events-tbl =
 			< 0x0008 0xFF 0xFF 0xFF >,
 			< 0x0011 0xFF 0xFF 0xFF >,
@@ -1576,6 +1766,13 @@
 		0x18020060 0x18030060>;
 	};
 
+	dsu_pmu@0 {
+		compatible = "arm,dsu-pmu";
+		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+		cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
+			<&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
+	};
+
 	qcom,chd_gold {
 		compatible = "qcom,core-hang-detect";
 		label = "gold";
@@ -1585,13 +1782,6 @@
 		0x18060060 0x18070060>;
 	};
 
-	cache-controller@9200000 {
-		compatible = "qcom,kona-llcc";
-		reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>;
-		reg-names = "llcc_base", "llcc_broadcast_base";
-		cap-based-alloc-and-pwr-collapse;
-	};
-
 	ufsphy_mem: ufsphy_mem@1d87000 {
 		reg = <0x1d87000 0xe00>; /* PHY regs */
 		reg-names = "phy_mem";
@@ -1796,6 +1986,91 @@
 		};
 	};
 
+	tcsr_mutex_block: syscon@1f40000 {
+		compatible = "syscon";
+		reg = <0x1f40000 0x20000>;
+	};
+
+	tcsr_mutex: hwlock {
+		compatible = "qcom,tcsr-mutex";
+		syscon = <&tcsr_mutex_block 0 0x1000>;
+		#hwlock-cells = <1>;
+	};
+
+	smem: qcom,smem {
+		compatible = "qcom,smem";
+		memory-region = <&smem_mem>;
+		depends-on-supply = <&tcsr_mutex>;
+		hwlocks = <&tcsr_mutex 3>;
+	};
+
+	tcsr: syscon@1fc0000 {
+		compatible = "syscon";
+		reg = <0x1fc0000 0x30000>;
+	};
+
+	cluster-device {
+		compatible = "qcom,lpm-cluster-dev";
+		power-domains = <&CLUSTER_PD>;
+	};
+
+	soc-sleep-stats@c3f0000 {
+		compatible = "qcom,rpmh-sleep-stats";
+		reg = <0xc3f0000 0x400>;
+		ss-name = "modem", "adsp", "adsp_island",
+			  "cdsp", "apss";
+		mboxes = <&qmp_aop 0>;
+		mbox-names = "aop";
+	};
+
+	subsystem-sleep-stats@c3f0000 {
+		compatible = "qcom,subsystem-sleep-stats";
+		reg = <0xc3f0000 0x400>;
+	};
+
+	ipcc_mproc: qcom,ipcc@408000 {
+		compatible = "qcom,ipcc";
+		reg = <0x408000 0x1000>;
+		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		#mbox-cells = <2>;
+	};
+
+	aoss_qmp: power-controller@c300000 {
+		compatible = "qcom,kona-aoss-qmp";
+		reg = <0xc300000 0x400>;
+		interrupt-parent = <&ipcc_mproc>;
+		interrupts = <IPCC_CLIENT_AOP
+			      IPCC_MPROC_SIGNAL_GLINK_QMP
+			      IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
+			  IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+		#power-domain-cells = <1>;
+		#clock-cells = <0>;
+	};
+
+	qmp_aop: qcom,qmp-aop {
+		compatible = "qcom,qmp-mbox";
+		qcom,qmp = <&aoss_qmp>;
+		label = "aop";
+		#mbox-cells = <1>;
+	};
+
+	cache-controller@9200000 {
+		compatible = "qcom,kona-llcc";
+		reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>;
+		reg-names = "llcc_base", "llcc_broadcast_base";
+		cap-based-alloc-and-pwr-collapse;
+
+		llcc-perfmon {
+			compatible = "qcom,llcc-perfmon";
+			clocks = <&aoss_qmp>;
+			clock-names = "qdss_clk";
+		};
+	};
+
 	wdog: qcom,wdt@17c10000 {
 		compatible = "qcom,msm-watchdog";
 		reg = <0x17c10000 0x1000>;
@@ -1808,6 +2083,16 @@
 		qcom,ipi-ping;
 	};
 
+	qcom,mem-buf {
+		compatible = "qcom,mem-buf";
+		qcom,mem-buf-capabilities = "supplier";
+		qcom,vmid = <3>;
+	};
+
+	qcom,mem-buf-msgq {
+		compatible = "qcom,mem-buf-msgq";
+	};
+
 	qcom,msm-imem@146bf000 {
 		compatible = "qcom,msm-imem";
 		reg = <0x146bf000 0x1000>;
@@ -1841,16 +2126,27 @@
 		};
 
 		pil@94c {
-			compatible = "qcom,msm-imem-pil";
+			compatible = "qcom,pil-reloc-info";
 			reg = <0x94c 0xc8>;
 		};
 
+		pil@6dc {
+			compatible = "qcom,msm-imem-pil-disable-timeout";
+			reg = <0x6dc 0x4>;
+		};
+
 		diag_dload@c8 {
 			compatible = "qcom,msm-imem-diag-dload";
 			reg = <0xc8 0xc8>;
 		};
 	};
 
+	restart@c264000 {
+		compatible = "qcom,pshold";
+		reg = <0xc264000 0x4>, <0x1fd3000 0x4>;
+		reg-names = "pshold-base", "tcsr-boot-misc-detect";
+	};
+
 	qcom,mpm2-sleep-counter@c221000 {
 		compatible = "qcom,mpm2-sleep-counter";
 		reg = <0xc221000 0x1000>;
@@ -1866,6 +2162,13 @@
 		status = "ok";
 	};
 
+	ssc_sensors: qcom,msm-ssc-sensors {
+		compatible = "qcom,msm-ssc-sensors";
+		status = "ok";
+		qcom,firmware-name = "slpi";
+		qcom,rproc-handle = <&slpi_pas>;
+	};
+
 	mem_dump {
 		compatible = "qcom,mem-dump";
 		memory-region = <&dump_mem>;
@@ -2206,32 +2509,6 @@
 		};
 	};
 
-	tsens0: tsens@c222000 {
-		compatible = "qcom,tsens24xx";
-		reg = <0xc222000 0x4>,
-			<0xc263000 0x1ff>;
-		reg-names = "tsens_srot_physical",
-				"tsens_tm_physical";
-		interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "tsens-upper-lower", "tsens-critical";
-		tsens-reinit-wa;
-		#thermal-sensor-cells = <1>;
-	};
-
-	tsens1: tsens@c223000 {
-		compatible = "qcom,tsens24xx";
-		reg = <0xc223000 0x4>,
-			<0xc265000 0x1ff>;
-		reg-names = "tsens_srot_physical",
-			"tsens_tm_physical";
-		interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "tsens-upper-lower", "tsens-critical";
-		tsens-reinit-wa;
-		#thermal-sensor-cells = <1>;
-	};
-
 	eud: qcom,msm-eud@88e0000 {
 		compatible = "qcom,msm-eud";
 		interrupt-names = "eud_irq";
@@ -2244,8 +2521,1540 @@
 		qcom,eud-clock-vote-req;
 		clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_BCR>;
 		clock-names = "eud_ahb2phy_clk";
+	};
+
+	adsp_pas: remoteproc-adsp@17300000 {
+		compatible = "qcom,kona-adsp-pas";
+		reg = <0x17300000 0x00100>;
+		status = "ok";
+
+		cx-supply = <&L11A_LEVEL>;
+		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+		mx-supply = <&L4A_LEVEL>;
+		mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+		reg-names = "cx", "mx";
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clock-names = "xo";
+
+		qcom,signal-aop;
+		qcom,qmp = <&aoss_qmp>;
+
+		memory-region = <&rproc_adsp_mem>;
+
+		/* Inputs from ssc */
+		interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+					<&adsp_smp2p_in 0 0>,
+					<&adsp_smp2p_in 2 0>,
+					<&adsp_smp2p_in 1 0>,
+					<&adsp_smp2p_in 3 0>,
+					<&adsp_smp2p_in 7 0>;
+
+		interrupt-names = "wdog",
+				"fatal",
+				"handover",
+				"ready",
+				"stop-ack",
+				"shutdown-ack";
+
+		/* Outputs to turing */
+		qcom,smem-states = <&adsp_smp2p_out 0>;
+		qcom,smem-state-names = "stop";
+
+		glink_edge: glink-edge {
+			qcom,remote-pid = <2>;
+			transport = "smem";
+			mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
+				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
+			mbox-names = "adsp_smem";
+			interrupt-parent = <&ipcc_mproc>;
+			interrupts = <IPCC_CLIENT_LPASS
+				      IPCC_MPROC_SIGNAL_GLINK_QMP
+				      IRQ_TYPE_EDGE_RISING>;
+
+			label = "adsp";
+			qcom,glink-label = "lpass";
+
+			qcom,adsp_qrtr {
+				qcom,glink-channels = "IPCRTR";
+				qcom,intents = <0x800  5
+						0x2000 3
+						0x4400 2>;
+				qcom,no-wake-svc = <0x190>;
+			};
+
+			qcom,apr_tal_rpmsg {
+				qcom,glink-channels = "apr_audio_svc";
+				qcom,intents = <0x200 20>;
+			};
+
+			qcom,msm_fastrpc_rpmsg {
+				compatible = "qcom,msm-fastrpc-rpmsg";
+				qcom,glink-channels = "fastrpcglink-apps-dsp";
+				qcom,intents = <0x64 64>;
+			};
+
+			qcom,adsp_glink_ssr {
+				qcom,glink-channels = "glink_ssr";
+			};
+		};
+	};
+
+	cdsp_pas: remoteproc-cdsp@8300000 {
+		compatible = "qcom,kona-cdsp-pas";
+		reg = <0x8300000 0x100000>;
+		status = "ok";
+
+		cx-supply = <&VDD_CX_LEVEL>;
+		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+		reg-names = "cx";
+
+		memory-region = <&rproc_cdsp_mem>;
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clock-names = "xo";
+
+		qcom,signal-aop;
+		qcom,qmp = <&aoss_qmp>;
+
+		interconnects = <&compute_noc MASTER_NPU &compute_noc SLAVE_CDSP_MEM_NOC>;
+		interconnect-names = "rproc_ddr";
+
+		/* Inputs from turing */
+		interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
+					<&cdsp_smp2p_in 0 0>,
+					<&cdsp_smp2p_in 2 0>,
+					<&cdsp_smp2p_in 1 0>,
+					<&cdsp_smp2p_in 3 0>,
+					<&cdsp_smp2p_in 7 0>;
+
+		interrupt-names = "wdog",
+				"fatal",
+				"handover",
+				"ready",
+				"stop-ack",
+				"shutdown-ack";
+
+		/* Outputs to turing */
+		qcom,smem-states = <&cdsp_smp2p_out 0>;
+		qcom,smem-state-names = "stop";
+
+		glink-edge {
+			qcom,remote-pid = <5>;
+			transport = "smem";
+			mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP
+				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
+			mbox-names = "cdsp_smem";
+			interrupt-parent = <&ipcc_mproc>;
+			interrupts = <IPCC_CLIENT_CDSP
+				      IPCC_MPROC_SIGNAL_GLINK_QMP
+				      IRQ_TYPE_EDGE_RISING>;
+
+			label = "cdsp";
+			qcom,glink-label = "cdsp";
+
+			qcom,cdsp_qrtr {
+				qcom,glink-channels = "IPCRTR";
+				qcom,intents = <0x800  5
+						0x2000 3
+						0x4400 2>;
+			};
+
+			qcom,msm_fastrpc_rpmsg {
+				compatible = "qcom,msm-fastrpc-rpmsg";
+				qcom,glink-channels = "fastrpcglink-apps-dsp";
+				qcom,intents = <0x64 64>;
+			};
+
+			qcom,msm_cdsprm_rpmsg {
+				compatible = "qcom,msm-cdsprm-rpmsg";
+				qcom,glink-channels = "cdsprmglink-apps-dsp";
+				qcom,intents = <0x20 12>;
+
+				msm_cdsp_rm: qcom,msm_cdsp_rm {
+					compatible = "qcom,msm-cdsp-rm";
+					qcom,qos-latency-us = <44>;
+					qcom,qos-maxhold-ms = <20>;
+					qcom,compute-cx-limit-en;
+					qcom,compute-priority-mode = <2>;
+					#cooling-cells = <2>;
+				};
+
+				msm_hvx_rm: qcom,msm_hvx_rm {
+					compatible = "qcom,msm-hvx-rm";
+					#cooling-cells = <2>;
+				};
+			};
+
+			qcom,cdsp_glink_ssr {
+				qcom,glink-channels = "glink_ssr";
+			};
+		};
+	};
+
+	slpi_pas: remoteproc-slpi@5c00000 {
+		compatible = "qcom,kona-slpi-pas";
+		reg = <0x5c00000 0x4000>;
+		status = "disabled";
+
+		cx-supply = <&L11A_LEVEL>;
+		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+		mx-supply = <&L4A_LEVEL>;
+		mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+		reg-names = "cx", "mx";
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clock-names = "xo";
+
+		qcom,qmp = <&aoss_qmp>;
+
+
+		memory-region = <&rproc_slpi_mem>;
+
+		qcom,signal-aop;
+
+		/* Inputs from ssc */
+		interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
+					<&dsps_smp2p_in 0 0>,
+					<&dsps_smp2p_in 2 0>,
+					<&dsps_smp2p_in 1 0>,
+					<&dsps_smp2p_in 3 0>,
+					<&dsps_smp2p_in 7 0>;
+
+		interrupt-names = "wdog",
+				"fatal",
+				"handover",
+				"ready",
+				"stop-ack",
+				"shutdown-ack";
+
+		/* Outputs to turing */
+		qcom,smem-states = <&dsps_smp2p_out 0>;
+		qcom,smem-state-names = "stop";
+
+		glink-edge {
+			qcom,remote-pid = <3>;
+			transport = "smem";
+			mboxes = <&ipcc_mproc IPCC_CLIENT_SLPI
+				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
+			mbox-names = "dsps_smem";
+			interrupt-parent = <&ipcc_mproc>;
+			interrupts = <IPCC_CLIENT_SLPI
+				      IPCC_MPROC_SIGNAL_GLINK_QMP
+				      IRQ_TYPE_EDGE_RISING>;
+
+			label = "slpi";
+			qcom,glink-label = "dsps";
+
+			qcom,slpi_qrtr {
+				qcom,glink-channels = "IPCRTR";
+				qcom,net-id = <2>;
+				qcom,low-latency;
+				qcom,intents = <0x800  5
+						0x2000 3
+						0x4400 2>;
+			};
+
+			qcom,msm_fastrpc_rpmsg {
+				compatible = "qcom,msm-fastrpc-rpmsg";
+				qcom,glink-channels = "fastrpcglink-apps-dsp";
+				qcom,intents = <0x64 64>;
+			};
+
+			qcom,slpi_glink_ssr {
+				qcom,glink-channels = "glink_ssr";
+			};
+		};
+	};
+
+	spss_pas: remoteproc-spss@1880000 {
+		compatible = "qcom,kona-spss-pas";
+		ranges;
+		reg = <0x188101c 0x4>,
+		      <0x1881024 0x4>,
+		      <0x1881028 0x4>,
+		      <0x188103c 0x4>,
+		      <0x1881100 0x4>,
+		      <0x1882014 0x4>;
+		reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", "sp2soc_irq_mask",
+			    "rmb_err", "rmb_general_purpose", "rmb_err_spare2";
+		interrupts = <0 352 1>;
+
+		cx-supply = <&VDD_CX_LEVEL>;
+		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+		mx-supply = <&VDD_MX_LEVEL>;
+		mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clock-names = "xo";
+		qcom,proxy-clock-names = "xo";
+		status = "ok";
+
+		memory-region = <&rproc_spss_mem>;
+		qcom,spss-scsr-bits = <24 25>;
+		qcom,extra-size = <4096>;
+		qcom,signal-aop;
+
+		glink-edge {
+			qcom,remote-pid = <8>;
+			mboxes = <&ipcc_mproc IPCC_CLIENT_SPSS
+				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
+			mbox-names = "spss_spss";
+			interrupt-parent = <&ipcc_mproc>;
+			interrupts = <IPCC_CLIENT_SPSS
+				      IPCC_MPROC_SIGNAL_GLINK_QMP
+				      IRQ_TYPE_EDGE_RISING>;
+
+			reg = <0x1885008 0x8>,
+			      <0x1885010 0x4>;
+			reg-names = "qcom,spss-addr",
+				    "qcom,spss-size";
+
+			label = "spss";
+			qcom,glink-label = "spss";
+		};
+	};
+
+	qcom,smp2p_sleepstate {
+		compatible = "qcom,smp2p-sleepstate";
+		qcom,smem-states = <&sleepstate_smp2p_out 0>;
+		interrupt-parent = <&sleepstate_smp2p_in>;
+		interrupts = <0 0>;
+		interrupt-names = "smp2p-sleepstate-in";
+	};
+
+	qcom,msm-cdsp-loader {
+		compatible = "qcom,cdsp-loader";
+		qcom,proc-img-to-load = "cdsp";
+		qcom,rproc-handle = <&cdsp_pas>;
+	};
+
+	qcom,msm-adsprpc-mem {
+		compatible = "qcom,msm-adsprpc-mem-region";
+		memory-region = <&adsp_mem>;
+		restrict-access;
+	};
+
+	msm_fastrpc: qcom,msm_fastrpc {
+		compatible = "qcom,msm-fastrpc-compute";
+		qcom,adsp-remoteheap-vmid = <22 37>;
+		qcom,fastrpc-adsp-audio-pdr;
+		qcom,fastrpc-slpi-sensors-pdr;
+		qcom,rpc-latency-us = <235>;
+		qcom,qos-cores = <0 1 2 3>;
+
+		qcom,msm_fastrpc_compute_cb1 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x1001 0x0460>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb2 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x1002 0x0460>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb3 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x1003 0x0460>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb4 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x1004 0x0460>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb5 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x1005 0x0460>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb6 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x1006 0x0460>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb7 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x1007 0x0460>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb8 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x1008 0x0460>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb9 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			qcom,secure-context-bank;
+			iommus = <&apps_smmu 0x1009 0x0460>;
+			qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			qcom,iommu-vmid = <0xA>;	/* VMID_CP_PIXEL */
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb10 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "adsprpc-smd";
+			iommus = <&apps_smmu 0x1803 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb11 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "adsprpc-smd";
+			iommus = <&apps_smmu 0x1804 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb12 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "adsprpc-smd";
+			iommus = <&apps_smmu 0x1805 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb13 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "sdsprpc-smd";
+			iommus = <&apps_smmu 0x0541 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb14 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "sdsprpc-smd";
+			iommus = <&apps_smmu 0x0542 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb15 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "sdsprpc-smd";
+			iommus = <&apps_smmu 0x0543 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			shared-cb = <4>;
+			dma-coherent;
+		};
+	};
+
+	qcom,spcom {
+		compatible = "qcom,spcom";
+
+		qcom,rproc-handle = <&spss_pas>;
+		qcom,boot-enabled;
+		/* predefined channels, remote side is server */
+		qcom,spcom-ch-names = "sp_kernel", "sp_ssr";
+		/* sp2soc rmb shared register physical address and bmsk */
+		qcom,spcom-sp2soc-rmb-reg-addr = <0x01881020>;
+		qcom,spcom-sp2soc-rmb-initdone-bit = <24>;
+		qcom,spcom-sp2soc-rmb-pbldone-bit = <25>;
+		/* soc2sp rmb shared register physical address */
+		qcom,spcom-soc2sp-rmb-reg-addr = <0x01881030>;
+		qcom,spcom-soc2sp-rmb-sp-ssr-bit = <0>;
 		status = "ok";
 	};
+
+	spss_utils: qcom,spss_utils {
+		compatible = "qcom,spss-utils";
+		/* spss fuses physical address */
+		qcom,rproc-handle = <&spss_pas>;
+		qcom,spss-fuse1-addr = <0x00780234>;
+		qcom,spss-fuse1-bit = <27>;
+		qcom,spss-fuse2-addr = <0x00780234>;
+		qcom,spss-fuse2-bit = <26>;
+		qcom,spss-dev-firmware-name  = "spss1d.mdt";  /* 8 chars max */
+		qcom,spss-test-firmware-name = "spss1t.mdt";  /* 8 chars max */
+		qcom,spss-prod-firmware-name = "spss1p.mdt";  /* 8 chars max */
+		qcom,spss-debug-reg-addr = <0x01886020>;
+		qcom,spss-debug-reg-addr1 = <0x01888020>;
+		qcom,spss-debug-reg-addr3 = <0x0188C020>;
+		qcom,spss-emul-type-reg-addr = <0x01fc8004>;
+		pil-mem = <&rproc_spss_mem>;
+		qcom,pil-addr = <0x8BE00000>; // backward compatible
+		qcom,pil-size = <0x0F0000>; // padding to 960KB
+		status = "ok";
+	};
+
+	qcom,glinkpkt {
+		compatible = "qcom,glinkpkt";
+
+		qcom,glinkpkt-at-mdm0 {
+			qcom,glinkpkt-edge = "mpss";
+			qcom,glinkpkt-ch-name = "DS";
+			qcom,glinkpkt-dev-name = "at_mdm0";
+		};
+
+		qcom,glinkpkt-apr-apps2 {
+			qcom,glinkpkt-edge = "adsp";
+			qcom,glinkpkt-ch-name = "apr_apps2";
+			qcom,glinkpkt-dev-name = "apr_apps2";
+		};
+
+		qcom,glinkpkt-data40-cntl {
+			qcom,glinkpkt-edge = "mpss";
+			qcom,glinkpkt-ch-name = "DATA40_CNTL";
+			qcom,glinkpkt-dev-name = "smdcntl8";
+		};
+
+		qcom,glinkpkt-data1 {
+			qcom,glinkpkt-edge = "mpss";
+			qcom,glinkpkt-ch-name = "DATA1";
+			qcom,glinkpkt-dev-name = "smd7";
+		};
+
+		qcom,glinkpkt-data4 {
+			qcom,glinkpkt-edge = "mpss";
+			qcom,glinkpkt-ch-name = "DATA4";
+			qcom,glinkpkt-dev-name = "smd8";
+		};
+
+		qcom,glinkpkt-data11 {
+			qcom,glinkpkt-edge = "mpss";
+			qcom,glinkpkt-ch-name = "DATA11";
+			qcom,glinkpkt-dev-name = "smd11";
+		};
+
+		qcom,glinkpkt-slate-ssc-hal {
+			qcom,glinkpkt-edge = "slate";
+			qcom,glinkpkt-ch-name = "ssc_hal";
+			qcom,glinkpkt-dev-name = "glinkpkt_slate_ssc_hal";
+			qcom,glinkpkt-enable-ch-close;
+		};
+	};
+
+	qcom,glink {
+		compatible = "qcom,glink";
+	};
+
+	dcc: dcc_v2@1023000 {
+		compatible = "qcom,dcc-v2";
+		reg = <0x1023000 0x1000>,
+		      <0x103a000 0x6000>;
+		reg-names = "dcc-base", "dcc-ram-base";
+
+		dcc-ram-offset = <0x1a000>;
+
+		link_list1 {
+			qcom,curr-link-list = <3>;
+			qcom,data-sink = "sram";
+			qcom,link-list = <DCC_READ 0x18220d14 3 0>,
+				<DCC_READ 0x18220d30 4 0>,
+				<DCC_READ 0x18220d44 4 0>,
+				<DCC_READ 0x18220d58 4 0>,
+				<DCC_READ 0x18220fb4 3 0>,
+				<DCC_READ 0x18220fd0 4 0>,
+				<DCC_READ 0x18220fe4 4 0>,
+				<DCC_READ 0x18220ff8 4 0>,
+				<DCC_READ 0x18220d04 1 0>,
+				<DCC_READ 0x18220d00 1 0>,
+				<DCC_READ 0x18000024 1 0>,
+				<DCC_READ 0x18000040 4 0>,
+				<DCC_READ 0x18010024 1 0>,
+				<DCC_READ 0x18010040 4 0>,
+				<DCC_READ 0x18020024 1 0>,
+				<DCC_READ 0x18020040 4 0>,
+				<DCC_READ 0x18030024 1 0>,
+				<DCC_READ 0x18030040 4 0>,
+				<DCC_READ 0x18040024 1 0>,
+				<DCC_READ 0x18040040 4 0>,
+				<DCC_READ 0x18050024 1 0>,
+				<DCC_READ 0x18050040 4 0>,
+				<DCC_READ 0x18060024 1 0>,
+				<DCC_READ 0x18060040 4 0>,
+				<DCC_READ 0x18070024 1 0>,
+				<DCC_READ 0x18070040 4 0>,
+				<DCC_READ 0x18080104 1 0>,
+				<DCC_READ 0x18080168 1 0>,
+				<DCC_READ 0x18080198 1 0>,
+				<DCC_READ 0x18080128 1 0>,
+				<DCC_READ 0x18080024 1 0>,
+				<DCC_READ 0x18080040 3 0>,
+				<DCC_READ 0x18200400 3 0>,
+				<DCC_READ 0x0b201020 2 0>,
+				<DCC_READ 0x0b204520 1 0>,
+				<DCC_READ 0x1800005c 1 0>,
+				<DCC_READ 0x1801005c 1 0>,
+				<DCC_READ 0x1802005c 1 0>,
+				<DCC_READ 0x1803005c 1 0>,
+				<DCC_READ 0x1804005c 1 0>,
+				<DCC_READ 0x1805005c 1 0>,
+				<DCC_READ 0x1806005c 1 0>,
+				<DCC_READ 0x1807005c 1 0>,
+				<DCC_READ 0x18101908 1 0>,
+				<DCC_READ 0x18101c18 1 0>,
+				<DCC_READ 0x18390810 1 0>,
+				<DCC_READ 0x18390c50 1 0>,
+				<DCC_READ 0x18390814 1 0>,
+				<DCC_READ 0x18390c54 1 0>,
+				<DCC_READ 0x18390818 1 0>,
+				<DCC_READ 0x18390c58 1 0>,
+				<DCC_READ 0x18393a84 2 0>,
+				<DCC_READ 0x18100908 1 0>,
+				<DCC_READ 0x18100c18 1 0>,
+				<DCC_READ 0x183a0810 1 0>,
+				<DCC_READ 0x183a0c50 1 0>,
+				<DCC_READ 0x183a0814 1 0>,
+				<DCC_READ 0x183a0c54 1 0>,
+				<DCC_READ 0x183a0818 1 0>,
+				<DCC_READ 0x183a0c58 1 0>,
+				<DCC_READ 0x183a3a84 2 0>,
+				<DCC_READ 0x18393500 1 0>,
+				<DCC_READ 0x18393580 1 0>,
+				<DCC_READ 0x183a3500 1 0>,
+				<DCC_READ 0x183a3580 1 0>,
+				<DCC_READ 0x18282000 4 0>,
+				<DCC_READ 0x18282028 1 0>,
+				<DCC_READ 0x18282038 1 0>,
+				<DCC_READ 0x18282080 5 0>,
+				<DCC_READ 0x18286000 4 0>,
+				<DCC_READ 0x18286028 1 0>,
+				<DCC_READ 0x18286038 1 0>,
+				<DCC_READ 0x18286080 5 0>,
+				<DCC_READ 0x0c201244 1 0>,
+				<DCC_READ 0x0c202244 1 0>,
+				<DCC_READ 0x18300000 1 0>,
+				<DCC_READ 0x1829208c 1 0>,
+				<DCC_READ 0x18292098 1 0>,
+				<DCC_READ 0x18292098 1 0>,
+				<DCC_READ 0x1829608c 1 0>,
+				<DCC_READ 0x18296098 1 0>,
+				<DCC_READ 0x18296098 1 0>,
+				<DCC_READ 0x091a9020 1 0>,
+				<DCC_READ_WRITE 0x5 0x1 0>,
+				<DCC_READ 0x09102008 1 0>,
+				<DCC_READ_WRITE 0x2 0x2 0>,
+				<DCC_READ 0x09142008 1 0>,
+				<DCC_READ_WRITE 0x2 0x2 0>,
+				<DCC_READ 0x09102408 1 0>,
+				<DCC_READ_WRITE 0x2 0x2 0>,
+				<DCC_READ 0x09142408 1 0>,
+				<DCC_READ_WRITE 0x2 0x2 0>,
+				<DCC_READ 0x09103808 1 0>,
+				<DCC_LOOP 3 0 0>,
+				<DCC_READ 0x09103810 1 0>,
+				<DCC_READ 0x09103814 1 0>,
+				<DCC_LOOP 1 0 0>,
+				<DCC_READ 0x09103888 1 0>,
+				<DCC_LOOP 2 0 0>,
+				<DCC_READ 0x09103890 1 0>,
+				<DCC_READ 0x09103894 1 0>,
+				<DCC_LOOP 1 0 0>,
+				<DCC_READ 0x09143808 1 0>,
+				<DCC_LOOP 3 0 0>,
+				<DCC_READ 0x09143810 1 0>,
+				<DCC_READ 0x09143814 1 0>,
+				<DCC_LOOP 1 0 0>,
+				<DCC_READ 0x09143888 1 0>,
+				<DCC_LOOP 2 0 0>,
+				<DCC_READ 0x09143890 1 0>,
+				<DCC_READ 0x09143894 1 0>,
+				<DCC_LOOP 1 0 0>,
+				<DCC_READ 0x09182808 1 0>,
+				<DCC_LOOP 2 0 0>,
+				<DCC_READ 0x09182810 1 0>,
+				<DCC_READ 0x09182814 1 0>,
+				<DCC_LOOP 1 0 0>,
+				<DCC_READ 0x09182888 1 0>,
+				<DCC_LOOP 3 0 0>,
+				<DCC_READ 0x09182890 1 0>,
+				<DCC_READ 0x09182894 1 0>,
+				<DCC_LOOP 1 0 0>,
+				<DCC_READ 0x09103008 1 0>,
+				<DCC_READ 0x0910300c 1 0>,
+				<DCC_WRITE 0x09103028 0x00000001 1>,
+				<DCC_LOOP 41 0 0>,
+				<DCC_READ 0x09103010 1 0>,
+				<DCC_READ 0x09103014 1 0>,
+				<DCC_LOOP 1 0 0>,
+				<DCC_READ 0x09103408 1 0>,
+				<DCC_READ 0x0910340c 1 0>,
+				<DCC_WRITE 0x09103428 0x00000001 1>,
+				<DCC_LOOP 41 0 0>,
+				<DCC_READ 0x09103410 1 0>,
+				<DCC_READ 0x09103414 1 0>,
+				<DCC_LOOP 1 0 0>,
+				<DCC_READ 0x09143008 1 0>,
+				<DCC_READ 0x0914300c 1 0>,
+				<DCC_WRITE 0x09143028 0x00000001 1>,
+				<DCC_LOOP 41 0 0>,
+				<DCC_READ 0x09143010 1 0>,
+				<DCC_READ 0x09143014 1 0>,
+				<DCC_LOOP 1 0 0>,
+				<DCC_READ 0x09143408 1 0>,
+				<DCC_READ 0x0914340c 1 0>,
+				<DCC_WRITE 0x09143428 0x00000001 1>,
+				<DCC_LOOP 41 0 0>,
+				<DCC_READ 0x09143410 1 0>,
+				<DCC_READ 0x09143414 1 0>,
+				<DCC_LOOP 1 0 0>,
+				<DCC_READ 0x09182008 1 0>,
+				<DCC_READ 0x0918200c 1 0>,
+				<DCC_WRITE 0x09182028 0x00000001 1>,
+				<DCC_LOOP 11 0 0>,
+				<DCC_READ 0x09182010 1 0>,
+				<DCC_READ 0x09182014 1 0>,
+				<DCC_LOOP 1 0 0>,
+				<DCC_READ 0x09182408 1 0>,
+				<DCC_READ 0x0918240c 1 0>,
+				<DCC_WRITE 0x09182428 0x00000001 1>,
+				<DCC_LOOP 11 0 0>,
+				<DCC_READ 0x09182410 1 0>,
+				<DCC_READ 0x09182414 1 0>,
+				<DCC_LOOP 1 0 0>;
+		};
+
+		link_list2 {
+			qcom,curr-link-list = <6>;
+			qcom,data-sink = "sram";
+			qcom,link-list = <DCC_READ 0x9050078 1 0>,
+				<DCC_READ 0x9050110 8 0>,
+				<DCC_READ 0x9080058 2 0>,
+				<DCC_READ 0x90800c8 1 0>,
+				<DCC_READ 0x90800d4 1 0>,
+				<DCC_READ 0x90800e0 1 0>,
+				<DCC_READ 0x90800ec 1 0>,
+				<DCC_READ 0x90800f8 1 0>,
+				<DCC_READ 0x908401c 1 0>,
+				<DCC_READ 0x908403c 1 0>,
+				<DCC_READ 0x908404c 2 0>,
+				<DCC_READ 0x90840d4 1 0>,
+				<DCC_READ 0x9084204 1 0>,
+				<DCC_READ 0x908420c 1 0>,
+				<DCC_READ 0x9084250 2 0>,
+				<DCC_READ 0x9084260 3 0>,
+				<DCC_READ 0x9084280 1 0>,
+				<DCC_READ 0x90ba280 1 0>,
+				<DCC_READ 0x90ba288 7 0>,
+				<DCC_READ 0x9258610 4 0>,
+				<DCC_READ 0x92d8610 4 0>,
+				<DCC_READ 0x9358610 4 0>,
+				<DCC_READ 0x93d8610 4 0>,
+				<DCC_READ 0x9220344 8 0>,
+				<DCC_READ 0x9220370 6 0>,
+				<DCC_READ 0x9220480 1 0>,
+				<DCC_READ 0x9222400 1 0>,
+				<DCC_READ 0x922240c 1 0>,
+				<DCC_READ 0x9223214 2 0>,
+				<DCC_READ 0x9223220 3 0>,
+				<DCC_READ 0x9223308 1 0>,
+				<DCC_READ 0x9223318 1 0>,
+				<DCC_READ 0x9232100 1 0>,
+				<DCC_READ 0x9236040 6 0>,
+				<DCC_READ 0x92360b0 1 0>,
+				<DCC_READ 0x923e030 2 0>,
+				<DCC_READ 0x9241000 1 0>,
+				<DCC_READ 0x9242028 1 0>,
+				<DCC_READ 0x9242044 3 0>,
+				<DCC_READ 0x9242070 1 0>,
+				<DCC_READ 0x9248030 1 0>,
+				<DCC_READ 0x9248048 8 0>,
+				<DCC_READ 0x92a0344 8 0>,
+				<DCC_READ 0x92a0370 6 0>,
+				<DCC_READ 0x92a0480 1 0>,
+				<DCC_READ 0x92a2400 1 0>,
+				<DCC_READ 0x92a240c 1 0>,
+				<DCC_READ 0x92a3214 2 0>,
+				<DCC_READ 0x92a3220 3 0>,
+				<DCC_READ 0x92a3308 1 0>,
+				<DCC_READ 0x92a3318 1 0>,
+				<DCC_READ 0x92b2100 1 0>,
+				<DCC_READ 0x92b6040 6 0>,
+				<DCC_READ 0x92b60b0 1 0>,
+				<DCC_READ 0x92be030 2 0>,
+				<DCC_READ 0x92c1000 1 0>,
+				<DCC_READ 0x92c2028 1 0>,
+				<DCC_READ 0x92c2044 3 0>,
+				<DCC_READ 0x92c2070 1 0>,
+				<DCC_READ 0x92c8030 1 0>,
+				<DCC_READ 0x92c8048 8 0>,
+				<DCC_READ 0x9320344 8 0>,
+				<DCC_READ 0x9320370 6 0>,
+				<DCC_READ 0x9320480 1 0>,
+				<DCC_READ 0x9322400 1 0>,
+				<DCC_READ 0x932240c 1 0>,
+				<DCC_READ 0x9323214 2 0>,
+				<DCC_READ 0x9323220 3 0>,
+				<DCC_READ 0x9323308 1 0>,
+				<DCC_READ 0x9323318 1 0>,
+				<DCC_READ 0x9332100 1 0>,
+				<DCC_READ 0x9336040 6 0>,
+				<DCC_READ 0x93360b0 1 0>,
+				<DCC_READ 0x933e030 2 0>,
+				<DCC_READ 0x9341000 1 0>,
+				<DCC_READ 0x9342028 1 0>,
+				<DCC_READ 0x9342044 3 0>,
+				<DCC_READ 0x9342070 1 0>,
+				<DCC_READ 0x9348030 1 0>,
+				<DCC_READ 0x9348048 8 0>,
+				<DCC_READ 0x93a0344 8 0>,
+				<DCC_READ 0x93a0370 6 0>,
+				<DCC_READ 0x93a0480 1 0>,
+				<DCC_READ 0x93a2400 1 0>,
+				<DCC_READ 0x93a240c 1 0>,
+				<DCC_READ 0x93a3214 2 0>,
+				<DCC_READ 0x93a3220 3 0>,
+				<DCC_READ 0x93a3308 1 0>,
+				<DCC_READ 0x93a3318 1 0>,
+				<DCC_READ 0x93b2100 1 0>,
+				<DCC_READ 0x93b6040 6 0>,
+				<DCC_READ 0x93b60b0 1 0>,
+				<DCC_READ 0x93be030 2 0>,
+				<DCC_READ 0x93c1000 1 0>,
+				<DCC_READ 0x93c2028 1 0>,
+				<DCC_READ 0x93c2044 3 0>,
+				<DCC_READ 0x93c2070 1 0>,
+				<DCC_READ 0x93c8030 1 0>,
+				<DCC_READ 0x93c8048 8 0>,
+				<DCC_READ 0x9270080 1 0>,
+				<DCC_READ 0x9270400 1 0>,
+				<DCC_READ 0x9270410 6 0>,
+				<DCC_READ 0x9270430 1 0>,
+				<DCC_READ 0x9270440 1 0>,
+				<DCC_READ 0x9270448 1 0>,
+				<DCC_READ 0x92704a0 1 0>,
+				<DCC_READ 0x92704b0 1 0>,
+				<DCC_READ 0x92704b8 2 0>,
+				<DCC_READ 0x92704d0 1 0>,
+				<DCC_READ 0x9271400 1 0>,
+				<DCC_READ 0x92753b0 1 0>,
+				<DCC_READ 0x9275c1c 1 0>,
+				<DCC_READ 0x9275c2c 1 0>,
+				<DCC_READ 0x9275c38 1 0>,
+				<DCC_READ 0x9276418 2 0>,
+				<DCC_READ 0x92f0080 1 0>,
+				<DCC_READ 0x92f0400 1 0>,
+				<DCC_READ 0x92f0410 6 0>,
+				<DCC_READ 0x92f0430 1 0>,
+				<DCC_READ 0x92f0440 1 0>,
+				<DCC_READ 0x92f0448 1 0>,
+				<DCC_READ 0x92f04a0 1 0>,
+				<DCC_READ 0x92f04b0 1 0>,
+				<DCC_READ 0x92f04b8 2 0>,
+				<DCC_READ 0x92f04d0 1 0>,
+				<DCC_READ 0x92f1400 1 0>,
+				<DCC_READ 0x92f53b0 1 0>,
+				<DCC_READ 0x92f5c1c 1 0>,
+				<DCC_READ 0x92f5c2c 1 0>,
+				<DCC_READ 0x92f5c38 1 0>,
+				<DCC_READ 0x92f6418 2 0>,
+				<DCC_READ 0x9370080 1 0>,
+				<DCC_READ 0x9370400 1 0>,
+				<DCC_READ 0x9370410 6 0>,
+				<DCC_READ 0x9370430 1 0>,
+				<DCC_READ 0x9370440 1 0>,
+				<DCC_READ 0x9370448 1 0>,
+				<DCC_READ 0x93704a0 1 0>,
+				<DCC_READ 0x93704b0 1 0>,
+				<DCC_READ 0x93704b8 2 0>,
+				<DCC_READ 0x93704d0 1 0>,
+				<DCC_READ 0x9371400 1 0>,
+				<DCC_READ 0x93753b0 1 0>,
+				<DCC_READ 0x9375c1c 1 0>,
+				<DCC_READ 0x9375c2c 1 0>,
+				<DCC_READ 0x9375c38 1 0>,
+				<DCC_READ 0x9376418 2 0>,
+				<DCC_READ 0x93f0080 1 0>,
+				<DCC_READ 0x93f0400 1 0>,
+				<DCC_READ 0x93f0410 6 0>,
+				<DCC_READ 0x93f0430 1 0>,
+				<DCC_READ 0x93f0440 1 0>,
+				<DCC_READ 0x93f0448 1 0>,
+				<DCC_READ 0x93f04a0 1 0>,
+				<DCC_READ 0x93f04b0 1 0>,
+				<DCC_READ 0x93f04b8 2 0>,
+				<DCC_READ 0x93f04d0 1 0>,
+				<DCC_READ 0x93f1400 1 0>,
+				<DCC_READ 0x93f53b0 1 0>,
+				<DCC_READ 0x93f5c1c 1 0>,
+				<DCC_READ 0x93f5c2c 1 0>,
+				<DCC_READ 0x93f5c38 1 0>,
+				<DCC_READ 0x93f6418 2 0>,
+				<DCC_READ 0x9260080 1 0>,
+				<DCC_READ 0x9260400 1 0>,
+				<DCC_READ 0x9260410 3 0>,
+				<DCC_READ 0x9260420 2 0>,
+				<DCC_READ 0x9260430 1 0>,
+				<DCC_READ 0x9260440 1 0>,
+				<DCC_READ 0x9260448 1 0>,
+				<DCC_READ 0x92604a0 1 0>,
+				<DCC_READ 0x92604b0 1 0>,
+				<DCC_READ 0x92604b8 2 0>,
+				<DCC_READ 0x92604d0 2 0>,
+				<DCC_READ 0x9261400 1 0>,
+				<DCC_READ 0x9263410 1 0>,
+				<DCC_READ 0x92653b0 1 0>,
+				<DCC_READ 0x9265804 1 0>,
+				<DCC_READ 0x9265b1c 1 0>,
+				<DCC_READ 0x9265b2c 1 0>,
+				<DCC_READ 0x9265b38 1 0>,
+				<DCC_READ 0x9269100 1 0>,
+				<DCC_READ 0x9269110 1 0>,
+				<DCC_READ 0x9269120 1 0>,
+				<DCC_READ 0x92e0080 1 0>,
+				<DCC_READ 0x92e0400 1 0>,
+				<DCC_READ 0x92e0410 3 0>,
+				<DCC_READ 0x92e0420 2 0>,
+				<DCC_READ 0x92e0430 1 0>,
+				<DCC_READ 0x92e0440 1 0>,
+				<DCC_READ 0x92e0448 1 0>,
+				<DCC_READ 0x92e04a0 1 0>,
+				<DCC_READ 0x92e04b0 1 0>,
+				<DCC_READ 0x92e04b8 2 0>,
+				<DCC_READ 0x92e04d0 2 0>,
+				<DCC_READ 0x92e1400 1 0>,
+				<DCC_READ 0x92e3410 1 0>,
+				<DCC_READ 0x92e53b0 1 0>,
+				<DCC_READ 0x92e5804 1 0>,
+				<DCC_READ 0x92e5b1c 1 0>,
+				<DCC_READ 0x92e5b2c 1 0>,
+				<DCC_READ 0x92e5b38 1 0>,
+				<DCC_READ 0x92e9100 1 0>,
+				<DCC_READ 0x92e9110 1 0>,
+				<DCC_READ 0x92e9120 1 0>,
+				<DCC_READ 0x9360080 1 0>,
+				<DCC_READ 0x9360400 1 0>,
+				<DCC_READ 0x9360410 3 0>,
+				<DCC_READ 0x9360420 2 0>,
+				<DCC_READ 0x9360430 1 0>,
+				<DCC_READ 0x9360440 1 0>,
+				<DCC_READ 0x9360448 1 0>,
+				<DCC_READ 0x93604a0 1 0>,
+				<DCC_READ 0x93604b0 1 0>,
+				<DCC_READ 0x93604b8 2 0>,
+				<DCC_READ 0x93604d0 2 0>,
+				<DCC_READ 0x9361400 1 0>,
+				<DCC_READ 0x9363410 1 0>,
+				<DCC_READ 0x93653b0 1 0>,
+				<DCC_READ 0x9365804 1 0>,
+				<DCC_READ 0x9365b1c 1 0>,
+				<DCC_READ 0x9365b2c 1 0>,
+				<DCC_READ 0x9365b38 1 0>,
+				<DCC_READ 0x9369100 1 0>,
+				<DCC_READ 0x9369110 1 0>,
+				<DCC_READ 0x9369120 1 0>,
+				<DCC_READ 0x93e0080 1 0>,
+				<DCC_READ 0x93e0400 1 0>,
+				<DCC_READ 0x93e0410 3 0>,
+				<DCC_READ 0x93e0420 2 0>,
+				<DCC_READ 0x93e0430 1 0>,
+				<DCC_READ 0x93e0440 1 0>,
+				<DCC_READ 0x93e0448 1 0>,
+				<DCC_READ 0x93e04a0 1 0>,
+				<DCC_READ 0x93e04b0 1 0>,
+				<DCC_READ 0x93e04b8 2 0>,
+				<DCC_READ 0x93e04d0 2 0>,
+				<DCC_READ 0x93e1400 1 0>,
+				<DCC_READ 0x93e3410 1 0>,
+				<DCC_READ 0x93e53b0 1 0>,
+				<DCC_READ 0x93e5804 1 0>,
+				<DCC_READ 0x93e5b1c 1 0>,
+				<DCC_READ 0x93e5b2c 1 0>,
+				<DCC_READ 0x93e5b38 1 0>,
+				<DCC_READ 0x93e9100 1 0>,
+				<DCC_READ 0x93e9110 1 0>,
+				<DCC_READ 0x93e9120 1 0>,
+				<DCC_READ 0x96b0868 1 0>,
+				<DCC_READ 0x96b0870 1 0>,
+				<DCC_READ 0x96b1004 1 0>,
+				<DCC_READ 0x96b100c 1 0>,
+				<DCC_READ 0x96b1014 1 0>,
+				<DCC_READ 0x96b1204 1 0>,
+				<DCC_READ 0x96b120c 1 0>,
+				<DCC_READ 0x96b1214 1 0>,
+				<DCC_READ 0x96b1504 1 0>,
+				<DCC_READ 0x96b150c 1 0>,
+				<DCC_READ 0x96b1514 1 0>,
+				<DCC_READ 0x96b1604 1 0>,
+				<DCC_READ 0x96b8100 1 0>,
+				<DCC_READ 0x96b813c 1 0>,
+				<DCC_READ 0x96b8500 1 0>,
+				<DCC_READ 0x96b853c 1 0>,
+				<DCC_READ 0x96b8a04 1 0>,
+				<DCC_READ 0x96b8a18 1 0>,
+				<DCC_READ 0x96b8ea8 1 0>,
+				<DCC_READ 0x96b9044 1 0>,
+				<DCC_READ 0x96b904c 1 0>,
+				<DCC_READ 0x96b9054 1 0>,
+				<DCC_READ 0x96b905c 1 0>,
+				<DCC_READ 0x96b910c 2 0>,
+				<DCC_READ 0x96b9204 1 0>,
+				<DCC_READ 0x96b920c 1 0>,
+				<DCC_READ 0x96b9238 1 0>,
+				<DCC_READ 0x96b9240 1 0>,
+				<DCC_READ 0x96b926c 1 0>,
+				<DCC_READ 0x96b9394 1 0>,
+				<DCC_READ 0x96b939c 1 0>,
+				<DCC_READ 0x96b9704 1 0>,
+				<DCC_READ 0x96b970c 1 0>,
+				<DCC_READ 0x96f0868 1 0>,
+				<DCC_READ 0x96f0870 1 0>,
+				<DCC_READ 0x96f1004 1 0>,
+				<DCC_READ 0x96f100c 1 0>,
+				<DCC_READ 0x96f1014 1 0>,
+				<DCC_READ 0x96f1204 1 0>,
+				<DCC_READ 0x96f120c 1 0>,
+				<DCC_READ 0x96f1214 1 0>,
+				<DCC_READ 0x96f1504 1 0>,
+				<DCC_READ 0x96f150c 1 0>,
+				<DCC_READ 0x96f1514 1 0>,
+				<DCC_READ 0x96f1604 1 0>,
+				<DCC_READ 0x96f8100 1 0>,
+				<DCC_READ 0x96f813c 1 0>,
+				<DCC_READ 0x96f8500 1 0>,
+				<DCC_READ 0x96f853c 1 0>,
+				<DCC_READ 0x96f8a04 1 0>,
+				<DCC_READ 0x96f8a18 1 0>,
+				<DCC_READ 0x96f8ea8 1 0>,
+				<DCC_READ 0x96f9044 1 0>,
+				<DCC_READ 0x96f904c 1 0>,
+				<DCC_READ 0x96f9054 1 0>,
+				<DCC_READ 0x96f905c 1 0>,
+				<DCC_READ 0x96f910c 2 0>,
+				<DCC_READ 0x96f9204 1 0>,
+				<DCC_READ 0x96f920c 1 0>,
+				<DCC_READ 0x96f9238 1 0>,
+				<DCC_READ 0x96f9240 1 0>,
+				<DCC_READ 0x96f926c 1 0>,
+				<DCC_READ 0x96f9394 1 0>,
+				<DCC_READ 0x96f939c 1 0>,
+				<DCC_READ 0x96f9704 1 0>,
+				<DCC_READ 0x96f970c 1 0>,
+				<DCC_READ 0x9730868 1 0>,
+				<DCC_READ 0x9730870 1 0>,
+				<DCC_READ 0x9731004 1 0>,
+				<DCC_READ 0x973100c 1 0>,
+				<DCC_READ 0x9731014 1 0>,
+				<DCC_READ 0x9731204 1 0>,
+				<DCC_READ 0x973120c 1 0>,
+				<DCC_READ 0x9731214 1 0>,
+				<DCC_READ 0x9731504 1 0>,
+				<DCC_READ 0x973150c 1 0>,
+				<DCC_READ 0x9731514 1 0>,
+				<DCC_READ 0x9731604 1 0>,
+				<DCC_READ 0x9738100 1 0>,
+				<DCC_READ 0x973813c 1 0>,
+				<DCC_READ 0x9738500 1 0>,
+				<DCC_READ 0x973853c 1 0>,
+				<DCC_READ 0x9738a04 1 0>,
+				<DCC_READ 0x9738a18 1 0>,
+				<DCC_READ 0x9738ea8 1 0>,
+				<DCC_READ 0x9739044 1 0>,
+				<DCC_READ 0x973904c 1 0>,
+				<DCC_READ 0x9739054 1 0>,
+				<DCC_READ 0x973905c 1 0>,
+				<DCC_READ 0x973910c 2 0>,
+				<DCC_READ 0x9739204 1 0>,
+				<DCC_READ 0x973920c 1 0>,
+				<DCC_READ 0x9739238 1 0>,
+				<DCC_READ 0x9739240 1 0>,
+				<DCC_READ 0x973926c 1 0>,
+				<DCC_READ 0x9739394 1 0>,
+				<DCC_READ 0x973939c 1 0>,
+				<DCC_READ 0x9739704 1 0>,
+				<DCC_READ 0x973970c 1 0>,
+				<DCC_READ 0x9770868 1 0>,
+				<DCC_READ 0x9770870 1 0>,
+				<DCC_READ 0x9771004 1 0>,
+				<DCC_READ 0x977100c 1 0>,
+				<DCC_READ 0x9771014 1 0>,
+				<DCC_READ 0x9771204 1 0>,
+				<DCC_READ 0x977120c 1 0>,
+				<DCC_READ 0x9771214 1 0>,
+				<DCC_READ 0x9771504 1 0>,
+				<DCC_READ 0x977150c 1 0>,
+				<DCC_READ 0x9771514 1 0>,
+				<DCC_READ 0x9771604 1 0>,
+				<DCC_READ 0x9778100 1 0>,
+				<DCC_READ 0x977813c 1 0>,
+				<DCC_READ 0x9778500 1 0>,
+				<DCC_READ 0x977853c 1 0>,
+				<DCC_READ 0x9778a04 1 0>,
+				<DCC_READ 0x9778a18 1 0>,
+				<DCC_READ 0x9778ea8 1 0>,
+				<DCC_READ 0x9779044 1 0>,
+				<DCC_READ 0x977904c 1 0>,
+				<DCC_READ 0x9779054 1 0>,
+				<DCC_READ 0x977905c 1 0>,
+				<DCC_READ 0x977910c 2 0>,
+				<DCC_READ 0x9779204 1 0>,
+				<DCC_READ 0x977920c 1 0>,
+				<DCC_READ 0x9779238 1 0>,
+				<DCC_READ 0x9779240 1 0>,
+				<DCC_READ 0x977926c 1 0>,
+				<DCC_READ 0x9779394 1 0>,
+				<DCC_READ 0x977939c 1 0>,
+				<DCC_READ 0x9779704 1 0>,
+				<DCC_READ 0x977970c 1 0>,
+				<DCC_READ 0x910d100 3 0>,
+				<DCC_READ 0x914d100 3 0>,
+				<DCC_READ 0x918d100 4 0>,
+				<DCC_READ 0x91a5100 1 0>,
+				<DCC_READ 0x91ad100 1 0>;
+		};
+
+		link_list3 {
+			qcom,curr-link-list = <7>;
+			qcom,data-sink = "sram";
+			qcom,link-list = <DCC_READ 0x9050078 1 0>,
+				<DCC_READ 0x9050110 8 0>,
+				<DCC_READ 0x9080058 2 0>,
+				<DCC_READ 0x90800c8 1 0>,
+				<DCC_READ 0x90800d4 1 0>,
+				<DCC_READ 0x90800e0 1 0>,
+				<DCC_READ 0x90800ec 1 0>,
+				<DCC_READ 0x90800f8 1 0>,
+				<DCC_READ 0x908401c 1 0>,
+				<DCC_READ 0x908403c 1 0>,
+				<DCC_READ 0x908404c 2 0>,
+				<DCC_READ 0x90840d4 1 0>,
+				<DCC_READ 0x9084204 1 0>,
+				<DCC_READ 0x908420c 1 0>,
+				<DCC_READ 0x9084250 2 0>,
+				<DCC_READ 0x9084260 3 0>,
+				<DCC_READ 0x9084280 1 0>,
+				<DCC_READ 0x90ba280 1 0>,
+				<DCC_READ 0x90ba288 7 0>,
+				<DCC_READ 0x9258610 4 0>,
+				<DCC_READ 0x92d8610 4 0>,
+				<DCC_READ 0x9358610 4 0>,
+				<DCC_READ 0x93d8610 4 0>,
+				<DCC_READ 0x9220344 8 0>,
+				<DCC_READ 0x9220370 6 0>,
+				<DCC_READ 0x9220480 1 0>,
+				<DCC_READ 0x9222400 1 0>,
+				<DCC_READ 0x922240c 1 0>,
+				<DCC_READ 0x9223214 2 0>,
+				<DCC_READ 0x9223220 3 0>,
+				<DCC_READ 0x9223308 1 0>,
+				<DCC_READ 0x9223318 1 0>,
+				<DCC_READ 0x9232100 1 0>,
+				<DCC_READ 0x9236040 6 0>,
+				<DCC_READ 0x92360b0 1 0>,
+				<DCC_READ 0x923e030 2 0>,
+				<DCC_READ 0x9241000 1 0>,
+				<DCC_READ 0x9242028 1 0>,
+				<DCC_READ 0x9242044 3 0>,
+				<DCC_READ 0x9242070 1 0>,
+				<DCC_READ 0x9248030 1 0>,
+				<DCC_READ 0x9248048 8 0>,
+				<DCC_READ 0x92a0344 8 0>,
+				<DCC_READ 0x92a0370 6 0>,
+				<DCC_READ 0x92a0480 1 0>,
+				<DCC_READ 0x92a2400 1 0>,
+				<DCC_READ 0x92a240c 1 0>,
+				<DCC_READ 0x92a3214 2 0>,
+				<DCC_READ 0x92a3220 3 0>,
+				<DCC_READ 0x92a3308 1 0>,
+				<DCC_READ 0x92a3318 1 0>,
+				<DCC_READ 0x92b2100 1 0>,
+				<DCC_READ 0x92b6040 6 0>,
+				<DCC_READ 0x92b60b0 1 0>,
+				<DCC_READ 0x92be030 2 0>,
+				<DCC_READ 0x92c1000 1 0>,
+				<DCC_READ 0x92c2028 1 0>,
+				<DCC_READ 0x92c2044 3 0>,
+				<DCC_READ 0x92c2070 1 0>,
+				<DCC_READ 0x92c8030 1 0>,
+				<DCC_READ 0x92c8048 8 0>,
+				<DCC_READ 0x9320344 8 0>,
+				<DCC_READ 0x9320370 6 0>,
+				<DCC_READ 0x9320480 1 0>,
+				<DCC_READ 0x9322400 1 0>,
+				<DCC_READ 0x932240c 1 0>,
+				<DCC_READ 0x9323214 2 0>,
+				<DCC_READ 0x9323220 3 0>,
+				<DCC_READ 0x9323308 1 0>,
+				<DCC_READ 0x9323318 1 0>,
+				<DCC_READ 0x9332100 1 0>,
+				<DCC_READ 0x9336040 6 0>,
+				<DCC_READ 0x93360b0 1 0>,
+				<DCC_READ 0x933e030 2 0>,
+				<DCC_READ 0x9341000 1 0>,
+				<DCC_READ 0x9342028 1 0>,
+				<DCC_READ 0x9342044 3 0>,
+				<DCC_READ 0x9342070 1 0>,
+				<DCC_READ 0x9348030 1 0>,
+				<DCC_READ 0x9348048 8 0>,
+				<DCC_READ 0x93a0344 8 0>,
+				<DCC_READ 0x93a0370 6 0>,
+				<DCC_READ 0x93a0480 1 0>,
+				<DCC_READ 0x93a2400 1 0>,
+				<DCC_READ 0x93a240c 1 0>,
+				<DCC_READ 0x93a3214 2 0>,
+				<DCC_READ 0x93a3220 3 0>,
+				<DCC_READ 0x93a3308 1 0>,
+				<DCC_READ 0x93a3318 1 0>,
+				<DCC_READ 0x93b2100 1 0>,
+				<DCC_READ 0x93b6040 6 0>,
+				<DCC_READ 0x93b60b0 1 0>,
+				<DCC_READ 0x93be030 2 0>,
+				<DCC_READ 0x93c1000 1 0>,
+				<DCC_READ 0x93c2028 1 0>,
+				<DCC_READ 0x93c2044 3 0>,
+				<DCC_READ 0x93c2070 1 0>,
+				<DCC_READ 0x93c8030 1 0>,
+				<DCC_READ 0x93c8048 8 0>,
+				<DCC_READ 0x9270080 1 0>,
+				<DCC_READ 0x9270400 1 0>,
+				<DCC_READ 0x9270410 6 0>,
+				<DCC_READ 0x9270430 1 0>,
+				<DCC_READ 0x9270440 1 0>,
+				<DCC_READ 0x9270448 1 0>,
+				<DCC_READ 0x92704a0 1 0>,
+				<DCC_READ 0x92704b0 1 0>,
+				<DCC_READ 0x92704b8 2 0>,
+				<DCC_READ 0x92704d0 1 0>,
+				<DCC_READ 0x9271400 1 0>,
+				<DCC_READ 0x92753b0 1 0>,
+				<DCC_READ 0x9275c1c 1 0>,
+				<DCC_READ 0x9275c2c 1 0>,
+				<DCC_READ 0x9275c38 1 0>,
+				<DCC_READ 0x9276418 2 0>,
+				<DCC_READ 0x92f0080 1 0>,
+				<DCC_READ 0x92f0400 1 0>,
+				<DCC_READ 0x92f0410 6 0>,
+				<DCC_READ 0x92f0430 1 0>,
+				<DCC_READ 0x92f0440 1 0>,
+				<DCC_READ 0x92f0448 1 0>,
+				<DCC_READ 0x92f04a0 1 0>,
+				<DCC_READ 0x92f04b0 1 0>,
+				<DCC_READ 0x92f04b8 2 0>,
+				<DCC_READ 0x92f04d0 1 0>,
+				<DCC_READ 0x92f1400 1 0>,
+				<DCC_READ 0x92f53b0 1 0>,
+				<DCC_READ 0x92f5c1c 1 0>,
+				<DCC_READ 0x92f5c2c 1 0>,
+				<DCC_READ 0x92f5c38 1 0>,
+				<DCC_READ 0x92f6418 2 0>,
+				<DCC_READ 0x9370080 1 0>,
+				<DCC_READ 0x9370400 1 0>,
+				<DCC_READ 0x9370410 6 0>,
+				<DCC_READ 0x9370430 1 0>,
+				<DCC_READ 0x9370440 1 0>,
+				<DCC_READ 0x9370448 1 0>,
+				<DCC_READ 0x93704a0 1 0>,
+				<DCC_READ 0x93704b0 1 0>,
+				<DCC_READ 0x93704b8 2 0>,
+				<DCC_READ 0x93704d0 1 0>,
+				<DCC_READ 0x9371400 1 0>,
+				<DCC_READ 0x93753b0 1 0>,
+				<DCC_READ 0x9375c1c 1 0>,
+				<DCC_READ 0x9375c2c 1 0>,
+				<DCC_READ 0x9375c38 1 0>,
+				<DCC_READ 0x9376418 2 0>,
+				<DCC_READ 0x93f0080 1 0>,
+				<DCC_READ 0x93f0400 1 0>,
+				<DCC_READ 0x93f0410 6 0>,
+				<DCC_READ 0x93f0430 1 0>,
+				<DCC_READ 0x93f0440 1 0>,
+				<DCC_READ 0x93f0448 1 0>,
+				<DCC_READ 0x93f04a0 1 0>,
+				<DCC_READ 0x93f04b0 1 0>,
+				<DCC_READ 0x93f04b8 2 0>,
+				<DCC_READ 0x93f04d0 1 0>,
+				<DCC_READ 0x93f1400 1 0>,
+				<DCC_READ 0x93f53b0 1 0>,
+				<DCC_READ 0x93f5c1c 1 0>,
+				<DCC_READ 0x93f5c2c 1 0>,
+				<DCC_READ 0x93f5c38 1 0>,
+				<DCC_READ 0x93f6418 2 0>,
+				<DCC_READ 0x9260080 1 0>,
+				<DCC_READ 0x9260400 1 0>,
+				<DCC_READ 0x9260410 3 0>,
+				<DCC_READ 0x9260420 2 0>,
+				<DCC_READ 0x9260430 1 0>,
+				<DCC_READ 0x9260440 1 0>,
+				<DCC_READ 0x9260448 1 0>,
+				<DCC_READ 0x92604a0 1 0>,
+				<DCC_READ 0x92604b0 1 0>,
+				<DCC_READ 0x92604b8 2 0>,
+				<DCC_READ 0x92604d0 2 0>,
+				<DCC_READ 0x9261400 1 0>,
+				<DCC_READ 0x9263410 1 0>,
+				<DCC_READ 0x92653b0 1 0>,
+				<DCC_READ 0x9265804 1 0>,
+				<DCC_READ 0x9265b1c 1 0>,
+				<DCC_READ 0x9265b2c 1 0>,
+				<DCC_READ 0x9265b38 1 0>,
+				<DCC_READ 0x9269100 1 0>,
+				<DCC_READ 0x9269110 1 0>,
+				<DCC_READ 0x9269120 1 0>,
+				<DCC_READ 0x92e0080 1 0>,
+				<DCC_READ 0x92e0400 1 0>,
+				<DCC_READ 0x92e0410 3 0>,
+				<DCC_READ 0x92e0420 2 0>,
+				<DCC_READ 0x92e0430 1 0>,
+				<DCC_READ 0x92e0440 1 0>,
+				<DCC_READ 0x92e0448 1 0>,
+				<DCC_READ 0x92e04a0 1 0>,
+				<DCC_READ 0x92e04b0 1 0>,
+				<DCC_READ 0x92e04b8 2 0>,
+				<DCC_READ 0x92e04d0 2 0>,
+				<DCC_READ 0x92e1400 1 0>,
+				<DCC_READ 0x92e3410 1 0>,
+				<DCC_READ 0x92e53b0 1 0>,
+				<DCC_READ 0x92e5804 1 0>,
+				<DCC_READ 0x92e5b1c 1 0>,
+				<DCC_READ 0x92e5b2c 1 0>,
+				<DCC_READ 0x92e5b38 1 0>,
+				<DCC_READ 0x92e9100 1 0>,
+				<DCC_READ 0x92e9110 1 0>,
+				<DCC_READ 0x92e9120 1 0>,
+				<DCC_READ 0x9360080 1 0>,
+				<DCC_READ 0x9360400 1 0>,
+				<DCC_READ 0x9360410 3 0>,
+				<DCC_READ 0x9360420 2 0>,
+				<DCC_READ 0x9360430 1 0>,
+				<DCC_READ 0x9360440 1 0>,
+				<DCC_READ 0x9360448 1 0>,
+				<DCC_READ 0x93604a0 1 0>,
+				<DCC_READ 0x93604b0 1 0>,
+				<DCC_READ 0x93604b8 2 0>,
+				<DCC_READ 0x93604d0 2 0>,
+				<DCC_READ 0x9361400 1 0>,
+				<DCC_READ 0x9363410 1 0>,
+				<DCC_READ 0x93653b0 1 0>,
+				<DCC_READ 0x9365804 1 0>,
+				<DCC_READ 0x9365b1c 1 0>,
+				<DCC_READ 0x9365b2c 1 0>,
+				<DCC_READ 0x9365b38 1 0>,
+				<DCC_READ 0x9369100 1 0>,
+				<DCC_READ 0x9369110 1 0>,
+				<DCC_READ 0x9369120 1 0>,
+				<DCC_READ 0x93e0080 1 0>,
+				<DCC_READ 0x93e0400 1 0>,
+				<DCC_READ 0x93e0410 3 0>,
+				<DCC_READ 0x93e0420 2 0>,
+				<DCC_READ 0x93e0430 1 0>,
+				<DCC_READ 0x93e0440 1 0>,
+				<DCC_READ 0x93e0448 1 0>,
+				<DCC_READ 0x93e04a0 1 0>,
+				<DCC_READ 0x93e04b0 1 0>,
+				<DCC_READ 0x93e04b8 2 0>,
+				<DCC_READ 0x93e04d0 2 0>,
+				<DCC_READ 0x93e1400 1 0>,
+				<DCC_READ 0x93e3410 1 0>,
+				<DCC_READ 0x93e53b0 1 0>,
+				<DCC_READ 0x93e5804 1 0>,
+				<DCC_READ 0x93e5b1c 1 0>,
+				<DCC_READ 0x93e5b2c 1 0>,
+				<DCC_READ 0x93e5b38 1 0>,
+				<DCC_READ 0x93e9100 1 0>,
+				<DCC_READ 0x93e9110 1 0>,
+				<DCC_READ 0x93e9120 1 0>,
+				<DCC_READ 0x96b0868 1 0>,
+				<DCC_READ 0x96b0870 1 0>,
+				<DCC_READ 0x96b1004 1 0>,
+				<DCC_READ 0x96b100c 1 0>,
+				<DCC_READ 0x96b1014 1 0>,
+				<DCC_READ 0x96b1204 1 0>,
+				<DCC_READ 0x96b120c 1 0>,
+				<DCC_READ 0x96b1214 1 0>,
+				<DCC_READ 0x96b1504 1 0>,
+				<DCC_READ 0x96b150c 1 0>,
+				<DCC_READ 0x96b1514 1 0>,
+				<DCC_READ 0x96b1604 1 0>,
+				<DCC_READ 0x96b8100 1 0>,
+				<DCC_READ 0x96b813c 1 0>,
+				<DCC_READ 0x96b8500 1 0>,
+				<DCC_READ 0x96b853c 1 0>,
+				<DCC_READ 0x96b8a04 1 0>,
+				<DCC_READ 0x96b8a18 1 0>,
+				<DCC_READ 0x96b8ea8 1 0>,
+				<DCC_READ 0x96b9044 1 0>,
+				<DCC_READ 0x96b904c 1 0>,
+				<DCC_READ 0x96b9054 1 0>,
+				<DCC_READ 0x96b905c 1 0>,
+				<DCC_READ 0x96b910c 2 0>,
+				<DCC_READ 0x96b9204 1 0>,
+				<DCC_READ 0x96b920c 1 0>,
+				<DCC_READ 0x96b9238 1 0>,
+				<DCC_READ 0x96b9240 1 0>,
+				<DCC_READ 0x96b926c 1 0>,
+				<DCC_READ 0x96b9394 1 0>,
+				<DCC_READ 0x96b939c 1 0>,
+				<DCC_READ 0x96b9704 1 0>,
+				<DCC_READ 0x96b970c 1 0>,
+				<DCC_READ 0x96f0868 1 0>,
+				<DCC_READ 0x96f0870 1 0>,
+				<DCC_READ 0x96f1004 1 0>,
+				<DCC_READ 0x96f100c 1 0>,
+				<DCC_READ 0x96f1014 1 0>,
+				<DCC_READ 0x96f1204 1 0>,
+				<DCC_READ 0x96f120c 1 0>,
+				<DCC_READ 0x96f1214 1 0>,
+				<DCC_READ 0x96f1504 1 0>,
+				<DCC_READ 0x96f150c 1 0>,
+				<DCC_READ 0x96f1514 1 0>,
+				<DCC_READ 0x96f1604 1 0>,
+				<DCC_READ 0x96f8100 1 0>,
+				<DCC_READ 0x96f813c 1 0>,
+				<DCC_READ 0x96f8500 1 0>,
+				<DCC_READ 0x96f853c 1 0>,
+				<DCC_READ 0x96f8a04 1 0>,
+				<DCC_READ 0x96f8a18 1 0>,
+				<DCC_READ 0x96f8ea8 1 0>,
+				<DCC_READ 0x96f9044 1 0>,
+				<DCC_READ 0x96f904c 1 0>,
+				<DCC_READ 0x96f9054 1 0>,
+				<DCC_READ 0x96f905c 1 0>,
+				<DCC_READ 0x96f910c 2 0>,
+				<DCC_READ 0x96f9204 1 0>,
+				<DCC_READ 0x96f920c 1 0>,
+				<DCC_READ 0x96f9238 1 0>,
+				<DCC_READ 0x96f9240 1 0>,
+				<DCC_READ 0x96f926c 1 0>,
+				<DCC_READ 0x96f9394 1 0>,
+				<DCC_READ 0x96f939c 1 0>,
+				<DCC_READ 0x96f9704 1 0>,
+				<DCC_READ 0x96f970c 1 0>,
+				<DCC_READ 0x9730868 1 0>,
+				<DCC_READ 0x9730870 1 0>,
+				<DCC_READ 0x9731004 1 0>,
+				<DCC_READ 0x973100c 1 0>,
+				<DCC_READ 0x9731014 1 0>,
+				<DCC_READ 0x9731204 1 0>,
+				<DCC_READ 0x973120c 1 0>,
+				<DCC_READ 0x9731214 1 0>,
+				<DCC_READ 0x9731504 1 0>,
+				<DCC_READ 0x973150c 1 0>,
+				<DCC_READ 0x9731514 1 0>,
+				<DCC_READ 0x9731604 1 0>,
+				<DCC_READ 0x9738100 1 0>,
+				<DCC_READ 0x973813c 1 0>,
+				<DCC_READ 0x9738500 1 0>,
+				<DCC_READ 0x973853c 1 0>,
+				<DCC_READ 0x9738a04 1 0>,
+				<DCC_READ 0x9738a18 1 0>,
+				<DCC_READ 0x9738ea8 1 0>,
+				<DCC_READ 0x9739044 1 0>,
+				<DCC_READ 0x973904c 1 0>,
+				<DCC_READ 0x9739054 1 0>,
+				<DCC_READ 0x973905c 1 0>,
+				<DCC_READ 0x973910c 2 0>,
+				<DCC_READ 0x9739204 1 0>,
+				<DCC_READ 0x973920c 1 0>,
+				<DCC_READ 0x9739238 1 0>,
+				<DCC_READ 0x9739240 1 0>,
+				<DCC_READ 0x973926c 1 0>,
+				<DCC_READ 0x9739394 1 0>,
+				<DCC_READ 0x973939c 1 0>,
+				<DCC_READ 0x9739704 1 0>,
+				<DCC_READ 0x973970c 1 0>,
+				<DCC_READ 0x9770868 1 0>,
+				<DCC_READ 0x9770870 1 0>,
+				<DCC_READ 0x9771004 1 0>,
+				<DCC_READ 0x977100c 1 0>,
+				<DCC_READ 0x9771014 1 0>,
+				<DCC_READ 0x9771204 1 0>,
+				<DCC_READ 0x977120c 1 0>,
+				<DCC_READ 0x9771214 1 0>,
+				<DCC_READ 0x9771504 1 0>,
+				<DCC_READ 0x977150c 1 0>,
+				<DCC_READ 0x9771514 1 0>,
+				<DCC_READ 0x9771604 1 0>,
+				<DCC_READ 0x9778100 1 0>,
+				<DCC_READ 0x977813c 1 0>,
+				<DCC_READ 0x9778500 1 0>,
+				<DCC_READ 0x977853c 1 0>,
+				<DCC_READ 0x9778a04 1 0>,
+				<DCC_READ 0x9778a18 1 0>,
+				<DCC_READ 0x9778ea8 1 0>,
+				<DCC_READ 0x9779044 1 0>,
+				<DCC_READ 0x977904c 1 0>,
+				<DCC_READ 0x9779054 1 0>,
+				<DCC_READ 0x977905c 1 0>,
+				<DCC_READ 0x977910c 2 0>,
+				<DCC_READ 0x9779204 1 0>,
+				<DCC_READ 0x977920c 1 0>,
+				<DCC_READ 0x9779238 1 0>,
+				<DCC_READ 0x9779240 1 0>,
+				<DCC_READ 0x977926c 1 0>,
+				<DCC_READ 0x9779394 1 0>,
+				<DCC_READ 0x977939c 1 0>,
+				<DCC_READ 0x9779704 1 0>,
+				<DCC_READ 0x977970c 1 0>,
+				<DCC_READ 0x910d100 3 0>,
+				<DCC_READ 0x914d100 3 0>,
+				<DCC_READ 0x918d100 4 0>,
+				<DCC_READ 0x91a5100 1 0>,
+				<DCC_READ 0x91ad100 1 0>;
+		};
+
+	};
+
+	qfprom: qfprom@780000 {
+		compatible = "qcom,qfprom";
+		reg = <0x00784000 0x3000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		read-only;
+		ranges;
+
+		gpu_lm_efuse: gpu_lm_efuse@5c8 {
+			reg = <0x5c8 0x4>;
+		};
+
+		gpu_speed_bin: gpu_speed_bin@19b {
+			reg = <0x19b 0x1>;
+			bits = <5 3>;
+		};
+	};
+
+	kryo-erp {
+		compatible = "arm,arm64-kryo-cpu-erp";
+		interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "l1-l2-faultirq",
+				  "l3-scu-faultirq";
+	};
+
+	msm_gpu: qcom,kgsl-3d0@3d00000 { };
 };
 
 #include "kona-usb.dtsi"
@@ -2257,3 +4066,7 @@
 #include "kona-dma-heaps.dtsi"
 #include "kona-qupv3.dtsi"
 #include "kona-pcie.dtsi"
+#include "kona-smp2p.dtsi"
+#include "msm-rdbg.dtsi"
+#include "kona-thermal.dtsi"
+#include "kona-coresight.dtsi"
diff --git a/qcom/lemans-4pmic-regulators.dtsi b/qcom/lemans-4pmic-regulators.dtsi
index 520d5624..a01279b2 100755
--- a/qcom/lemans-4pmic-regulators.dtsi
+++ b/qcom/lemans-4pmic-regulators.dtsi
@@ -408,7 +408,7 @@
 		pm8775_a_l8: regulator-pm8775_a-l8 {
 			regulator-name = "pm8775_a_l8";
 			qcom,set = <RPMH_REGULATOR_SET_ALL>;
-			regulator-min-microvolt = <2400000>;
+			regulator-min-microvolt = <2504000>;
 			regulator-max-microvolt = <3300000>;
 			qcom,init-mode =
 				<RPMH_REGULATOR_MODE_HPM>;
diff --git a/qcom/lemans-adas-high.dtsi b/qcom/lemans-adas-high.dtsi
index 6f9db8b2..dfb6d5fe 100755
--- a/qcom/lemans-adas-high.dtsi
+++ b/qcom/lemans-adas-high.dtsi
@@ -1,4 +1,5 @@
 #include "lemans.dtsi"
+#include "lemans-adp-common.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. LeMans ADAS HIGH SoC";
diff --git a/qcom/lemans-adp-common.dtsi b/qcom/lemans-adp-common.dtsi
index 12115d7c..fd32927e 100755
--- a/qcom/lemans-adp-common.dtsi
+++ b/qcom/lemans-adp-common.dtsi
@@ -1,5 +1,6 @@
 #include "lemans-pmic-overlay.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include "lemans-thermal-overlay.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. Lemans ADP";
@@ -7,6 +8,84 @@
 	qcom,board-id = <25 0>;
 };
 
+&thermal_zones {
+	xo-therm {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm8775_1_adc PM8775_1_ADC5_GEN3_AMUX1_THM_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	ufs0_therm {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm8775_1_adc PM8775_1_ADC5_GEN3_AMUX5_THM_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	soc_therm {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm8775_1_adc PM8775_1_ADC5_GEN3_AMUX6_THM_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdram_therm1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm8775_3_adc PM8775_3_ADC5_GEN3_AMUX6_THM_100K_PU>;
+		trips {
+			active-config0 {
+			temperature = <125000>;
+			hysteresis = <1000>;
+			type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+};
+
 &soc {
 	/* PWR_CTR1_VDD_PA supply */
 	vreg_conn_pa: vreg_conn_pa {
@@ -17,6 +96,15 @@
 		gpio = <&pm8775_2_gpios 6 0>;
 	};
 
+	/* PWR_CTR2_VDD_1P8 supply */
+	vreg_conn_1p8: vreg_conn_1p8 {
+		compatible = "regulator-fixed";
+		regulator-name = "vreg_conn_1p8";
+		startup-delay-us = <4000>;
+		enable-active-high;
+		gpio = <&pm8775_2_gpios 4 0>;
+	};
+
 };
 
 &pm8775_1_adc {
@@ -25,6 +113,7 @@
 		label = "pm8775_1_xo_therm";
 		qcom,ratiometric;
 		qcom,hw-settle-time = <700>;
+		qcom,adc-tm-type = <1>;
 		qcom,pre-scaling = <1 1>;
 	};
 
diff --git a/qcom/lemans-gdsc.dtsi b/qcom/lemans-gdsc.dtsi
index 33c5bab9..b4e77429 100755
--- a/qcom/lemans-gdsc.dtsi
+++ b/qcom/lemans-gdsc.dtsi
@@ -107,6 +107,7 @@
 		compatible = "qcom,gdsc";
 		reg = <0x181004 0x4>;
 		regulator-name = "gcc_ufs_card_gdsc";
+		qcom,gds-timeout = <1500>;
 		qcom,retain-regs;
 		status = "disabled";
 	};
diff --git a/qcom/lemans-ivi-adas.dtsi b/qcom/lemans-ivi-adas.dtsi
index a30d7f15..e73c226d 100755
--- a/qcom/lemans-ivi-adas.dtsi
+++ b/qcom/lemans-ivi-adas.dtsi
@@ -1,4 +1,5 @@
 #include "lemans.dtsi"
+#include "lemans-adp-common.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. LeMans IVI ADAS SoC";
diff --git a/qcom/lemans-ivi.dtsi b/qcom/lemans-ivi.dtsi
index 69752f67..eb39aa28 100755
--- a/qcom/lemans-ivi.dtsi
+++ b/qcom/lemans-ivi.dtsi
@@ -1,5 +1,5 @@
 #include "lemans.dtsi"
-
+#include "lemans-adp-common.dtsi"
 / {
 	model = "Qualcomm Technologies, Inc. LeMans IVI SoC";
 	compatible = "qcom,lemans", "qcom,lemans-ivi";
diff --git a/qcom/lemans-pinctrl.dtsi b/qcom/lemans-pinctrl.dtsi
index be937ead..f638d908 100755
--- a/qcom/lemans-pinctrl.dtsi
+++ b/qcom/lemans-pinctrl.dtsi
@@ -803,84 +803,32 @@
 		};
 	};
 
-	qupv3_se12_4uart_pins: qupv3_se12_4uart_pins {
-		qupv3_se12_default_cts: qupv3_se12_default_cts {
+	qupv3_se12_2uart_pins: qupv3_se12_2uart_pins {
+		qupv3_se12_2uart_active: qupv3_se12_2uart_active {
 			mux {
-				pins = "gpio52";
-				function = "gpio";
-			};
-
-			config {
-				pins = "gpio52";
-				drive-strength = <2>;
-				bias-disable;
-			};
-		};
-
-		qupv3_se12_default_rtsrx: qupv3_se12_default_rtsrx {
-			mux {
-				pins = "gpio53", "gpio55";
-				function = "gpio";
-			};
-
-			config {
-				pins = "gpio53", "gpio55";
-				drive-strength = <2>;
-				bias-pull-down;
-			};
-		};
-
-		qupv3_se12_default_tx: qupv3_se12_default_tx {
-			mux {
-				pins = "gpio54";
-				function = "gpio";
-			};
-
-			config {
-				pins = "gpio54";
-				drive-strength = <2>;
-				bias-pull-up;
-			};
-		};
-
-		qupv3_se12_ctsrx: qupv3_se12_ctsrx {
-			mux {
-				pins = "gpio52", "gpio55";
+				pins = "gpio54", "gpio55";
 				function = "qup1_se5";
 			};
 
 			config {
-				pins = "gpio52", "gpio55";
+				pins = "gpio54", "gpio55";
 				drive-strength = <2>;
 				bias-disable;
 			};
 		};
 
-		qupv3_se12_rts: qupv3_se12_rts {
+		qupv3_se12_2uart_sleep: qupv3_se12_2uart_sleep {
 			mux {
-				pins = "gpio53";
-				function = "qup1_se5";
+				pins = "gpio54", "gpio55";
+				function = "gpio";
 			};
 
 			config {
-				pins = "gpio53";
+				pins = "gpio54", "gpio55";
 				drive-strength = <2>;
 				bias-pull-down;
 			};
 		};
-
-		qupv3_se12_tx: qupv3_se12_tx {
-			mux {
-				pins = "gpio54";
-				function = "qup1_se5";
-			};
-
-			config {
-				pins = "gpio54";
-				drive-strength = <2>;
-				bias-pull-up;
-			};
-		};
 	};
 
 	qupv3_se13_i2c_pins: qupv3_se13_i2c_pins {
diff --git a/qcom/lemans-qam-star.dtsi b/qcom/lemans-qam-star.dtsi
index d14e1d28..fccf29b5 100755
--- a/qcom/lemans-qam-star.dtsi
+++ b/qcom/lemans-qam-star.dtsi
@@ -1,5 +1,3 @@
-#include  "lemans-adp-common.dtsi"
-
 &cdsp1_pas {
 	status = "disabled";
 };
diff --git a/qcom/lemans-qupv3.dtsi b/qcom/lemans-qupv3.dtsi
index 2dc039a9..1a1441ed 100755
--- a/qcom/lemans-qupv3.dtsi
+++ b/qcom/lemans-qupv3.dtsi
@@ -1,4 +1,32 @@
 &soc {
+	/* GPI Instance */
+	gpi_dma0: qcom,gpi-dma@900000  {
+		compatible = "qcom,gpi-dma";
+		#dma-cells = <5>;
+		reg = <0x900000  0x60000>;
+		reg-names = "gpi-top";
+		iommus = <&apps_smmu 0x456 0x0>;
+		qcom,max-num-gpii = <12>;
+		interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,gpii-mask = <0xfff>;
+		qcom,ev-factor = <2>;
+		qcom,gpi-ee-offset = <0x10000>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
+		dma-coherent;
+		status = "disabled";
+	};
+
 	/* QUPv3_0  wrapper  instance */
 	qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
 		compatible = "qcom,geni-se-qup";
@@ -275,6 +303,34 @@
 		};
 	};
 
+	/* GPI Instance */
+	gpi_dma1: qcom,gpi-dma@a00000  {
+		compatible = "qcom,gpi-dma";
+		#dma-cells = <5>;
+		reg = <0xa00000  0x60000>;
+		reg-names = "gpi-top";
+		iommus = <&apps_smmu 0x456 0x0>;
+		qcom,max-num-gpii = <12>;
+		interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,gpii-mask = <0xfff>;
+		qcom,ev-factor = <2>;
+		qcom,gpi-ee-offset = <0x10000>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
+		dma-coherent;
+		status = "ok";
+	};
+
 	/* QUPv3_1  wrapper  instance */
 	qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
 		compatible = "qcom,geni-se-qup";
@@ -569,11 +625,11 @@
 			status = "disabled";
 		};
 
-		qupv3_se12_4uart: qcom,qup_uart@a94000 {
+		qupv3_se12_2uart: qcom,qup_uart@a94000 {
 			compatible = "qcom,msm-geni-serial-hs";
 			reg = <0xa94000 0x4000>;
 			reg-names = "se_phys";
-			interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
 			clock-names = "se-clk";
 			clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
 			interconnect-names = "qup-core", "qup-config", "qup-memory";
@@ -581,15 +637,12 @@
 			<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
 			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
 			<&aggre2_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>;
-			pinctrl-names = "default", "active", "sleep", "shutdown";
-			pinctrl-0 = <&qupv3_se12_default_cts>,
-					<&qupv3_se12_default_rtsrx>, <&qupv3_se12_default_tx>;
-			pinctrl-1 = <&qupv3_se12_ctsrx>, <&qupv3_se12_rts>,
-					<&qupv3_se12_tx>;
-			pinctrl-2 = <&qupv3_se12_ctsrx>, <&qupv3_se12_rts>,
-					<&qupv3_se12_tx>;
-			pinctrl-3 = <&qupv3_se12_default_cts>,
-					<&qupv3_se12_default_rtsrx>, <&qupv3_se12_default_tx>;
+			dmas = <&gpi_dma1 0 5 2 64 0>,
+				<&gpi_dma1 1 5 2 64 0>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se12_2uart_active>;
+			pinctrl-1 = <&qupv3_se12_2uart_sleep>;
 			status = "disabled";
 		};
 
@@ -613,6 +666,34 @@
 		};
 	};
 
+	/* GPI Instance */
+	gpi_dma2: qcom,gpi-dma@800000  {
+		compatible = "qcom,gpi-dma";
+		#dma-cells = <5>;
+		reg = <0x800000  0x60000>;
+		reg-names = "gpi-top";
+		iommus = <&apps_smmu 0x456 0x0>;
+		qcom,max-num-gpii = <12>;
+		interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,gpii-mask = <0xfff>;
+		qcom,ev-factor = <2>;
+		qcom,gpi-ee-offset = <0x10000>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
+		dma-coherent;
+		status = "disabled";
+	};
+
 	/* QUPv3_2  wrapper  instance */
 	qupv3_2: qcom,qupv3_2_geni_se@8c0000 {
 		compatible = "qcom,geni-se-qup";
diff --git a/qcom/lemans-rumi.dtsi b/qcom/lemans-rumi.dtsi
index 6d2a9510..0cd1c988 100755
--- a/qcom/lemans-rumi.dtsi
+++ b/qcom/lemans-rumi.dtsi
@@ -37,3 +37,19 @@
 		maximum-speed = "high-speed";
 	};
 };
+
+&tsens0 {
+		status = "disabled";
+};
+
+&tsens1 {
+		status = "disabled";
+};
+
+&tsens2 {
+		status = "disabled";
+};
+
+&tsens3 {
+		status = "disabled";
+};
diff --git a/qcom/lemans-thermal-overlay.dtsi b/qcom/lemans-thermal-overlay.dtsi
new file mode 100755
index 00000000..f2db3b80
--- /dev/null
+++ b/qcom/lemans-thermal-overlay.dtsi
@@ -0,0 +1,69 @@
+#include <dt-bindings/thermal/thermal_qti.h>
+
+&thermal_zones {
+	pm8775_1_tz {
+		cooling-maps {
+			pm8775_1_gpu {
+				trip = <&pm8775_1_trip0>;
+				cooling-device = <&msm_gpu 4 THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	pm8775_2_tz {
+		cooling-maps {
+			pm8775_2_cdsp0 {
+				trip = <&pm8775_2_trip0>;
+				cooling-device = <&cdsp_sw0 5 5>;
+			};
+		};
+	};
+
+	pm8775_3_tz {
+		cooling-maps {
+			pm8775_3_cpu1 {
+				trip = <&pm8775_3_trip0>;
+				cooling-device = <&cpu1_pause 1 1>;
+			};
+
+			pm8775_3_cpu2 {
+				trip = <&pm8775_3_trip0>;
+				cooling-device = <&cpu2_pause 1 1>;
+			};
+
+			pm8775_3_cpu3 {
+				trip = <&pm8775_3_trip0>;
+				cooling-device = <&cpu3_pause 1 1>;
+			};
+
+			pm8775_3_cpu4 {
+				trip = <&pm8775_3_trip0>;
+				cooling-device = <&cpu4_pause 1 1>;
+			};
+
+			pm8775_3_cpu5 {
+				trip = <&pm8775_3_trip0>;
+				cooling-device = <&cpu5_pause 1 1>;
+			};
+
+			pm8775_3_cpu6 {
+				trip = <&pm8775_3_trip0>;
+				cooling-device = <&cpu6_pause 1 1>;
+			};
+
+			pm8775_3_cpu7 {
+				trip = <&pm8775_3_trip0>;
+				cooling-device = <&cpu7_pause 1 1>;
+			};
+		};
+	};
+
+	pm8775_4_tz {
+		cooling-maps {
+			pm8775_4_cdsp1 {
+				trip = <&pm8775_4_trip0>;
+				cooling-device = <&cdsp_sw1 5 5>;
+			};
+		};
+	};
+};
diff --git a/qcom/lemans-thermal.dtsi b/qcom/lemans-thermal.dtsi
new file mode 100755
index 00000000..07a2aaa1
--- /dev/null
+++ b/qcom/lemans-thermal.dtsi
@@ -0,0 +1,1629 @@
+#include <dt-bindings/thermal/thermal_qti.h>
+
+&msm_gpu {
+	#cooling-cells = <2>;
+};
+
+&soc {
+	tsens0:tsens@c222000 {
+		compatible = "qcom,tsens-v2";
+		reg = <0x0C263000 0x1ff>,
+		      <0x0C222000 0x1ff>;
+		#qcom,sensors = <12>;
+		interrupts = <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "uplow","critical";
+		#thermal-sensor-cells = <1>;
+	};
+
+	tsens1:tsens@c223000 {
+		compatible = "qcom,tsens-v2";
+		reg = <0x0C265000 0x1ff>,
+			<0x0C223000 0x1ff>;
+		#qcom,sensors = <12>;
+		interrupts = <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "uplow","critical";
+		#thermal-sensor-cells = <1>;
+	};
+
+	tsens2:tsens@c224000 {
+		compatible = "qcom,tsens-v2";
+		reg = <0x0C251000 0x1ff>,
+			<0x0C224000 0x1ff>;
+		#qcom,sensors = <13>;
+		interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "uplow","critical";
+		#thermal-sensor-cells = <1>;
+	};
+
+	tsens3:tsens@c225000 {
+		compatible = "qcom,tsens-v2";
+		reg = <0x0C252000 0x1ff>,
+			<0x0C225000 0x1ff>;
+		#qcom,sensors = <13>;
+		interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "uplow","critical";
+		#thermal-sensor-cells = <1>;
+	};
+
+	qcom,cpu-pause {
+		compatible = "qcom,thermal-pause";
+
+		cpu0_pause: cpu0-pause {
+			qcom,cpus = <&CPU0>;
+			#cooling-cells = <2>;
+		};
+
+		cpu1_pause: cpu1-pause {
+			qcom,cpus = <&CPU1>;
+			#cooling-cells = <2>;
+		};
+
+		cpu2_pause: cpu2-pause {
+			qcom,cpus = <&CPU2>;
+			#cooling-cells = <2>;
+		};
+
+		cpu3_pause: cpu3-pause {
+			qcom,cpus = <&CPU3>;
+			#cooling-cells = <2>;
+		};
+
+		cpu4_pause: cpu4-pause {
+			qcom,cpus = <&CPU4>;
+			#cooling-cells = <2>;
+		};
+
+		cpu5_pause: cpu5-pause {
+			qcom,cpus = <&CPU5>;
+			#cooling-cells = <2>;
+		};
+
+		cpu6_pause: cpu6-pause {
+			qcom,cpus = <&CPU6>;
+			#cooling-cells = <2>;
+		};
+
+		cpu7_pause: cpu7-pause {
+			qcom,cpus = <&CPU7>;
+			#cooling-cells = <2>;
+		};
+
+		/* Thermal-engine cooling devices */
+		pause-cpu0 {
+			qcom,cpus = <&CPU0>;
+			qcom,cdev-alias = "pause-cpu0";
+		};
+
+		pause-cpu1 {
+			qcom,cpus = <&CPU1>;
+			qcom,cdev-alias = "pause-cpu1";
+		};
+
+		pause-cpu2 {
+			qcom,cpus = <&CPU2>;
+			qcom,cdev-alias = "pause-cpu2";
+		};
+
+		pause-cpu3 {
+			qcom,cpus = <&CPU3>;
+			qcom,cdev-alias = "pause-cpu3";
+		};
+
+		pause-cpu4 {
+			qcom,cpus = <&CPU4>;
+			qcom,cdev-alias = "pause-cpu4";
+		};
+
+		pause-cpu5 {
+			qcom,cpus = <&CPU5>;
+			qcom,cdev-alias = "pause-cpu5";
+		};
+
+		pause-cpu6 {
+			qcom,cpus = <&CPU6>;
+			qcom,cdev-alias = "pause-cpu6";
+		};
+
+		pause-cpu7 {
+			qcom,cpus = <&CPU7>;
+			qcom,cdev-alias = "pause-cpu7";
+		};
+	};
+
+	qcom,cpu-hotplug {
+		compatible = "qcom,cpu-hotplug";
+
+		cpu1_hotplug: cpu1-hotplug {
+			qcom,cpu = <&CPU1>;
+			#cooling-cells = <2>;
+		};
+
+		cpu2_hotplug: cpu2-hotplug {
+			qcom,cpu = <&CPU2>;
+			#cooling-cells = <2>;
+		};
+
+		cpu3_hotplug: cpu3-hotplug {
+			qcom,cpu = <&CPU3>;
+			#cooling-cells = <2>;
+		};
+
+		cpu4_hotplug: cpu4-hotplug {
+			qcom,cpu = <&CPU4>;
+			#cooling-cells = <2>;
+		};
+
+		cpu5_hotplug: cpu5-hotplug {
+			qcom,cpu = <&CPU5>;
+			#cooling-cells = <2>;
+		};
+
+		cpu6_hotplug: cpu6-hotplug {
+			qcom,cpu = <&CPU6>;
+			#cooling-cells = <2>;
+		};
+
+		cpu7_hotplug: cpu7-hotplug {
+			qcom,cpu = <&CPU7>;
+			#cooling-cells = <2>;
+		};
+	};
+
+	qcom,devfreq-cdev {
+		compatible = "qcom,devfreq-cdev";
+		qcom,devfreq = <&msm_gpu>;
+	};
+
+	qcom,cpufreq-cdev {
+		compatible = "qcom,cpufreq-cdev";
+		qcom,cpus = <&CPU0 &CPU4>;
+	};
+
+	qmi-tmd-devices {
+		compatible = "qcom,qmi-cooling-devices";
+
+		cdsp0 {
+			qcom,instance-id = <QMI_CDSP_INST_ID>;
+
+			cdsp_sw0: cdsp_sw0 {
+				qcom,qmi-dev-name = "cdsp_sw";
+				#cooling-cells = <2>;
+			};
+
+			cdsp_hw0: cdsp_hw0 {
+				qcom,qmi-dev-name = "cdsp_hw";
+				#cooling-cells = <2>;
+			};
+		};
+
+		cdsp1 {
+			qcom,instance-id = <QMI_CDSP1_INST_ID>;
+
+			cdsp_sw1: cdsp_sw1 {
+				qcom,qmi-dev-name = "cdsp_sw";
+				#cooling-cells = <2>;
+			};
+
+			cdsp_hw1: cdsp_hw1 {
+				qcom,qmi-dev-name = "cdsp_hw";
+				#cooling-cells = <2>;
+			};
+		};
+	};
+};
+
+&thermal_zones {
+	aoss-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 0>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpu-0-0-0 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 1>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			cpu000_config: cpu000-config {
+				temperature = <116000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu000_cdev {
+				trip = <&cpu000_config>;
+				cooling-device = <&cpu0_pause 1 1>;
+			};
+		};
+	};
+
+	cpu-0-1-0 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 2>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			cpu010_config: cpu010-config {
+				temperature = <116000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu010_cdev {
+				trip = <&cpu010_config>;
+				cooling-device = <&cpu1_pause 1 1>;
+			};
+		};
+	};
+
+	cpu-0-2-0 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 3>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			cpu020_config: cpu020-config {
+				temperature = <116000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu020_cdev {
+				trip = <&cpu020_config>;
+				cooling-device = <&cpu2_pause 1 1>;
+			};
+		};
+	};
+
+	cpu-0-3-0 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 4>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			cpu030_config: cpu030-config {
+				temperature = <116000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu030_cdev {
+				trip = <&cpu030_config>;
+				cooling-device = <&cpu3_pause 1 1>;
+			};
+		};
+	};
+
+	gpuss-0 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 5>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			gpuss0_config: gpuss0-config {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			gpu0_cdev {
+				trip = <&gpuss0_config>;
+				cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	gpuss-1 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 6>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			gpuss1_config: gpuss1-config {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			gpu1_cdev {
+				trip = <&gpuss1_config>;
+				cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	gpuss-2 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 7>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			gpuss2_config: gpuss2-config {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			gpu2_cdev {
+				trip = <&gpuss2_config>;
+				cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	audio {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 8>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	camss-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 9>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	pcie-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 10>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpuss-0-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 11>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	aoss-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 0>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpu-0-0-1 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 1>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			cpu001_config: cpu001-config {
+				temperature = <116000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu001_cdev {
+				trip = <&cpu001_config>;
+				cooling-device = <&cpu0_pause 1 1>;
+			};
+		};
+	};
+
+	cpu-0-1-1 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 2>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			cpu011_config: cpu011-config {
+				temperature = <116000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu011_cdev {
+				trip = <&cpu011_config>;
+				cooling-device = <&cpu1_pause 1 1>;
+			};
+		};
+	};
+
+	cpu-0-2-1 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 3>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			cpu021_config: cpu021-config {
+				temperature = <116000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu021_cdev {
+				trip = <&cpu021_config>;
+				cooling-device = <&cpu2_pause 1 1>;
+			};
+		};
+	};
+
+	cpu-0-3-1 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 4>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			cpu031_config: cpu031-config {
+				temperature = <116000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu031_cdev {
+				trip = <&cpu031_config>;
+				cooling-device = <&cpu3_pause 1 1>;
+			};
+		};
+	};
+
+	gpuss-3 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 5>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			gpuss3_config: gpuss3-config {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			gpu3_cdev {
+				trip = <&gpuss3_config>;
+				cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	gpuss-4 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 6>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			gpuss4_config: gpuss4-config {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			gpu4_cdev {
+				trip = <&gpuss4_config>;
+				cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	gpuss-5 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 7>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			gpuss5_config: gpuss5-config {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			gpu5_cdev {
+				trip = <&gpuss5_config>;
+				cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	video {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 8>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	camss-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 9>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	pcie-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 10>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpuss-0-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 11>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	aoss-2 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 0>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpu-1-0-0 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 1>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			cpu100_config: cpu100-config {
+				temperature = <116000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu100_cdev {
+				trip = <&cpu100_config>;
+				cooling-device = <&cpu4_pause 1 1>;
+			};
+		};
+	};
+
+	cpu-1-1-0 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 2>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			cpu110_config: cpu110-config {
+				temperature = <116000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu110_cdev {
+				trip = <&cpu110_config>;
+				cooling-device = <&cpu5_pause 1 1>;
+			};
+		};
+	};
+
+	cpu-1-2-0 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 3>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			cpu120_config: cpu120-config {
+				temperature = <116000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu120_cdev {
+				trip = <&cpu120_config>;
+				cooling-device = <&cpu6_pause 1 1>;
+			};
+		};
+	};
+
+	cpu-1-3-0 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 4>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			cpu130_config: cpu130-config {
+				temperature = <116000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu130_cdev {
+				trip = <&cpu130_config>;
+				cooling-device = <&cpu7_pause 1 1>;
+			};
+		};
+	};
+
+	nsp-0-0-0 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 5>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			nsp000_config: nsp000-config {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			nsp000_cdev {
+				trip = <&nsp000_config>;
+				cooling-device = <&cdsp_sw0 THERMAL_NO_LIMIT
+								THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	nsp-0-1-0 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 6>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			nsp010_config: nsp010-config {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			nsp010_cdev {
+				trip = <&nsp010_config>;
+				cooling-device = <&cdsp_sw0 THERMAL_NO_LIMIT
+								THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	nsp-0-2-0 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 7>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			nsp020_config: nsp020-config {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			nsp020_cdev {
+				trip = <&nsp020_config>;
+				cooling-device = <&cdsp_sw0 THERMAL_NO_LIMIT
+								THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	nsp-1-0-0 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 8>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			nsp100_config: nsp100-config {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			nsp100_cdev {
+				trip = <&nsp100_config>;
+				cooling-device = <&cdsp_sw1 THERMAL_NO_LIMIT
+									THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	nsp-1-1-0 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 9>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			nsp110_config: nsp110-config {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			nsp110_cdev {
+				trip = <&nsp110_config>;
+				cooling-device = <&cdsp_sw1 THERMAL_NO_LIMIT
+								THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	nsp-1-2-0 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 10>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			nsp120_config: nsp120-config {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			nsp120_cdev {
+				trip = <&nsp120_config>;
+				cooling-device = <&cdsp_sw1 THERMAL_NO_LIMIT
+								THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	ddrss-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 11>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpuss-1-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 12>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	aoss-3 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens3 0>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpu-1-0-1 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens3 1>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			cpu101_config: cpu101-config {
+				temperature = <116000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu101_cdev {
+				trip = <&cpu101_config>;
+				cooling-device = <&cpu4_pause 1 1>;
+			};
+		};
+	};
+
+	cpu-1-1-1 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens3 2>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			cpu111_config: cpu111-config {
+				temperature = <116000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu111_cdev {
+				trip = <&cpu111_config>;
+				cooling-device = <&cpu5_pause 1 1>;
+			};
+		};
+	};
+
+	cpu-1-2-1 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens3 3>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			cpu121_config: cpu121-config {
+				temperature = <116000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu121_cdev {
+				trip = <&cpu121_config>;
+				cooling-device = <&cpu6_pause 1 1>;
+			};
+		};
+	};
+
+	cpu-1-3-1 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens3 4>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			cpu131_config: cpu131-config {
+				temperature = <116000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu131_cdev {
+				trip = <&cpu131_config>;
+				cooling-device = <&cpu7_pause 1 1>;
+			};
+		};
+	};
+
+	nsp-0-0-1 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens3 5>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			nsp001_config: nsp001-config {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			nsp001_cdev {
+				trip = <&nsp001_config>;
+				cooling-device = <&cdsp_sw0 THERMAL_NO_LIMIT
+								THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	nsp-0-1-1 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens3 6>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			nsp011_config: nsp011-config {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			nsp011_cdev {
+				trip = <&nsp011_config>;
+				cooling-device = <&cdsp_sw0 THERMAL_NO_LIMIT
+								THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	nsp-0-2-1 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens3 7>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			nsp021_config: nsp021-config {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			nsp021_cdev {
+				trip = <&nsp021_config>;
+				cooling-device = <&cdsp_sw0 THERMAL_NO_LIMIT
+								THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	nsp-1-0-1 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens3 8>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			nsp101_config: nsp101-config {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			nsp101_cdev {
+				trip = <&nsp101_config>;
+				cooling-device = <&cdsp_sw1 THERMAL_NO_LIMIT
+								THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	nsp-1-1-1 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens3 9>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			nsp111_config: nsp111-config {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			nsp111_cdev {
+				trip = <&nsp111_config>;
+				cooling-device = <&cdsp_sw1 THERMAL_NO_LIMIT
+								THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	nsp-1-2-1 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens3 10>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			nsp121_config: nsp121-config {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			nsp121_cdev {
+				trip = <&nsp121_config>;
+				cooling-device = <&cdsp_sw1 THERMAL_NO_LIMIT
+								THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	ddrss-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens3 11>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpuss-1-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens3 12>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <120000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+};
diff --git a/qcom/lemans-usb.dtsi b/qcom/lemans-usb.dtsi
index 9aaf5232..1a34f303 100755
--- a/qcom/lemans-usb.dtsi
+++ b/qcom/lemans-usb.dtsi
@@ -255,6 +255,7 @@
 		qcom,pm-qos-latency = <2>;
 
 		qcom,host-poweroff-in-pm-suspend;
+		qcom,default-mode-host;
 
 		interconnect-names = "usb-ddr", "ddr-usb";
 		interconnects = <&aggre1_noc MASTER_USB3_1 &mc_virt SLAVE_EBI1>,
diff --git a/qcom/lemans-vm-la.dtsi b/qcom/lemans-vm-la.dtsi
index d1fc80fb..eb7bd3a2 100755
--- a/qcom/lemans-vm-la.dtsi
+++ b/qcom/lemans-vm-la.dtsi
@@ -38,3 +38,26 @@
 	status = "ok";
 };
 
+&usb1 {
+	status = "ok";
+};
+
+&usb2_phy1 {
+	status = "ok";
+};
+
+&usb_qmp_phy1 {
+	status = "ok";
+};
+
+&usb2 {
+	status = "ok";
+};
+
+&usb2_phy2 {
+	status = "ok";
+};
+
+&qupv3_se17_4uart {
+	status = "ok";
+};
diff --git a/qcom/lemans-vm-lv.dtsi b/qcom/lemans-vm-lv.dtsi
index c7c4f15c..4e85f50a 100755
--- a/qcom/lemans-vm-lv.dtsi
+++ b/qcom/lemans-vm-lv.dtsi
@@ -4,3 +4,39 @@
 &hab {
 	vmid = <3>;
 };
+
+&qupv3_se17_4uart {
+	status = "ok";
+};
+
+&usb0 {
+	status = "ok";
+};
+
+&usb2_phy0 {
+	status = "ok";
+};
+
+&usb_qmp_phy0 {
+	status = "ok";
+};
+
+&usb1 {
+	status = "ok";
+};
+
+&usb2_phy1 {
+	status = "ok";
+};
+
+&usb_qmp_phy1 {
+	status = "ok";
+};
+
+&usb2 {
+	status = "ok";
+};
+
+&usb2_phy2 {
+	status = "ok";
+};
diff --git a/qcom/lemans-vm-qupv3.dtsi b/qcom/lemans-vm-qupv3.dtsi
index e6e79dcd..069a2bc3 100755
--- a/qcom/lemans-vm-qupv3.dtsi
+++ b/qcom/lemans-vm-qupv3.dtsi
@@ -61,6 +61,22 @@
 		qcom,iommu-dma = "fastmap";
 		status = "ok";
 
+		qupv3_se14_spi: spi@880000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x880000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se14_spi_active>;
+			pinctrl-1 = <&qupv3_se14_spi_sleep>;
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
 		/* BT UART Instance */
 		qupv3_se17_4uart: qcom,qup_uart@88c000 {
 			compatible = "qcom,msm-geni-serial-hs";
diff --git a/qcom/lemans-vm-usb.dtsi b/qcom/lemans-vm-usb.dtsi
index aaf76834..471dbd2d 100755
--- a/qcom/lemans-vm-usb.dtsi
+++ b/qcom/lemans-vm-usb.dtsi
@@ -11,8 +11,14 @@
 		#size-cells = <1>;
 		ranges;
 
-		interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "pwr_event_irq";
+		interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>,
+				<&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
+				<&pdc 12 IRQ_TYPE_LEVEL_HIGH>,
+				<&pdc 15 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
+				"ss_phy_irq", "dm_hs_phy_irq";
+		qcom,use-pdc-interrupts;
+
 
 		USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
 		clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
@@ -222,8 +228,13 @@
 		#size-cells = <1>;
 		ranges;
 
-		interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "pwr_event_irq";
+		interrupts-extended = <&pdc 8 IRQ_TYPE_EDGE_RISING>,
+				<&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
+				<&pdc 13 IRQ_TYPE_LEVEL_HIGH>,
+				<&pdc 7 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
+				"ss_phy_irq", "dm_hs_phy_irq";
+		qcom,use-pdc-interrupts;
 
 		USB3_GDSC-supply = <&gcc_usb30_sec_gdsc>;
 		clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>,
@@ -243,6 +254,7 @@
 		qcom,pm-qos-latency = <2>;
 
 		qcom,host-poweroff-in-pm-suspend;
+		qcom,default-mode-host;
 
 		status = "disabled";
 
@@ -264,6 +276,7 @@
 			tx-fifo-resize;
 			maximum-speed = "super-speed-plus";
 			dr_mode = "otg";
+			usb-role-switch;
 		};
 	};
 
@@ -435,8 +448,12 @@
 		#size-cells = <1>;
 		ranges;
 
-		interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "pwr_event_irq";
+		interrupts-extended = <&pdc 10 IRQ_TYPE_EDGE_RISING>,
+				<&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
+				<&pdc 9 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
+				"dm_hs_phy_irq";
+		qcom,use-pdc-interrupts;
 
 		USB3_GDSC-supply = <&gcc_usb20_prim_gdsc>;
 		clocks = <&gcc GCC_USB20_MASTER_CLK>,
diff --git a/qcom/lemans-vm.dtsi b/qcom/lemans-vm.dtsi
index 8b65cec4..3a610881 100755
--- a/qcom/lemans-vm.dtsi
+++ b/qcom/lemans-vm.dtsi
@@ -3,7 +3,7 @@
 
 / {
 	model = "Qualcomm Technologies, Inc. Lemans Guest Virtual Machine";
-	qcom,msm-name  = "Lemans";
+	qcom,msm-name  = "SA_LEMANS_IVI";
 	qcom,msm-id = <532 0x20000>;
 
 	aliases {
@@ -18,6 +18,65 @@
 };
 
 &soc {
+	tcsr_compute_signal_glb: syscon@0x1fd8000 {
+		compatible = "syscon";
+		reg = <0x1fd8000 0x1000>;
+	};
+
+	tcsr_compute_signal_sender0: syscon@0x1fd9000 {
+		compatible = "syscon";
+		reg = <0x1fd9000 0x1000>;
+	};
+
+	tcsr_compute_signal_sender1: syscon@0x1fdd000 {
+		compatible = "syscon";
+		reg = <0x1fdd000 0x1000>;
+	};
+
+	tcsr_compute_signal_receiver0: syscon@0x1fdb000 {
+		compatible = "syscon";
+		reg = <0x1fdb000 0x1000>;
+	};
+
+	tcsr_compute_signal_receiver1: syscon@0x1fdf000 {
+		compatible = "syscon";
+		reg = <0x1fdf000 0x1000>;
+	};
+
+	hgsl_tcsr_sender0: hgsl_tcsr_sender0 {
+		compatible = "qcom,hgsl-tcsr-sender";
+		syscon = <&tcsr_compute_signal_sender0>;
+		syscon-glb = <&tcsr_compute_signal_glb>;
+	};
+
+	hgsl_tcsr_sender1: hgsl_tcsr_sender1 {
+		compatible = "qcom,hgsl-tcsr-sender";
+		syscon = <&tcsr_compute_signal_sender1>;
+		syscon-glb = <&tcsr_compute_signal_glb>;
+	};
+
+	hgsl_tcsr_receiver0: hgsl_tcsr_receiver0 {
+		compatible = "qcom,hgsl-tcsr-receiver";
+		syscon = <&tcsr_compute_signal_receiver0>;
+		interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	hgsl_tcsr_receiver1: hgsl_tcsr_receiver1 {
+		compatible = "qcom,hgsl-tcsr-receiver";
+		syscon = <&tcsr_compute_signal_receiver1>;
+		interrupts = <0 239 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	msm_gpu_hyp: qcom,hgsl@0x2c00000 {
+		compatible = "qcom,hgsl";
+		reg = <0x2c00000 0x8>, <0x2c8f000 0x4>;
+		reg-names = "hgsl_reg_hwinf", "hgsl_reg_gmucx";
+
+		qcom,glb-db-senders = <&hgsl_tcsr_sender0
+					&hgsl_tcsr_sender1>;
+		qcom,glb-db-receivers = <&hgsl_tcsr_receiver0
+					&hgsl_tcsr_receiver1>;
+	};
 
 	apps_smmu: apps-smmu@15000000 {
 		compatible = "qcom,qsmmu-v500";
@@ -26,6 +85,7 @@
 		reg-names = "base", "tcu-base";
 		#iommu-cells = <2>;
 		qcom,skip-init;
+		qcom,handoff-smrs = <0x100 0x0>,<0x420 0x0>,<0x20 0x0>,<0x80 0x0>,<0xa0 0x0>,<0x1800 0x402>,<0x1000 0x402>,<0x1001 0x400>,<0x4a0 0x40>,<0x4c0 0x0>,<0x120 0xf>,<0x1801 0x400>,<0x140 0xf>,<0x880 0x400>,<0x887 0x400>,<0x883 0x400>,<0x881 0x404>,<0x884 0x400>,<0x8a0 0x400>,<0x8a3 0x400>,<0x8a4 0x400>,<0x460 0x0>,<0x461 0x0>,<0x462 0x0>,<0x860 0x400>,<0x840 0x480>,<0x800 0x0>,<0xc00 0x0>,<0x3400 0x0>,<0x3420 0x0>,<0x3403 0x20>,<0x803 0x400>,<0x3001 0x0>,<0x3003 0x0>,<0x3005 0x0>,<0x21c1 0x0>,<0x25c1 0x0>,<0x2161 0x0>,<0x2561 0x0>,<0x2141 0x0>,<0x2541 0x0>,<0x21e1 0x0>,<0x25e1 0x0>,<0x2181 0x0>,<0x2581 0x0>,<0x21c2 0x0>,<0x2162 0x0>,<0x2562 0x0>,<0x25c2 0x0>,<0x2142 0x0>,<0x2542 0x0>,<0x21e2 0x0>,<0x25e2 0x0>,<0x2182 0x0>,<0x2582 0x0>,<0x21c3 0x0>,<0x2163 0x0>,<0x2563 0x0>,<0x25c3 0x0>,<0x2143 0x0>,<0x2543 0x0>,<0x21e3 0x0>,<0x25e3 0x0>,<0x2183 0x0>,<0x2583 0x0>,<0x21c4 0x0>,<0x25c4 0x0>,<0x2164 0x0>,<0x2564 0x0>,<0x2144 0x0>,<0x2544 0x0>,<0x21e4 0x0>,<0x25e4 0x0>,<0x2184 0x0>,<0x2584 0x0>,<0x2961 0x0>,<0x2d61 0x0>,<0x29c1 0x0>,<0x2dc1 0x0>,<0x2941 0x0>,<0x2d41 0x0>,<0x29e1 0x0>,<0x2de1 0x0>,<0x2981 0x0>,<0x2d81 0x0>,<0x2962 0x0>,<0x2d62 0x0>,<0x29c2 0x0>,<0x2dc2 0x0>,<0x2942 0x0>,<0x2d42 0x0>,<0x29e2 0x0>,<0x2de2 0x0>,<0x2982 0x0>,<0x2d82 0x0>,<0x2963 0x0>,<0x2d63 0x0>,<0x29c3 0x0>,<0x2dc3 0x0>,<0x2943 0x0>,<0x2d43 0x0>,<0x29e3 0x0>,<0x2de3 0x0>,<0x2983 0x0>,<0x2d83 0x0>,<0x2964 0x0>,<0x2d64 0x0>,<0x29c4 0x0>,<0x2dc4 0x0>,<0x2944 0x0>,<0x2d44 0x0>,<0x29e4 0x0>,<0x2de4 0x0>,<0x2984 0x0>,<0x2d84 0x0>,<0x416 0x0>,<0x456 0x0>,<0x5b6 0x0>,<0x56 0x0>,<0x403 0x0>,<0x443 0x0>,<0x5a3 0x0>,<0x43 0x0>,<0x38a1 0x0>,<0x38a2 0x0>,<0x38a3 0x0>,<0x38c1 0x0>,<0x38c2 0x0>,<0x38c3 0x0>,<0x481 0x0>,<0x5c1 0x0>,<0x480 0x0>,<0x5c0 0x0>,<0x580 0x0>,<0x882 0x400>,<0x29c0 0x400>,<0x21c0 0x400>,<0x45 0x0>,<0x5a5 0x0>,<0x445 0x0>,<0x405 0x0>,<0x3048 0x5>,<0x304a 0x1>,<0x3040 0x0>,<0x3062 0x0>,<0x3060 0x9>,<0x3000 0x0>,<0x3064 0x0>,<0x3063 0x0>,<0x3035 0x0>,<0x303b 0x0>,<0x303a 0x4>,<0x303c 0x1>,<0x3020 0x7>,<0x38c0 0x0>,<0x38a0 0x0>,<0x8a2 0x400>,<0x8a7 0x400>,<0x810 0x40f>,<0x3410 0x2f>,<0x8c1 0x400>,<0x8c2 0x400>,<0x841 0x420>;
 		qcom,use-3-lvl-tables;
 		#global-interrupts = <2>;
 		#size-cells = <1>;
@@ -179,6 +239,15 @@
 		#interrupt-cells = <2>;
 	};
 
+	pdc: interrupt-controller@b220000 {
+			compatible = "qcom,sm8150-pdc","qcom,pdc";
+			reg = <0xb220000 0x30000>;
+			qcom,pdc-ranges = <7 487 4>, <12 492 4>;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&intc>;
+			interrupt-controller;
+	};
+
 	qcom_rng_ee3: qrng@10d3000 {
 		compatible = "qcom,msm-rng";
 		reg = <0x10d3000 0x1000>;
@@ -221,6 +290,25 @@
 		clock-output-names = "usb3_phy_wrapper_gcc_usb30_sec_pipe_clk";
 		#clock-cells = <0>;
 	};
+
+	/* PWR_CTR1_VDD_PA supply */
+	vreg_conn_pa: vreg_conn_pa {
+		compatible = "regulator-fixed";
+		regulator-name = "vreg_conn_pa";
+		startup-delay-us = <4000>;
+		enable-active-high;
+		gpio = <&pm8775_2_gpios 6 0>;
+	};
+
+	/* PWR_CTR2_VDD_1P8 supply */
+	vreg_conn_1p8: vreg_conn_1p8 {
+		compatible = "regulator-fixed";
+		regulator-name = "vreg_conn_1p8";
+		startup-delay-us = <4000>;
+		enable-active-high;
+		gpio = <&pm8775_2_gpios 4 0>;
+	};
+
 };
 
 &regulator {
@@ -275,6 +363,24 @@
 		regulator-min-microvolt = <1620000>;
 		regulator-max-microvolt = <1980000>;
 	};
+
+	L2C: pm8775_c_l2: regulator-pm8775_c-l2 {
+		regulator-name = "ldoc2";
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <1100000>;
+	};
+
+	L6E: pm8775_e_l6: regulator-pm8775_e-l6 {
+		regulator-name = "ldoe6";
+		regulator-min-microvolt = <1280000>;
+		regulator-max-microvolt = <1450000>;
+	};
+
+	S5A: pm8775_a_s5: regulator-pm8775_a-s5 {
+		regulator-name = "smpa5";
+		regulator-min-microvolt = <1850000>;
+		regulator-max-microvolt = <2100000>;
+	};
 };
 
 &scc {
@@ -285,3 +391,47 @@
 #include "pm8775-vm.dtsi"
 #include "lemans-vm-qupv3.dtsi"
 #include "lemans-vm-usb.dtsi"
+
+&pm8775_3_gpios {
+	usb201_vbus_boost {
+		usb20_vbus_boost_default: usb20_vbus_boost_default {
+			pins = "gpio3";
+			function = "normal";
+			output-high;
+			power-source = <0>;
+		};
+
+		usb21_vbus_boost_default: usb21_vbus_boost_default {
+			pins = "gpio10";
+			function = "normal";
+			output-high;
+			power-source = <0>;
+		};
+	};
+};
+
+&pm8775_2_gpios {
+	usb22_vbus_boost {
+		usb22_vbus_boost_default: usb22_vbus_boost_default {
+			pins = "gpio9";
+			function = "normal";
+			output-high;
+			power-source = <0>;
+		};
+	};
+};
+
+&usb0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb20_vbus_boost_default>;
+};
+
+&usb1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb21_vbus_boost_default>;
+};
+
+&usb2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb22_vbus_boost_default>;
+};
diff --git a/qcom/lemans.dtsi b/qcom/lemans.dtsi
index ebdb2df7..3b0f14f1 100755
--- a/qcom/lemans.dtsi
+++ b/qcom/lemans.dtsi
@@ -24,7 +24,9 @@
 
 	reserved_memory: reserved-memory { };
 
-	chosen: chosen { };
+	chosen: chosen {
+		bootargs = "qcom_dma_heaps.enable_bitstream_contig_heap=y";
+	};
 
 	aliases {
 		serial0 = &qupv3_se10_2uart;
@@ -33,6 +35,7 @@
 		i2c4 = &qupv3_se11_i2c;
 		spi16 = &qupv3_se16_spi;
 		hsuart0 = &qupv3_se17_4uart;
+		hsuart1 = &qupv3_se12_2uart; /* GSI GNSS */
 	};
 
 	soc: soc { };
@@ -55,6 +58,7 @@
 			cache-size = <0x20000>;
 			qcom,freq-domain = <&cpufreq_hw 0 4>;
 			next-level-cache = <&L2_0>;
+			#cooling-cells = <2>;
 			L2_0: l2-cache {
 			      compatible = "arm,arch-cache";
 			      cache-level = <2>;
@@ -81,6 +85,7 @@
 			cache-size = <0x20000>;
 			qcom,freq-domain = <&cpufreq_hw 0 4>;
 			next-level-cache = <&L2_1>;
+			#cooling-cells = <2>;
 			L2_1: l2-cache {
 			      compatible = "arm,arch-cache";
 			      cache-level = <2>;
@@ -101,6 +106,7 @@
 			cache-size = <0x20000>;
 			qcom,freq-domain = <&cpufreq_hw 0 4>;
 			next-level-cache = <&L2_2>;
+			#cooling-cells = <2>;
 			L2_2: l2-cache {
 			      compatible = "arm,arch-cache";
 			      cache-level = <2>;
@@ -121,6 +127,7 @@
 			cache-size = <0x20000>;
 			qcom,freq-domain = <&cpufreq_hw 0 4>;
 			next-level-cache = <&L2_3>;
+			#cooling-cells = <2>;
 			L2_3: l2-cache {
 			      compatible = "arm,arch-cache";
 			      cache-level = <2>;
@@ -141,6 +148,7 @@
 			cpu-release-addr = <0x0 0x90000000>;
 			qcom,freq-domain = <&cpufreq_hw 1 4>;
 			next-level-cache = <&L2_4>;
+			#cooling-cells = <2>;
 			L2_4: l2-cache {
 			      compatible = "arm,arch-cache";
 			      cache-level = <2>;
@@ -167,6 +175,7 @@
 			cache-size = <0x20000>;
 			qcom,freq-domain = <&cpufreq_hw 1 4>;
 			next-level-cache = <&L2_5>;
+			#cooling-cells = <2>;
 			L2_5: l2-cache {
 			      compatible = "arm,arch-cache";
 			      cache-level = <2>;
@@ -187,6 +196,7 @@
 			cache-size = <0x20000>;
 			qcom,freq-domain = <&cpufreq_hw 1 4>;
 			next-level-cache = <&L2_6>;
+			#cooling-cells = <2>;
 			L2_6: l2-cache {
 			      compatible = "arm,arch-cache";
 			      cache-level = <2>;
@@ -207,6 +217,7 @@
 			cache-size = <0x20000>;
 			qcom,freq-domain = <&cpufreq_hw 1 4>;
 			next-level-cache = <&L2_7>;
+			#cooling-cells = <2>;
 			L2_7: l2-cache {
 			      compatible = "arm,arch-cache";
 			      cache-level = <2>;
@@ -679,6 +690,12 @@
 			apps_bcm_voter: bcm_voter {
 				compatible = "qcom,bcm-voter";
 			};
+
+			dcvs_fp: qcom,dcvs-fp {
+				compatible = "qcom,dcvs-fp";
+				qcom,ddr-bcm-name = "MC4";
+				qcom,llcc-bcm-name = "SH5";
+			};
 		};
 	};
 
@@ -847,6 +864,16 @@
 		qcom,vmid-cp-camera-preview-ro;
 	};
 
+	qcom,mem-buf {
+		compatible = "qcom,mem-buf";
+		qcom,mem-buf-capabilities = "supplier";
+		qcom,vmid = <3>;
+	};
+
+	qcom,mem-buf-msgq {
+		compatible = "qcom,mem-buf-msgq";
+	};
+
 	wdog: qcom,wdt@17c10000 {
 		compatible = "qcom,msm-watchdog";
 		reg = <0x17c10000 0x1000>;
@@ -1256,6 +1283,217 @@
 		reg = <0x1fc0000 0x30000>;
 	};
 
+	llcc_pmu: llcc-pmu@9095000 {
+		compatible = "qcom,llcc-pmu-ver2";
+		reg = <0x09095000 0x300>;
+		reg-names = "lagg-base";
+	};
+
+	ddr_freq_table: ddr-freq-table {
+		qcom,freq-tbl =
+			<  200000 >,
+			<  451000 >,
+			<  547000 >,
+			<  682000 >,
+			<  768000 >,
+			< 1555000 >,
+			< 1708000 >,
+			< 2093000 >,
+			< 2736000 >,
+			< 3197000 >;
+	};
+
+	llcc_freq_table: llcc-freq-table {
+		qcom,freq-tbl =
+			<  600000 >,
+			<  806000 >,
+			<  933000 >,
+			< 1066000 >;
+	};
+
+	ddrqos_freq_table: ddrqos-freq-table {
+		qcom,freq-tbl =
+			< 0 >,
+			< 1 >;
+	};
+
+	qcom_dcvs: qcom,dcvs {
+		compatible = "qcom,dcvs";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		qcom_ddr_dcvs_hw: ddr {
+			compatible = "qcom,dcvs-hw";
+			qcom,dcvs-hw-type = <0>;
+			qcom,bus-width = <4>;
+			qcom,freq-tbl = <&ddr_freq_table>;
+
+			ddr_dcvs_sp: sp {
+				compatible = "qcom,dcvs-path";
+				qcom,dcvs-path-type = <0>;
+				interconnects = <&mc_virt MASTER_LLCC
+						 &mc_virt SLAVE_EBI1>;
+			};
+
+			ddr_dcvs_fp: fp {
+				compatible = "qcom,dcvs-path";
+				qcom,dcvs-path-type = <1>;
+				qcom,fp-voter = <&dcvs_fp>;
+			};
+		};
+
+		qcom_llcc_dcvs_hw: llcc {
+			compatible = "qcom,dcvs-hw";
+			qcom,dcvs-hw-type = <1>;
+			qcom,bus-width = <16>;
+			qcom,freq-tbl = <&llcc_freq_table>;
+
+			llcc_dcvs_sp: sp {
+				compatible = "qcom,dcvs-path";
+				qcom,dcvs-path-type = <0>;
+				interconnects = <&gem_noc MASTER_APPSS_PROC
+						 &gem_noc SLAVE_LLCC>;
+			};
+
+			llcc_dcvs_fp: fp {
+				compatible = "qcom,dcvs-path";
+				qcom,dcvs-path-type = <1>;
+				qcom,fp-voter = <&dcvs_fp>;
+			};
+		};
+
+		qcom_ddrqos_dcvs_hw: ddrqos {
+			compatible = "qcom,dcvs-hw";
+			qcom,dcvs-hw-type = <3>;
+			qcom,bus-width = <1>;
+			qcom,freq-tbl = <&ddrqos_freq_table>;
+
+			ddrqos_dcvs_sp: sp {
+				compatible = "qcom,dcvs-path";
+				qcom,dcvs-path-type = <0>;
+				interconnects = <&mc_virt MASTER_LLCC
+						 &mc_virt SLAVE_EBI1>;
+			};
+		};
+	};
+
+	qcom_memlat: qcom,memlat {
+		compatible = "qcom,memlat";
+
+		ddr {
+			compatible = "qcom,memlat-grp";
+			qcom,target-dev = <&qcom_ddr_dcvs_hw>;
+			qcom,sampling-path = <&ddr_dcvs_fp>;
+			qcom,miss-ev = <0x1000>;
+
+			gold-0 {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+				qcom,cpufreq-memfreq-tbl =
+					< 1268000 1708000 >,
+					< 1632000 2093000 >,
+					< 2112000 2736000 >,
+					< 2362000 3197000 >;
+				qcom,sampling-enabled;
+			};
+
+			gold-1 {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+				qcom,cpufreq-memfreq-tbl =
+					< 1268000 1708000 >,
+					< 1632000 2093000 >,
+					< 2112000 2736000 >,
+					< 2362000 3197000 >;
+				qcom,sampling-enabled;
+			};
+
+			gold-compute {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
+				qcom,cpufreq-memfreq-tbl =
+					< 2112000 2736000 >,
+					< 2362000 3197000 >;
+				qcom,sampling-enabled;
+				qcom,compute-mon;
+			};
+		};
+
+		llcc {
+			compatible = "qcom,memlat-grp";
+			qcom,target-dev = <&qcom_llcc_dcvs_hw>;
+			qcom,sampling-path = <&llcc_dcvs_fp>;
+			qcom,miss-ev = <0x37>;
+
+			gold-0 {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+				qcom,cpufreq-memfreq-tbl =
+					< 2112000  933000 >,
+					< 2362000 1066000 >;
+				qcom,sampling-enabled;
+			};
+
+			gold-1 {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+				qcom,cpufreq-memfreq-tbl =
+					< 2112000  933000 >,
+					< 2362000 1066000 >;
+				qcom,sampling-enabled;
+			};
+
+
+			gold-compute {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
+				qcom,cpufreq-memfreq-tbl =
+					< 2112000  933000 >,
+					< 2362000 1066000 >;
+				qcom,sampling-enabled;
+				qcom,compute-mon;
+			};
+		};
+
+		ddrqos {
+			compatible = "qcom,memlat-grp";
+			qcom,target-dev = <&qcom_ddrqos_dcvs_hw>;
+			qcom,sampling-path = <&ddrqos_dcvs_sp>;
+			qcom,miss-ev = <0x1000>;
+
+			ddrqos_gold_lat: gold {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
+				qcom,cpufreq-memfreq-tbl =
+					< 1881600 0 >,
+					< 2707200 1 >;
+				qcom,sampling-enabled;
+			};
+		};
+	};
+
+	bwmon_llcc: qcom,bwmon-llcc@240B6300 {
+		compatible = "qcom,bwmon4";
+		reg = <0x90B6400 0x300>, <0x90B6300 0x200>;
+		reg-names = "base", "global_base";
+		interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,mport = <0>;
+		qcom,hw-timer-hz = <19200000>;
+		qcom,count-unit = <0x10000>;
+		qcom,target-dev = <&qcom_llcc_dcvs_hw>;
+	};
+
+	bwmon_ddr: qcom,bwmon-ddr@0x9091000 {
+		compatible = "qcom,bwmon5";
+		reg = <0x9091000 0x1000>;
+		reg-names = "base";
+		interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,hw-timer-hz = <19200000>;
+		qcom,count-unit = <0x10000>;
+		qcom,target-dev = <&qcom_ddr_dcvs_hw>;
+	};
+
 	adsp_pas: remoteproc-adsp@3000000 {
 		compatible = "qcom,lemans-adsp-pas";
 		reg = <0x3000000 0x00100>;
@@ -1898,6 +2136,11 @@
 		hwlocks = <&tcsr_mutex 3>;
 	};
 
+	mini_dump_mode {
+		compatible = "qcom,minidump";
+		status = "ok";
+	};
+
 	aoss_qmp: power-controller@c300000 {
 
 		compatible = "qcom,sm8150-aoss-qmp";
@@ -2332,6 +2575,12 @@
 	};
 };
 
+&firmware {
+	qcom_smcinvoke {
+		compatible = "qcom,smcinvoke";
+	};
+};
+
 #include "lemans-4pmic-regulators.dtsi"
 #include "lemans-gdsc.dtsi"
 #include "lemans-pinctrl.dtsi"
@@ -2562,3 +2811,5 @@
 &qupv3_se10_2uart {
 	status = "ok";
 };
+
+#include "lemans-thermal.dtsi"
diff --git a/qcom/monaco-idp-v1.dtsi b/qcom/monaco-idp-v1.dtsi
index 09e756db..2f49be9a 100755
--- a/qcom/monaco-idp-v1.dtsi
+++ b/qcom/monaco-idp-v1.dtsi
@@ -26,6 +26,15 @@
 			   "batt-volt";
 };
 
+&spmi_bus {
+	qcom,pm5100@0 {
+		pmic_lpm: qti,pmic-lpm@7200 {
+			compatible = "qti,pmic-lpm";
+			reg = <0x7200>;
+		};
+	};
+};
+
 &pm5100_gpios {
 	nfc_clk {
 		nfc_clk_default: nfc_clk_default {
diff --git a/qcom/monaco-pmic.dtsi b/qcom/monaco-pmic.dtsi
index 5d3277df..d521c3a2 100755
--- a/qcom/monaco-pmic.dtsi
+++ b/qcom/monaco-pmic.dtsi
@@ -175,8 +175,8 @@
 	status = "okay";
 	qcom,battery-data = <&monaco_batterydata>;
 	dpdm-supply = <&usb2_phy0>;
-	nvmem-cell-names = "charger_debug_mask";
-	nvmem-cells = <&charger_debug_mask>;
+	nvmem-cell-names = "charger_debug_mask", "charger_soc";
+	nvmem-cells = <&charger_debug_mask>, <&charger_soc>;
 	qcom,auto-recharge-soc = <98>;
 	qcom,suspend-input-on-debug-batt;
 	qcom,chg-term-src = <1>;
diff --git a/qcom/monaco-qupv3.dtsi b/qcom/monaco-qupv3.dtsi
index b9484188..6718240b 100755
--- a/qcom/monaco-qupv3.dtsi
+++ b/qcom/monaco-qupv3.dtsi
@@ -96,6 +96,7 @@
 			pinctrl-3 = <&qupv3_se5_default_cts>, <&qupv3_se5_default_rts>,
 			<&qupv3_se5_default_tx>, <&qupv3_se5_default_rx>;
 			qcom,wakeup-byte = <0xFD>;
+			qcom,compat-ioctl-support;
 			status = "disabled";
 		};
 
diff --git a/qcom/monaco-standalone-idp-v1.dtsi b/qcom/monaco-standalone-idp-v1.dtsi
index fe84251f..58bb3ceb 100755
--- a/qcom/monaco-standalone-idp-v1.dtsi
+++ b/qcom/monaco-standalone-idp-v1.dtsi
@@ -24,7 +24,7 @@
 	qcom,ibat-cutoff-ma = <10>;
 	qcom,vph-min-mv = <2500>;
 	qcom,iterm-ma = <20>;
-	qcom,vbatt-empty-threshold-mv = <3600>;
+	qcom,vbatt-empty-threshold-mv = <3000>;
 };
 
 &pm5100_charger {
diff --git a/qcom/monaco-standalone-wdp-v1.dtsi b/qcom/monaco-standalone-wdp-v1.dtsi
index d8a5c8c6..46a78b35 100755
--- a/qcom/monaco-standalone-wdp-v1.dtsi
+++ b/qcom/monaco-standalone-wdp-v1.dtsi
@@ -1 +1,2 @@
 #include "monaco-standalone-idp-v1.dtsi"
+#include "monaco-thermal-wdp.dtsi"
diff --git a/qcom/monaco-thermal-overlay.dtsi b/qcom/monaco-thermal-overlay.dtsi
index d9b05e60..6907536e 100755
--- a/qcom/monaco-thermal-overlay.dtsi
+++ b/qcom/monaco-thermal-overlay.dtsi
@@ -5,9 +5,7 @@
 		cooling-maps {
 			trip0_cpu0 {
 				trip = <&pm5100_trip0>;
-				cooling-device =
-					<&CPU0 (THERMAL_MAX_LIMIT-2)
-						(THERMAL_MAX_LIMIT-2)>;
+				cooling-device = <&CPU0 1 1>;
 			};
 
 			trip1_cpu2 {
@@ -26,9 +24,7 @@
 		cooling-maps {
 			cpu0_cdev {
 				trip = <&bcl_lvl0>;
-				cooling-device =
-					<&CPU0 (THERMAL_MAX_LIMIT-1)
-						(THERMAL_MAX_LIMIT-1)>;
+				cooling-device = <&CPU0 2 2>;
 			};
 
 			cpu2_cdev {
@@ -43,8 +39,7 @@
 
 			gpu_cdev {
 				trip = <&bcl_lvl0>;
-				cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-2)
-							(THERMAL_MAX_LIMIT-2)>;
+				cooling-device = <&msm_gpu 2 2>;
 			};
 		};
 	};
@@ -53,9 +48,7 @@
 		cooling-maps {
 			cpu0_cdev {
 				trip = <&bcl_lvl1>;
-				cooling-device =
-					<&CPU0 (THERMAL_MAX_LIMIT-1)
-						(THERMAL_MAX_LIMIT-1)>;
+				cooling-device = <&CPU0 2 2>;
 			};
 
 			cpu1_cdev {
@@ -65,8 +58,7 @@
 
 			gpu_cdev {
 				trip = <&bcl_lvl1>;
-				cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
-							THERMAL_MAX_LIMIT>;
+				cooling-device = <&msm_gpu 4 THERMAL_NO_LIMIT>;
 			};
 		};
 	};
@@ -81,9 +73,7 @@
 		cooling-maps {
 			soc_cpu0 {
 				trip = <&socd_trip>;
-				cooling-device =
-					<&CPU0 (THERMAL_MAX_LIMIT-2)
-						(THERMAL_MAX_LIMIT-2)>;
+				cooling-device = <&CPU0 1 1>;
 			};
 
 			soc_cpu2 {
@@ -98,8 +88,7 @@
 
 			gpu_cdev {
 				trip = <&socd_trip>;
-				cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-2)
-							(THERMAL_MAX_LIMIT-2)>;
+				cooling-device = <&msm_gpu 2 2>;
 			};
 		};
 	};
diff --git a/qcom/monaco-thermal-wdp.dtsi b/qcom/monaco-thermal-wdp.dtsi
new file mode 100755
index 00000000..de020434
--- /dev/null
+++ b/qcom/monaco-thermal-wdp.dtsi
@@ -0,0 +1,154 @@
+&pm5100_adc {
+	pm5100_pa_therm_0 {
+		reg = <PM5100_ADC5_GEN3_AMUX5_THM_100K_PU>;
+	};
+
+	pm5100_quiet_therm {
+		status = "disabled";
+	};
+
+	pm5100_cam_therm {
+		reg = <PM5100_ADC5_GEN3_AMUX4_THM_100K_PU>;
+		label = "pm5100_cam_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		qcom,adc-tm-type = <1>;
+	};
+};
+
+&thermal_zones {
+	quiet-therm {
+		status = "disabled";
+	};
+
+	pa-therm0 {
+		polling-delay-passive = <1000>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm5100_adc PM5100_ADC5_GEN3_AMUX5_THM_100K_PU>;
+		trips {
+			pa_bat_trip0: pa-bat-trip0 {
+				temperature = <42000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			pa_silver_trip: pa-silver-trip {
+				temperature = <44000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			pa_cx_trip: pa-cx-trip {
+				temperature = <44000>;
+				hysteresis = <4000>;
+				type = "passive";
+			};
+
+			pa_bat_trip1: pa-bat-trip1 {
+				temperature = <45000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			pa_gpu_trip: pa-gpu-trip {
+				temperature = <48000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			pa_bat_trip2: pa-bat-trip2 {
+				temperature = <48000>;
+				hysteresis = <4000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			pa_silver_cdev {
+				trip = <&pa_silver_trip>;
+				/* throttle to 864000KHz */
+				cooling-device = <&CPU0 0 2>;
+			};
+
+			pa_gpu_cdev {
+				trip = <&pa_gpu_trip>;
+				/* throttle to 700000000Hz */
+				cooling-device = <&msm_gpu 0 3>;
+			};
+
+			queit_cdev2 {
+				trip = <&pa_cx_trip>;
+				cooling-device = <&cpu2_pause 1 1>;
+			};
+
+			pa_cdev3 {
+				trip = <&pa_cx_trip>;
+				cooling-device = <&cpu3_pause 1 1>;
+			};
+
+			pa_cdev4 {
+				trip = <&pa_bat_trip0>;
+				cooling-device = <&pm5100_charger 7 7>;
+			};
+
+			pa_cdev5 {
+				trip = <&pa_bat_trip1>;
+				cooling-device = <&pm5100_charger 9 9>;
+			};
+
+			pa_cdev6 {
+				trip = <&pa_bat_trip2>;
+				cooling-device = <&pm5100_charger 15 15>;
+			};
+		};
+	};
+
+	cam-therm {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm5100_adc PM5100_ADC5_GEN3_AMUX4_THM_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			cam_therm0_trip0: cam-therm0-trip0 {
+				temperature = <42000>;
+				hysteresis = <2000>;
+				type = "passive";
+			};
+
+			cam_therm0_trip1: cam-therm0-trip1 {
+				temperature = <44000>;
+				hysteresis = <2000>;
+				type = "passive";
+			};
+
+			cam_therm0_trip2: cam-therm0-trip2 {
+				temperature = <52000>;
+				hysteresis = <2000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cam_therm0_cdev0:cam-therm0-cdev0 {
+				trip = <&cam_therm0_trip0>;
+				cooling-device = <&modem_pa 1 1>;
+			};
+
+			cam_therm0_cdev1:cam-therm0-cdev1 {
+				trip = <&cam_therm0_trip1>;
+				cooling-device = <&modem_pa 2 2>;
+			};
+
+			cam_therm0_cdev2:cam-therm0-cdev2 {
+				trip = <&cam_therm0_trip2>;
+				cooling-device = <&modem_pa 3 3>;
+			};
+		};
+	};
+};
diff --git a/qcom/monaco-thermal.dtsi b/qcom/monaco-thermal.dtsi
index b87f297a..d106aea0 100755
--- a/qcom/monaco-thermal.dtsi
+++ b/qcom/monaco-thermal.dtsi
@@ -260,7 +260,7 @@
 	};
 
 	mdm-0 {
-		polling-delay-passive = <0>;
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
 		thermal-sensors = <&tsens0 4>;
 		trips {
@@ -297,7 +297,7 @@
 	};
 
 	mdm-1 {
-		polling-delay-passive = <0>;
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
 		thermal-sensors = <&tsens0 5>;
 		trips {
@@ -334,7 +334,7 @@
 	};
 
 	gpu {
-		polling-delay-passive = <0>;
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
 		thermal-sensors = <&tsens0 6>;
 		trips {
diff --git a/qcom/monaco-wdp-v1.dtsi b/qcom/monaco-wdp-v1.dtsi
index e90da247..9acc1ace 100755
--- a/qcom/monaco-wdp-v1.dtsi
+++ b/qcom/monaco-wdp-v1.dtsi
@@ -1,5 +1,5 @@
 #include "monaco-idp-v1.dtsi"
-
+#include "monaco-thermal-wdp.dtsi"
 
 
 
diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi
index a9ac408c..360e59f9 100755
--- a/qcom/monaco.dtsi
+++ b/qcom/monaco.dtsi
@@ -183,7 +183,7 @@
 	soc: soc { };
 
 	chosen {
-		bootargs = "console=ttyMSM0,115200n8 loglevel=6 kpti=off log_buf_len=256K kernel.panic_on_rcu_stall=1 msm_rtb.filter=0x237 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops fw_devlink.strict=1 allow_mismatched_32bit_el0 printk.console_no_auto_verbose=1 irqaffinity=0-2";
+		bootargs = "console=ttyMSM0,115200n8 loglevel=6 kpti=off log_buf_len=256K kernel.panic_on_rcu_stall=1 msm_rtb.filter=0x237 rcupdate.rcu_expedited=1 rcu_nocbs=0-3 ftrace_dump_on_oops fw_devlink.strict=1 allow_mismatched_32bit_el0 printk.console_no_auto_verbose=1 irqaffinity=0-2 cpufreq.default_governor=performance";
 	};
 
 	reserved-memory {
@@ -1010,7 +1010,7 @@
 		memory-region = <&pil_adsp_mem>;
 
 		/* Inputs from lpass */
-		interrupts-extended = <&intc 0 282 IRQ_TYPE_LEVEL_HIGH>,
+		interrupts-extended = <&intc 0 282 IRQ_TYPE_EDGE_RISING>,
 				      <&adsp_smp2p_in 0 0>,
 				      <&adsp_smp2p_in 2 0>,
 				      <&adsp_smp2p_in 1 0>,
@@ -1604,6 +1604,23 @@
 			qcom,glinkpkt-ch-name = "slate_bt_app";
 			qcom,glinkpkt-dev-name = "glink_pkt_slate_bt_app";
 		};
+
+		qcom,glinkpkt-slate-dfu {
+			qcom,glinkpkt-edge = "slate";
+			qcom,glinkpkt-ch-name = "slate-dfu";
+			qcom,glinkpkt-dev-name = "glink_pkt_slate_dfu";
+		};
+		qcom,glinkpkt-ss-bt-ctrl {
+			qcom,glinkpkt-edge = "slate";
+			qcom,glinkpkt-ch-name = "ss_bt_ctrl";
+			qcom,glinkpkt-dev-name = "glink_pkt_ss_bt_ctrl";
+			};
+
+		qcom,glinkpkt-ss-bt-data {
+			qcom,glinkpkt-edge = "slate";
+			qcom,glinkpkt-ch-name = "ss_bt_data";
+			qcom,glinkpkt-dev-name = "glink_pkt_ss_bt_data";
+			};
 	};
 
 	jtag_mm0: jtagmm@9040000 {
@@ -1958,6 +1975,8 @@
 
 	qcom,power-state {
 		compatible = "qcom,power-state";
+		qcom,subsys-name = "adsp", "modem";
+		qcom,rproc-handle = <&adsp_pas>, <&modem_pas>;
 	};
 
 	slimbam: bamdma@A584000 {
diff --git a/qcom/monaco_auto-pinctrl.dtsi b/qcom/monaco_auto-pinctrl.dtsi
new file mode 100755
index 00000000..4d1f6044
--- /dev/null
+++ b/qcom/monaco_auto-pinctrl.dtsi
@@ -0,0 +1,3 @@
+&tlmm {
+
+};
diff --git a/qcom/monaco_auto-rumi-overlay.dts b/qcom/monaco_auto-rumi-overlay.dts
new file mode 100755
index 00000000..157684f8
--- /dev/null
+++ b/qcom/monaco_auto-rumi-overlay.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+/plugin/;
+
+#include "monaco_auto-rumi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. MONACO AUTO RUMI";
+	compatible = "qcom,monaco_auto", "qcom,rumi", "qcom,monaco_auto-rumi";
+	qcom,board-id = <0x1000F 0>;
+};
diff --git a/qcom/monaco_auto-rumi.dts b/qcom/monaco_auto-rumi.dts
new file mode 100755
index 00000000..dba52a47
--- /dev/null
+++ b/qcom/monaco_auto-rumi.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+/memreserve/ 0xc0000000 0x00000100;
+
+#include "monaco_auto.dtsi"
+#include "monaco_auto-rumi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. MONACO AUTO RUMI";
+	compatible = "qcom,monaco_auto", "qcom,rumi", "qcom,monaco_auto-rumi";
+	qcom,board-id = <15 0>;
+};
diff --git a/qcom/monaco_auto-rumi.dtsi b/qcom/monaco_auto-rumi.dtsi
new file mode 100755
index 00000000..ed634a58
--- /dev/null
+++ b/qcom/monaco_auto-rumi.dtsi
@@ -0,0 +1,11 @@
+
+&arch_timer {
+	clock-frequency = <500000>;
+};
+
+&memtimer {
+	clock-frequency = <500000>;
+};
+
+&soc {
+};
diff --git a/qcom/monaco_auto.dts b/qcom/monaco_auto.dts
new file mode 100755
index 00000000..4a900c4d
--- /dev/null
+++ b/qcom/monaco_auto.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "monaco_auto.dtsi"
+/ {
+	model = "Qualcomm Technologies, Inc. Monaco AUTO";
+	compatible = "qcom,monaco_auto";
+	qcom,board-id = <0 0>;
+};
+
diff --git a/qcom/monaco_auto.dtsi b/qcom/monaco_auto.dtsi
new file mode 100755
index 00000000..821d6eef
--- /dev/null
+++ b/qcom/monaco_auto.dtsi
@@ -0,0 +1,299 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	model = "Qualcomm Technologies, Inc. Monaco AUTO";
+	compatible = "qcom,monaco_auto";
+	qcom,msm-id = <532 0x10000>;
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	memory { device_type = "memory"; reg = <0 0 0 0>; };
+
+	reserved_memory: reserved-memory { };
+
+	chosen: chosen { };
+
+	soc: soc { };
+
+	firmware: firmware { };
+
+	aliases {
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x0>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0xc0000000>;
+			next-level-cache = <&L2_0>;
+			L2_0: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+
+				L3_0: l3-cache {
+				      compatible = "arm,arch-cache";
+				      cache-level = <3>;
+				};
+			};
+		};
+
+		CPU1: cpu@100 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x100>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0xc0000000>;
+			next-level-cache = <&L2_1>;
+			L2_1: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU2: cpu@200 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x200>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0xc0000000>;
+			next-level-cache = <&L2_2>;
+			L2_2: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU3: cpu@300 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x300>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0xc0000000>;
+			next-level-cache = <&L2_3>;
+			L2_3: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU4: cpu@10000 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x10000>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0xc0000000>;
+			next-level-cache = <&L2_4>;
+			L2_4: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_1>;
+				L3_1: l3-cache {
+				      compatible = "arm,arch-cache";
+				      cache-level = <3>;
+				};
+
+			};
+		};
+
+		CPU5: cpu@10100 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x10100>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0xc0000000>;
+			next-level-cache = <&L2_5>;
+			L2_5: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_1>;
+			};
+		};
+
+		CPU6: cpu@10200 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x10200>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0xc0000000>;
+			next-level-cache = <&L2_6>;
+			L2_6: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_1>;
+			};
+		};
+
+		CPU7: cpu@10300 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x10300>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0xc0000000>;
+			next-level-cache = <&L2_7>;
+			L2_7: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_1>;
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+
+				core1 {
+					cpu = <&CPU1>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&CPU2>;
+				};
+
+				core1 {
+					cpu = <&CPU3>;
+				};
+			};
+
+			cluster2 {
+				core0 {
+					cpu = <&CPU4>;
+				};
+
+				core1 {
+					cpu = <&CPU5>;
+				};
+
+				core2 {
+					cpu = <&CPU6>;
+				};
+
+				core3 {
+					cpu = <&CPU7>;
+				};
+			};
+		};
+	};
+};
+
+&firmware {
+};
+
+&reserved_memory {
+};
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0 0 0 0xffffffff>;
+	compatible = "simple-bus";
+
+	tlmm: pinctrl@f000000 {
+		compatible = "qcom,monaco_auto-pinctrl";
+		reg = <0xf000000 0x1000000>;
+		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	intc: interrupt-controller@17a00000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		#redistributor-regions = <1>;
+		redistributor-stride = <0x0 0x20000>;
+		reg = <0x17a00000 0x10000>,     /* GICD */
+		      <0x17a60000 0x100000>;    /* GICR * 8 */
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <19200000>;
+	};
+
+	memtimer: timer@17c20000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		compatible = "arm,armv7-timer-mem";
+		reg = <0x17c20000 0x1000>;
+		clock-frequency = <19200000>;
+
+		frame@17c21000 {
+			frame-number = <0>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17c21000 0x1000>,
+			      <0x17c22000 0x1000>;
+		};
+
+		frame@17c23000 {
+			frame-number = <1>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17c23000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17c25000 {
+			frame-number = <2>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17c25000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17c27000 {
+			frame-number = <3>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17c27000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17c29000 {
+			frame-number = <4>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17c29000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17c2b000 {
+			frame-number = <5>;
+			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17c2b000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17c2d000 {
+			frame-number = <6>;
+			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17c2d000 0x1000>;
+			status = "disabled";
+		};
+	};
+
+};
+
+#include "monaco_auto-pinctrl.dtsi"
diff --git a/qcom/msm-arm-smmu-bengal.dtsi b/qcom/msm-arm-smmu-bengal.dtsi
index a423ad7c..ab362465 100755
--- a/qcom/msm-arm-smmu-bengal.dtsi
+++ b/qcom/msm-arm-smmu-bengal.dtsi
@@ -3,7 +3,7 @@
 &soc {
 	kgsl_smmu: kgsl-smmu@0x59a0000 {
 		status = "okay";
-		compatible = "qcom,qsmmu-v500";
+		compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu";
 		reg = <0x59a0000 0x10000>,
 			<0x59c2000 0x20>;
 		reg-names = "base", "tcu-base";
@@ -13,6 +13,8 @@
 		qcom,testbus-version = <1>;
 		qcom,no-dynamic-asid;
 		qcom,use-3-lvl-tables;
+		qcom,num-context-banks-override = <0x05>;
+		qcom,num-smr-override = <0x04>;
 		#global-interrupts = <1>;
 		qcom,regulator-names = "vdd";
 		vdd-supply = <&gpu_cx_gdsc>;
@@ -60,6 +62,8 @@
 		#iommu-cells = <2>;
 		qcom,skip-init;
 		qcom,use-3-lvl-tables;
+		qcom,num-context-banks-override = <0x30>;
+		qcom,num-smr-override = <0x32>;
 		qcom,handoff-smrs = <0x420 0x2>;
 		#global-interrupts = <1>;
 		#size-cells = <1>;
diff --git a/qcom/msm-arm-smmu-kona.dtsi b/qcom/msm-arm-smmu-kona.dtsi
index 513a697e..d120810c 100755
--- a/qcom/msm-arm-smmu-kona.dtsi
+++ b/qcom/msm-arm-smmu-kona.dtsi
@@ -2,7 +2,7 @@
 
 &soc {
 	kgsl_smmu: kgsl-smmu@3da0000 {
-		compatible = "qcom,qsmmu-v500";
+		compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu";
 		reg = <0x3DA0000 0x10000>,
 			<0x3DC2000 0x20>;
 		reg-names = "base", "tcu-base";
@@ -13,7 +13,6 @@
 		#size-cells = <1>;
 		#address-cells = <1>;
 		ranges;
-		dma-coherent;
 		qcom,regulator-names = "vdd";
 		vdd-supply = <&gpu_cx_gdsc>;
 
@@ -73,7 +72,6 @@
 		#size-cells = <1>;
 		#address-cells = <1>;
 		ranges;
-		dma-coherent;
 		interrupts =	<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
@@ -333,31 +331,38 @@
 	iommu_test_device {
 		compatible = "qcom,iommu-debug-test";
 
-		kgsl_iommu_test_device {
+		usecase0_apps {
 			compatible = "qcom,iommu-debug-usecase";
-			iommus = <&kgsl_smmu 0x7 0>;
-			qcom,iommu-dma = "disabled";
+			iommus = <&apps_smmu 0x23 0x0>;
 		};
 
-		kgsl_iommu_coherent_test_device {
-			status = "disabled";
+		usecase1_apps_fastmap {
 			compatible = "qcom,iommu-debug-usecase";
-			iommus = <&kgsl_smmu 0x9 0>;
-			qcom,iommu-dma = "disabled";
-			dma-coherent;
+			iommus = <&apps_smmu 0x23 0x0>;
+			qcom,iommu-dma = "fastmap";
 		};
 
-		apps_iommu_test_device {
+		usecase2_apps_atomic {
 			compatible = "qcom,iommu-debug-usecase";
-			iommus = <&apps_smmu 0x21 0>;
-			qcom,iommu-dma = "disabled";
+			iommus = <&apps_smmu 0x23 0x0>;
+			qcom,iommu-dma = "atomic";
 		};
 
-		apps_iommu_coherent_test_device {
+		usecase3_apps_dma {
 			compatible = "qcom,iommu-debug-usecase";
-			iommus = <&apps_smmu 0x23 0>;
-			qcom,iommu-dma = "disabled";
+			iommus = <&apps_smmu 0x23 0x0>;
 			dma-coherent;
 		};
+
+		usecase4_apps_secure {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x23 0x0>;
+			qcom,iommu-vmid = <0xa>; /* VMID_CP_PIXEL */
+		};
+
+		usecase5_kgsl {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&kgsl_smmu 0x7 0x0>;
+		};
 	};
 };
diff --git a/qcom/msm-arm-smmu-monaco.dtsi b/qcom/msm-arm-smmu-monaco.dtsi
index cb34461f..ff853465 100755
--- a/qcom/msm-arm-smmu-monaco.dtsi
+++ b/qcom/msm-arm-smmu-monaco.dtsi
@@ -4,13 +4,15 @@
 &soc {
 	kgsl_smmu: kgsl-smmu@0x59a0000 {
 		status = "okay";
-		compatible = "qcom,qsmmu-v500";
+		compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu";
 		reg = <0x59a0000 0x10000>,
 			<0x59da000 0x20>;
 		reg-names = "base", "tcu-base";
 		#iommu-cells = <2>;
 		qcom,skip-init;
 		qcom,use-3-lvl-tables;
+		qcom,num-context-banks-override = <0x05>;
+		qcom,num-smr-override = <0x04>;
 		#global-interrupts = <1>;
 		qcom,regulator-names = "vdd";
 		vdd-supply = <&gpu_cx_gdsc>;
@@ -57,6 +59,8 @@
 				#iommu-cells = <2>;
 				qcom,skip-init;
 				qcom,use-3-lvl-tables;
+				qcom,num-context-banks-override = <0x32>;
+				qcom,num-smr-override = <0x28>;
 				qcom,handoff-smrs = <0x420 0x2>;
 				#global-interrupts = <1>;
 				#size-cells = <1>;
diff --git a/qcom/pm5100.dtsi b/qcom/pm5100.dtsi
index a4f3b005..15c1a55a 100755
--- a/qcom/pm5100.dtsi
+++ b/qcom/pm5100.dtsi
@@ -313,6 +313,14 @@
 			reg = <0x7600>;
 		};
 
+		pm5100_sdam_8: sdam@7700 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x7700>;
+			charger_soc: charger_soc@47 {
+				reg = <0x65 0x2>;
+			};
+		};
+
 		pm5100_sdam_22: sdam@8500 {
 			compatible = "qcom,spmi-sdam";
 			reg = <0x8500>;
@@ -333,8 +341,9 @@
 			compatible = "qcom,qbg";
 			#address-cells = <1>;
 			reg = <0x4f00>;
-			interrupt-names = "qbg-sdam";
-			interrupts = <0x0 0x76 0x1 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "qbg-sdam", "qbg-vbatt-empty";
+			interrupts = <0x0 0x76 0x1 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x4F 0x1 IRQ_TYPE_EDGE_RISING>;
 			qcom,num-data-sdams = <5>;
 			qcom,sdam-base = <0x7600>;
 			qcom,adc-cmn-wb-base = <0x3000>;
diff --git a/qcom/pm8009.dtsi b/qcom/pm8009.dtsi
index 3e15fdbd..188f6888 100755
--- a/qcom/pm8009.dtsi
+++ b/qcom/pm8009.dtsi
@@ -28,7 +28,7 @@
 
 		pm8009_gpios: pinctrl@c000 {
 			status = "okay";
-			compatible = "qcom,pm8150b-gpio";
+			compatible = "qcom,pm8009-gpio";
 			reg = <0xc000 0x400>;
 			interrupts = <0xa 0xc0 0 IRQ_TYPE_NONE>,
 				     <0xa 0xc1 0 IRQ_TYPE_NONE>,
diff --git a/qcom/pm8150.dtsi b/qcom/pm8150.dtsi
index 9ce9c1db..c2af308e 100755
--- a/qcom/pm8150.dtsi
+++ b/qcom/pm8150.dtsi
@@ -160,7 +160,6 @@
 	pm8150_temp_alarm: pm8150_tz {
 		polling-delay-passive = <100>;
 		polling-delay = <0>;
-		thermal-governor = "step_wise";
 		thermal-sensors = <&pm8150_tz>;
 
 		trips {
diff --git a/qcom/pm8150b.dtsi b/qcom/pm8150b.dtsi
index 3bee9948..cbe3588c 100755
--- a/qcom/pm8150b.dtsi
+++ b/qcom/pm8150b.dtsi
@@ -593,9 +593,7 @@
 	pm8150b_temp_alarm: pm8150b_tz {
 		polling-delay-passive = <100>;
 		polling-delay = <0>;
-		thermal-governor = "step_wise";
 		thermal-sensors = <&pm8150b_tz>;
-		wake-capable-sensor;
 
 		trips {
 			pm8150b_trip0: trip0 {
@@ -621,9 +619,7 @@
 	pm8150b-ibat-lvl0 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "step_wise";
 		thermal-sensors = <&pm8150b_bcl 0>;
-		wake-capable-sensor;
 
 		trips {
 			ibat_lvl0:ibat-lvl0 {
@@ -637,9 +633,7 @@
 	pm8150b-ibat-lvl1 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "step_wise";
 		thermal-sensors = <&pm8150b_bcl 1>;
-		wake-capable-sensor;
 
 		trips {
 			ibat_lvl1:ibat-lvl1 {
@@ -650,65 +644,24 @@
 		};
 	};
 
-	pm8150b-vbat-lvl0 {
-		polling-delay-passive = <0>;
-		polling-delay = <0>;
-		thermal-governor = "low_limits_cap";
-		thermal-sensors = <&pm8150b_bcl 2>;
-		tracks-low;
-		wake-capable-sensor;
-
-		trips {
-			vbat_lvl0: vbat-lvl0 {
-				temperature = <3000>;
-				hysteresis = <200>;
-				type = "passive";
-			};
-		};
-	};
-
-	pm8150b-vbat-lvl1 {
-		polling-delay-passive = <0>;
+	pm8150b-bcl-lvl0 {
+		polling-delay-passive = <100>;
 		polling-delay = <0>;
-		thermal-governor = "low_limits_cap";
-		thermal-sensors = <&pm8150b_bcl 3>;
-		tracks-low;
-		wake-capable-sensor;
+		thermal-sensors = <&pm8150b_bcl 5>;
 
 		trips {
-			vbat_lvl1:vbat-lvl1 {
-				temperature = <2800>;
-				hysteresis = <200>;
+			thermal-engine-trip {
+				temperature = <100>;
+				hysteresis = <0>;
 				type = "passive";
 			};
-		};
-	};
-
-	pm8150b-vbat-lvl2 {
-		polling-delay-passive = <0>;
-		polling-delay = <0>;
-		thermal-governor = "low_limits_cap";
-		thermal-sensors = <&pm8150b_bcl 4>;
-		tracks-low;
-		wake-capable-sensor;
 
-		trips {
-			vbat_lvl2:vbat-lvl2 {
-				temperature = <2600>;
-				hysteresis = <200>;
+			thermal-hal-trip {
+				temperature = <100>;
+				hysteresis = <0>;
 				type = "passive";
 			};
-		};
-	};
-
-	pm8150b-bcl-lvl0 {
-		polling-delay-passive = <100>;
-		polling-delay = <0>;
-		thermal-governor = "step_wise";
-		thermal-sensors = <&pm8150b_bcl 5>;
-		wake-capable-sensor;
 
-		trips {
 			b_bcl_lvl0: b-bcl-lvl0 {
 				temperature = <1>;
 				hysteresis = <1>;
@@ -720,11 +673,21 @@
 	pm8150b-bcl-lvl1 {
 		polling-delay-passive = <100>;
 		polling-delay = <0>;
-		thermal-governor = "step_wise";
 		thermal-sensors = <&pm8150b_bcl 6>;
-		wake-capable-sensor;
 
 		trips {
+			thermal-engine-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			thermal-hal-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
 			b_bcl_lvl1: b-bcl-lvl1 {
 				temperature = <1>;
 				hysteresis = <1>;
@@ -736,11 +699,21 @@
 	pm8150b-bcl-lvl2 {
 		polling-delay-passive = <100>;
 		polling-delay = <0>;
-		thermal-governor = "step_wise";
 		thermal-sensors = <&pm8150b_bcl 7>;
-		wake-capable-sensor;
 
 		trips {
+			thermal-engine-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			thermal-hal-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
 			b_bcl_lvl2: b-bcl-lvl2 {
 				temperature = <1>;
 				hysteresis = <1>;
@@ -749,17 +722,26 @@
 		};
 	};
 
-	soc {
+	socd {
 		polling-delay-passive = <100>;
 		polling-delay = <0>;
-		thermal-governor = "low_limits_cap";
 		thermal-sensors = <&bcl_soc>;
-		tracks-low;
-		wake-capable-sensor;
 
 		trips {
-			soc_trip:soc-trip {
-				temperature = <10>;
+			thermal-engine-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			thermal-hal-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			socd_trip:socd-trip {
+				temperature = <90>;
 				hysteresis = <0>;
 				type = "passive";
 			};
diff --git a/qcom/pm8150l.dtsi b/qcom/pm8150l.dtsi
index 13132be8..c786d31d 100755
--- a/qcom/pm8150l.dtsi
+++ b/qcom/pm8150l.dtsi
@@ -470,9 +470,7 @@
 	pm8150l_temp_alarm: pm8150l_tz {
 		polling-delay-passive = <100>;
 		polling-delay = <0>;
-		thermal-governor = "step_wise";
 		thermal-sensors = <&pm8150l_tz>;
-		wake-capable-sensor;
 
 		trips {
 			trip0 {
@@ -495,65 +493,24 @@
 		};
 	};
 
-	pm8150l-vph-lvl0 {
-		polling-delay-passive = <0>;
-		polling-delay = <0>;
-		thermal-governor = "low_limits_cap";
-		thermal-sensors = <&pm8150l_bcl 2>;
-		tracks-low;
-		wake-capable-sensor;
-
-		trips {
-			vph_lvl0: vph-lvl0 {
-				temperature = <3000>;
-				hysteresis = <200>;
-				type = "passive";
-			};
-		};
-	};
-
-	pm8150l-vph-lvl1 {
-		polling-delay-passive = <0>;
+	pm8150l-bcl-lvl0 {
+		polling-delay-passive = <100>;
 		polling-delay = <0>;
-		thermal-governor = "low_limits_cap";
-		thermal-sensors = <&pm8150l_bcl 3>;
-		tracks-low;
-		wake-capable-sensor;
+		thermal-sensors = <&pm8150l_bcl 5>;
 
 		trips {
-			vph_lvl1:vph-lvl1 {
-				temperature = <2750>;
-				hysteresis = <200>;
+			thermal-engine-trip {
+				temperature = <100>;
+				hysteresis = <0>;
 				type = "passive";
 			};
-		};
-	};
-
-	pm8150l-vph-lvl2 {
-		polling-delay-passive = <0>;
-		polling-delay = <0>;
-		thermal-governor = "low_limits_cap";
-		thermal-sensors = <&pm8150l_bcl 4>;
-		tracks-low;
-		wake-capable-sensor;
 
-		trips {
-			vph_lvl2:vph-lvl2 {
-				temperature = <2500>;
-				hysteresis = <200>;
+			thermal-hal-trip {
+				temperature = <100>;
+				hysteresis = <0>;
 				type = "passive";
 			};
-		};
-	};
-
-	pm8150l-bcl-lvl0 {
-		polling-delay-passive = <100>;
-		polling-delay = <0>;
-		thermal-governor = "step_wise";
-		thermal-sensors = <&pm8150l_bcl 5>;
-		wake-capable-sensor;
 
-		trips {
 			l_bcl_lvl0: l-bcl-lvl0 {
 				temperature = <1>;
 				hysteresis = <1>;
@@ -565,11 +522,21 @@
 	pm8150l-bcl-lvl1 {
 		polling-delay-passive = <100>;
 		polling-delay = <0>;
-		thermal-governor = "step_wise";
 		thermal-sensors = <&pm8150l_bcl 6>;
-		wake-capable-sensor;
 
 		trips {
+			thermal-engine-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			thermal-hal-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
 			l_bcl_lvl1: l-bcl-lvl1 {
 				temperature = <1>;
 				hysteresis = <1>;
@@ -581,11 +548,21 @@
 	pm8150l-bcl-lvl2 {
 		polling-delay-passive = <100>;
 		polling-delay = <0>;
-		thermal-governor = "step_wise";
 		thermal-sensors = <&pm8150l_bcl 7>;
-		wake-capable-sensor;
 
 		trips {
+			thermal-engine-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			thermal-hal-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
 			l_bcl_lvl2: l-bcl-lvl2 {
 				temperature = <1>;
 				hysteresis = <1>;
diff --git a/qcom/pm8550b.dtsi b/qcom/pm8550b.dtsi
index f8091848..f26f098f 100755
--- a/qcom/pm8550b.dtsi
+++ b/qcom/pm8550b.dtsi
@@ -156,6 +156,105 @@
 				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
 				qcom,wf-auto-res-disable;
 			};
+
+			primitive_0 {
+				/* NOOP */
+				qcom,primitive-id = <0>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0  S_PERIOD_T_LRA  0>,
+							<0  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			primitive_1 {
+				/* CLICK */
+				qcom,primitive-id = <1>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x0ff  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			primitive_2 {
+				/* THUD */
+				qcom,primitive-id = <2>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x0ff  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			primitive_3 {
+				/* SPIN */
+				qcom,primitive-id = <3>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x0ff  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			primitive_4 {
+				/* QUICK_RISE */
+				qcom,primitive-id = <4>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x0ff  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			primitive_5 {
+				/* SLOW_RISE */
+				qcom,primitive-id = <5>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x0ff  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			primitive_6 {
+				/* QUICK_FALL */
+				qcom,primitive-id = <6>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x0ff  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			primitive_7 {
+				/* LIGHT_TICK */
+				qcom,primitive-id = <7>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x0ff  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			primitive_8 {
+				/* LOW_TICK */
+				qcom,primitive-id = <8>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x0ff  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
 		};
 
 		pm8550b_bcl: bcl@4700 {
diff --git a/qcom/pm8775.dtsi b/qcom/pm8775.dtsi
index 766ac923..42752196 100755
--- a/qcom/pm8775.dtsi
+++ b/qcom/pm8775.dtsi
@@ -35,6 +35,7 @@
 			#size-cells = <0>;
 			interrupts = <0x0 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
 			interrupt-names = "adc-sdam0";
+			#thermal-sensor-cells = <1>;
 			#io-channel-cells = <1>;
 			status = "disabled";
 
diff --git a/qcom/pms405-rpm-regulator.dtsi b/qcom/pms405-rpm-regulator.dtsi
new file mode 100755
index 00000000..690da0c4
--- /dev/null
+++ b/qcom/pms405-rpm-regulator.dtsi
@@ -0,0 +1,305 @@
+&rpm_bus {
+	/* VDD_MX/CX supply */
+	rpm-regulator-smpa1 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "rwmx";
+		qcom,resource-id = <0>;
+		qcom,regulator-type = <1>;
+		qcom,hpm-min-load = <100000>;
+		status = "disabled";
+
+		regulator-s1 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pms405_s1";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	/* VDD_LPI_CX supply */
+	rpm-regulator-smpa2 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "rwlc";
+		qcom,resource-id = <0>;
+		qcom,regulator-type = <1>;
+		qcom,hpm-min-load = <100000>;
+		status = "disabled";
+
+		regulator-s2 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pms405_s2";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-smpa3 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "smpa";
+		qcom,resource-id = <3>;
+		qcom,regulator-type = <1>;
+		qcom,hpm-min-load = <100000>;
+		status = "disabled";
+
+		regulator-s3 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pms405_s3";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-smpa4 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "smpa";
+		qcom,resource-id = <4>;
+		qcom,regulator-type = <1>;
+		qcom,hpm-min-load = <100000>;
+		status = "disabled";
+
+		regulator-s4 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pms405_s4";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-smpa5 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "smpa";
+		qcom,resource-id = <5>;
+		qcom,regulator-type = <1>;
+		qcom,hpm-min-load = <100000>;
+		status = "disabled";
+
+		regulator-s5 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pms405_s5";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa1 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <1>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic4-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l1 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pms405_l1";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa2 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <2>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic4-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l2 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pms405_l2";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa3 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <3>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic4-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l3 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pms405_l3";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa4 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <4>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic4-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l4 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pms405_l4";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa5 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <5>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic4-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l5 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pms405_l5";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa6 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <6>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic4-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l6 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pms405_l6";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa7 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <7>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic4-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l7 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pms405_l7";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa8 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <8>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic4-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l8 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pms405_l8";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	/* VDD_LPI_MX supply */
+	rpm-regulator-ldoa9 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "rwlm";
+		qcom,resource-id = <0>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic4-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l9 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pms405_l9";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa10 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <10>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic4-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l10 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pms405_l10";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa11 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <11>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic4-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l11 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pms405_l11";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa12 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <12>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic4-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l12 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pms405_l12";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa13 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <13>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic4-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l13 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pms405_l13";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/qcom/pms405.dtsi b/qcom/pms405.dtsi
new file mode 100755
index 00000000..e66c7688
--- /dev/null
+++ b/qcom/pms405.dtsi
@@ -0,0 +1,148 @@
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/input/qcom,qpnp-power-on.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+	qcom,pms405@0 {
+		compatible ="qcom,spmi-pmic";
+		reg = <0 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pms405_vadc: vadc@3100 {
+			compatible = "qcom,spmi-adc-rev2";
+			reg = <0x3100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+			#io-channel-cells = <1>;
+			io-channel-ranges;
+
+			ref_gnd {
+				label = "ref_gnd";
+				reg = <ADC5_REF_GND>;
+				qcom,pre-scaling = <1 1>;
+			};
+
+			vref_1p25 {
+				label = "vref_1p25";
+				reg = <ADC5_1P25VREF>;
+				qcom,pre-scaling = <1 1>;
+			};
+
+			die_temp {
+				label = "die_temp";
+				reg = <ADC5_DIE_TEMP>;
+				qcom,pre-scaling = <1 1>;
+			};
+
+			vph_pwr {
+				label = "vph_pwr";
+				reg = <ADC5_VPH_PWR>;
+				qcom,pre-scaling = <1 3>;
+			};
+
+			xo_therm {
+				label = "xo_therm";
+				reg = <ADC5_XO_THERM_100K_PU>;
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pa_therm1 {
+				label = "pa_therm1";
+				reg = <ADC5_AMUX_THM1_100K_PU>;
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pa_therm3 {
+				label = "pa_therm3";
+				reg = <ADC5_AMUX_THM3_100K_PU>;
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
+			};
+		};
+
+		pms405_adc_tm_iio: adc_tm@3500 {
+			compatible = "qcom,spmi-adc-tm5-iio";
+			reg = <0x3500>;
+			#thermal-sensor-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			io-channels = <&pms405_vadc ADC5_XO_THERM_100K_PU>,
+					<&pms405_vadc ADC5_AMUX_THM1_100K_PU>,
+					<&pms405_vadc ADC5_AMUX_THM3_100K_PU>;
+
+			xo_therm {
+				reg = <ADC5_XO_THERM_100K_PU>;
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+			};
+
+			pa_therm1 {
+				reg = <ADC5_AMUX_THM1_100K_PU>;
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+			};
+
+			pa_therm3 {
+				reg = <ADC5_AMUX_THM3_100K_PU>;
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+			};
+		};
+
+		pms405_pon: qcom,power-on@800 {
+			compatible = "qcom,qpnp-power-on";
+			reg = <0x800>;
+			interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>;
+			interrupt-names = "kpdpwr";
+			qcom,pon-dbc-delay = <15625>;
+			qcom,system-reset;
+			qcom,store-hard-reset-reason;
+
+			qcom,pon_1 {
+				qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
+				qcom,pull-up;
+				linux,code = <KEY_POWER>;
+			};
+		};
+
+		/* QCS405 + PMS405 GPIO configuration */
+		pms405_gpios: pinctrl@c000 {
+			compatible = "qcom,pms405-gpio";
+			reg = <0xc000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		qcom,pms405_rtc {
+			compatible = "qcom,pm8941-rtc";
+			reg = <0x6000>, <0x6100>;
+			reg-names = "rtc", "alarm";
+			interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
+		};
+	};
+
+	qcom,pms405@1 {
+		compatible = "qcom,spmi-pmic";
+		reg = <1 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pms405_pwm: qcom,pwms@bc00 {
+			compatible = "qcom,pwm-lpg";
+			reg = <0xbc00>;
+			reg-names = "lpg-base";
+			qcom,num-lpg-channels = <2>;
+			#pwm-cells = <2>;
+		};
+	};
+};
diff --git a/qcom/pmx35.dtsi b/qcom/pmx35.dtsi
index f8fc7081..e633ab80 100755
--- a/qcom/pmx35.dtsi
+++ b/qcom/pmx35.dtsi
@@ -11,7 +11,7 @@
 
 	qcom,pmx35@0 {
 		compatible = "qcom,spmi-pmic";
-		reg = <1 SPMI_USID>;
+		reg = <0 SPMI_USID>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 
@@ -81,12 +81,17 @@
 			#size-cells = <1>;
 		};
 
+		pmx35_sdam_5: sdam@7400 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x7400>;
+		};
+
 		pmx35_vadc: qcom,pmx35_vadc {
 			compatible = "qcom,spmi-adc5-gen3";
 			reg = <0x7700>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <0x0 0x76 0x1 IRQ_TYPE_EDGE_RISING>;
+			interrupts = <0x0 0x77 0x1 IRQ_TYPE_EDGE_RISING>;
 			interrupt-names = "adc-sdam0";
 			#io-channel-cells = <1>;
 			#thermal-sensor-cells = <1>;
@@ -112,3 +117,31 @@
 		};
 	};
 };
+
+&thermal_zones {
+	pmx35_temp_alarm: pmx35_tz {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-sensors = <&pmx35_tz>;
+
+		trips {
+			pmx35_trip0: trip0 {
+				temperature = <95000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			pmx35_trip1: trip1 {
+				temperature = <115000>;
+				hysteresis = <0>;
+				type = "critical";
+			};
+
+			pmx35_trip2: trip2 {
+				temperature = <145000>;
+				hysteresis = <0>;
+				type = "critical";
+			};
+		};
+	};
+};
diff --git a/qcom/qcs405-cpu.dtsi b/qcom/qcs405-cpu.dtsi
new file mode 100755
index 00000000..07c83a54
--- /dev/null
+++ b/qcom/qcs405-cpu.dtsi
@@ -0,0 +1,114 @@
+/ {
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+
+				core1 {
+					cpu = <&CPU1>;
+				};
+
+				core2 {
+					cpu = <&CPU2>;
+				};
+
+				core3 {
+					cpu = <&CPU3>;
+				};
+			};
+		};
+
+		CPU0: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x100>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <1024>;
+			next-level-cache = <&L2_1>;
+			#cooling-cells = <2>;
+			L2_1: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      /* A53 L2 dump not supported */
+			      qcom,dump-size = <0x0>;
+			};
+
+			L1_I_100: l1-icache {
+				compatible = "arm,arch-cache";
+				qcom,dump-size = <0x8800>;
+			};
+
+			L1_D_100: l1-dcache {
+				compatible = "arm,arch-cache";
+				qcom,dump-size = <0x9000>;
+			};
+		};
+
+		CPU1: cpu@101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x101>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <1024>;
+			next-level-cache = <&L2_1>;
+			#cooling-cells = <2>;
+			L1_I_101: l1-icache {
+				compatible = "arm,arch-cache";
+				qcom,dump-size = <0x8800>;
+			};
+
+			L1_D_101: l1-dcache {
+				compatible = "arm,arch-cache";
+				qcom,dump-size = <0x9000>;
+			};
+		};
+
+		CPU2: cpu@102 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x102>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <1024>;
+			next-level-cache = <&L2_1>;
+			#cooling-cells = <2>;
+			L1_I_102: l1-icache {
+				compatible = "arm,arch-cache";
+				qcom,dump-size = <0x8800>;
+			};
+
+			L1_D_102: l1-dcache {
+				compatible = "arm,arch-cache";
+				qcom,dump-size = <0x9000>;
+			};
+		};
+
+		CPU3: cpu@103 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x103>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <1024>;
+			next-level-cache = <&L2_1>;
+			#cooling-cells = <2>;
+			L1_I_103: l1-icache {
+				compatible = "arm,arch-cache";
+				qcom,dump-size = <0x8800>;
+			};
+
+			L1_D_103: l1-dcache {
+				compatible = "arm,arch-cache";
+				qcom,dump-size = <0x9000>;
+			};
+		};
+	};
+
+};
diff --git a/qcom/qcs405-iot-sku1-overlay.dts b/qcom/qcs405-iot-sku1-overlay.dts
new file mode 100755
index 00000000..3cf90647
--- /dev/null
+++ b/qcom/qcs405-iot-sku1-overlay.dts
@@ -0,0 +1,18 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Qualcomm Technologies, Inc. QCS405 EVB1 1000 IOT";
+	qcom,board-id = <0x010020 0x0>;
+};
+
+&soc {
+	gpio_keys {
+		vol_mute {
+			gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
diff --git a/qcom/qcs405-iot-sku10-overlay.dts b/qcom/qcs405-iot-sku10-overlay.dts
new file mode 100755
index 00000000..cf900e0f
--- /dev/null
+++ b/qcom/qcs405-iot-sku10-overlay.dts
@@ -0,0 +1,7 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	model = "Qualcomm Technologies, Inc. QCS405 EVB1 4000 TDM Mic";
+	qcom,board-id = <0x070020 0x1>;
+};
diff --git a/qcom/qcs405-iot-sku2-overlay.dts b/qcom/qcs405-iot-sku2-overlay.dts
new file mode 100755
index 00000000..a1a374f1
--- /dev/null
+++ b/qcom/qcs405-iot-sku2-overlay.dts
@@ -0,0 +1,7 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	model = "Qualcomm Technologies, Inc. QCS405 EVB1 4000 SPI IOT";
+	qcom,board-id = <0x010020 0x1>;
+};
diff --git a/qcom/qcs405-iot-sku3-overlay.dts b/qcom/qcs405-iot-sku3-overlay.dts
new file mode 100755
index 00000000..3b7ab4f5
--- /dev/null
+++ b/qcom/qcs405-iot-sku3-overlay.dts
@@ -0,0 +1,7 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	model = "Qualcomm Technologies, Inc. QCS405 sEVB/SLT IOT";
+	qcom,board-id = <0x010020 0x2>;
+};
diff --git a/qcom/qcs405-iot-sku4-overlay.dts b/qcom/qcs405-iot-sku4-overlay.dts
new file mode 100755
index 00000000..e8c0d4ab
--- /dev/null
+++ b/qcom/qcs405-iot-sku4-overlay.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+/plugin/;
+
+
+/ {
+	model = "Qualcomm Technologies, Inc. QCS405 EVB1 4000 DSI IOT";
+	qcom,board-id = <0x020020 0x1>;
+};
+
diff --git a/qcom/qcs405-iot-sku5-overlay.dts b/qcom/qcs405-iot-sku5-overlay.dts
new file mode 100755
index 00000000..2b6e627b
--- /dev/null
+++ b/qcom/qcs405-iot-sku5-overlay.dts
@@ -0,0 +1,8 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	model = "Qualcomm Technologies, Inc. QCS405 EVB1 4000 RGB IOT";
+	qcom,board-id = <0x030020 0x1>;
+};
+
diff --git a/qcom/qcs405-iot-sku6-overlay.dts b/qcom/qcs405-iot-sku6-overlay.dts
new file mode 100755
index 00000000..edde7f1a
--- /dev/null
+++ b/qcom/qcs405-iot-sku6-overlay.dts
@@ -0,0 +1,8 @@
+/dts-v1/;
+/plugin/;
+
+
+/ {
+	model = "Qualcomm Technologies, Inc. QCS405 EVB1 4000 CSRA1 IOT";
+	qcom,board-id = <0x040020 0x1>;
+};
diff --git a/qcom/qcs405-iot-sku7-overlay.dts b/qcom/qcs405-iot-sku7-overlay.dts
new file mode 100755
index 00000000..f5a4e875
--- /dev/null
+++ b/qcom/qcs405-iot-sku7-overlay.dts
@@ -0,0 +1,7 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	model = "Qualcomm Technologies, Inc. QCS405 EVB1 4000 CSRA6 IOT";
+	qcom,board-id = <0x050020 0x1>;
+};
diff --git a/qcom/qcs405-iot-sku8-overlay.dts b/qcom/qcs405-iot-sku8-overlay.dts
new file mode 100755
index 00000000..5c56321b
--- /dev/null
+++ b/qcom/qcs405-iot-sku8-overlay.dts
@@ -0,0 +1,7 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	model = "Qualcomm Technologies, Inc. QCS405 EVB1 4k with AMIC";
+	qcom,board-id = <0x060020 0x1>;
+};
diff --git a/qcom/qcs405-iot-sku9-overlay.dts b/qcom/qcs405-iot-sku9-overlay.dts
new file mode 100755
index 00000000..54176e5e
--- /dev/null
+++ b/qcom/qcs405-iot-sku9-overlay.dts
@@ -0,0 +1,7 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	model = "Qualcomm Technologies, Inc. QCS405 RCM IOT";
+	qcom,board-id = <0x010015 0x0>;
+};
diff --git a/qcom/qcs405-pinctrl.dtsi b/qcom/qcs405-pinctrl.dtsi
new file mode 100755
index 00000000..a9a7e957
--- /dev/null
+++ b/qcom/qcs405-pinctrl.dtsi
@@ -0,0 +1,826 @@
+&soc {
+	tlmm: pinctrl@1000000 {
+		compatible = "qcom,qcs404-pinctrl";
+		reg = <0x01000000 0x200000>,
+		      <0x01300000 0x200000>,
+		      <0x07b00000 0x200000>;
+		reg-names = "south", "north", "east";
+		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		gpio-ranges = <&tlmm 0 0 120>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		wakeup-parent = <&wakegic>;
+
+		blsp1_uart2_default: blsp1-uart2-default {
+			rx {
+				pins = "gpio18";
+				function = "blsp_uart_rx_a2";
+			};
+
+			tx {
+				pins = "gpio17";
+				function = "blsp_uart_tx_a2";
+			};
+		};
+
+		sdc1_on: sdc1_on {
+			clk {
+				pins = "sdc1_clk";
+				bias-disable;
+				drive-strength = <16>;
+			};
+
+			cmd {
+				pins = "sdc1_cmd";
+				bias-pull-up;
+				drive-strength = <10>;
+			};
+
+			data {
+				pins = "sdc1_data";
+				bias-pull-up;
+				drive-strength = <10>;
+			};
+
+			rclk {
+				pins = "sdc1_rclk";
+				bias-pull-down;
+			};
+		};
+
+		sdc1_off: sdc1_off {
+			clk {
+				pins = "sdc1_clk";
+				bias-disable;
+				drive-strength = <2>;
+			};
+
+			cmd {
+				pins = "sdc1_cmd";
+				bias-pull-up;
+				drive-strength = <2>;
+			};
+
+			data {
+				pins = "sdc1_data";
+				bias-pull-up;
+				drive-strength = <2>;
+			};
+
+			rclk {
+				pins = "sdc1_rclk";
+				bias-pull-down;
+			};
+		};
+
+		sdc2_on: sdc2_on {
+			clk {
+				pins = "sdc2_clk";
+				bias-disable;
+				drive-strength = <16>;
+			};
+
+			cmd {
+				pins = "sdc2_cmd";
+				bias-pull-up;
+				drive-strength = <10>;
+			};
+
+			data {
+				pins = "sdc2_data";
+				bias-pull-up;
+				drive-strength = <10>;
+			};
+
+			sd-cd {
+				pins = "gpio21";
+				bias-pull-up;
+				drive-strength = <2>;
+			};
+		};
+
+		sdc2_off: sdc2_off {
+			clk {
+				pins = "sdc2_clk";
+				bias-disable;
+				drive-strength = <2>;
+			};
+
+			cmd {
+				pins = "sdc2_cmd";
+				bias-pull-up;
+				drive-strength = <2>;
+			};
+
+			data {
+				pins = "sdc2_data";
+				bias-pull-up;
+				drive-strength = <2>;
+			};
+
+			sd-cd {
+				pins = "gpio21";
+				bias-disable;
+				drive-strength = <2>;
+			};
+		};
+
+		pcie0 {
+			pcie0_perst_default: pcie0_perst_default {
+				mux {
+					pins = "gpio43";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio43";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+
+			pcie0_wake_default: pcie0_wake_default {
+				mux {
+					pins = "gpio21";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio21";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+		};
+
+		usb2_id_det_default: usb2_id_det_default {
+			mux {
+				pins = "gpio53";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio53";
+				drive-strength = <2>;
+				bias-pull-up;
+				input-enable;
+			};
+		};
+
+		usb2_vbus_boost_default: usb2_vbus_boost_default {
+			mux {
+				pins = "gpio108";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio108";
+				drive-strength = <2>;
+				bias-pull-down;
+				output-low;
+			};
+		};
+
+		usb2_vbus_det_default: usb2_vbus_det_default {
+			mux {
+				pins = "gpio116";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio116";
+				drive-strength = <2>;
+				bias-pull-down;
+				input-enable;
+			};
+		};
+
+		usb3_id_det_default: usb3_id_det_default {
+			mux {
+				pins = "gpio113";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio113";
+				drive-strength = <2>;
+				bias-pull-up;
+				input-enable;
+			};
+		};
+
+		/* UART configuration */
+		blsp1_uart1 {
+			blsp1_uart1_active: blsp1_uart1_active {
+				mux {
+					pins = "gpio30", "gpio31";
+					function = "blsp_uart0";
+				};
+
+				config {
+					pins = "gpio30", "gpio31";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+
+			blsp1_uart1_sleep: blsp1_uart1_sleep {
+				mux {
+					pins = "gpio30", "gpio31";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio30", "gpio31";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+		};
+
+		blsp1_uart2 {
+			blsp1_uart2_active: blsp1_uart2_active {
+				mux {
+					pins = "gpio22", "gpio23";
+					function = "blsp_uart1";
+				};
+
+				config {
+					pins = "gpio22", "gpio23";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+
+			blsp1_uart2_sleep: blsp1_uart2_sleep {
+				mux {
+					pins = "gpio22", "gpio23";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio22", "gpio23";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+		};
+
+		blsp1_uart3 {
+			blsp1_uart3_active: blsp1_uart3_active {
+				mux {
+					pins = "gpio17", "gpio18",
+						"gpio19", "gpio20";
+					function = "blsp_uart2";
+				};
+
+				config {
+					pins = "gpio17", "gpio18",
+						"gpio19", "gpio20";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+
+			blsp1_uart3_sleep: blsp1_uart3_sleep {
+				mux {
+					pins = "gpio17", "gpio18",
+						"gpio19", "gpio20";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio17", "gpio18",
+						"gpio19", "gpio20";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+		};
+
+		blsp1_uart4 {
+			blsp1_uart4_active: blsp1_uart4_active {
+				mux {
+					pins = "gpio82", "gpio83";
+					function = "blsp_uart3";
+				};
+
+				config {
+					pins = "gpio82", "gpio83";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+
+			blsp1_uart4_sleep: blsp1_uart4_sleep {
+				mux {
+					pins = "gpio82", "gpio83";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio82", "gpio83";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+		};
+
+		blsp2_uart1 {
+			blsp2_uart1_active: blsp2_uart1_active {
+				mux {
+					pins = "gpio26", "gpio27",
+						"gpio28", "gpio29";
+					function = "blsp_uart5";
+				};
+
+				config {
+					pins = "gpio26", "gpio27",
+						"gpio28", "gpio29";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+
+			blsp2_uart1_sleep: blsp2_uart1_sleep {
+				mux {
+					pins = "gpio26", "gpio27",
+						"gpio28", "gpio29";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio26", "gpio27",
+						"gpio28", "gpio29";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+		};
+
+		/* SPI CONFIGURATION */
+		spi_1 {
+			spi_1_active: spi_1_active {
+				mux {
+					pins = "gpio30", "gpio31",
+						"gpio32", "gpio33";
+					function = "blsp_spi0";
+				};
+
+				config {
+					pins = "gpio30", "gpio31",
+						"gpio32", "gpio33";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			spi_1_sleep: spi_1_sleep {
+				mux {
+					pins = "gpio30", "gpio31",
+						"gpio32", "gpio33";
+					function = "blsp_spi0";
+				};
+
+				config {
+					pins = "gpio30", "gpio31",
+						"gpio32", "gpio33";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+		};
+
+		spi_2 {
+			spi_2_mosi_a1_active: spi_2_mosi_a1_active {
+				mux {
+					pins = "gpio22";
+					function = "blsp_spi_mosi_a1";
+				};
+
+				config {
+					pins = "gpio22";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			spi_2_mosi_a1_sleep: spi_2_mosi_a1_sleep {
+				mux {
+					pins = "gpio22";
+					function = "blsp_spi_mosi_a1";
+				};
+
+				config {
+					pins = "gpio22";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			spi_2_miso_a1_active: spi_2_miso_a1_active {
+				mux {
+					pins = "gpio23";
+					function = "blsp_spi_miso_a1";
+				};
+
+				config {
+					pins = "gpio23";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			spi_2_miso_a1_sleep: spi_2_miso_a1_sleep {
+				mux {
+					pins = "gpio23";
+					function = "blsp_spi_miso_a1";
+				};
+
+				config {
+					pins = "gpio23";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			spi_2_cs_n_a1_active: spi_2_cs_n_a1_active {
+				mux {
+					pins = "gpio24";
+					function = "blsp_spi_cs_n_a1";
+				};
+
+				config {
+					pins = "gpio24";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			spi_2_cs_n_a1_sleep: spi_2_cs_n_a1_sleep {
+				mux {
+					pins = "gpio24";
+					function = "blsp_spi_cs_n_a1";
+				};
+
+				config {
+					pins = "gpio24";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			spi_2_clk_a1_active: spi_2_clk_a1_active {
+				mux {
+					pins = "gpio25";
+					function = "blsp_spi_clk_a1";
+				};
+
+				config {
+					pins = "gpio25";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			spi_2_clk_a1_sleep: spi_2_clk_a1_sleep {
+				mux {
+					pins = "gpio25";
+					function = "blsp_spi_clk_a1";
+				};
+
+				config {
+					pins = "gpio25";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+		};
+
+		spi_3 {
+			spi_3_active: spi_3_active {
+				mux {
+					pins = "gpio17", "gpio18",
+						"gpio19", "gpio20";
+					function = "blsp_spi2";
+				};
+
+				config {
+					pins = "gpio17", "gpio18",
+						"gpio19", "gpio20";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			spi_3_sleep: spi_3_sleep {
+				mux {
+					pins = "gpio17", "gpio18",
+						"gpio19", "gpio20";
+					function = "blsp_spi2";
+				};
+
+				config {
+					pins = "gpio17", "gpio18",
+						"gpio19", "gpio20";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+		};
+
+		spi_4 {
+			spi_4_active: spi_4_active {
+				mux {
+					pins = "gpio82", "gpio83",
+						"gpio84", "gpio85";
+					function = "blsp_spi3";
+				};
+
+				config {
+					pins = "gpio82", "gpio83",
+						"gpio84", "gpio85";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			spi_4_sleep: spi_4_sleep {
+				mux {
+					pins = "gpio82", "gpio83",
+						"gpio84", "gpio85";
+					function = "blsp_spi3";
+				};
+
+				config {
+					pins = "gpio82", "gpio83",
+						"gpio84", "gpio85";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+		};
+
+		spi_5 {
+			spi_5_active: spi_5_active {
+				mux {
+					pins = "gpio37", "gpio38",
+						"gpio117", "gpio118";
+					function = "blsp_spi4";
+				};
+
+				config {
+					pins = "gpio37", "gpio38",
+						"gpio117", "gpio118";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			spi_5_sleep: spi_5_sleep {
+				mux {
+					pins = "gpio37", "gpio38",
+							"gpio117", "gpio118";
+					function = "blsp_spi4";
+				};
+
+				config {
+					pins = "gpio37", "gpio38",
+						"gpio117", "gpio118";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+		};
+
+		spi_6 {
+			spi_6_active: spi_6_active {
+				mux {
+					pins = "gpio26", "gpio27",
+						"gpio28", "gpio29";
+					function = "blsp_spi5";
+				};
+
+				config {
+					pins = "gpio26", "gpio27",
+						"gpio28", "gpio29";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			spi_6_sleep: spi_6_sleep {
+				mux {
+					pins = "gpio26", "gpio27",
+						"gpio28", "gpio29";
+					function = "blsp_spi5";
+				};
+
+				config {
+					pins = "gpio26", "gpio27",
+						"gpio28", "gpio29";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+		};
+
+		/* I2C configuration */
+		i2c_1 {
+			i2c_1_active: i2c_1_active {
+				/* active state */
+				mux {
+					pins = "gpio32", "gpio33";
+					function = "blsp_i2c0";
+				};
+
+				config {
+					pins = "gpio32", "gpio33";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+
+			i2c_1_sleep: i2c_1_sleep {
+				/* suspended state */
+				mux {
+					pins = "gpio32", "gpio33";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio32", "gpio33";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+		};
+
+		i2c_2 {
+			i2c_2_active: i2c_2_active {
+				/* active state */
+				mux {
+					pins = "gpio24", "gpio25";
+					function = "blsp_i2c1";
+				};
+
+				config {
+					pins = "gpio24", "gpio25";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+
+			i2c_2_sleep: i2c_2_sleep {
+				/* suspended state */
+				mux {
+					pins = "gpio24", "gpio25";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio24", "gpio25";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+		};
+
+		i2c_3 {
+			i2c_3_sda_active: i2c_3_sda_active {
+				/* active state */
+				mux {
+					pins = "gpio19";
+					function = "blsp_i2c_sda_a2";
+				};
+
+				config {
+					pins = "gpio19";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+
+			i2c_3_scl_active: i2c_3_scl_active {
+				/* active state */
+				mux {
+					pins = "gpio20";
+					function = "blsp_i2c_scl_a2";
+				};
+
+				config {
+					pins = "gpio20";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+
+			i2c_3_sleep: i2c_3_sleep {
+				/* suspended state */
+				mux {
+					pins = "gpio19", "gpio20";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio19", "gpio20";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+		};
+
+		i2c_4 {
+			i2c_4_active: i2c_4_active {
+				/* active state */
+				mux {
+					pins = "gpio84", "gpio85";
+					function = "blsp_i2c3";
+				};
+
+				config {
+					pins = "gpio84", "gpio85";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+
+			i2c_4_sleep: i2c_4_sleep {
+				/* suspended state */
+				mux {
+					pins = "gpio84", "gpio85";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio84", "gpio85";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+		};
+
+		i2c_5 {
+			i2c_5_active: i2c_5_active {
+				/* active state */
+				mux {
+					pins = "gpio117", "gpio118";
+					function = "blsp_i2c4";
+				};
+
+				config {
+					pins = "gpio117", "gpio118";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+
+			i2c_5_sleep: i2c_5_sleep {
+				/* suspended state */
+				mux {
+					pins = "gpio117", "gpio118";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio117", "gpio118";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+		};
+
+		i2c_6 {
+			i2c_6_active: i2c_6_active {
+				/* active state */
+				mux {
+					pins = "gpio28", "gpio29";
+					function = "blsp_i2c5";
+				};
+
+				config {
+					pins = "gpio28", "gpio29";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+
+			i2c_6_sleep: i2c_6_sleep {
+				/* suspended state */
+				mux {
+					pins = "gpio28", "gpio29";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio28", "gpio29";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+		};
+
+	};
+};
diff --git a/qcom/qcs405-regulator.dtsi b/qcom/qcs405-regulator.dtsi
new file mode 100755
index 00000000..5de01a02
--- /dev/null
+++ b/qcom/qcs405-regulator.dtsi
@@ -0,0 +1,357 @@
+#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
+
+&rpm_bus {
+	/* PMS405 S1 - VDD_MX/CX supply */
+	rpm-regulator-smpa1 {
+		status = "okay";
+		VDD_CX_LEVEL:
+		pms405_s1_level: regulator-s1-level {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pms405_s1_level";
+			qcom,set = <3>;
+			regulator-min-microvolt =
+					<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+					<RPM_SMD_REGULATOR_LEVEL_BINNING>;
+			qcom,use-voltage-level;
+		};
+
+		pms405_s1_floor_level: regulator-s1-floor-level {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pms405_s1_floor_level";
+			qcom,set = <3>;
+			regulator-min-microvolt =
+					<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+					<RPM_SMD_REGULATOR_LEVEL_BINNING>;
+			qcom,use-voltage-floor-level;
+			qcom,always-send-voltage;
+		};
+
+		pms405_s1_level_ao: regulator-s1-level-ao {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pms405_s1_level_ao";
+			qcom,set = <1>;
+			regulator-min-microvolt =
+					<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+					<RPM_SMD_REGULATOR_LEVEL_BINNING>;
+			qcom,use-voltage-level;
+		};
+
+		cx_cdev: cx-cdev-lvl {
+			compatible = "qcom,regulator-cooling-device";
+			regulator-cdev-supply = <&pms405_s1_floor_level>;
+			regulator-levels = <RPM_SMD_REGULATOR_LEVEL_NOM_PLUS
+					RPM_SMD_REGULATOR_LEVEL_NONE>;
+			#cooling-cells = <2>;
+		};
+
+		mx_cdev: mx-cdev-lvl {
+			compatible = "qcom,regulator-cooling-device";
+			regulator-cdev-supply = <&pms405_s1_level>;
+			regulator-levels = <RPM_SMD_REGULATOR_LEVEL_SVS
+					RPM_SMD_REGULATOR_LEVEL_NONE>;
+			#cooling-cells = <2>;
+		};
+	};
+
+	/* PMS405 S2 - VDD_LPI_CX supply */
+	rpm-regulator-smpa2 {
+		status = "okay";
+		pms405_s2_level: regulator-s2-level {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pms405_s2_level";
+			qcom,set = <3>;
+			regulator-min-microvolt =
+					<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+					<RPM_SMD_REGULATOR_LEVEL_BINNING>;
+			qcom,use-voltage-level;
+		};
+
+		pms405_s2_floor_level: regulator-s2-floor-level {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pms405_s2_floor_level";
+			qcom,set = <3>;
+			regulator-min-microvolt =
+					<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+					<RPM_SMD_REGULATOR_LEVEL_BINNING>;
+			qcom,use-voltage-floor-level;
+			qcom,always-send-voltage;
+		};
+	};
+
+	rpm-regulator-smpa4 {
+		status = "okay";
+		pms405_s4: regulator-s4 {
+			regulator-min-microvolt = <1728000>;
+			regulator-max-microvolt = <1920000>;
+			qcom,init-voltage = <1728000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa1 {
+		status = "okay";
+		pms405_l1: regulator-l1 {
+			regulator-min-microvolt = <1240000>;
+			regulator-max-microvolt = <1352000>;
+			qcom,init-voltage = <1240000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa2 {
+		status = "okay";
+		pms405_l2: regulator-l2 {
+			regulator-min-microvolt = <1048000>;
+			regulator-max-microvolt = <1280000>;
+			qcom,init-voltage = <1048000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa3 {
+		status = "okay";
+		VDD_SR_PLL_LEVEL:
+		pms405_l3: regulator-l3 {
+			regulator-min-microvolt = <976000>;
+			regulator-max-microvolt = <1160000>;
+			qcom,init-voltage = <976000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa4 {
+		status = "okay";
+		pms405_l4: regulator-l4 {
+			regulator-min-microvolt = <1144000>;
+			regulator-max-microvolt = <1256000>;
+			qcom,init-voltage = <1144000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa5 {
+		status = "okay";
+		pms405_l5: regulator-l5 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			status = "okay";
+		};
+
+		pms405_l5_ao: regulator-l5-ao {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pms405_l5_ao";
+			qcom,set = <1>;
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa6 {
+		status = "okay";
+		pms405_l6: regulator-l6 {
+			regulator-min-microvolt = <1704000>;
+			regulator-max-microvolt = <1896000>;
+			qcom,init-voltage = <1704000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa7 {
+		status = "okay";
+		pms405_l7: regulator-l7 {
+			regulator-min-microvolt = <1616000>;
+			regulator-max-microvolt = <3000000>;
+			qcom,init-voltage = <1616000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa8 {
+		status = "okay";
+		pms405_l8: regulator-l8 {
+			regulator-min-microvolt = <1136000>;
+			regulator-max-microvolt = <1352000>;
+			qcom,init-voltage = <1136000>;
+			status = "okay";
+		};
+	};
+
+	/* PMS405 L9 - VDD_LPI_MX supply */
+	rpm-regulator-ldoa9 {
+		status = "okay";
+		pms405_l9_level: regulator-l9-level {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pms405_l9_level";
+			qcom,set = <3>;
+			regulator-min-microvolt =
+					<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+					<RPM_SMD_REGULATOR_LEVEL_BINNING>;
+			qcom,use-voltage-level;
+		};
+
+		pms405_l9_floor_level: regulator-l9-floor-level {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pms405_l9_floor_level";
+			qcom,set = <3>;
+			regulator-min-microvolt =
+					<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+					<RPM_SMD_REGULATOR_LEVEL_BINNING>;
+			qcom,use-voltage-floor-level;
+			qcom,always-send-voltage;
+		};
+	};
+
+	rpm-regulator-ldoa10 {
+		status = "okay";
+		pms405_l10: regulator-l10 {
+			regulator-min-microvolt = <2936000>;
+			regulator-max-microvolt = <3088000>;
+			qcom,init-voltage = <2936000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa11 {
+		status = "okay";
+		pms405_l11: regulator-l11 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3304000>;
+			qcom,init-voltage = <1800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa12 {
+		status = "okay";
+		pms405_l12: regulator-l12 {
+			regulator-min-microvolt = <2968000>;
+			regulator-max-microvolt = <3300000>;
+			qcom,init-voltage = <2968000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa13 {
+		status = "okay";
+		pms405_l13: regulator-l13 {
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3300000>;
+			qcom,init-voltage = <3000000>;
+			status = "okay";
+		};
+	};
+};
+
+&spmi_bus {
+	qcom,pms405@1 {
+		/* PMS405 S3 = VDD_APC_supply */
+		pms405_s3: spm-regulator@1a00 {
+			compatible = "qcom,spm-regulator";
+			reg = <0x1a00>;
+			regulator-name = "pms405_s3";
+			regulator-min-microvolt = <1048000>;
+			regulator-max-microvolt = <1384000>;
+		};
+	};
+};
+
+&soc {
+	/* APC CPR and MEM ACC regulators */
+	mem_acc_vreg_corner: regulator@1942120 {
+		compatible = "qcom,mem-acc-regulator";
+		regulator-name = "mem_acc_corner";
+		regulator-min-microvolt = <1>;
+		regulator-max-microvolt = <2>;
+
+		qcom,acc-reg-addr-list =
+			<0x01942138 0x01942130 0x01942120 0x01942124>;
+
+		qcom,acc-init-reg-config = <1 0xff>, <2 0x5555>;
+
+		qcom,num-acc-corners = <2>;
+		qcom,boot-acc-corner = <2>;
+		qcom,corner1-reg-config =
+			/* INT2 => INT2 */
+			<(-1) (-1)>,     <(-1) (-1)>,
+			/* INT2 => NOM */
+			<  3 0x0>,       <  4  0x0>;
+
+		qcom,corner2-reg-config =
+			/* NOM => INT2 */
+			<  3 0x1041040>, <  4  0x41>,
+			/* NOM => NOM */
+			<(-1) (-1)>,     <(-1) (-1)>;
+	};
+
+	apc_vreg_corner: regulator@b018000 {
+		compatible = "qcom,cpr-regulator";
+		reg = <0xb018000 0x1000>, <0xb011064 0x4>, <0xa4000 0x1000>;
+		reg-names = "rbcpr", "rbcpr_clk", "efuse_addr";
+		interrupts = <0 15 0>;
+		regulator-name = "apc_corner";
+		regulator-min-microvolt = <1>;
+		regulator-max-microvolt = <3>;
+
+		qcom,cpr-fuse-corners = <3>;
+		qcom,cpr-voltage-ceiling = <1224000 1288000 1384000>;
+		qcom,cpr-voltage-floor =   <1048000 1048000 1088000>;
+		vdd-apc-supply = <&pms405_s3>;
+
+		mem-acc-supply = <&mem_acc_vreg_corner>;
+
+		qcom,cpr-ref-clk = <19200>;
+		qcom,cpr-timer-delay = <5000>;
+		qcom,cpr-timer-cons-up = <0>;
+		qcom,cpr-timer-cons-down = <2>;
+		qcom,cpr-irq-line = <0>;
+		qcom,cpr-step-quotient = <25>;
+		qcom,cpr-up-threshold = <1>;
+		qcom,cpr-down-threshold = <3>;
+		qcom,cpr-idle-clocks = <15>;
+		qcom,cpr-gcnt-time = <1>;
+		qcom,vdd-apc-step-up-limit = <1>;
+		qcom,vdd-apc-step-down-limit = <1>;
+		qcom,cpr-apc-volt-step = <8000>;
+
+		qcom,cpr-fuse-row = <69 0>;
+		qcom,cpr-fuse-target-quot = <30 42 64>;
+		qcom,cpr-fuse-ro-sel = <0 4 8>;
+		qcom,cpr-init-voltage-ref = <1224000 1288000 1352000>;
+		qcom,cpr-fuse-init-voltage =
+					<69 12 6 0>,
+					<69 18 6 0>,
+					<69 24 6 0>;
+		qcom,cpr-fuse-quot-offset =
+					<70 12 7 0>,
+					<70 19 7 0>,
+					<70 26 7 0>;
+		qcom,cpr-fuse-quot-offset-scale = <5 5 5>;
+		qcom,cpr-init-voltage-step = <8000>;
+		qcom,cpr-corner-map = <1 2 3>;
+		qcom,mem-acc-corner-map = <1 2 2>;
+		qcom,cpr-corner-frequency-map =
+				<1 1094400000>,
+				<2 1248000000>,
+				<3 1401600000>;
+		qcom,speed-bin-fuse-sel = <39 34 3 0>;
+		qcom,cpr-fuse-revision = <67 3 3 0>;
+		qcom,cpr-speed-bin-max-corners =
+					<(-1) (-1) 1 2 3>;
+		qcom,cpr-quot-adjust-scaling-factor-max = <0 1400 1400>;
+		qcom,cpr-voltage-scaling-factor-max = <0 2000 2000>;
+		qcom,cpr-scaled-init-voltage-as-ceiling;
+		qcom,cpr-quotient-adjustment =
+			<0	(-20)	0>;
+		qcom,cpr-enable;
+	};
+};
diff --git a/qcom/qcs405.dts b/qcom/qcs405.dts
new file mode 100755
index 00000000..3607837d
--- /dev/null
+++ b/qcom/qcs405.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "qcs405.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. QCS405 SoC";
+	compatible = "qcom,qcs405";
+	qcom,board-id = <0 0>;
+};
diff --git a/qcom/qcs405.dtsi b/qcom/qcs405.dtsi
new file mode 100755
index 00000000..6567969a
--- /dev/null
+++ b/qcom/qcs405.dtsi
@@ -0,0 +1,491 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/gpio/gpio.h>
+
+#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
+#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
+
+/ {
+	model = "Qualcomm Technologies, Inc. QCS405";
+	compatible = "qcom,qcs405";
+	qcom,msm-id = <352 0x0>, <452 0x0>;
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen {
+	};
+
+	memory { device_type = "memory"; reg = <0 0 0 0>; };
+
+	firmware: firmware {
+	};
+
+	reserved_mem: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		removed_region0: removed_region@85900000 {
+			no-map;
+			reg = <0x0 0x85900000 0x0 0x600000>;
+		};
+
+		smem_region: smem@85f00000 {
+			no-map;
+			reg = <0x0 0x85f00000 0x0 0x200000>;
+		};
+
+		removed_region1: removed_region@86100000 {
+			no-map;
+			reg = <0x0 0x86100000 0x0 0x300000>;
+		};
+
+		dump_mem: mem_dump_region {
+		compatible = "shared-dma-pool";
+		reusable;
+		size = <0 0x400000>;
+		};
+	};
+
+	soc: soc { };
+
+};
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0 0 0 0xffffffff>;
+	compatible = "simple-bus";
+
+	intc: interrupt-controller@b000000 {
+		compatible = "qcom,msm-qgic2";
+		interrupt-controller;
+		interrupt-parent = <&intc>;
+		#interrupt-cells = <3>;
+		reg = <0x0b000000 0x1000>,
+		      <0x0b002000 0x1000>;
+	};
+
+	wakegic: wake-gic {
+		compatible = "qcom,mpm-qcs405", "qcom,mpm";
+		interrupts = <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>;
+		reg = <0x601b8 0x1000>,
+			<0xb011008 0x4>;  /* MSM_APCS_GCC_BASE 4K */
+		reg-names = "vmpm", "ipc";
+		qcom,num-mpm-irqs = <96>;
+		interrupt-controller;
+		interrupt-parent = <&intc>;
+		#interrupt-cells = <2>;
+	};
+
+	qcom-secure-buffer {
+		compatible = "qcom,secure-buffer";
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <19200000>;
+	};
+
+	memtimer@b120000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		compatible = "arm,armv7-timer-mem";
+		reg = <0xb120000 0x1000>;
+		clock-frequency = <19200000>;
+		frame@b121000 {
+			frame-number = <0>;
+			interrupts = <0 8 0x4>,
+				     <0 7 0x4>;
+			reg = <0xb121000 0x1000>,
+			      <0xb122000 0x1000>;
+		};
+
+		frame@b123000 {
+			frame-number = <1>;
+			interrupts = <0 9 0x4>;
+			reg = <0xb123000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@b124000 {
+			frame-number = <2>;
+			interrupts = <0 10 0x4>;
+			reg = <0xb124000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@b125000 {
+			frame-number = <3>;
+			interrupts = <0 11 0x4>;
+			reg = <0xb125000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@b126000 {
+			frame-number = <4>;
+			interrupts = <0 12 0x4>;
+			reg = <0xb126000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@b127000 {
+			frame-number = <5>;
+			interrupts = <0 13 0x4>;
+			reg = <0xb127000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@b128000 {
+			frame-number = <6>;
+			interrupts = <0 14 0x4>;
+			reg = <0xb128000 0x1000>;
+			status = "disabled";
+		};
+	};
+
+	restart@4ab000 {
+		compatible = "qcom,pshold";
+		reg = <0x4ab000 0x4>,
+			<0x193d100 0x4>;
+		reg-names = "pshold-base", "tcsr-boot-misc-detect";
+	};
+
+	qcom,msm-rtb {
+		compatible = "qcom,msm-rtb";
+		qcom,rtb-size = <0x100000>;
+	};
+
+	qcom,mpm2-sleep-counter@4a3000 {
+		compatible = "qcom,mpm2-sleep-counter";
+		reg = <0x4a3000 0x1000>;
+		clock-frequency = <32768>;
+	};
+
+	cpu-pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	qcom,msm-imem@8600000 {
+		compatible = "qcom,msm-imem";
+		reg = <0x08600000 0x1000>; /* Address and size of IMEM */
+		ranges = <0x0 0x08600000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mem_dump_table@10 {
+			compatible = "qcom,msm-imem-mem_dump_table";
+			reg = <0x10 0x8>;
+		};
+
+		dload_type@18 {
+			compatible = "qcom,msm-imem-dload-type";
+			reg = <0x18 0x4>;
+		};
+
+		restart_reason@65c {
+			compatible = "qcom,msm-imem-restart_reason";
+			reg = <0x65c 0x4>;
+		};
+
+		boot_stats@6b0 {
+			compatible = "qcom,msm-imem-boot_stats";
+			reg = <0x6b0 0x20>;
+		};
+
+		pil@94c {
+			compatible = "qcom,pil-reloc-info";
+			reg = <0x94c 0xc8>;
+		};
+
+		pil@6dc {
+			compatible = "qcom,msm-imem-pil-disable-timeout";
+			reg = <0x6dc 0x4>;
+		};
+
+		diag_dload@c8 {
+			compatible = "qcom,msm-imem-diag-dload";
+			reg = <0xc8 0xc8>;
+		};
+
+		kaslr_offset@6d0 {
+			compatible = "qcom,msm-imem-kaslr_offset";
+			reg = <0x6d0 0xc>;
+		};
+
+	};
+
+	mini_dump_mode {
+		compatible = "qcom,minidump";
+		status = "ok";
+	};
+
+	vendor_hooks: qcom,cpu-vendor-hooks {
+		compatible = "qcom,cpu-vendor-hooks";
+	};
+
+	spmi_bus: qcom,spmi@200f000 {
+		compatible = "qcom,spmi-pmic-arb";
+		reg = <0x200f000 0x1000>,
+			<0x2400000 0x800000>,
+			<0x2c00000 0x800000>,
+			<0x3800000 0x200000>,
+			<0x200a000 0x2100>;
+		reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+		interrupt-names = "periph_irq";
+		interrupts-extended = <&wakegic 62 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,ee = <0>;
+		qcom,channel = <0>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+		interrupt-controller;
+		#interrupt-cells = <4>;
+		cell-index = <0>;
+	};
+
+	wdog: qcom,wdt@b017000 {
+		compatible = "qcom,msm-watchdog";
+		reg = <0xb017000 0x1000>;
+		reg-names = "wdt-base";
+		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,bark-time = <11000>;
+		qcom,pet-time = <9744>;
+		qcom,ipi-ping;
+		qcom,wakeup-enable;
+		status = "okay";
+	};
+
+	rpm_bus: qcom,rpm-smd {
+		compatible = "qcom,rpm-smd";
+		rpm-channel-name = "rpm_requests";
+		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+		rpm-channel-type = <15>; /* SMD_APPS_RPM */
+	};
+
+	mem_dump {
+		compatible = "qcom,mem-dump";
+		memory-region = <&dump_mem>;
+
+		rpm_sw_dump {
+			qcom,dump-size = <0x28000>;
+			qcom,dump-id = <0xea>;
+		};
+
+		pmic_dump {
+			qcom,dump-size = <0x10000>;
+			qcom,dump-id = <0xe4>;
+		};
+
+		misc_data_dump {
+			qcom,dump-size = <0x1000>;
+			qcom,dump-id = <0xe8>;
+		};
+
+		vsense_dump {
+			qcom,dump-size = <0x10000>;
+			qcom,dump-id = <0xe9>;
+		};
+
+		tmc_etf_dump {
+			qcom,dump-size = <0x10000>;
+			qcom,dump-id = <0xf0>;
+		};
+
+		tmc_etr_reg_dump {
+			qcom,dump-size = <0x1000>;
+			qcom,dump-id = <0x100>;
+		};
+
+		tmc_etf_reg_dump {
+			qcom,dump-size = <0x1000>;
+			qcom,dump-id = <0x101>;
+		};
+
+		l2_dump1 {
+			qcom,dump-size = <0x0>;
+			qcom,dump-id = <0xC1>;
+		};
+
+		l1_i_cache100 {
+			qcom,dump-size = <0x8800>;
+			qcom,dump-id = <0x60>;
+		};
+
+		l1_i_cache101 {
+			qcom,dump-size = <0x8800>;
+			qcom,dump-id = <0x61>;
+		};
+
+		l1_i_cache102 {
+			qcom,dump-size = <0x8800>;
+			qcom,dump-id = <0x62>;
+		};
+
+		l1_i_cache103 {
+			qcom,dump-size = <0x8800>;
+			qcom,dump-id = <0x63>;
+		};
+
+		l1_d_cache100 {
+			qcom,dump-size = <0x9000>;
+			qcom,dump-id = <0x80>;
+		};
+
+		l1_d_cache101 {
+			qcom,dump-size = <0x9000>;
+			qcom,dump-id = <0x81>;
+		};
+
+		l1_d_cache102 {
+			qcom,dump-size = <0x9000>;
+			qcom,dump-id = <0x82>;
+		};
+
+		l1_d_cache103 {
+			qcom,dump-size = <0x9000>;
+			qcom,dump-id = <0x83>;
+		};
+	};
+
+	tcsr_mutex_block: syscon@1905000 {
+		compatible = "syscon";
+		reg = <0x1905000 0x20000>;
+	};
+
+	tcsr: syscon@1937000 {
+		compatible = "syscon";
+		reg = <0x1937000 0x30000>;
+	};
+
+	tcsr_mutex: hwlock {
+		compatible = "qcom,tcsr-mutex";
+		syscon = <&tcsr_mutex_block 0 0x1000>;
+		#hwlock-cells = <1>;
+	};
+
+	smem: qcom,smem {
+		compatible = "qcom,smem";
+		memory-region = <&smem_region>;
+		hwlocks = <&tcsr_mutex 3>;
+	};
+
+	rpm_msg_ram: memory@60000 {
+		compatible = "qcom,rpm-msg-ram";
+		reg = <0x60000 0x6000>;
+	};
+
+	apcs: syscon@b011008 {
+		compatible = "syscon";
+		reg = <0xb011008 0x4>;
+	};
+
+	apcs_glb: mailbox@b011000 {
+		compatible = "qcom,msm8916-apcs-kpss-global";
+		reg = <0xb011000 0x1000>;
+
+		#mbox-cells = <1>;
+	};
+
+	smp2p_sleepstate: qcom,smp2p_sleepstate {
+		compatible = "qcom,smp2p-sleepstate";
+		qcom,smem-states = <&sleepstate_smp2p_out 0>;
+	};
+
+	rpm-glink {
+		compatible = "qcom,glink-rpm";
+		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+		qcom,rpm-msg-ram = <&rpm_msg_ram>;
+		mboxes = <&apcs_glb 0>;
+	};
+
+	qcom,glink {
+		compatible = "qcom,glink";
+	};
+
+	qcom,smp2p-modem {
+		compatible = "qcom,smp2p";
+		qcom,smem = <435>, <428>;
+		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&apcs 18>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <1>;
+
+		modem_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		modem_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	qcom,smp2p-adsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <443>, <429>;
+		interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&apcs 10>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <2>;
+
+		adsp_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		adsp_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		sleepstate_smp2p_out: sleepstate-out {
+			qcom,entry-name = "sleepstate";
+			#qcom,smem-state-cells = <1>;
+		};
+	};
+
+	qcom,smp2p-cdsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <94>, <432>;
+		interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&apcs 14>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <5>;
+
+		cdsp_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		cdsp_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+};
+
+&firmware {
+	qcom_scm {
+		compatible = "qcom,scm";
+		qcom,dload-mode = <&tcsr 0x13000>;
+	};
+};
+
+
+#include "qcs405-cpu.dtsi"
+#include "qcs405-pinctrl.dtsi"
+#include "pms405-rpm-regulator.dtsi"
+#include "qcs405-regulator.dtsi"
+
diff --git a/qcom/qcs407-iot-sku12-overlay.dts b/qcom/qcs407-iot-sku12-overlay.dts
new file mode 100755
index 00000000..9759a745
--- /dev/null
+++ b/qcom/qcs407-iot-sku12-overlay.dts
@@ -0,0 +1,7 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	model = "Qualcomm Technologies, Inc. QCS407 EVB1 4K/CSRA8 SPI/LiN";
+	qcom,board-id = <0x080020 0x1>;
+};
diff --git a/qcom/qcs407-iot-sku13-overlay.dts b/qcom/qcs407-iot-sku13-overlay.dts
new file mode 100755
index 00000000..bc2ffc8f
--- /dev/null
+++ b/qcom/qcs407-iot-sku13-overlay.dts
@@ -0,0 +1,7 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	model = "Qualcomm Technologies, Inc. QCS407 EVB1-4K-CSRA8 I2S-GROUPING";
+	qcom,board-id = <0x090020 0x1>;
+};
diff --git a/qcom/qcs407-iot-sku4-overlay.dts b/qcom/qcs407-iot-sku4-overlay.dts
new file mode 100755
index 00000000..14b7bf4c
--- /dev/null
+++ b/qcom/qcs407-iot-sku4-overlay.dts
@@ -0,0 +1,7 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	model = "Qualcomm Technologies, Inc. QCS407 EVB1 4000 DSI IOT";
+	qcom,board-id = <0x020020 0x1>;
+};
diff --git a/qcom/qcs407-iot-sku6-overlay.dts b/qcom/qcs407-iot-sku6-overlay.dts
new file mode 100755
index 00000000..b2308fce
--- /dev/null
+++ b/qcom/qcs407-iot-sku6-overlay.dts
@@ -0,0 +1,7 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	model = "Qualcomm Technologies, Inc. QCS407 EVB1 4000 CSRA1 IOT";
+	qcom,board-id = <0x040020 0x1>;
+};
diff --git a/qcom/qcs407-iot-sku9-overlay.dts b/qcom/qcs407-iot-sku9-overlay.dts
new file mode 100755
index 00000000..5c3e6c6c
--- /dev/null
+++ b/qcom/qcs407-iot-sku9-overlay.dts
@@ -0,0 +1,7 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	model = "Qualcomm Technologies, Inc. QCS407 RCM IOT";
+	qcom,board-id = <0x010015 0x0>;
+};
diff --git a/qcom/qcs407.dtsi b/qcom/qcs407.dtsi
new file mode 100755
index 00000000..94521f21
--- /dev/null
+++ b/qcom/qcs407.dtsi
@@ -0,0 +1,7 @@
+#include "qcs405.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. QCS407";
+	qcom,msm-name = "QCS407";
+	qcom,msm-id = <411 0x0>;
+};
diff --git a/qcom/qrb3165-cpu.dtsi b/qcom/qrb3165-cpu.dtsi
new file mode 100755
index 00000000..13391309
--- /dev/null
+++ b/qcom/qrb3165-cpu.dtsi
@@ -0,0 +1,399 @@
+/ {
+	/delete-node/ cpus;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			cpu-release-addr = <0x0 0x90000000>;
+			next-level-cache = <&L2_0>;
+			qcom,freq-domain = <&cpufreq_hw 0 4>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			#cooling-cells = <2>;
+			L2_0: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+
+				L3_0: l3-cache {
+				      compatible = "arm,arch-cache";
+				      cache-level = <3>;
+				};
+			};
+
+			L1_I_0: l1-icache {
+				compatible = "arm,arch-cache";
+			};
+
+			L1_D_0: l1-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		CPU1: cpu@100 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			cpu-release-addr = <0x0 0x90000000>;
+			next-level-cache = <&L2_1>;
+			qcom,freq-domain = <&cpufreq_hw 0 4>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			L2_1: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+
+			L1_I_100: l1-icache {
+				compatible = "arm,arch-cache";
+			};
+
+			L1_D_100: l1-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		CPU2: cpu@200 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x200>;
+			enable-method = "psci";
+			cpu-release-addr = <0x0 0x90000000>;
+			next-level-cache = <&L2_2>;
+			qcom,freq-domain = <&cpufreq_hw 0 4>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			L2_2: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+
+			L2_I_100: l2-icache {
+				compatible = "arm,arch-cache";
+			};
+
+			L2_D_100: l2-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		CPU3: cpu@400 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x400>;
+			enable-method = "psci";
+			cpu-release-addr = <0x0 0x90000000>;
+			next-level-cache = <&L2_4>;
+			qcom,freq-domain = <&cpufreq_hw 1 4>;
+			capacity-dmips-mhz = <1894>;
+			dynamic-power-coefficient = <514>;
+			#cooling-cells = <2>;
+			L2_4: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+
+			L1_I_400: l1-icache {
+				compatible = "arm,arch-cache";
+			};
+
+			L1_D_400: l1-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		CPU4: cpu@500 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x500>;
+			enable-method = "psci";
+			cpu-release-addr = <0x0 0x90000000>;
+			next-level-cache = <&L2_5>;
+			qcom,freq-domain = <&cpufreq_hw 1 4>;
+			capacity-dmips-mhz = <1894>;
+			dynamic-power-coefficient = <514>;
+			L2_5: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+
+			L1_I_500: l1-icache {
+				compatible = "arm,arch-cache";
+			};
+
+			L1_D_500: l1-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		CPU5: cpu@600 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x600>;
+			enable-method = "psci";
+			cpu-release-addr = <0x0 0x90000000>;
+			next-level-cache = <&L2_6>;
+			qcom,freq-domain = <&cpufreq_hw 1 4>;
+			capacity-dmips-mhz = <1894>;
+			dynamic-power-coefficient = <514>;
+			L2_6: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+
+			L1_I_600: l1-icache {
+				compatible = "arm,arch-cache";
+			};
+
+			L1_D_600: l1-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+
+				core1 {
+					cpu = <&CPU1>;
+				};
+
+				core2 {
+					cpu = <&CPU2>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&CPU3>;
+				};
+
+				core1 {
+					cpu = <&CPU4>;
+				};
+
+				core2 {
+					cpu = <&CPU5>;
+				};
+			};
+		};
+	};
+};
+
+&soc {
+	/delete-node/ dsu_pmu@0;
+	/delete-node/ jtagmm@7340000;
+	/delete-node/ cti@7320000;
+	/delete-node/ cti@7720000;
+	/delete-node/ etm@7340000;
+	/delete-node/ etm@7740000;
+
+	dsu_pmu@0 {
+		compatible = "arm,dsu-pmu";
+		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+		cpus = <&CPU0>, <&CPU1>,<&CPU2>,
+			<&CPU3>, <&CPU4>, <&CPU5>;
+	};
+
+	qcom,lpm-levels {
+		qcom,pm-cluster@0 {
+			qcom,pm-cpu@0 {
+				/delete-property/  qcom,cpu;
+				qcom,cpu = <&CPU0 &CPU1 &CPU2>;
+			};
+
+			qcom,pm-cpu@1 {
+				/delete-property/  qcom,cpu;
+				qcom,cpu = <&CPU3 &CPU4 &CPU5>;
+
+			};
+		};
+	};
+
+	cti_cpu4: cti@7420000 {
+		cpu = <&CPU3>;
+	};
+
+	cti_cpu5: cti@7520000 {
+		cpu = <&CPU4>;
+	};
+
+	cti_cpu6: cti@7620000 {
+		cpu = <&CPU5>;
+	};
+
+	etm4: etm@7440000 {
+		cpu = <&CPU3>;
+	};
+
+	etm5: etm@7540000 {
+		cpu = <&CPU4>;
+	};
+
+	etm6: etm@7640000 {
+		cpu = <&CPU5>;
+	};
+
+	funnel_apss: funnel@7800000 {
+		in-ports {
+			/delete-node/ port@4;
+			/delete-node/ port@8;
+		};
+	};
+};
+
+&cpufreq_hw {
+	/delete-node/ cpu7-notify;
+};
+
+&qcom_memlat {
+	ddr {
+		silver {
+			/delete-property/  qcom,cpulist;
+			qcom,cpulist = <&CPU0 &CPU1 &CPU2>;
+		};
+
+		gold {
+			/delete-property/  qcom,cpulist;
+			qcom,cpulist = <&CPU3 &CPU4 &CPU5>;
+		};
+
+		gold-compute {
+			/delete-property/  qcom,cpulist;
+			qcom,cpulist = <&CPU3 &CPU4 &CPU5>;
+		};
+	};
+
+	llcc {
+		silver {
+			/delete-property/  qcom,cpulist;
+			qcom,cpulist = <&CPU0 &CPU1 &CPU2>;
+		};
+
+		gold {
+			/delete-property/  qcom,cpulist;
+			qcom,cpulist = <&CPU3 &CPU4 &CPU5>;
+		};
+	};
+
+	l3 {
+		/delete-node/ prime;
+		silver {
+			/delete-property/  qcom,cpulist;
+			qcom,cpulist = <&CPU0 &CPU1 &CPU2>;
+		};
+
+		gold {
+			/delete-property/  qcom,cpulist;
+			qcom,cpulist = <&CPU3 &CPU4 &CPU5>;
+		};
+	};
+
+	ddrqos {
+		ddrqos_gold_lat: gold {
+			/delete-property/  qcom,cpulist;
+			qcom,cpulist = <&CPU3 &CPU4 &CPU5>;
+		};
+	};
+};
+
+&soc {
+
+	qcom,cpu-pause {
+		/delete-node/ cpu6-pause;
+		/delete-node/ cpu7-pause;
+		/delete-node/ pause-cpu6;
+		/delete-node/ pause-cpu7;
+	};
+
+	qcom,cpu-hotplug {
+		/delete-node/ cpu6-hotplug;
+		/delete-node/ cpu7-hotplug;
+	};
+
+	/delete-node/ cpufreq_cdev;
+	cpufreq_cdev: qcom,cpufreq-cdev {
+		compatible = "qcom,cpufreq-cdev";
+		qcom,cpus = <&CPU0 &CPU3>;
+	};
+};
+
+&thermal_zones {
+
+	cpu-1-0 {
+		cooling-maps {
+			/delete-node/ cpufreq_cdev;
+		};
+	};
+
+	cpu-1-1 {
+		cooling-maps {
+			/delete-node/ cpufreq_cdev;
+		};
+	};
+
+	cpu-1-2 {
+		cooling-maps {
+			/delete-node/ cpufreq_cdev;
+			/delete-node/ cpu12_cdev;
+		};
+	};
+
+	cpu-1-3 {
+		cooling-maps {
+			/delete-node/ cpufreq_cdev;
+			/delete-node/ cpu13_cdev;
+		};
+	};
+
+	cpu-1-4 {
+		cooling-maps {
+			/delete-node/ cpufreq_cdev;
+		};
+	};
+
+	cpu-1-5 {
+		cooling-maps {
+			/delete-node/ cpufreq_cdev;
+		};
+	};
+
+	cpu-1-6 {
+		cooling-maps {
+			/delete-node/ cpufreq_cdev;
+			/delete-node/ cpu16_cdev;
+		};
+	};
+
+	cpu-1-7 {
+		cooling-maps {
+			/delete-node/ cpufreq_cdev;
+			/delete-node/ cpu17_cdev;
+		};
+	};
+
+	ddr {
+		cooling-maps {
+			/delete-node/ cpu_cdev7;
+			cpu_cdev4 {
+			/delete-property/  cooling-device;
+			cooling-device = <&CPU3 THERMAL_NO_LIMIT
+					THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+};
diff --git a/qcom/qrb3165-iot.dts b/qcom/qrb3165-iot.dts
new file mode 100755
index 00000000..5196b1d6
--- /dev/null
+++ b/qcom/qrb3165-iot.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "qrb3165-iot.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. kona-iot RB5 Platform";
+	compatible = "qcom,kona-iot";
+	qcom,board-id = <0 0>;
+};
diff --git a/qcom/qrb3165-iot.dtsi b/qcom/qrb3165-iot.dtsi
new file mode 100755
index 00000000..31657ed5
--- /dev/null
+++ b/qcom/qrb3165-iot.dtsi
@@ -0,0 +1,7 @@
+ #include "kona-iot-v2.1.dtsi"
+ #include "qrb3165-cpu.dtsi"
+/ {
+	model = "Qualcomm Technologies, Inc. kona-iot RB5 Platform";
+	compatible = "qcom,kona-iot";
+	qcom,msm-id = <598 0x0>;
+};
diff --git a/qcom/qrb3165n-iot.dts b/qcom/qrb3165n-iot.dts
new file mode 100755
index 00000000..55b65895
--- /dev/null
+++ b/qcom/qrb3165n-iot.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "qrb3165n-iot.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. kona-iot RB5 NON POP Platform";
+	compatible = "qcom,kona-iot";
+	qcom,board-id = <0 0>;
+};
diff --git a/qcom/qrb3165n-iot.dtsi b/qcom/qrb3165n-iot.dtsi
new file mode 100755
index 00000000..1c2c5e38
--- /dev/null
+++ b/qcom/qrb3165n-iot.dtsi
@@ -0,0 +1,7 @@
+ #include "qrb3165-iot.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. kona-iot RB5 NON POP Platform";
+	compatible = "qcom,kona-iot";
+	qcom,msm-id = <599 0x0>;
+};
diff --git a/qcom/qrb5165-iot.dtsi b/qcom/qrb5165-iot.dtsi
index d6cdd304..d6c8ce4e 100755
--- a/qcom/qrb5165-iot.dtsi
+++ b/qcom/qrb5165-iot.dtsi
@@ -1,4 +1,4 @@
- #include "kona.dtsi"
+ #include "kona-iot-v2.1.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. kona-iot RB5 Platform";
diff --git a/qcom/quin-vm-common.dtsi b/qcom/quin-vm-common.dtsi
index 2c736a90..27918977 100755
--- a/qcom/quin-vm-common.dtsi
+++ b/qcom/quin-vm-common.dtsi
@@ -141,7 +141,35 @@
 		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 
 		regulator: virtio_regulator_device {
-			compatible = "virtio,device31";
+			compatible = "virtio,device31", "virtio,device49153";
+					/* VIRTIO_ID_BC: 0x1F, VIRTIO_ID: 0xC001 */
+		};
+	};
+
+	subsys_notif_virt: qcom,subsys_notif_virt@2D000000 {
+		compatible = "qcom,subsys-notif-virt";
+		reg = <0x2D000000 0x400>;
+		reg-names = "vdev_base";
+		cdsp0 {
+			subsys-name = "cdsp0";
+			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "state-irq";
+			type = "virtual";
+			offset = <768>;
+		};
+
+		adsp {
+			subsys-name = "adsp";
+			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "state-irq";
+			type = "virtual";
+			offset = <0>;
+		};
+
+		wlan {
+			subsys-name = "wlan";
+			type = "native";
+			offset = <512>;
 		};
 	};
 
@@ -205,6 +233,7 @@
 			grp-start-id = <700>;
 			role = "fe";
 			remote-vmids = <0>;
+			kernel_only;
 		};
 
 		mmidgrp900: mmidgrp900 {
@@ -291,7 +320,8 @@
 		status = "okay";
 
 		spmi_bus: virt_spmi {
-			compatible = "virtio,device33";
+			compatible = "virtio,device33", "virtio,device49155";
+					/* VIRTIO_ID_BC: 0x21, VIRTIO_ID: 0xC003 */
 		};
 	};
 
diff --git a/qcom/sa8155-adp-common.dtsi b/qcom/sa8155-adp-common.dtsi
index 1f9c6a67..8972c6ae 100755
--- a/qcom/sa8155-adp-common.dtsi
+++ b/qcom/sa8155-adp-common.dtsi
@@ -69,9 +69,9 @@
 	vdd-hba-fixed-regulator;
 
 	vcc-supply = <&pm8150_1_l10>;
-	vcc-voltage-level = <2950000 2960000>;
 	vcc-max-microamp = <750000>;
 
+	vccq-supply = <&pm8150_2_l5>;
 	vccq2-supply = <&pm8150_1_s4>;
 	vccq2-max-microamp = <750000>;
 
diff --git a/qcom/sa8155-regulator.dtsi b/qcom/sa8155-regulator.dtsi
index 5db7c789..3ab7b7dd 100755
--- a/qcom/sa8155-regulator.dtsi
+++ b/qcom/sa8155-regulator.dtsi
@@ -208,8 +208,7 @@
 			qcom,set = <RPMH_REGULATOR_SET_ALL>;
 			regulator-min-microvolt = <2504000>;
 			regulator-max-microvolt = <2960000>;
-			qcom,init-voltage = <2504000>;
-			qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
 		};
 	};
 
@@ -507,7 +506,7 @@
 			regulator-min-microvolt = <1200000>;
 			regulator-max-microvolt = <1200000>;
 			qcom,init-voltage = <1200000>;
-			qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
 		};
 	};
 
diff --git a/qcom/sa8155-vm-la.dtsi b/qcom/sa8155-vm-la.dtsi
index 6132aa88..e55f0152 100755
--- a/qcom/sa8155-vm-la.dtsi
+++ b/qcom/sa8155-vm-la.dtsi
@@ -121,6 +121,11 @@
 	};
 };
 
+&qupv3_se2_i2c {
+	qcom,clk-freq-out = <400000>;
+	status = "ok";
+};
+
 &usb0 {
 	status = "ok";
 };
@@ -129,6 +134,10 @@
 	status = "ok";
 };
 
+&sdhc_2 {
+	status = "ok";
+};
+
 / {
 	rename_devices: rename_devices {
 		compatible = "qcom,rename-devices";
diff --git a/qcom/sa8155-vm-qupv3.dtsi b/qcom/sa8155-vm-qupv3.dtsi
index 44b37eb5..94bb6827 100755
--- a/qcom/sa8155-vm-qupv3.dtsi
+++ b/qcom/sa8155-vm-qupv3.dtsi
@@ -21,7 +21,37 @@
 	 * Qup2 4: SE 18
 	 * Qup2 5: SE 19
 	 */
+	/* QUPv3_0 wrapper instance */
+	qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
+		compatible = "qcom,geni-se-qup";
+		reg = <0x8c0000 0x6000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		clock-names = "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		iommus = <&apps_smmu 0xc3 0x0>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
+		qcom,iommu-geometry = <0x40000000 0x10000000>;
+		qcom,iommu-dma = "fastmap";
+		status = "ok";
 
+		/* I2C instance for SDR Card*/
+		qupv3_se2_i2c: i2c@888000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x888000 0x4000>;
+			interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se2_i2c_active>;
+			pinctrl-1 = <&qupv3_se2_i2c_sleep>;
+			status = "disabled";
+		};
+	};
 	/* QUPv3_1  wrapper  instance */
 	qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
 		compatible = "qcom,geni-se-qup";
@@ -104,5 +134,6 @@
 			pinctrl-1 = <&qupv3_se19_i2c_sleep>;
 			status = "disabled";
 		};
+
 	};
 };
diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi
index da1a0546..60318490 100755
--- a/qcom/sa8155-vm.dtsi
+++ b/qcom/sa8155-vm.dtsi
@@ -8,17 +8,41 @@
 	aliases {
 		hsuart0 = &qupv3_se17_4uart;
 		serial0 = &qupv3_se12_2uart;
+		i2c2 = &qupv3_se2_i2c;
+		mmc1 = &sdhc_2; /* SDC2 SD card slot */
 	};
 
 	cpus {
 		#address-cells = <2>;
 		#size-cells = <0>;
 
+		cluster_0_opp_table: opp-table0 {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			opp-2131200000 {
+				opp-hz = /bits/ 64 <2131200000>;
+				opp-microvolt = <948000>;
+			};
+		};
+
+		cluster_1_opp_table: opp-table1 {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			opp-1785600000 {
+				opp-hz = /bits/ 64 <1785600000>;
+				opp-microvolt = <892000>;
+			};
+		};
+
 		CPU0: cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,armv8";
 			reg = <0x0 0x0>;
 			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <374>;
+			operating-points-v2 = <&cluster_0_opp_table>;
 		};
 
 		CPU1: cpu@1 {
@@ -26,6 +50,8 @@
 			compatible = "arm,armv8";
 			reg = <0x0 0x1>;
 			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <374>;
+			operating-points-v2 = <&cluster_0_opp_table>;
 		};
 
 		CPU2: cpu@2 {
@@ -33,6 +59,8 @@
 			compatible = "arm,armv8";
 			reg = <0x0 0x2>;
 			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <374>;
+			operating-points-v2 = <&cluster_0_opp_table>;
 		};
 
 		CPU3: cpu@3 {
@@ -40,34 +68,44 @@
 			compatible = "arm,armv8";
 			reg = <0x0 0x3>;
 			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <374>;
+			operating-points-v2 = <&cluster_0_opp_table>;
 		};
 
 		CPU4: cpu@4 {
 			device_type = "cpu";
 			compatible = "arm,armv8";
 			reg = <0x0 0x4>;
-			capacity-dmips-mhz = <414>;
+			capacity-dmips-mhz = <419>;
+			dynamic-power-coefficient = <100>;
+			operating-points-v2 = <&cluster_1_opp_table>;
 		};
 
 		CPU5: cpu@5 {
 			device_type = "cpu";
 			compatible = "arm,armv8";
 			reg = <0x0 0x5>;
-			capacity-dmips-mhz = <414>;
+			capacity-dmips-mhz = <419>;
+			dynamic-power-coefficient = <100>;
+			operating-points-v2 = <&cluster_1_opp_table>;
 		};
 
 		CPU6: cpu@6 {
 			device_type = "cpu";
 			compatible = "arm,armv8";
 			reg = <0x0 0x6>;
-			capacity-dmips-mhz = <414>;
+			capacity-dmips-mhz = <419>;
+			dynamic-power-coefficient = <100>;
+			operating-points-v2 = <&cluster_1_opp_table>;
 		};
 
 		CPU7: cpu@7 {
 			device_type = "cpu";
 			compatible = "arm,armv8";
 			reg = <0x0 0x7>;
-			capacity-dmips-mhz = <414>;
+			capacity-dmips-mhz = <419>;
+			dynamic-power-coefficient = <100>;
+			operating-points-v2 = <&cluster_1_opp_table>;
 		};
 
 		cpu-map {
@@ -293,6 +331,44 @@
 		interrupt-parent = <&intc>;
 		interrupt-controller;
 	};
+
+	sdhc_2: sdhci@8804000 {
+		compatible = "qcom,sdhci-msm-v5";
+		reg = <0x8804000 0x1000>;
+		reg-names = "hc";
+
+		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "hc_irq", "pwr_irq";
+
+		clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+			<&gcc GCC_SDCC2_APPS_CLK>;
+		clock-names = "iface", "core";
+
+		bus-width = <4>;
+		no-sdio;
+		no-mmc;
+		qcom,restore-after-cx-collapse;
+
+		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+		qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>;
+
+		vdd-supply = <&L17A>;
+		qcom,vdd-voltage-level = <2950000 2960000>;
+		qcom,vdd-current-level = <200 800000>;
+
+		vdd-io-supply = <&L13C>;
+		qcom,vdd-io-voltage-level = <1808000 2960000>;
+		qcom,vdd-io-current-level = <200 22000>;
+
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&sdc2_on>;
+		pinctrl-1 = <&sdc2_off>;
+
+		cd-gpios = <&pm8150_gpios 4 GPIO_ACTIVE_LOW>;
+
+		status = "disabled";
+	};
 };
 
 #include "sm8150-pinctrl.dtsi"
@@ -395,6 +471,18 @@
 	/delete-node/ mmidgrp1500;
 };
 
+&qupv3_0 {
+	qcom,iommu-dma = "bypass";
+};
+
+&qupv3_1 {
+	qcom,iommu-dma = "bypass";
+};
+
+&qupv3_2 {
+	qcom,iommu-dma = "bypass";
+};
+
 &pcie0_msi {
 	status = "ok";
 };
diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi
index e3a034d5..450b5d26 100755
--- a/qcom/sa8155.dtsi
+++ b/qcom/sa8155.dtsi
@@ -61,6 +61,13 @@
 		read-only;
 		ranges;
 	};
+
+	aop-set-ddr-freq {
+		compatible = "qcom,aop-set-ddr-freq";
+		mboxes = <&qmp_aop 0>;
+		mbox-names = "aop";
+	};
+
 hsi2s: qcom,hsi2s {
 		compatible = "qcom,sa8155-hsi2s", "qcom,hsi2s";
 		number-of-interfaces = <3>;
@@ -595,4 +602,5 @@ hsi2s: qcom,hsi2s {
 
 &msm_fastrpc {
 	qcom,adsp-remoteheap-vmid = <3 5 6>;
+	qcom,mdsp-remoteheap-vmid = <3 0xf>;
 };
diff --git a/qcom/sa8195-thermal.dtsi b/qcom/sa8195-thermal.dtsi
index c708ed82..d582ecff 100755
--- a/qcom/sa8195-thermal.dtsi
+++ b/qcom/sa8195-thermal.dtsi
@@ -1057,6 +1057,15 @@
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			npu_cdev {
+				trip = <&npu_trip0>;
+				cooling-device =
+					<&msm_npu THERMAL_NO_LIMIT
+						THERMAL_NO_LIMIT>;
+			};
+		};
 	};
 
 	mdm-vec {
diff --git a/qcom/sa8195-vm-la.dtsi b/qcom/sa8195-vm-la.dtsi
index 2eea62b1..03eebbbe 100755
--- a/qcom/sa8195-vm-la.dtsi
+++ b/qcom/sa8195-vm-la.dtsi
@@ -18,6 +18,106 @@
 };
 
 &soc {
+	hsi2s: qcom,hsi2s@172c0000 {
+		compatible = "qcom,sa8195-hsi2s", "qcom,hsi2s";
+		number-of-interfaces = <3>;
+		reg = <0x172c0000 0x28000>,
+		      <0x17080000 0xe000>;
+		reg-names = "lpa_if", "lpass_tcsr";
+		interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+		number-of-rate-detectors = <2>;
+		rate-detector-interfaces = <0 1>;
+		iommus = <&apps_smmu 0x1B5C 0x1>,
+			 <&apps_smmu 0x1B5E 0x0>;
+		qcom,iommu-dma-addr-pool = <0x0 0xFFFFFFFF>;
+
+		sdr0: qcom,hs0_i2s {
+			compatible = "qcom,hsi2s-interface";
+			minor-number = <0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&hs1_i2s_mclk_active &hs1_i2s_sck_active
+				     &hs1_i2s_ws_active &hs1_i2s_data0_active
+				     &hs1_i2s_data1_active>;
+			pinctrl-1 = <&hs1_i2s_mclk_sleep &hs1_i2s_sck_sleep
+				     &hs1_i2s_ws_sleep &hs1_i2s_data0_sleep
+				     &hs1_i2s_data1_sleep>;
+			bit-clock-hz = <12288000>;
+			data-buffer-ms = <10>;
+			bit-depth = <32>;
+			spkr-channel-count = <2>;
+			mic-channel-count = <2>;
+			pcm-rate = <2>;
+			pcm-sync-src = <0>;
+			aux-mode = <0>;
+			rpcm-width = <1>;
+			tpcm-width = <1>;
+			enable-tdm = <1>;
+			tdm-rate = <32>;
+			tdm-rpcm-width = <16>;
+			tdm-tpcm-width = <16>;
+			tdm-sync-delay = <2>;
+			tdm-inv-sync = <0>;
+			pcm-lane-config = <1>;
+		};
+
+		sdr1: qcom,hs1_i2s {
+			compatible = "qcom,hsi2s-interface";
+			minor-number = <1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&hs2_i2s_mclk_active &hs2_i2s_sck_active
+				     &hs2_i2s_ws_active &hs2_i2s_data0_active
+				     &hs2_i2s_data1_active>;
+			pinctrl-1 = <&hs2_i2s_mclk_sleep &hs2_i2s_sck_sleep
+				     &hs2_i2s_ws_sleep &hs2_i2s_data0_sleep
+				     &hs2_i2s_data1_sleep>;
+			bit-clock-hz = <12288000>;
+			data-buffer-ms = <10>;
+			bit-depth = <32>;
+			spkr-channel-count = <2>;
+			mic-channel-count = <2>;
+			pcm-rate = <2>;
+			pcm-sync-src = <0>;
+			aux-mode = <0>;
+			rpcm-width = <1>;
+			tpcm-width = <1>;
+			enable-tdm = <1>;
+			tdm-rate = <32>;
+			tdm-rpcm-width = <16>;
+			tdm-tpcm-width = <16>;
+			tdm-sync-delay = <2>;
+			tdm-inv-sync = <0>;
+			pcm-lane-config = <1>;
+		};
+
+		sdr2: qcom,hs2_i2s {
+			compatible = "qcom,hsi2s-interface";
+			minor-number = <2>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&hs3_i2s_mclk_active &hs3_i2s_sck_active
+				     &hs3_i2s_ws_active &hs3_i2s_data0_active
+				     &hs3_i2s_data1_active>;
+			pinctrl-1 = <&hs3_i2s_mclk_sleep &hs3_i2s_sck_sleep
+				     &hs3_i2s_ws_sleep &hs3_i2s_data0_sleep
+				     &hs3_i2s_data1_sleep>;
+			bit-clock-hz = <12288000>;
+			data-buffer-ms = <10>;
+			bit-depth = <32>;
+			spkr-channel-count = <2>;
+			mic-channel-count = <2>;
+			pcm-rate = <2>;
+			pcm-sync-src = <0>;
+			aux-mode = <0>;
+			rpcm-width = <1>;
+			tpcm-width = <1>;
+			enable-tdm = <1>;
+			tdm-rate = <32>;
+			tdm-rpcm-width = <16>;
+			tdm-tpcm-width = <16>;
+			tdm-sync-delay = <2>;
+			tdm-inv-sync = <0>;
+			pcm-lane-config = <1>;
+		};
+	};
 };
 
 / {
@@ -60,3 +160,12 @@
 &pcie0 {
 	status = "ok";
 };
+
+&sdhc_2 {
+	status = "ok";
+};
+
+&qupv3_se2_i2c {
+	qcom,clk-freq-out = <400000>;
+	status = "ok";
+};
diff --git a/qcom/sa8195-vm-qupv3.dtsi b/qcom/sa8195-vm-qupv3.dtsi
index 4f1f384c..6899748c 100755
--- a/qcom/sa8195-vm-qupv3.dtsi
+++ b/qcom/sa8195-vm-qupv3.dtsi
@@ -22,6 +22,39 @@
 	 * Qup2 5: SE 19
 	 */
 
+
+	/* QUPv3_0 wrapper instance */
+	qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
+		compatible = "qcom,geni-se-qup";
+		reg = <0x8c0000 0x6000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		clock-names = "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		iommus = <&apps_smmu 0xc3 0x0>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
+		qcom,iommu-geometry = <0x40000000 0x10000000>;
+		qcom,iommu-dma = "fastmap";
+		status = "ok";
+
+		/* I2C instance for SDR Card*/
+		qupv3_se2_i2c: i2c@888000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x888000 0x4000>;
+			interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se2_i2c_active>;
+			pinctrl-1 = <&qupv3_se2_i2c_sleep>;
+			status = "disabled";
+		};
+	};
+
 	/* QUPv3_2  wrapper  instance */
 	qupv3_2: qcom,qupv3_2_geni_se@cc0000 {
 		compatible = "qcom,geni-se-qup";
diff --git a/qcom/sa8195-vm.dtsi b/qcom/sa8195-vm.dtsi
index 69853b52..941cbfd9 100755
--- a/qcom/sa8195-vm.dtsi
+++ b/qcom/sa8195-vm.dtsi
@@ -8,6 +8,143 @@
 	qcom,msm-id = <405 0x20000>;
 	aliases {
 		hsuart0 = &qupv3_se17_4uart;
+		mmc1 = &sdhc_2; /* SDC2 SD card slot */
+		i2c2 = &qupv3_se2_i2c;
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cluster_0_opp_table: opp-table0 {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			opp-2496000000 {
+				opp-hz = /bits/ 64 <2496000000>;
+				opp-microvolt = <980000>;
+			};
+		};
+
+		cluster_1_opp_table: opp-table1 {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			opp-1766400000 {
+				opp-hz = /bits/ 64 <1766400000>;
+				opp-microvolt = <888000>;
+			};
+		};
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x0>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <431>;
+			operating-points-v2 = <&cluster_0_opp_table>;
+		};
+
+		CPU1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x1>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <431>;
+			operating-points-v2 = <&cluster_0_opp_table>;
+		};
+
+		CPU2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x2>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <431>;
+			operating-points-v2 = <&cluster_0_opp_table>;
+		};
+
+		CPU3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x3>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <431>;
+			operating-points-v2 = <&cluster_0_opp_table>;
+		};
+
+		CPU4: cpu@4 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x4>;
+			capacity-dmips-mhz = <414>;
+			dynamic-power-coefficient = <100>;
+			operating-points-v2 = <&cluster_1_opp_table>;
+		};
+
+		CPU5: cpu@5 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x5>;
+			capacity-dmips-mhz = <414>;
+			dynamic-power-coefficient = <100>;
+			operating-points-v2 = <&cluster_1_opp_table>;
+		};
+
+		CPU6: cpu@6 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x6>;
+			capacity-dmips-mhz = <414>;
+			dynamic-power-coefficient = <100>;
+			operating-points-v2 = <&cluster_1_opp_table>;
+		};
+
+		CPU7: cpu@7 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x7>;
+			capacity-dmips-mhz = <414>;
+			dynamic-power-coefficient = <100>;
+			operating-points-v2 = <&cluster_1_opp_table>;
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+
+				core1 {
+					cpu = <&CPU1>;
+				};
+
+				core2 {
+					cpu = <&CPU2>;
+				};
+
+				core3 {
+					cpu = <&CPU3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&CPU4>;
+				};
+
+				core1 {
+					cpu = <&CPU5>;
+				};
+
+				core2 {
+					cpu = <&CPU6>;
+				};
+
+				core3 {
+					cpu = <&CPU7>;
+				};
+			};
+		};
 	};
 };
 
@@ -231,6 +368,70 @@
 		regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
 		regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
 	};
+
+	sdhc_2: sdhci@8804000 {
+		compatible = "qcom,sdhci-msm-v5";
+		reg = <0x8804000 0x1000>;
+		reg-names = "hc_mem";
+
+		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "hc_irq", "pwr_irq";
+
+		clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+			<&gcc GCC_SDCC2_APPS_CLK>;
+		clock-names = "iface", "core";
+
+		bus-width = <4>;
+		qcom,restore-after-cx-collapse;
+
+		qcom,msm-bus,name = "sdhc2";
+		qcom,msm-bus,num-cases = <6>;
+		qcom,msm-bus,num-paths = <2>;
+		qcom,msm-bus,vectors-KBps =
+			/* No vote */
+			<0 0>, <0 0>,
+			/* 25 MB/s */
+			<65360 100000>, <100000 100000>,
+			/* 50 MB/s */
+			<130718 200000>, <100000 100000>,
+			/* 100 MB/s */
+			<261438 200000>, <130000 130000>,
+			/* 200 MB/s */
+			<261438 400000>, <300000 300000>,
+			/* Max. bandwidth */
+			<1338562 4096000>, <1338562 4096000>;
+
+		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+		qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>;
+
+		qcom,devfreq,freq-table = <50000000 200000000>;
+
+		vdd-supply = <&pm8195_1_l10>;
+		qcom,vdd-voltage-level = <2950000 2960000>;
+		qcom,vdd-current-level = <200 800000>;
+
+		vdd-io-supply = <&pm8195_1_l2>;
+		qcom,vdd-io-voltage-level = <1808000 2960000>;
+		qcom,vdd-io-current-level = <200 22000>;
+
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&sdc2_on>;
+		pinctrl-1 = <&sdc2_off>;
+
+		cd-gpios = <&pm8195_1_gpios 4 GPIO_ACTIVE_LOW>;
+		status = "disabled";
+
+		qos0 {
+			mask = <0x0f>;
+			vote = <70>;
+		};
+
+		qos1 {
+			mask = <0xf0>;
+			vote = <70>;
+		};
+	};
 };
 
 &firmware {
@@ -248,6 +449,14 @@
 	/delete-property/ wakeup-parent;
 };
 
+&qupv3_0 {
+	qcom,iommu-dma = "bypass";
+};
+
+&qupv3_2 {
+	qcom,iommu-dma = "bypass";
+};
+
 &regulator {
 	usb30_prim_gdsc: usb30_prim_gdsc {
 		regulator-name = "usb30_prim_gdsc";
diff --git a/qcom/sa8195p-regulator.dtsi b/qcom/sa8195p-regulator.dtsi
index 05abc06b..65823f2b 100755
--- a/qcom/sa8195p-regulator.dtsi
+++ b/qcom/sa8195p-regulator.dtsi
@@ -260,7 +260,7 @@
 			regulator-min-microvolt = <1100000>;
 			regulator-max-microvolt = <1300000>;
 			qcom,init-voltage = <1100000>;
-			qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
 		};
 	};
 
@@ -652,7 +652,7 @@
 			regulator-min-microvolt = <1700000>;
 			regulator-max-microvolt = <1950000>;
 			qcom,init-voltage = <1700000>;
-			qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
 		};
 	};
 
@@ -704,8 +704,7 @@
 			qcom,set = <RPMH_REGULATOR_SET_ALL>;
 			regulator-min-microvolt = <2500000>;
 			regulator-max-microvolt = <3544000>;
-			qcom,init-voltage = <2500000>;
-			qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
 		};
 	};
 
diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi
index 89b1509d..29ddd5d2 100755
--- a/qcom/sa8195p.dtsi
+++ b/qcom/sa8195p.dtsi
@@ -164,8 +164,6 @@
 	vdd-hba-supply = <&ufs_phy_gdsc>;
 	vdd-hba-fixed-regulator;
 	vcc-supply = <&pm8195_3_l10>;
-	vcc-voltage-level = <2894000 2904000>;
-	vcc-low-voltage-sup;
 	vccq-supply = <&pm8195_1_l11>;
 	vccq2-supply = <&pm8195_3_l7>;
 	vcc-max-microamp = <750000>;
diff --git a/qcom/sdmshrike-debug.dtsi b/qcom/sdmshrike-debug.dtsi
index 254d4f90..7a553cc6 100755
--- a/qcom/sdmshrike-debug.dtsi
+++ b/qcom/sdmshrike-debug.dtsi
@@ -1,3 +1,4 @@
+#include <dt-bindings/soc/qcom,dcc_v2.h>
 
 &reserved_memory {
 	#address-cells = <2>;
@@ -13,6 +14,15 @@
 };
 
 &soc {
+	dcc: dcc_v2@010a2000 {
+		compatible = "qcom,dcc-v2";
+		reg = <0x10a2000 0x1000>,
+			<0x10ac000 0x4000>;
+		reg-names = "dcc-base", "dcc-ram-base";
+
+		dcc-ram-offset = <0xC000>;
+	};
+
 	mem_dump {
 		compatible = "qcom,mem-dump";
 		memory-region = <&dump_mem>;
diff --git a/qcom/sdmshrike-v2.dtsi b/qcom/sdmshrike-v2.dtsi
index 4192585c..bfeedbf6 100755
--- a/qcom/sdmshrike-v2.dtsi
+++ b/qcom/sdmshrike-v2.dtsi
@@ -7,3 +7,162 @@
 };
 
 /delete-node/ &ufs_card_gdsc;
+
+&msm_npu {
+	iommus = <&apps_smmu 0x1481 0x400>, <&apps_smmu 0x1081 0x400>;
+	qcom,npu-pwrlevels {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "qcom,npu-pwrlevels";
+		initial-pwrlevel = <5>;
+		qcom,npu-pwrlevel@0 {
+			reg = <0>;
+			vreg = <1>;
+			clk-freq = <0
+				0
+				0
+				100000000
+				300000000
+				300000000
+				19200000
+				150000000
+				100000000
+				37500000
+				19200000
+				60000000
+				100000000
+				19200000
+				19200000
+				0
+				19200000
+				300000000
+				19200000
+				19200000>;
+		};
+
+		qcom,npu-pwrlevel@1 {
+			reg = <1>;
+			vreg = <2>;
+			clk-freq = <0
+				0
+				0
+				150000000
+				400000000
+				400000000
+				37500000
+				200000000
+				150000000
+				75000000
+				19200000
+				120000000
+				150000000
+				19200000
+				19200000
+				0
+				19200000
+				400000000
+				19200000
+				19200000>;
+		};
+
+		qcom,npu-pwrlevel@2 {
+			reg = <2>;
+			vreg = <3>;
+			clk-freq = <0
+				0
+				0
+				200000000
+				487000000
+				487000000
+				37500000
+				300000000
+				200000000
+				150000000
+				19200000
+				240000000
+				200000000
+				19200000
+				19200000
+				0
+				19200000
+				487000000
+				19200000
+				19200000>;
+		};
+
+		qcom,npu-pwrlevel@3 {
+			reg = <3>;
+			vreg = <4>;
+			clk-freq = <0
+				0
+				0
+				300000000
+				652000000
+				652000000
+				75000000
+				403000000
+				300000000
+				150000000
+				19200000
+				240000000
+				300000000
+				19200000
+				19200000
+				0
+				19200000
+				652000000
+				19200000
+				19200000>;
+		};
+
+		qcom,npu-pwrlevel@4 {
+			reg = <4>;
+			vreg = <6>;
+			clk-freq = <0
+				0
+				0
+				400000000
+				811000000
+				811000000
+				75000000
+				533000000
+				400000000
+				150000000
+				19200000
+				300000000
+				400000000
+				19200000
+				19200000
+				0
+				19200000
+				811000000
+				19200000
+				19200000>;
+		};
+
+		qcom,npu-pwrlevel@5 {
+			reg = <5>;
+			vreg = <7>;
+			clk-freq = <0
+				0
+				0
+				400000000
+				908000000
+				908000000
+				75000000
+				533000000
+				400000000
+				150000000
+				19200000
+				300000000
+				400000000
+				19200000
+				19200000
+				0
+				19200000
+				908000000
+				19200000
+				19200000>;
+		};
+	};
+};
diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi
index 3180dd22..0d7ccca1 100755
--- a/qcom/sdmshrike.dtsi
+++ b/qcom/sdmshrike.dtsi
@@ -1080,6 +1080,12 @@
 		#power-domain-cells = <1>;
 	};
 
+	aop-set-ddr-freq {
+		compatible = "qcom,aop-set-ddr-freq";
+		mboxes = <&qmp_aop 0>;
+		mbox-names = "aop";
+	};
+
 	qmp_aop: qcom,qmp-aop@c300000 {
 		compatible = "qcom,qmp-mbox";
 		qcom,qmp = <&aoss_qmp>;
@@ -1630,6 +1636,23 @@
 		};
 	};
 
+	ufs_ice: ufsice@1d90000 {
+		compatible = "qcom,ice";
+		reg = <0x1d90000 0x8000>;
+		qcom,enable-ice-clk;
+		clock-names = "ufs_core_clk",
+			"iface_clk", "ice_core_clk";
+		clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+			<&gcc GCC_UFS_PHY_AHB_CLK>,
+			<&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+		qcom,op-freq-hz = <0>, <0>, <300000000>;
+		vdd-hba-supply = <&ufs_phy_gdsc>;
+		qcom,bus-vector-names = "MIN",
+				"MAX";
+		qcom,instance-type = "ufs";
+		qcom,num-fde-slots = <31>;
+	};
+
 	ufsphy_mem: ufsphy_mem@1d87000 {
 		reg = <0x1d87000 0xe00>; /* PHY regs */
 		reg-names = "phy_mem";
@@ -1759,7 +1782,7 @@
 		reset-names = "rst";
 
 		iommus = <&apps_smmu 0x300 0x0>;
-		qcom,iommu-dma = "bypass";
+		qcom,iommu-dma = "fastmap";
 		dma-coherent;
 
 		status = "disabled";
@@ -2028,6 +2051,7 @@
 #include "msm-arm-smmu-sdmshrike.dtsi"
 #include "sdmshrike-debug.dtsi"
 #include "sa8195-usb.dtsi"
+#include "sm8150-npu.dtsi"
 
 &slpi_tlmm {
 	status = "ok";
diff --git a/qcom/sdxbaagha-dma-heaps.dtsi b/qcom/sdxbaagha-dma-heaps.dtsi
index 224331fe..44c39d56 100755
--- a/qcom/sdxbaagha-dma-heaps.dtsi
+++ b/qcom/sdxbaagha-dma-heaps.dtsi
@@ -3,5 +3,17 @@
 &soc {
 	qcom,dma-heaps {
 		compatible = "qcom,dma-heaps";
+
+		qcom,qseecom {
+			qcom,dma-heap-name = "qcom,qseecom";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&qseecom_mem>;
+		};
+
+		qcom,qseecom_ta {
+			qcom,dma-heap-name = "qcom,qseecom-ta";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&qseecom_ta_mem>;
+		};
 	};
 };
diff --git a/qcom/sdxbaagha-pcie.dtsi b/qcom/sdxbaagha-pcie.dtsi
index d39e9848..2a6ff4b0 100755
--- a/qcom/sdxbaagha-pcie.dtsi
+++ b/qcom/sdxbaagha-pcie.dtsi
@@ -113,6 +113,8 @@
 		qcom,tpwr-on-value = <9>;
 		qcom,eq-fmdc-t-min-phase23 = <1>;
 		qcom,slv-addr-space-size = <0x4000000>;
+		qcom,l1-2-th-scale = <2>;
+		qcom,l1-2-th-value = <150>;
 		qcom,ep-latency = <10>;
 		qcom,num-parf-testbus-sel = <0xb9>;
 
diff --git a/qcom/sdxbaagha-pinctrl.dtsi b/qcom/sdxbaagha-pinctrl.dtsi
index 670aeac4..2c0f1803 100755
--- a/qcom/sdxbaagha-pinctrl.dtsi
+++ b/qcom/sdxbaagha-pinctrl.dtsi
@@ -478,7 +478,7 @@
 			pcie0_clkreq_default: pcie0_clkreq_default {
 				mux {
 					pins = "gpio56";
-					function = "pcie0_clkreq_n";
+					function = "pcie_clkreq_n";
 				};
 
 				config {
diff --git a/qcom/sdxbaagha-pmic-overlay.dtsi b/qcom/sdxbaagha-pmic-overlay.dtsi
index 1a54923c..801e0405 100755
--- a/qcom/sdxbaagha-pmic-overlay.dtsi
+++ b/qcom/sdxbaagha-pmic-overlay.dtsi
@@ -23,11 +23,13 @@
 };
 
 &qupv3_se4_i2c {
-	smb23x-lbc@24 {
+	status = "ok";
+	smb23x-lbc@12 {
 		compatible = "qcom,smb231-lbc";
-		reg = <0x24>;
-		interrupt-parent = <&pmx35_gpios>;
-		interrupts = <&pmx35_gpios 7 IRQ_TYPE_LEVEL_LOW>;
+		reg = <0x12>;
+		interrupt-parent = <&spmi_bus>;
+		interrupts = <0x0 0x8E 0x0 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-names = "smb23x_stat_irq";
 		pinctrl-names = "default";
 		pinctrl-0 = <&smb_int_default>;
 		#io-channel-cells = <1>;
@@ -55,7 +57,7 @@
 &soc {
 	pmic-pon-log {
 		compatible = "qcom,pmic-pon-log";
-		nvmem = <&pmx35_sdam_2>;
+		nvmem = <&pmx35_sdam_5>;
 		nvmem-names = "pon_log";
 	};
 };
@@ -115,8 +117,13 @@
 
 };
 
+&pmx35_tz {
+	io-channels = <&pmx35_vadc PMX35_ADC5_GEN3_DIE_TEMP>;
+	io-channel-names = "thermal";
+};
+
 &thermal_zones {
-	sys-therm-0 {
+	sys-therm-1 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
 		thermal-sensors = <&pmx35_vadc PMX35_ADC5_GEN3_AMUX_THM1_100K_PU>;
@@ -135,10 +142,10 @@
 		};
 	};
 
-	sys-therm-1 {
+	sys-therm-2 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-sensors = <&pmx35_vadc PMX35_ADC5_GEN3_AMUX_THM3_100K_PU>;
+		thermal-sensors = <&pmx35_vadc PMX35_ADC5_GEN3_AMUX_THM2_100K_PU>;
 		trips {
 			active-config0 {
 				temperature = <125000>;
@@ -154,10 +161,10 @@
 		};
 	};
 
-	sys-therm-2 {
+	sys-therm-3 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-sensors = <&pmx35_vadc PMX35_ADC5_GEN3_AMUX_THM5_100K_PU>;
+		thermal-sensors = <&pmx35_vadc PMX35_ADC5_GEN3_AMUX_THM3_100K_PU>;
 		trips {
 			active-config0 {
 				temperature = <125000>;
@@ -173,12 +180,10 @@
 		};
 	};
 
-	sys-therm-3 {
+	xo-therm {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
-		thermal-sensors = <&pmx35_vadc PMX35_ADC5_GEN3_AMUX_THM2_100K_PU>;
-		wake-capable-sensor;
+		thermal-sensors = <&pmx35_vadc PMX35_ADC5_GEN3_AMUX_THM5_100K_PU>;
 		trips {
 			active-config0 {
 				temperature = <125000>;
diff --git a/qcom/sdxbaagha-regulators.dtsi b/qcom/sdxbaagha-regulators.dtsi
index 4d38a328..1f8bd2f3 100755
--- a/qcom/sdxbaagha-regulators.dtsi
+++ b/qcom/sdxbaagha-regulators.dtsi
@@ -105,9 +105,48 @@
 		};
 	};
 
-	rpmh-regulator-ldo3a {
+	rpmh-regulator-smpa2 {
 		compatible = "qcom,rpmh-vrm-regulator";
-		qcom,resource-name = "ldo3a";
+		qcom,resource-name = "smpa2";
+
+		S2A: pmx35_s2: regulator-pmx35-s2 {
+			regulator-name = "pmx35_s2";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <830000>;
+			regulator-max-microvolt = <1414000>;
+			qcom,init-voltage = <1280000>;
+		};
+	};
+
+	rpmh-regulator-smpa3 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "smpa3";
+
+		S3A: pmx35_s3: regulator-pmx35-s3 {
+			regulator-name = "pmx35_s3";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <382000>;
+			regulator-max-microvolt = <1170000>;
+			qcom,init-voltage = <880000>;
+		};
+	};
+
+	rpmh-regulator-smpa4 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "smpa4";
+
+		S4A: pmx35_s4: regulator-pmx35-s4 {
+			regulator-name = "pmx35_s4";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1670000>;
+			regulator-max-microvolt = <2040000>;
+			qcom,init-voltage = <1880000>;
+		};
+	};
+
+	rpmh-regulator-ldoa3 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoa3";
 		qcom,regulator-type = "pmic5-ldo";
 		qcom,supported-modes =
 			<RPMH_REGULATOR_MODE_LPM
@@ -120,14 +159,14 @@
 			qcom,set = <RPMH_REGULATOR_SET_ALL>;
 			regulator-min-microvolt = <720000>;
 			regulator-max-microvolt = <950000>;
-			qcom,init-voltage = <910000>;
+			qcom,init-voltage = <912000>;
 			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
 		};
 	};
 
-	rpmh-regulator-ldo4a {
+	rpmh-regulator-ldoa4 {
 		compatible = "qcom,rpmh-vrm-regulator";
-		qcom,resource-name = "ldo4a";
+		qcom,resource-name = "ldoa4";
 		qcom,regulator-type = "pmic5-ldo";
 		qcom,supported-modes =
 			<RPMH_REGULATOR_MODE_LPM
@@ -140,14 +179,14 @@
 			qcom,set = <RPMH_REGULATOR_SET_ALL>;
 			regulator-min-microvolt = <570000>;
 			regulator-max-microvolt = <650000>;
-			qcom,init-voltage = <620000>;
+			qcom,init-voltage = <624000>;
 			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
 		};
 	};
 
-	rpmh-regulator-ldo5a {
+	rpmh-regulator-ldoa5 {
 		compatible = "qcom,rpmh-vrm-regulator";
-		qcom,resource-name = "ldo5a";
+		qcom,resource-name = "ldoa5";
 		qcom,regulator-type = "pmic5-ldo";
 		qcom,supported-modes =
 			<RPMH_REGULATOR_MODE_LPM
@@ -165,9 +204,9 @@
 		};
 	};
 
-	rpmh-regulator-ldo6a {
+	rpmh-regulator-ldoa6 {
 		compatible = "qcom,rpmh-vrm-regulator";
-		qcom,resource-name = "ldo6a";
+		qcom,resource-name = "ldoa6";
 		qcom,regulator-type = "pmic5-ldo";
 		qcom,supported-modes =
 			<RPMH_REGULATOR_MODE_LPM
@@ -178,16 +217,16 @@
 		L6A: pmx35_l6: regulator-pmx35-l6 {
 			regulator-name = "pmx35_l6";
 			qcom,set = <RPMH_REGULATOR_SET_ALL>;
-			regulator-min-microvolt = <1504000>;
+			regulator-min-microvolt = <1800000>;
 			regulator-max-microvolt = <1980000>;
 			qcom,init-voltage = <1800000>;
 			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
 		};
 	};
 
-	rpmh-regulator-ldo7a {
+	rpmh-regulator-ldoa7 {
 		compatible = "qcom,rpmh-vrm-regulator";
-		qcom,resource-name = "ldo7a";
+		qcom,resource-name = "ldoa7";
 		qcom,regulator-type = "pmic5-ldo";
 		qcom,supported-modes =
 			<RPMH_REGULATOR_MODE_LPM
@@ -205,9 +244,9 @@
 		};
 	};
 
-	rpmh-regulator-ldo8a {
+	rpmh-regulator-ldoa8 {
 		compatible = "qcom,rpmh-vrm-regulator";
-		qcom,resource-name = "ldo8a";
+		qcom,resource-name = "ldoa8";
 		qcom,regulator-type = "pmic5-ldo";
 		qcom,supported-modes =
 			<RPMH_REGULATOR_MODE_LPM
@@ -225,9 +264,9 @@
 		};
 	};
 
-	rpmh-regulator-ldo9a {
+	rpmh-regulator-ldoa9 {
 		compatible = "qcom,rpmh-vrm-regulator";
-		qcom,resource-name = "ldo9a";
+		qcom,resource-name = "ldoa9";
 		qcom,regulator-type = "pmic5-ldo";
 		qcom,supported-modes =
 			<RPMH_REGULATOR_MODE_LPM
@@ -244,9 +283,9 @@
 		};
 	};
 
-	rpmh-regulator-ldo10a {
+	rpmh-regulator-ldoa10 {
 		compatible = "qcom,rpmh-vrm-regulator";
-		qcom,resource-name = "ldo10a";
+		qcom,resource-name = "ldoa10";
 		qcom,regulator-type = "pmic5-ldo";
 		qcom,supported-modes =
 			<RPMH_REGULATOR_MODE_LPM
@@ -264,9 +303,9 @@
 		};
 	};
 
-	rpmh-regulator-ldo11a {
+	rpmh-regulator-ldoa11 {
 		compatible = "qcom,rpmh-vrm-regulator";
-		qcom,resource-name = "ldo11a";
+		qcom,resource-name = "ldoa11";
 		qcom,regulator-type = "pmic5-ldo";
 		qcom,supported-modes =
 			<RPMH_REGULATOR_MODE_LPM
@@ -278,15 +317,15 @@
 			regulator-name = "pmx35_l11";
 			qcom,set = <RPMH_REGULATOR_SET_ALL>;
 			regulator-min-microvolt = <1650000>;
-			regulator-max-microvolt = <1950000>;
+			regulator-max-microvolt = <3300000>;
 			qcom,init-voltage = <1650000>;
 			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
 		};
 	};
 
-	rpmh-regulator-ldo12a {
+	rpmh-regulator-ldoa12 {
 		compatible = "qcom,rpmh-vrm-regulator";
-		qcom,resource-name = "ldo12a";
+		qcom,resource-name = "ldoa12";
 		qcom,regulator-type = "pmic5-ldo";
 		qcom,supported-modes =
 			<RPMH_REGULATOR_MODE_LPM
@@ -304,9 +343,9 @@
 		};
 	};
 
-	rpmh-regulator-ldo13a {
+	rpmh-regulator-ldoa13 {
 		compatible = "qcom,rpmh-vrm-regulator";
-		qcom,resource-name = "ldo13a";
+		qcom,resource-name = "ldoa13";
 		qcom,regulator-type = "pmic5-ldo";
 		qcom,supported-modes =
 			<RPMH_REGULATOR_MODE_LPM
@@ -324,9 +363,9 @@
 		};
 	};
 
-	rpmh-regulator-ldo14a {
+	rpmh-regulator-ldoa14 {
 		compatible = "qcom,rpmh-vrm-regulator";
-		qcom,resource-name = "ldo14a";
+		qcom,resource-name = "ldoa14";
 		qcom,regulator-type = "pmic5-ldo";
 		qcom,supported-modes =
 			<RPMH_REGULATOR_MODE_LPM
@@ -344,9 +383,9 @@
 		};
 	};
 
-	rpmh-regulator-ldo15a {
+	rpmh-regulator-ldoa15 {
 		compatible = "qcom,rpmh-vrm-regulator";
-		qcom,resource-name = "ldo15a";
+		qcom,resource-name = "ldoa15";
 		qcom,regulator-type = "pmic5-ldo";
 		qcom,supported-modes =
 			<RPMH_REGULATOR_MODE_LPM
@@ -358,7 +397,7 @@
 			regulator-name = "pmx35_l15";
 			qcom,set = <RPMH_REGULATOR_SET_ALL>;
 			regulator-min-microvolt = <1650000>;
-			regulator-max-microvolt = <1950000>;
+			regulator-max-microvolt = <3000000>;
 			qcom,init-voltage = <1650000>;
 			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
 		};
diff --git a/qcom/sdxbaagha.dtsi b/qcom/sdxbaagha.dtsi
index becc6be6..9d2c6768 100755
--- a/qcom/sdxbaagha.dtsi
+++ b/qcom/sdxbaagha.dtsi
@@ -29,6 +29,7 @@
 	};
 
 	memory { device_type = "memory"; reg = <0 0>; };
+	firmware: firmware { };
 
 	reserved_memory: reserved-memory {
 		#address-cells = <1>;
@@ -136,6 +137,21 @@
 			linux,cma-default;
 		};
 
+		qseecom_mem: qseecom_region {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x00000000 0xffffffff>;
+			reusable;
+			alignment = <0x400000>;
+			size = <0x800000>;
+		};
+
+		qseecom_ta_mem: qseecom_ta_region {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x00000000 0xffffffff>;
+			reusable;
+			alignment = <0x400000>;
+			size = <0x400000>;
+		};
 	};
 
 	cpus {
@@ -509,7 +525,6 @@
 	clk_virt: interconnect@0 {
 		compatible = "qcom,sdxbaagha-clk_virt";
 		#interconnect-cells = <1>;
-		qcom,skip-qos;
 		qcom,bcm-voter-names = "hlos";
 		qcom,bcm-voters = <&apps_bcm_voter>;
 	};
@@ -517,7 +532,6 @@
 	mc_virt: interconnect@1 {
 		compatible = "qcom,sdxbaagha-mc_virt";
 		#interconnect-cells = <1>;
-		qcom,skip-qos;
 		qcom,bcm-voter-names = "hlos";
 		qcom,bcm-voters = <&apps_bcm_voter>;
 	};
@@ -526,7 +540,6 @@
 		reg = <0x1640000 0x33400>;
 		compatible = "qcom,sdxbaagha-aggre_noc";
 		#interconnect-cells = <1>;
-		qcom,skip-qos;
 		qcom,bcm-voter-names = "hlos";
 		qcom,bcm-voters = <&apps_bcm_voter>;
 	};
@@ -535,7 +548,6 @@
 		reg = <0x01580000 0x19200>;
 		compatible = "qcom,sdxbaagha-cnoc_main";
 		#interconnect-cells = <1>;
-		qcom,skip-qos;
 		qcom,bcm-voter-names = "hlos";
 		qcom,bcm-voters = <&apps_bcm_voter>;
 	};
@@ -544,7 +556,6 @@
 		reg = <0x190E0000 0x5080>;
 		compatible = "qcom,sdxbaagha-dc_noc";
 		#interconnect-cells = <1>;
-		qcom,skip-qos;
 		qcom,bcm-voter-names = "hlos";
 		qcom,bcm-voters = <&apps_bcm_voter>;
 	};
@@ -553,7 +564,6 @@
 		reg = <0x19100000 0x2D080>;
 		compatible = "qcom,sdxbaagha-mem_noc";
 		#interconnect-cells = <1>;
-		qcom,skip-qos;
 		qcom,bcm-voter-names = "hlos";
 		qcom,bcm-voters = <&apps_bcm_voter>;
 	};
@@ -562,7 +572,6 @@
 		reg = <0x16C0000 0x16400>;
 		compatible = "qcom,sdxbaagha-pcie_anoc";
 		#interconnect-cells = <1>;
-		qcom,skip-qos;
 		qcom,bcm-voter-names = "hlos";
 		qcom,bcm-voters = <&apps_bcm_voter>;
 	};
@@ -571,7 +580,6 @@
 		reg = <0x15C0000 0x14080>;
 		compatible = "qcom,sdxbaagha-system_noc";
 		#interconnect-cells = <1>;
-		qcom,skip-qos;
 		qcom,bcm-voter-names = "hlos";
 		qcom,bcm-voters = <&apps_bcm_voter>;
 	};
@@ -753,6 +761,11 @@
 		status = "disabled";
 	};
 
+	qcom_tzlog: tz-log@14693720 {
+		compatible = "qcom,tz-log";
+		reg = <0x14693720 0x3000>;
+	};
+
 	spmi_bus: qcom,spmi@c42d000 {
 		compatible = "qcom,spmi-pmic-arb";
 		reg = <0xc42d000 0x4000>,
@@ -797,6 +810,17 @@
 	};
 };
 
+&firmware {
+	qtee_shmbridge {
+		compatible = "qcom,tee-shared-memory-bridge";
+	};
+
+	qcom_smcinvoke {
+		compatible = "qcom,smcinvoke";
+		qcom,support-legacy_smc;
+	};
+};
+
 #include "sdxbaagha-pinctrl.dtsi"
 #include "sdxbaagha-dma-heaps.dtsi"
 #include "msm-arm-smmu-sdxbaagha.dtsi"
diff --git a/qcom/sdxpinn-idp-mbb.dtsi b/qcom/sdxpinn-idp-mbb.dtsi
index 17f1e228..a5416ea0 100755
--- a/qcom/sdxpinn-idp-mbb.dtsi
+++ b/qcom/sdxpinn-idp-mbb.dtsi
@@ -1,2 +1,10 @@
 &soc {
 };
+
+&pcie1 {
+	status = "disabled";
+};
+
+&pcie2 {
+	status = "disabled";
+};
diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi
index 47139301..315942a6 100755
--- a/qcom/sdxpinn.dtsi
+++ b/qcom/sdxpinn.dtsi
@@ -670,6 +670,8 @@
 			      "pcie_pipe_clk",
 			      "sleep_clk",
 			      "usb3_phy_wrapper_gcc_usb30_pipe_clk";
+		protected-clocks = <GCC_TLMM_125_CLK>,
+				<GCC_TLMM_125_CLK_SRC>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
diff --git a/qcom/slate.dtsi b/qcom/slate.dtsi
index 11f9f7a2..2c7e3a71 100755
--- a/qcom/slate.dtsi
+++ b/qcom/slate.dtsi
@@ -24,6 +24,8 @@
 		compatible = "qcom,slate-daemon";
 		qcom,firmware-name = "slatefw.mdt";
 		qcom,rproc-handle = <&aon_pas>;
+		/* GPIO for external flash */
+		qcom,platform-reset-gpio = <&pm5100_gpios 15 0>;
 	};
 
 	glink_slatecom:qcom,glink-slatecom-xprt-slate {
@@ -50,6 +52,10 @@
 			qcom,intents = <0x0C 1>;
 		};
 
+		qcom,glink-slate-dfu {
+			qcom,glink-channels = "slate-dfu";
+			qcom,intents = <0x24 1>;
+		};
 
 		qcom,glinkpkt-slate-ssc-hal {
 			qcom,glink-channels = "ssc_hal";
@@ -164,6 +170,17 @@
 			qcom,intents = <0x2710 2
 					0x3E8  2>;
 		};
+
+		qcom,glink-ss-bt-ctrl {
+			qcom,glink-channels = "ss_bt_ctrl";
+			qcom,intents = <0x500 10>;
+		};
+
+		qcom,glink-ss-bt-data {
+			qcom,glink-channels = "ss_bt_data";
+			qcom,intents = <0x1000 10>;
+		};
+
 	};
 
 	qcom,slatecom-rpmsg {
diff --git a/qcom/sm8150-dma-heaps.dtsi b/qcom/sm8150-dma-heaps.dtsi
index 4c1aa3a5..60cf7a83 100755
--- a/qcom/sm8150-dma-heaps.dtsi
+++ b/qcom/sm8150-dma-heaps.dtsi
@@ -49,5 +49,11 @@
 			memory-region = <&secure_display_memory>;
 		};
 
+		qcom,audio-ml {
+			qcom,dma-heap-name = "qcom,audio-ml";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&audio_cma_mem>;
+		};
+
 	};
 };
diff --git a/qcom/sm8150-npu.dtsi b/qcom/sm8150-npu.dtsi
new file mode 100755
index 00000000..1d0b5759
--- /dev/null
+++ b/qcom/sm8150-npu.dtsi
@@ -0,0 +1,194 @@
+&soc {
+	msm_npu: qcom,msm_npu@9800000 {
+		compatible = "qcom,msm-npu";
+		status = "ok";
+		reg = <0x9800000 0x15000>,
+			<0x9900000 0x10000>,
+			<0x9960200 0x600>;
+		reg-names = "tcm", "core", "bwmon";
+		interrupts = <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "error_irq", "wdg_bite_irq", "ipc_irq";
+		iommus = <&apps_smmu 0x1461 0x0>, <&apps_smmu 0x2061 0x0>;
+		memory-region = <&pil_npu_mem>;
+		clocks = <&aoss_qmp>,
+				<&gcc GCC_NPU_AT_CLK>,
+				<&gcc GCC_NPU_TRIG_CLK>,
+				<&npucc NPU_CC_ARMWIC_CORE_CLK>,
+				<&npucc NPU_CC_CAL_DP_CLK>,
+				<&npucc NPU_CC_CAL_DP_CDC_CLK>,
+				<&npucc NPU_CC_CONF_NOC_AHB_CLK>,
+				<&npucc NPU_CC_COMP_NOC_AXI_CLK>,
+				<&npucc NPU_CC_NPU_CORE_CLK>,
+				<&npucc NPU_CC_NPU_CORE_CTI_CLK>,
+				<&npucc NPU_CC_NPU_CORE_APB_CLK>,
+				<&npucc NPU_CC_NPU_CORE_ATB_CLK>,
+				<&npucc NPU_CC_NPU_CPC_CLK>,
+				<&npucc NPU_CC_NPU_CPC_TIMER_CLK>,
+				<&npucc NPU_CC_QTIMER_CORE_CLK>,
+				<&npucc NPU_CC_SLEEP_CLK>,
+				<&npucc NPU_CC_BWMON_CLK>,
+				<&npucc NPU_CC_PERF_CNT_CLK>,
+				<&npucc NPU_CC_BTO_CORE_CLK>;
+		clock-names = "qdss_clk",
+				"at_clk",
+				"trig_clk",
+				"armwic_core_clk",
+				"cal_dp_clk",
+				"cal_dp_cdc_clk",
+				"conf_noc_ahb_clk",
+				"comp_noc_axi_clk",
+				"npu_core_clk",
+				"npu_core_cti_clk",
+				"npu_core_apb_clk",
+				"npu_core_atb_clk",
+				"npu_cpc_clk",
+				"npu_cpc_timer_clk",
+				"qtimer_core_clk",
+				"sleep_clk",
+				"bwmon_clk",
+				"perf_cnt_clk",
+				"bto_core_clk";
+		vdd-supply = <&npu_core_gdsc>;
+		vdd_cx-supply = <&VDD_CX_LEVEL>;
+		qcom,proxy-reg-names ="vdd", "vdd_cx";
+		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+		mboxes = <&qmp_aop 0>;
+		mbox-names = "aop";
+		#cooling-cells = <2>;
+		interconnects = <&compute_noc MASTER_NPU &compute_noc SLAVE_CDSP_MEM_NOC>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IMEM_CFG>;
+		interconnect-names = "icc-npu-cdspmem", "icc-cpu-imemcfg";
+		// qcom,npubw-dev = <&npu_npu_ddr_bw>;
+		qcom,npu-pwrlevels {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "qcom,npu-pwrlevels";
+			initial-pwrlevel = <4>;
+			qcom,npu-pwrlevel@0 {
+				reg = <0>;
+				vreg = <1>;
+				clk-freq = <0
+					0
+					0
+					100000000
+					300000000
+					300000000
+					19200000
+					150000000
+					100000000
+					37500000
+					19200000
+					60000000
+					100000000
+					19200000
+					19200000
+					0
+					19200000
+					300000000
+					19200000
+					19200000>;
+			};
+
+			qcom,npu-pwrlevel@1 {
+				reg = <1>;
+				vreg = <2>;
+				clk-freq = <0
+					0
+					0
+					150000000
+					350000000
+					350000000
+					37500000
+					200000000
+					150000000
+					75000000
+					19200000
+					120000000
+					150000000
+					19200000
+					19200000
+					0
+					19200000
+					350000000
+					19200000
+					19200000>;
+			};
+
+			qcom,npu-pwrlevel@2 {
+				reg = <2>;
+				vreg = <3>;
+				clk-freq = <0
+					0
+					0
+					200000000
+					400000000
+					400000000
+					37500000
+					300000000
+					200000000
+					75000000
+					19200000
+					120000000
+					200000000
+					19200000
+					19200000
+					0
+					19200000
+					400000000
+					19200000
+					19200000>;
+			};
+
+			qcom,npu-pwrlevel@3 {
+				reg = <3>;
+				vreg = <4>;
+				clk-freq = <0
+					0
+					0
+					300000000
+					600000000
+					600000000
+					75000000
+					403000000
+					300000000
+					150000000
+					19200000
+					240000000
+					300000000
+					19200000
+					19200000
+					0
+					19200000
+					600000000
+					19200000
+					19200000>;
+			};
+
+			qcom,npu-pwrlevel@4 {
+				reg = <4>;
+				vreg = <6>;
+				clk-freq = <0
+					0
+					0
+					350000000
+					715000000
+					715000000
+					75000000
+					533000000
+					350000000
+					150000000
+					19200000
+					240000000
+					350000000
+					19200000
+					19200000
+					0
+					19200000
+					715000000
+					19200000
+					19200000>;
+			};
+		};
+	};
+};
diff --git a/qcom/sm8150-smp2p.dtsi b/qcom/sm8150-smp2p.dtsi
index ac0f0e90..f35c5458 100755
--- a/qcom/sm8150-smp2p.dtsi
+++ b/qcom/sm8150-smp2p.dtsi
@@ -100,4 +100,41 @@
 		};
 	};
 
+	qcom,smp2p-modem@1799000c {
+		compatible = "qcom,smp2p";
+		qcom,smem = <435>, <428>;
+		interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
+		qcom,ipc = <&apcs 0 14>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <1>;
+
+		modem_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		modem_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
+			qcom,entry-name = "ipa";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		/* ipa - inbound entry from mss */
+		smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
+			qcom,entry-name = "ipa";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		smp2p_wlan_1_in: qcom,smp2p-wlan-1-in {
+			qcom,entry-name = "wlan";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
 };
diff --git a/qcom/sm8150-thermal.dtsi b/qcom/sm8150-thermal.dtsi
index e7a931c2..d73c03fc 100755
--- a/qcom/sm8150-thermal.dtsi
+++ b/qcom/sm8150-thermal.dtsi
@@ -389,6 +389,15 @@
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			npu_cdev {
+				trip = <&npu_trip0>;
+				cooling-device =
+					<&msm_npu THERMAL_NO_LIMIT
+						THERMAL_NO_LIMIT>;
+			};
+		};
 	};
 
 	cpu-0-0 {
diff --git a/qcom/sm8150-v2.dtsi b/qcom/sm8150-v2.dtsi
index ec01d86f..d323350b 100755
--- a/qcom/sm8150-v2.dtsi
+++ b/qcom/sm8150-v2.dtsi
@@ -271,3 +271,163 @@
 			0x0a00 0x00 0x0
 			0x0a44 0x03 0x0>;
 };
+
+/* NPU overrides */
+&msm_npu {
+	iommus = <&apps_smmu 0x1081 0x400>;
+	qcom,npu-pwrlevels {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "qcom,npu-pwrlevels";
+		initial-pwrlevel = <5>;
+		qcom,npu-pwrlevel@0 {
+			reg = <0>;
+			vreg = <1>;
+			clk-freq = <0
+				0
+				0
+				100000000
+				300000000
+				300000000
+				19200000
+				150000000
+				100000000
+				37500000
+				19200000
+				60000000
+				100000000
+				19200000
+				19200000
+				0
+				19200000
+				300000000
+				19200000
+				19200000>;
+		};
+
+		qcom,npu-pwrlevel@1 {
+			reg = <1>;
+			vreg = <2>;
+			clk-freq = <0
+				0
+				0
+				150000000
+				400000000
+				400000000
+				37500000
+				200000000
+				150000000
+				75000000
+				19200000
+				120000000
+				150000000
+				19200000
+				19200000
+				0
+				19200000
+				400000000
+				19200000
+				19200000>;
+		};
+
+		qcom,npu-pwrlevel@2 {
+			reg = <2>;
+			vreg = <3>;
+			clk-freq = <0
+				0
+				0
+				200000000
+				487000000
+				487000000
+				37500000
+				300000000
+				200000000
+				150000000
+				19200000
+				240000000
+				200000000
+				19200000
+				19200000
+				0
+				19200000
+				487000000
+				19200000
+				19200000>;
+		};
+
+		qcom,npu-pwrlevel@3 {
+			reg = <3>;
+			vreg = <4>;
+			clk-freq = <0
+				0
+				0
+				300000000
+				652000000
+				652000000
+				75000000
+				403000000
+				300000000
+				150000000
+				19200000
+				240000000
+				300000000
+				19200000
+				19200000
+				0
+				19200000
+				652000000
+				19200000
+				19200000>;
+		};
+
+		qcom,npu-pwrlevel@4 {
+			reg = <4>;
+			vreg = <6>;
+			clk-freq = <0
+				0
+				0
+				400000000
+				811000000
+				811000000
+				75000000
+				533000000
+				400000000
+				150000000
+				19200000
+				300000000
+				400000000
+				19200000
+				19200000
+				0
+				19200000
+				811000000
+				19200000
+				19200000>;
+		};
+
+		qcom,npu-pwrlevel@5 {
+			reg = <5>;
+			vreg = <7>;
+			clk-freq = <0
+				0
+				0
+				400000000
+				908000000
+				908000000
+				75000000
+				533000000
+				400000000
+				150000000
+				19200000
+				300000000
+				400000000
+				19200000
+				19200000
+				0
+				19200000
+				908000000
+				19200000
+				19200000>;
+		};
+	};
+};
diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi
index 149b1198..fac2d671 100755
--- a/qcom/sm8150.dtsi
+++ b/qcom/sm8150.dtsi
@@ -414,7 +414,7 @@
 			reg = <0x0 0x8be00000 0x0 0x1a00000>;
 		};
 
-		pil_modem_mem: modem_region {
+		rproc_modem_mem: rproc_modem_region {
 			no-map;
 			reg = <0x0 0x8d800000 0x0 0x4c1c000>;
 		};
@@ -483,6 +483,14 @@
 			size = <0x0 0x1000000>;
 		};
 
+		audio_cma_mem: audio_cma_region {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+			reusable;
+			alignment = <0x0 0x400000>;
+			size = <0x0 0x1000000>;
+		};
+
 		cdsp_mem: cdsp_region {
 			compatible = "shared-dma-pool";
 			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
@@ -491,6 +499,14 @@
 			size = <0x0 0x400000>;
 		};
 
+		mdsp_mem: mdsp_region {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+			reusable;
+			alignment = <0x0 0x400000>;
+			size = <0x0 0x1000000>;
+		};
+
 		user_contig_mem: user_contig_region {
 			compatible = "shared-dma-pool";
 			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
@@ -1096,6 +1112,24 @@
 		};
 	};
 
+	ufs_ice: ufsice@1d90000 {
+		compatible = "qcom,ice";
+		reg = <0x1d90000 0x8000>;
+		qcom,enable-ice-clk;
+		clock-names = "ufs_core_clk", "bus_clk",
+			"iface_clk", "ice_core_clk";
+		clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+			<&gcc GCC_UFS_MEM_CLKREF_CLK>,
+			<&gcc GCC_UFS_PHY_AHB_CLK>,
+			<&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+		qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;
+		vdd-hba-supply = <&ufs_phy_gdsc>;
+		qcom,bus-vector-names = "MIN",
+			"MAX";
+		qcom,instance-type = "ufs";
+		qcom,num-fde-slots = <31>;
+	};
+
 	ufsphy_mem: ufsphy_mem@1d87000 {
 		reg = <0x1d87000 0xda8>; /* PHY regs */
 		reg-names = "phy_mem";
@@ -1223,7 +1257,7 @@
 		reset-names = "rst";
 
 		iommus = <&apps_smmu 0x300 0x0>;
-		qcom,iommu-dma = "bypass";
+		qcom,iommu-dma = "fastmap";
 		dma-coherent;
 
 		status = "disabled";
@@ -1613,6 +1647,80 @@
 		};
 	};
 
+	modem_pas: remoteproc-modem@4080000 {
+		compatible = "qcom,sm8150-mpss-pas";
+		reg = <0x4080000 0x00100>;
+		status = "ok";
+
+		cx-supply = <&VDD_CX_LEVEL>;
+		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+		mx-supply = <&VDD_MX_LEVEL>;
+		mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+		reg-names = "cx", "mx";
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clock-names = "xo";
+
+		qcom,qmp = <&aoss_qmp>;
+
+		interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
+		interconnect-names = "crypto_ddr";
+
+		memory-region = <&rproc_modem_mem>;
+
+		/* Inputs from mss */
+		interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+					<&modem_smp2p_in 0 0>,
+					<&modem_smp2p_in 2 0>,
+					<&modem_smp2p_in 1 0>,
+					<&modem_smp2p_in 3 0>,
+					<&modem_smp2p_in 7 0>;
+
+		interrupt-names = "wdog",
+				"fatal",
+				"handover",
+				"ready",
+				"stop-ack",
+				"shutdown-ack";
+
+		/* Outputs to mss */
+		qcom,smem-states = <&modem_smp2p_out 0>;
+		qcom,smem-state-names = "stop";
+
+		glink-edge {
+			qcom,remote-pid = <1>;
+			transport = "smem";
+			mboxes = <&apss_shared 12>;
+			mbox-names = "mpss_smem";
+			interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
+
+			label = "modem";
+			qcom,glink-label = "mpss";
+
+			qcom,modem_qrtr {
+				qcom,glink-channels = "IPCRTR";
+				qcom,intents = <0x800  5
+						0x2000 3
+						0x4400 2>;
+			};
+
+			qcom,msm_fastrpc_rpmsg {
+				compatible = "qcom,msm-fastrpc-rpmsg";
+				qcom,glink-channels = "fastrpcglink-apps-dsp";
+				qcom,intents = <0x64 64>;
+			};
+
+			qcom,modem_glink_ssr {
+				qcom,glink-channels = "glink_ssr";
+			};
+
+			qcom,modem_ds {
+				qcom,glink-channels = "DS";
+				qcom,intents = <0x4000 0x2>;
+			};
+		};
+	};
+
 	qcom,pmu {
 		compatible = "qcom,pmu";
 		qcom,long-counter;
@@ -1954,6 +2062,11 @@
 		memory-region = <&adsp_mem>;
 	};
 
+	qcom,msm-mdsprpc-mem {
+		compatible = "qcom,msm-mdsprpc-mem-region";
+		memory-region = <&mdsp_mem>;
+	};
+
 	msm_fastrpc: qcom,msm_fastrpc {
 		compatible = "qcom,msm-fastrpc-compute";
 		qcom,fastrpc-adsp-audio-pdr;
@@ -2296,3 +2409,4 @@
 };
 
 #include "sm8150-thermal.dtsi"
+#include "sm8150-npu.dtsi"