diff options
author | qctecmdr <qctecmdr@localhost> | 2021-03-21 21:29:26 -0700 |
---|---|---|
committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2021-03-21 21:29:25 -0700 |
commit | b80c6698d32c1ea177e030e19eb42a1843242740 (patch) | |
tree | 210f0fedb4e07b7529420875df76084e6ab0b927 | |
parent | 71e94454da384058a33e3d319c9959dde9543b0d (diff) | |
parent | 9d088612ca6124e196691ee06bb39d1b37331a5f (diff) | |
download | devicetree-b80c6698d32c1ea177e030e19eb42a1843242740.tar.gz |
Merge "ARM: dts: msm: update mdss byte/pxl clocks for SPF targets"
-rw-r--r-- | qcom/msm8917-mdss.dtsi | 1 | ||||
-rw-r--r-- | qcom/msm8917.dtsi | 2 | ||||
-rw-r--r-- | qcom/msm8937-mdss.dtsi | 13 | ||||
-rw-r--r-- | qcom/msm8937.dtsi | 10 | ||||
-rw-r--r-- | qcom/sdm429.dtsi | 10 | ||||
-rw-r--r-- | qcom/sdm439.dtsi | 25 |
6 files changed, 34 insertions, 27 deletions
diff --git a/qcom/msm8917-mdss.dtsi b/qcom/msm8917-mdss.dtsi index 235c6534..0f2e80ed 100644 --- a/qcom/msm8917-mdss.dtsi +++ b/qcom/msm8917-mdss.dtsi @@ -1,5 +1,4 @@ #include "msm8937-mdss.dtsi" -#include <dt-bindings/clock/mdss-28nm-pll-clk.h> &mdss_dsi { vdda-supply = <&pm8937_l2>; vddio-supply = <&pm8937_l6>; diff --git a/qcom/msm8917.dtsi b/qcom/msm8917.dtsi index cdbed04b..854c2f54 100644 --- a/qcom/msm8917.dtsi +++ b/qcom/msm8917.dtsi @@ -1,6 +1,6 @@ #include "skeleton64.dtsi" #include <dt-bindings/clock/qcom,gcc-sdm429w.h> -#include <dt-bindings/clock/mdss-28nm-pll-clk.h> +#include <dt-bindings/clock/mdss-28nm-pll-clk-legacy.h> #include <dt-bindings/clock/qcom,cpu-sdm.h> #include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/regulator/qcom,rpm-smd-regulator.h> diff --git a/qcom/msm8937-mdss.dtsi b/qcom/msm8937-mdss.dtsi index 7bb62964..59b8a282 100644 --- a/qcom/msm8937-mdss.dtsi +++ b/qcom/msm8937-mdss.dtsi @@ -234,13 +234,12 @@ clocks = <&gcc_mdss MDSS_MDP_VOTE_CLK>, <&gcc GCC_MDSS_AHB_CLK>, - <&gcc GCC_MDSS_AXI_CLK>; - /* TODO - * <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>, - * <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>, - * <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>, - * <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>; - */ + <&gcc GCC_MDSS_AXI_CLK>, + <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>, + <&mdss_dsi1_pll BYTECLK_SRC_1_CLK>, + <&mdss_dsi0_pll PCLK_SRC_0_CLK>, + <&mdss_dsi1_pll PCLK_SRC_1_CLK>; + clock-names = "mdp_core_clk", "iface_clk", "bus_clk", "ext_byte0_clk", "ext_byte1_clk", "ext_pixel0_clk", "ext_pixel1_clk"; diff --git a/qcom/msm8937.dtsi b/qcom/msm8937.dtsi index a81f2afb..8b177b6a 100644 --- a/qcom/msm8937.dtsi +++ b/qcom/msm8937.dtsi @@ -4,7 +4,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-sdm429w.h> #include <dt-bindings/clock/qcom,rpmcc.h> -#include <dt-bindings/clock/mdss-28nm-pll-clk.h> +#include <dt-bindings/clock/mdss-28nm-pll-clk-legacy.h> #define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) #define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;} @@ -599,10 +599,10 @@ gcc_mdss: qcom,gcc-mdss@1800000 { compatible = "qcom,gcc-mdss-msm8937"; reg = <0x1800000 0x80000>; - clocks = <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>, - <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>, - <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>, - <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>; + clocks = <&mdss_dsi0_pll PCLK_SRC_0_CLK>, + <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>, + <&mdss_dsi1_pll PCLK_SRC_1_CLK>, + <&mdss_dsi1_pll BYTECLK_SRC_1_CLK>; clock-names = "pclk0_src", "byte0_src", "pclk1_src", "byte1_src"; #clock-cells = <1>; diff --git a/qcom/sdm429.dtsi b/qcom/sdm429.dtsi index 6c42cd19..506cd0d1 100644 --- a/qcom/sdm429.dtsi +++ b/qcom/sdm429.dtsi @@ -219,12 +219,10 @@ &gcc_mdss { compatible = "qcom,gcc-mdss-sdm429"; - /* TODO - * clocks = <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>, - * <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>, - * <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>, - * <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>; - */ + clocks = <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>, + <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>, + <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>, + <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>; clock-names = "pclk0_src", "byte0_src", "pclk1_src", "byte1_src"; #clock-cells = <1>; diff --git a/qcom/sdm439.dtsi b/qcom/sdm439.dtsi index da27c317..51e8e699 100644 --- a/qcom/sdm439.dtsi +++ b/qcom/sdm439.dtsi @@ -2,7 +2,7 @@ #include "sdm439-pm8953.dtsi" #include "sdm439-pmi632.dtsi" #include "sdm439-audio.dtsi" - +#include <dt-bindings/clock/mdss-12nm-pll-clk.h> / { model = "Qualcomm Technologies, Inc. SDM439"; compatible = "qcom,sdm439"; @@ -340,12 +340,10 @@ &gcc_mdss { compatible = "qcom,gcc-mdss-sdm439"; - /* TODO - * clocks = <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>, - * <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>, - * <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>, - * <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>; - */ + clocks = <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>, + <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>, + <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>, + <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>; clock-names = "pclk0_src", "byte0_src", "pclk1_src", "byte1_src"; #clock-cells = <1>; @@ -380,6 +378,19 @@ 0x1a96000 0x1a96000 0x300 0x1a96400 0x1a96400 0x400 0x193e000 0x193e000 0x30>; + + clocks = <&gcc_mdss MDSS_MDP_VOTE_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>, + <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>, + <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>, + <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>; + + clock-names = "mdp_core_clk", "iface_clk", "bus_clk", + "ext_byte0_clk", "ext_byte1_clk", "ext_pixel0_clk", + "ext_pixel1_clk"; + }; &mdss_dsi0 { |